1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36#include <linux/module.h> 37#include <linux/kernel.h> 38#include <linux/init.h> 39#include <linux/errno.h> 40#include <linux/pci.h> 41#include <linux/dma-mapping.h> 42#include <linux/slab.h> 43#include <linux/io-mapping.h> 44#include <linux/delay.h> 45#include <linux/kmod.h> 46#include <linux/etherdevice.h> 47#include <net/devlink.h> 48 49#include <uapi/rdma/mlx4-abi.h> 50#include <linux/mlx4/device.h> 51#include <linux/mlx4/doorbell.h> 52 53#include "mlx4.h" 54#include "fw.h" 55#include "icm.h" 56 57MODULE_AUTHOR("Roland Dreier"); 58MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 59MODULE_LICENSE("Dual BSD/GPL"); 60MODULE_VERSION(DRV_VERSION); 61 62struct workqueue_struct *mlx4_wq; 63 64#ifdef CONFIG_MLX4_DEBUG 65 66int mlx4_debug_level; /* 0 by default */ 67module_param_named(debug_level, mlx4_debug_level, int, 0644); 68MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 69 70#endif /* CONFIG_MLX4_DEBUG */ 71 72#ifdef CONFIG_PCI_MSI 73 74static int msi_x = 1; 75module_param(msi_x, int, 0444); 76MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 77 78#else /* CONFIG_PCI_MSI */ 79 80#define msi_x (0) 81 82#endif /* CONFIG_PCI_MSI */ 83 84static uint8_t num_vfs[3] = {0, 0, 0}; 85static int num_vfs_argc; 86module_param_array(num_vfs, byte, &num_vfs_argc, 0444); 87MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 88 "num_vfs=port1,port2,port1+2"); 89 90static uint8_t probe_vf[3] = {0, 0, 0}; 91static int probe_vfs_argc; 92module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 93MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 94 "probe_vf=port1,port2,port1+2"); 95 96static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 97module_param_named(log_num_mgm_entry_size, 98 mlx4_log_num_mgm_entry_size, int, 0444); 99MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 100 " of qp per mcg, for example:" 101 " 10 gives 248.range: 7 <=" 102 " log_num_mgm_entry_size <= 12." 103 " To activate device managed" 104 " flow steering when available, set to -1"); 105 106static bool enable_64b_cqe_eqe = true; 107module_param(enable_64b_cqe_eqe, bool, 0444); 108MODULE_PARM_DESC(enable_64b_cqe_eqe, 109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 110 111static bool enable_4k_uar; 112module_param(enable_4k_uar, bool, 0444); 113MODULE_PARM_DESC(enable_4k_uar, 114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 115 116#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 118 MLX4_FUNC_CAP_DMFS_A0_STATIC) 119 120#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 121 122static char mlx4_version[] = 123 DRV_NAME ": Mellanox ConnectX core driver v" 124 DRV_VERSION "\n"; 125 126static const struct mlx4_profile default_profile = { 127 .num_qp = 1 << 18, 128 .num_srq = 1 << 16, 129 .rdmarc_per_qp = 1 << 4, 130 .num_cq = 1 << 16, 131 .num_mcg = 1 << 13, 132 .num_mpt = 1 << 19, 133 .num_mtt = 1 << 20, /* It is really num mtt segements */ 134}; 135 136static const struct mlx4_profile low_mem_profile = { 137 .num_qp = 1 << 17, 138 .num_srq = 1 << 6, 139 .rdmarc_per_qp = 1 << 4, 140 .num_cq = 1 << 8, 141 .num_mcg = 1 << 8, 142 .num_mpt = 1 << 9, 143 .num_mtt = 1 << 7, 144}; 145 146static int log_num_mac = 7; 147module_param_named(log_num_mac, log_num_mac, int, 0444); 148MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 149 150static int log_num_vlan; 151module_param_named(log_num_vlan, log_num_vlan, int, 0444); 152MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 153/* Log2 max number of VLANs per ETH port (0-7) */ 154#define MLX4_LOG_NUM_VLANS 7 155#define MLX4_MIN_LOG_NUM_VLANS 0 156#define MLX4_MIN_LOG_NUM_MAC 1 157 158static bool use_prio; 159module_param_named(use_prio, use_prio, bool, 0444); 160MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 161 162int log_mtts_per_seg = ilog2(1); 163module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 164MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 165 "(0-7) (default: 0)"); 166 167static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 168static int arr_argc = 2; 169module_param_array(port_type_array, int, &arr_argc, 0444); 170MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 171 "1 for IB, 2 for Ethernet"); 172 173struct mlx4_port_config { 174 struct list_head list; 175 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 176 struct pci_dev *pdev; 177}; 178 179static atomic_t pf_loading = ATOMIC_INIT(0); 180 181static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 182 struct devlink_param_gset_ctx *ctx) 183{ 184 ctx->val.vbool = !!mlx4_internal_err_reset; 185 return 0; 186} 187 188static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 189 struct devlink_param_gset_ctx *ctx) 190{ 191 mlx4_internal_err_reset = ctx->val.vbool; 192 return 0; 193} 194 195static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 196 struct devlink_param_gset_ctx *ctx) 197{ 198 struct mlx4_priv *priv = devlink_priv(devlink); 199 struct mlx4_dev *dev = &priv->dev; 200 201 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 202 return 0; 203} 204 205static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 206 struct devlink_param_gset_ctx *ctx) 207{ 208 struct mlx4_priv *priv = devlink_priv(devlink); 209 struct mlx4_dev *dev = &priv->dev; 210 211 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 212 return 0; 213} 214 215static int 216mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 217 union devlink_param_value val, 218 struct netlink_ext_ack *extack) 219{ 220 u32 value = val.vu32; 221 222 if (value < 1 || value > 128) 223 return -ERANGE; 224 225 if (!is_power_of_2(value)) { 226 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 227 return -EINVAL; 228 } 229 230 return 0; 231} 232 233enum mlx4_devlink_param_id { 234 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 235 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 236 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 237}; 238 239static const struct devlink_param mlx4_devlink_params[] = { 240 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 241 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 242 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 243 mlx4_devlink_ierr_reset_get, 244 mlx4_devlink_ierr_reset_set, NULL), 245 DEVLINK_PARAM_GENERIC(MAX_MACS, 246 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 247 NULL, NULL, mlx4_devlink_max_macs_validate), 248 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 249 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 250 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 251 mlx4_devlink_crdump_snapshot_get, 252 mlx4_devlink_crdump_snapshot_set, NULL), 253 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 254 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 255 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 256 NULL, NULL, NULL), 257 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 258 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 259 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 260 NULL, NULL, NULL), 261}; 262 263static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 264{ 265 union devlink_param_value value; 266 267 value.vbool = !!mlx4_internal_err_reset; 268 devlink_param_driverinit_value_set(devlink, 269 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 270 value); 271 272 value.vu32 = 1UL << log_num_mac; 273 devlink_param_driverinit_value_set(devlink, 274 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 275 value); 276 277 value.vbool = enable_64b_cqe_eqe; 278 devlink_param_driverinit_value_set(devlink, 279 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 280 value); 281 282 value.vbool = enable_4k_uar; 283 devlink_param_driverinit_value_set(devlink, 284 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 285 value); 286 287 value.vbool = false; 288 devlink_param_driverinit_value_set(devlink, 289 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 290 value); 291} 292 293static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 294 struct mlx4_dev_cap *dev_cap) 295{ 296 /* The reserved_uars is calculated by system page size unit. 297 * Therefore, adjustment is added when the uar page size is less 298 * than the system page size 299 */ 300 dev->caps.reserved_uars = 301 max_t(int, 302 mlx4_get_num_reserved_uar(dev), 303 dev_cap->reserved_uars / 304 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 305} 306 307int mlx4_check_port_params(struct mlx4_dev *dev, 308 enum mlx4_port_type *port_type) 309{ 310 int i; 311 312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 313 for (i = 0; i < dev->caps.num_ports - 1; i++) { 314 if (port_type[i] != port_type[i + 1]) { 315 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 316 return -EOPNOTSUPP; 317 } 318 } 319 } 320 321 for (i = 0; i < dev->caps.num_ports; i++) { 322 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 323 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 324 i + 1); 325 return -EOPNOTSUPP; 326 } 327 } 328 return 0; 329} 330 331static void mlx4_set_port_mask(struct mlx4_dev *dev) 332{ 333 int i; 334 335 for (i = 1; i <= dev->caps.num_ports; ++i) 336 dev->caps.port_mask[i] = dev->caps.port_type[i]; 337} 338 339enum { 340 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 341}; 342 343static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 344{ 345 int err = 0; 346 struct mlx4_func func; 347 348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 349 err = mlx4_QUERY_FUNC(dev, &func, 0); 350 if (err) { 351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 352 return err; 353 } 354 dev_cap->max_eqs = func.max_eq; 355 dev_cap->reserved_eqs = func.rsvd_eqs; 356 dev_cap->reserved_uars = func.rsvd_uars; 357 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 358 } 359 return err; 360} 361 362static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 363{ 364 struct mlx4_caps *dev_cap = &dev->caps; 365 366 /* FW not supporting or cancelled by user */ 367 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 368 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 369 return; 370 371 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 372 * When FW has NCSI it may decide not to report 64B CQE/EQEs 373 */ 374 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 375 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 376 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 377 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 378 return; 379 } 380 381 if (cache_line_size() == 128 || cache_line_size() == 256) { 382 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 383 /* Changing the real data inside CQE size to 32B */ 384 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 385 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 386 387 if (mlx4_is_master(dev)) 388 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 389 } else { 390 if (cache_line_size() != 32 && cache_line_size() != 64) 391 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 392 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 393 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 394 } 395} 396 397static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 398 struct mlx4_port_cap *port_cap) 399{ 400 dev->caps.vl_cap[port] = port_cap->max_vl; 401 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 402 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 403 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 404 /* set gid and pkey table operating lengths by default 405 * to non-sriov values 406 */ 407 dev->caps.gid_table_len[port] = port_cap->max_gids; 408 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 409 dev->caps.port_width_cap[port] = port_cap->max_port_width; 410 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 411 dev->caps.max_tc_eth = port_cap->max_tc_eth; 412 dev->caps.def_mac[port] = port_cap->def_mac; 413 dev->caps.supported_type[port] = port_cap->supported_port_types; 414 dev->caps.suggested_type[port] = port_cap->suggested_type; 415 dev->caps.default_sense[port] = port_cap->default_sense; 416 dev->caps.trans_type[port] = port_cap->trans_type; 417 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 418 dev->caps.wavelength[port] = port_cap->wavelength; 419 dev->caps.trans_code[port] = port_cap->trans_code; 420 421 return 0; 422} 423 424static int mlx4_dev_port(struct mlx4_dev *dev, int port, 425 struct mlx4_port_cap *port_cap) 426{ 427 int err = 0; 428 429 err = mlx4_QUERY_PORT(dev, port, port_cap); 430 431 if (err) 432 mlx4_err(dev, "QUERY_PORT command failed.\n"); 433 434 return err; 435} 436 437static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 438{ 439 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 440 return; 441 442 if (mlx4_is_mfunc(dev)) { 443 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 444 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 445 return; 446 } 447 448 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 449 mlx4_dbg(dev, 450 "Keep FCS is not supported - Disabling Ignore FCS"); 451 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 452 return; 453 } 454} 455 456#define MLX4_A0_STEERING_TABLE_SIZE 256 457static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 458{ 459 int err; 460 int i; 461 462 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 463 if (err) { 464 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 465 return err; 466 } 467 mlx4_dev_cap_dump(dev, dev_cap); 468 469 if (dev_cap->min_page_sz > PAGE_SIZE) { 470 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 471 dev_cap->min_page_sz, PAGE_SIZE); 472 return -ENODEV; 473 } 474 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 475 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 476 dev_cap->num_ports, MLX4_MAX_PORTS); 477 return -ENODEV; 478 } 479 480 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 481 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 482 dev_cap->uar_size, 483 (unsigned long long) 484 pci_resource_len(dev->persist->pdev, 2)); 485 return -ENODEV; 486 } 487 488 dev->caps.num_ports = dev_cap->num_ports; 489 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 490 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 491 dev->caps.num_sys_eqs : 492 MLX4_MAX_EQ_NUM; 493 for (i = 1; i <= dev->caps.num_ports; ++i) { 494 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 495 if (err) { 496 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 497 return err; 498 } 499 } 500 501 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user; 502 dev->caps.uar_page_size = PAGE_SIZE; 503 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 504 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 505 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 506 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 507 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 508 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 509 dev->caps.max_wqes = dev_cap->max_qp_sz; 510 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 511 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 512 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 513 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 514 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 515 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 516 /* 517 * Subtract 1 from the limit because we need to allocate a 518 * spare CQE to enable resizing the CQ. 519 */ 520 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 521 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 522 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 523 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 524 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 525 526 dev->caps.reserved_pds = dev_cap->reserved_pds; 527 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 528 dev_cap->reserved_xrcds : 0; 529 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 530 dev_cap->max_xrcds : 0; 531 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 532 533 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 534 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 535 dev->caps.flags = dev_cap->flags; 536 dev->caps.flags2 = dev_cap->flags2; 537 dev->caps.bmme_flags = dev_cap->bmme_flags; 538 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 539 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 540 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 541 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 542 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 543 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 544 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 545 546 /* Save uar page shift */ 547 if (!mlx4_is_slave(dev)) { 548 /* Virtual PCI function needs to determine UAR page size from 549 * firmware. Only master PCI function can set the uar page size 550 */ 551 if (enable_4k_uar || !dev->persist->num_vfs) 552 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 553 else 554 dev->uar_page_shift = PAGE_SHIFT; 555 556 mlx4_set_num_reserved_uars(dev, dev_cap); 557 } 558 559 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 560 struct mlx4_init_hca_param hca_param; 561 562 memset(&hca_param, 0, sizeof(hca_param)); 563 err = mlx4_QUERY_HCA(dev, &hca_param); 564 /* Turn off PHV_EN flag in case phv_check_en is set. 565 * phv_check_en is a HW check that parse the packet and verify 566 * phv bit was reported correctly in the wqe. To allow QinQ 567 * PHV_EN flag should be set and phv_check_en must be cleared 568 * otherwise QinQ packets will be drop by the HW. 569 */ 570 if (err || hca_param.phv_check_en) 571 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 572 } 573 574 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 575 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 576 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 577 /* Don't do sense port on multifunction devices (for now at least) */ 578 if (mlx4_is_mfunc(dev)) 579 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 580 581 if (mlx4_low_memory_profile()) { 582 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 583 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 584 } else { 585 dev->caps.log_num_macs = log_num_mac; 586 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 587 } 588 589 for (i = 1; i <= dev->caps.num_ports; ++i) { 590 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 591 if (dev->caps.supported_type[i]) { 592 /* if only ETH is supported - assign ETH */ 593 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 594 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 595 /* if only IB is supported, assign IB */ 596 else if (dev->caps.supported_type[i] == 597 MLX4_PORT_TYPE_IB) 598 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 599 else { 600 /* if IB and ETH are supported, we set the port 601 * type according to user selection of port type; 602 * if user selected none, take the FW hint */ 603 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 604 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 605 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 606 else 607 dev->caps.port_type[i] = port_type_array[i - 1]; 608 } 609 } 610 /* 611 * Link sensing is allowed on the port if 3 conditions are true: 612 * 1. Both protocols are supported on the port. 613 * 2. Different types are supported on the port 614 * 3. FW declared that it supports link sensing 615 */ 616 mlx4_priv(dev)->sense.sense_allowed[i] = 617 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 618 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 619 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 620 621 /* 622 * If "default_sense" bit is set, we move the port to "AUTO" mode 623 * and perform sense_port FW command to try and set the correct 624 * port type from beginning 625 */ 626 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 627 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 628 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 629 mlx4_SENSE_PORT(dev, i, &sensed_port); 630 if (sensed_port != MLX4_PORT_TYPE_NONE) 631 dev->caps.port_type[i] = sensed_port; 632 } else { 633 dev->caps.possible_type[i] = dev->caps.port_type[i]; 634 } 635 636 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 637 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 638 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 639 i, 1 << dev->caps.log_num_macs); 640 } 641 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 642 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 643 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 644 i, 1 << dev->caps.log_num_vlans); 645 } 646 } 647 648 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 649 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 650 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 651 mlx4_warn(dev, 652 "Granular QoS per VF not supported with IB/Eth configuration\n"); 653 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 654 } 655 656 dev->caps.max_counters = dev_cap->max_counters; 657 658 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 660 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 661 (1 << dev->caps.log_num_macs) * 662 (1 << dev->caps.log_num_vlans) * 663 dev->caps.num_ports; 664 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 665 666 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 667 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 668 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 669 else 670 dev->caps.dmfs_high_rate_qpn_base = 671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 672 673 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 674 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 675 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 677 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 678 } else { 679 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 680 dev->caps.dmfs_high_rate_qpn_base = 681 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 682 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 683 } 684 685 dev->caps.rl_caps = dev_cap->rl_caps; 686 687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 688 dev->caps.dmfs_high_rate_qpn_range; 689 690 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 691 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 694 695 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 696 697 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 698 if (dev_cap->flags & 699 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 700 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 702 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 703 } 704 705 if (dev_cap->flags2 & 706 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 707 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 708 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 709 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 710 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 711 } 712 } 713 714 if ((dev->caps.flags & 715 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 716 mlx4_is_master(dev)) 717 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 718 719 if (!mlx4_is_slave(dev)) { 720 mlx4_enable_cqe_eqe_stride(dev); 721 dev->caps.alloc_res_qp_mask = 722 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 723 MLX4_RESERVE_A0_QP; 724 725 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 726 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 727 mlx4_warn(dev, "Old device ETS support detected\n"); 728 mlx4_warn(dev, "Consider upgrading device FW.\n"); 729 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 730 } 731 732 } else { 733 dev->caps.alloc_res_qp_mask = 0; 734 } 735 736 mlx4_enable_ignore_fcs(dev); 737 738 return 0; 739} 740 741/*The function checks if there are live vf, return the num of them*/ 742static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 743{ 744 struct mlx4_priv *priv = mlx4_priv(dev); 745 struct mlx4_slave_state *s_state; 746 int i; 747 int ret = 0; 748 749 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 750 s_state = &priv->mfunc.master.slave_state[i]; 751 if (s_state->active && s_state->last_cmd != 752 MLX4_COMM_CMD_RESET) { 753 mlx4_warn(dev, "%s: slave: %d is still active\n", 754 __func__, i); 755 ret++; 756 } 757 } 758 return ret; 759} 760 761int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 762{ 763 u32 qk = MLX4_RESERVED_QKEY_BASE; 764 765 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 766 qpn < dev->phys_caps.base_proxy_sqpn) 767 return -EINVAL; 768 769 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 770 /* tunnel qp */ 771 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 772 else 773 qk += qpn - dev->phys_caps.base_proxy_sqpn; 774 *qkey = qk; 775 return 0; 776} 777EXPORT_SYMBOL(mlx4_get_parav_qkey); 778 779void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 780{ 781 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 782 783 if (!mlx4_is_master(dev)) 784 return; 785 786 priv->virt2phys_pkey[slave][port - 1][i] = val; 787} 788EXPORT_SYMBOL(mlx4_sync_pkey_table); 789 790void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 791{ 792 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 793 794 if (!mlx4_is_master(dev)) 795 return; 796 797 priv->slave_node_guids[slave] = guid; 798} 799EXPORT_SYMBOL(mlx4_put_slave_node_guid); 800 801__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 802{ 803 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 804 805 if (!mlx4_is_master(dev)) 806 return 0; 807 808 return priv->slave_node_guids[slave]; 809} 810EXPORT_SYMBOL(mlx4_get_slave_node_guid); 811 812int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 813{ 814 struct mlx4_priv *priv = mlx4_priv(dev); 815 struct mlx4_slave_state *s_slave; 816 817 if (!mlx4_is_master(dev)) 818 return 0; 819 820 s_slave = &priv->mfunc.master.slave_state[slave]; 821 return !!s_slave->active; 822} 823EXPORT_SYMBOL(mlx4_is_slave_active); 824 825void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 826 struct _rule_hw *eth_header) 827{ 828 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 829 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 830 struct mlx4_net_trans_rule_hw_eth *eth = 831 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 832 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 833 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 834 next_rule->rsvd == 0; 835 836 if (last_rule) 837 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 838 } 839} 840EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 841 842static void slave_adjust_steering_mode(struct mlx4_dev *dev, 843 struct mlx4_dev_cap *dev_cap, 844 struct mlx4_init_hca_param *hca_param) 845{ 846 dev->caps.steering_mode = hca_param->steering_mode; 847 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 848 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 849 dev->caps.fs_log_max_ucast_qp_range_size = 850 dev_cap->fs_log_max_ucast_qp_range_size; 851 } else 852 dev->caps.num_qp_per_mgm = 853 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 854 855 mlx4_dbg(dev, "Steering mode is: %s\n", 856 mlx4_steering_mode_str(dev->caps.steering_mode)); 857} 858 859static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 860{ 861 kfree(dev->caps.spec_qps); 862 dev->caps.spec_qps = NULL; 863} 864 865static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 866{ 867 struct mlx4_func_cap *func_cap = NULL; 868 struct mlx4_caps *caps = &dev->caps; 869 int i, err = 0; 870 871 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 872 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 873 874 if (!func_cap || !caps->spec_qps) { 875 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 876 err = -ENOMEM; 877 goto err_mem; 878 } 879 880 for (i = 1; i <= caps->num_ports; ++i) { 881 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 882 if (err) { 883 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 884 i, err); 885 goto err_mem; 886 } 887 caps->spec_qps[i - 1] = func_cap->spec_qps; 888 caps->port_mask[i] = caps->port_type[i]; 889 caps->phys_port_id[i] = func_cap->phys_port_id; 890 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 891 &caps->gid_table_len[i], 892 &caps->pkey_table_len[i]); 893 if (err) { 894 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 895 i, err); 896 goto err_mem; 897 } 898 } 899 900err_mem: 901 if (err) 902 mlx4_slave_destroy_special_qp_cap(dev); 903 kfree(func_cap); 904 return err; 905} 906 907static int mlx4_slave_cap(struct mlx4_dev *dev) 908{ 909 int err; 910 u32 page_size; 911 struct mlx4_dev_cap *dev_cap = NULL; 912 struct mlx4_func_cap *func_cap = NULL; 913 struct mlx4_init_hca_param *hca_param = NULL; 914 915 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 916 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 917 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 918 if (!hca_param || !func_cap || !dev_cap) { 919 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 920 err = -ENOMEM; 921 goto free_mem; 922 } 923 924 err = mlx4_QUERY_HCA(dev, hca_param); 925 if (err) { 926 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 927 goto free_mem; 928 } 929 930 /* fail if the hca has an unknown global capability 931 * at this time global_caps should be always zeroed 932 */ 933 if (hca_param->global_caps) { 934 mlx4_err(dev, "Unknown hca global capabilities\n"); 935 err = -EINVAL; 936 goto free_mem; 937 } 938 939 dev->caps.hca_core_clock = hca_param->hca_core_clock; 940 941 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 942 err = mlx4_dev_cap(dev, dev_cap); 943 if (err) { 944 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 945 goto free_mem; 946 } 947 948 err = mlx4_QUERY_FW(dev); 949 if (err) 950 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 951 952 page_size = ~dev->caps.page_size_cap + 1; 953 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 954 if (page_size > PAGE_SIZE) { 955 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 956 page_size, PAGE_SIZE); 957 err = -ENODEV; 958 goto free_mem; 959 } 960 961 /* Set uar_page_shift for VF */ 962 dev->uar_page_shift = hca_param->uar_page_sz + 12; 963 964 /* Make sure the master uar page size is valid */ 965 if (dev->uar_page_shift > PAGE_SHIFT) { 966 mlx4_err(dev, 967 "Invalid configuration: uar page size is larger than system page size\n"); 968 err = -ENODEV; 969 goto free_mem; 970 } 971 972 /* Set reserved_uars based on the uar_page_shift */ 973 mlx4_set_num_reserved_uars(dev, dev_cap); 974 975 /* Although uar page size in FW differs from system page size, 976 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 977 * still works with assumption that uar page size == system page size 978 */ 979 dev->caps.uar_page_size = PAGE_SIZE; 980 981 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 982 if (err) { 983 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 984 err); 985 goto free_mem; 986 } 987 988 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 989 PF_CONTEXT_BEHAVIOUR_MASK) { 990 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 991 func_cap->pf_context_behaviour, 992 PF_CONTEXT_BEHAVIOUR_MASK); 993 err = -EINVAL; 994 goto free_mem; 995 } 996 997 dev->caps.num_ports = func_cap->num_ports; 998 dev->quotas.qp = func_cap->qp_quota; 999 dev->quotas.srq = func_cap->srq_quota; 1000 dev->quotas.cq = func_cap->cq_quota; 1001 dev->quotas.mpt = func_cap->mpt_quota; 1002 dev->quotas.mtt = func_cap->mtt_quota; 1003 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1004 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1005 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1006 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1007 dev->caps.num_eqs = func_cap->max_eq; 1008 dev->caps.reserved_eqs = func_cap->reserved_eq; 1009 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1010 dev->caps.num_pds = MLX4_NUM_PDS; 1011 dev->caps.num_mgms = 0; 1012 dev->caps.num_amgms = 0; 1013 1014 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1015 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1016 dev->caps.num_ports, MLX4_MAX_PORTS); 1017 err = -ENODEV; 1018 goto free_mem; 1019 } 1020 1021 mlx4_replace_zero_macs(dev); 1022 1023 err = mlx4_slave_special_qp_cap(dev); 1024 if (err) { 1025 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1026 goto free_mem; 1027 } 1028 1029 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1030 dev->caps.reserved_uars) > 1031 pci_resource_len(dev->persist->pdev, 1032 2)) { 1033 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1034 dev->caps.uar_page_size * dev->caps.num_uars, 1035 (unsigned long long) 1036 pci_resource_len(dev->persist->pdev, 2)); 1037 err = -ENOMEM; 1038 goto err_mem; 1039 } 1040 1041 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1042 dev->caps.eqe_size = 64; 1043 dev->caps.eqe_factor = 1; 1044 } else { 1045 dev->caps.eqe_size = 32; 1046 dev->caps.eqe_factor = 0; 1047 } 1048 1049 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1050 dev->caps.cqe_size = 64; 1051 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1052 } else { 1053 dev->caps.cqe_size = 32; 1054 } 1055 1056 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1057 dev->caps.eqe_size = hca_param->eqe_size; 1058 dev->caps.eqe_factor = 0; 1059 } 1060 1061 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1062 dev->caps.cqe_size = hca_param->cqe_size; 1063 /* User still need to know when CQE > 32B */ 1064 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1065 } 1066 1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1068 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1069 1070 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1071 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1072 1073 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1074 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1075 hca_param->rss_ip_frags ? "on" : "off"); 1076 1077 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1078 dev->caps.bf_reg_size) 1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1080 1081 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1082 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1083 1084err_mem: 1085 if (err) 1086 mlx4_slave_destroy_special_qp_cap(dev); 1087free_mem: 1088 kfree(hca_param); 1089 kfree(func_cap); 1090 kfree(dev_cap); 1091 return err; 1092} 1093 1094static void mlx4_request_modules(struct mlx4_dev *dev) 1095{ 1096 int port; 1097 int has_ib_port = false; 1098 int has_eth_port = false; 1099#define EN_DRV_NAME "mlx4_en" 1100#define IB_DRV_NAME "mlx4_ib" 1101 1102 for (port = 1; port <= dev->caps.num_ports; port++) { 1103 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1104 has_ib_port = true; 1105 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1106 has_eth_port = true; 1107 } 1108 1109 if (has_eth_port) 1110 request_module_nowait(EN_DRV_NAME); 1111 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 1112 request_module_nowait(IB_DRV_NAME); 1113} 1114 1115/* 1116 * Change the port configuration of the device. 1117 * Every user of this function must hold the port mutex. 1118 */ 1119int mlx4_change_port_types(struct mlx4_dev *dev, 1120 enum mlx4_port_type *port_types) 1121{ 1122 int err = 0; 1123 int change = 0; 1124 int port; 1125 1126 for (port = 0; port < dev->caps.num_ports; port++) { 1127 /* Change the port type only if the new type is different 1128 * from the current, and not set to Auto */ 1129 if (port_types[port] != dev->caps.port_type[port + 1]) 1130 change = 1; 1131 } 1132 if (change) { 1133 mlx4_unregister_device(dev); 1134 for (port = 1; port <= dev->caps.num_ports; port++) { 1135 mlx4_CLOSE_PORT(dev, port); 1136 dev->caps.port_type[port] = port_types[port - 1]; 1137 err = mlx4_SET_PORT(dev, port, -1); 1138 if (err) { 1139 mlx4_err(dev, "Failed to set port %d, aborting\n", 1140 port); 1141 goto out; 1142 } 1143 } 1144 mlx4_set_port_mask(dev); 1145 err = mlx4_register_device(dev); 1146 if (err) { 1147 mlx4_err(dev, "Failed to register device\n"); 1148 goto out; 1149 } 1150 mlx4_request_modules(dev); 1151 } 1152 1153out: 1154 return err; 1155} 1156 1157static ssize_t show_port_type(struct device *dev, 1158 struct device_attribute *attr, 1159 char *buf) 1160{ 1161 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1162 port_attr); 1163 struct mlx4_dev *mdev = info->dev; 1164 char type[8]; 1165 1166 sprintf(type, "%s", 1167 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1168 "ib" : "eth"); 1169 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1170 sprintf(buf, "auto (%s)\n", type); 1171 else 1172 sprintf(buf, "%s\n", type); 1173 1174 return strlen(buf); 1175} 1176 1177static int __set_port_type(struct mlx4_port_info *info, 1178 enum mlx4_port_type port_type) 1179{ 1180 struct mlx4_dev *mdev = info->dev; 1181 struct mlx4_priv *priv = mlx4_priv(mdev); 1182 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1183 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1184 int i; 1185 int err = 0; 1186 1187 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1188 mlx4_err(mdev, 1189 "Requested port type for port %d is not supported on this HCA\n", 1190 info->port); 1191 return -EOPNOTSUPP; 1192 } 1193 1194 mlx4_stop_sense(mdev); 1195 mutex_lock(&priv->port_mutex); 1196 info->tmp_type = port_type; 1197 1198 /* Possible type is always the one that was delivered */ 1199 mdev->caps.possible_type[info->port] = info->tmp_type; 1200 1201 for (i = 0; i < mdev->caps.num_ports; i++) { 1202 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1203 mdev->caps.possible_type[i+1]; 1204 if (types[i] == MLX4_PORT_TYPE_AUTO) 1205 types[i] = mdev->caps.port_type[i+1]; 1206 } 1207 1208 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1209 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1210 for (i = 1; i <= mdev->caps.num_ports; i++) { 1211 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1212 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1213 err = -EOPNOTSUPP; 1214 } 1215 } 1216 } 1217 if (err) { 1218 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1219 goto out; 1220 } 1221 1222 mlx4_do_sense_ports(mdev, new_types, types); 1223 1224 err = mlx4_check_port_params(mdev, new_types); 1225 if (err) 1226 goto out; 1227 1228 /* We are about to apply the changes after the configuration 1229 * was verified, no need to remember the temporary types 1230 * any more */ 1231 for (i = 0; i < mdev->caps.num_ports; i++) 1232 priv->port[i + 1].tmp_type = 0; 1233 1234 err = mlx4_change_port_types(mdev, new_types); 1235 1236out: 1237 mlx4_start_sense(mdev); 1238 mutex_unlock(&priv->port_mutex); 1239 1240 return err; 1241} 1242 1243static ssize_t set_port_type(struct device *dev, 1244 struct device_attribute *attr, 1245 const char *buf, size_t count) 1246{ 1247 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1248 port_attr); 1249 struct mlx4_dev *mdev = info->dev; 1250 enum mlx4_port_type port_type; 1251 static DEFINE_MUTEX(set_port_type_mutex); 1252 int err; 1253 1254 mutex_lock(&set_port_type_mutex); 1255 1256 if (!strcmp(buf, "ib\n")) { 1257 port_type = MLX4_PORT_TYPE_IB; 1258 } else if (!strcmp(buf, "eth\n")) { 1259 port_type = MLX4_PORT_TYPE_ETH; 1260 } else if (!strcmp(buf, "auto\n")) { 1261 port_type = MLX4_PORT_TYPE_AUTO; 1262 } else { 1263 mlx4_err(mdev, "%s is not supported port type\n", buf); 1264 err = -EINVAL; 1265 goto err_out; 1266 } 1267 1268 err = __set_port_type(info, port_type); 1269 1270err_out: 1271 mutex_unlock(&set_port_type_mutex); 1272 1273 return err ? err : count; 1274} 1275 1276enum ibta_mtu { 1277 IB_MTU_256 = 1, 1278 IB_MTU_512 = 2, 1279 IB_MTU_1024 = 3, 1280 IB_MTU_2048 = 4, 1281 IB_MTU_4096 = 5 1282}; 1283 1284static inline int int_to_ibta_mtu(int mtu) 1285{ 1286 switch (mtu) { 1287 case 256: return IB_MTU_256; 1288 case 512: return IB_MTU_512; 1289 case 1024: return IB_MTU_1024; 1290 case 2048: return IB_MTU_2048; 1291 case 4096: return IB_MTU_4096; 1292 default: return -1; 1293 } 1294} 1295 1296static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1297{ 1298 switch (mtu) { 1299 case IB_MTU_256: return 256; 1300 case IB_MTU_512: return 512; 1301 case IB_MTU_1024: return 1024; 1302 case IB_MTU_2048: return 2048; 1303 case IB_MTU_4096: return 4096; 1304 default: return -1; 1305 } 1306} 1307 1308static ssize_t show_port_ib_mtu(struct device *dev, 1309 struct device_attribute *attr, 1310 char *buf) 1311{ 1312 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1313 port_mtu_attr); 1314 struct mlx4_dev *mdev = info->dev; 1315 1316 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1317 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1318 1319 sprintf(buf, "%d\n", 1320 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1321 return strlen(buf); 1322} 1323 1324static ssize_t set_port_ib_mtu(struct device *dev, 1325 struct device_attribute *attr, 1326 const char *buf, size_t count) 1327{ 1328 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1329 port_mtu_attr); 1330 struct mlx4_dev *mdev = info->dev; 1331 struct mlx4_priv *priv = mlx4_priv(mdev); 1332 int err, port, mtu, ibta_mtu = -1; 1333 1334 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1335 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1336 return -EINVAL; 1337 } 1338 1339 err = kstrtoint(buf, 0, &mtu); 1340 if (!err) 1341 ibta_mtu = int_to_ibta_mtu(mtu); 1342 1343 if (err || ibta_mtu < 0) { 1344 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1345 return -EINVAL; 1346 } 1347 1348 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1349 1350 mlx4_stop_sense(mdev); 1351 mutex_lock(&priv->port_mutex); 1352 mlx4_unregister_device(mdev); 1353 for (port = 1; port <= mdev->caps.num_ports; port++) { 1354 mlx4_CLOSE_PORT(mdev, port); 1355 err = mlx4_SET_PORT(mdev, port, -1); 1356 if (err) { 1357 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1358 port); 1359 goto err_set_port; 1360 } 1361 } 1362 err = mlx4_register_device(mdev); 1363err_set_port: 1364 mutex_unlock(&priv->port_mutex); 1365 mlx4_start_sense(mdev); 1366 return err ? err : count; 1367} 1368 1369/* bond for multi-function device */ 1370#define MAX_MF_BOND_ALLOWED_SLAVES 63 1371static int mlx4_mf_bond(struct mlx4_dev *dev) 1372{ 1373 int err = 0; 1374 int nvfs; 1375 struct mlx4_slaves_pport slaves_port1; 1376 struct mlx4_slaves_pport slaves_port2; 1377 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX); 1378 1379 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1380 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1381 bitmap_and(slaves_port_1_2, 1382 slaves_port1.slaves, slaves_port2.slaves, 1383 dev->persist->num_vfs + 1); 1384 1385 /* only single port vfs are allowed */ 1386 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) { 1387 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1388 return -EINVAL; 1389 } 1390 1391 /* number of virtual functions is number of total functions minus one 1392 * physical function for each port. 1393 */ 1394 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1395 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1396 1397 /* limit on maximum allowed VFs */ 1398 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1399 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1400 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1401 return -EINVAL; 1402 } 1403 1404 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1405 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1406 return -EINVAL; 1407 } 1408 1409 err = mlx4_bond_mac_table(dev); 1410 if (err) 1411 return err; 1412 err = mlx4_bond_vlan_table(dev); 1413 if (err) 1414 goto err1; 1415 err = mlx4_bond_fs_rules(dev); 1416 if (err) 1417 goto err2; 1418 1419 return 0; 1420err2: 1421 (void)mlx4_unbond_vlan_table(dev); 1422err1: 1423 (void)mlx4_unbond_mac_table(dev); 1424 return err; 1425} 1426 1427static int mlx4_mf_unbond(struct mlx4_dev *dev) 1428{ 1429 int ret, ret1; 1430 1431 ret = mlx4_unbond_fs_rules(dev); 1432 if (ret) 1433 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1434 ret1 = mlx4_unbond_mac_table(dev); 1435 if (ret1) { 1436 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1437 ret = ret1; 1438 } 1439 ret1 = mlx4_unbond_vlan_table(dev); 1440 if (ret1) { 1441 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1442 ret = ret1; 1443 } 1444 return ret; 1445} 1446 1447int mlx4_bond(struct mlx4_dev *dev) 1448{ 1449 int ret = 0; 1450 struct mlx4_priv *priv = mlx4_priv(dev); 1451 1452 mutex_lock(&priv->bond_mutex); 1453 1454 if (!mlx4_is_bonded(dev)) { 1455 ret = mlx4_do_bond(dev, true); 1456 if (ret) 1457 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1458 if (!ret && mlx4_is_master(dev)) { 1459 ret = mlx4_mf_bond(dev); 1460 if (ret) { 1461 mlx4_err(dev, "bond for multifunction failed\n"); 1462 mlx4_do_bond(dev, false); 1463 } 1464 } 1465 } 1466 1467 mutex_unlock(&priv->bond_mutex); 1468 if (!ret) 1469 mlx4_dbg(dev, "Device is bonded\n"); 1470 1471 return ret; 1472} 1473EXPORT_SYMBOL_GPL(mlx4_bond); 1474 1475int mlx4_unbond(struct mlx4_dev *dev) 1476{ 1477 int ret = 0; 1478 struct mlx4_priv *priv = mlx4_priv(dev); 1479 1480 mutex_lock(&priv->bond_mutex); 1481 1482 if (mlx4_is_bonded(dev)) { 1483 int ret2 = 0; 1484 1485 ret = mlx4_do_bond(dev, false); 1486 if (ret) 1487 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1488 if (mlx4_is_master(dev)) 1489 ret2 = mlx4_mf_unbond(dev); 1490 if (ret2) { 1491 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1492 ret = ret2; 1493 } 1494 } 1495 1496 mutex_unlock(&priv->bond_mutex); 1497 if (!ret) 1498 mlx4_dbg(dev, "Device is unbonded\n"); 1499 1500 return ret; 1501} 1502EXPORT_SYMBOL_GPL(mlx4_unbond); 1503 1504 1505int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1506{ 1507 u8 port1 = v2p->port1; 1508 u8 port2 = v2p->port2; 1509 struct mlx4_priv *priv = mlx4_priv(dev); 1510 int err; 1511 1512 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1513 return -EOPNOTSUPP; 1514 1515 mutex_lock(&priv->bond_mutex); 1516 1517 /* zero means keep current mapping for this port */ 1518 if (port1 == 0) 1519 port1 = priv->v2p.port1; 1520 if (port2 == 0) 1521 port2 = priv->v2p.port2; 1522 1523 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1524 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1525 (port1 == 2 && port2 == 1)) { 1526 /* besides boundary checks cross mapping makes 1527 * no sense and therefore not allowed */ 1528 err = -EINVAL; 1529 } else if ((port1 == priv->v2p.port1) && 1530 (port2 == priv->v2p.port2)) { 1531 err = 0; 1532 } else { 1533 err = mlx4_virt2phy_port_map(dev, port1, port2); 1534 if (!err) { 1535 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1536 port1, port2); 1537 priv->v2p.port1 = port1; 1538 priv->v2p.port2 = port2; 1539 } else { 1540 mlx4_err(dev, "Failed to change port mape: %d\n", err); 1541 } 1542 } 1543 1544 mutex_unlock(&priv->bond_mutex); 1545 return err; 1546} 1547EXPORT_SYMBOL_GPL(mlx4_port_map_set); 1548 1549static int mlx4_load_fw(struct mlx4_dev *dev) 1550{ 1551 struct mlx4_priv *priv = mlx4_priv(dev); 1552 int err; 1553 1554 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1555 GFP_HIGHUSER | __GFP_NOWARN, 0); 1556 if (!priv->fw.fw_icm) { 1557 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1558 return -ENOMEM; 1559 } 1560 1561 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1562 if (err) { 1563 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1564 goto err_free; 1565 } 1566 1567 err = mlx4_RUN_FW(dev); 1568 if (err) { 1569 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1570 goto err_unmap_fa; 1571 } 1572 1573 return 0; 1574 1575err_unmap_fa: 1576 mlx4_UNMAP_FA(dev); 1577 1578err_free: 1579 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1580 return err; 1581} 1582 1583static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1584 int cmpt_entry_sz) 1585{ 1586 struct mlx4_priv *priv = mlx4_priv(dev); 1587 int err; 1588 int num_eqs; 1589 1590 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1591 cmpt_base + 1592 ((u64) (MLX4_CMPT_TYPE_QP * 1593 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1594 cmpt_entry_sz, dev->caps.num_qps, 1595 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1596 0, 0); 1597 if (err) 1598 goto err; 1599 1600 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1601 cmpt_base + 1602 ((u64) (MLX4_CMPT_TYPE_SRQ * 1603 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1604 cmpt_entry_sz, dev->caps.num_srqs, 1605 dev->caps.reserved_srqs, 0, 0); 1606 if (err) 1607 goto err_qp; 1608 1609 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1610 cmpt_base + 1611 ((u64) (MLX4_CMPT_TYPE_CQ * 1612 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1613 cmpt_entry_sz, dev->caps.num_cqs, 1614 dev->caps.reserved_cqs, 0, 0); 1615 if (err) 1616 goto err_srq; 1617 1618 num_eqs = dev->phys_caps.num_phys_eqs; 1619 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1620 cmpt_base + 1621 ((u64) (MLX4_CMPT_TYPE_EQ * 1622 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1623 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1624 if (err) 1625 goto err_cq; 1626 1627 return 0; 1628 1629err_cq: 1630 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1631 1632err_srq: 1633 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1634 1635err_qp: 1636 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1637 1638err: 1639 return err; 1640} 1641 1642static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1643 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1644{ 1645 struct mlx4_priv *priv = mlx4_priv(dev); 1646 u64 aux_pages; 1647 int num_eqs; 1648 int err; 1649 1650 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1651 if (err) { 1652 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1653 return err; 1654 } 1655 1656 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1657 (unsigned long long) icm_size >> 10, 1658 (unsigned long long) aux_pages << 2); 1659 1660 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1661 GFP_HIGHUSER | __GFP_NOWARN, 0); 1662 if (!priv->fw.aux_icm) { 1663 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1664 return -ENOMEM; 1665 } 1666 1667 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1668 if (err) { 1669 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1670 goto err_free_aux; 1671 } 1672 1673 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1674 if (err) { 1675 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1676 goto err_unmap_aux; 1677 } 1678 1679 1680 num_eqs = dev->phys_caps.num_phys_eqs; 1681 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1682 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1683 num_eqs, num_eqs, 0, 0); 1684 if (err) { 1685 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1686 goto err_unmap_cmpt; 1687 } 1688 1689 /* 1690 * Reserved MTT entries must be aligned up to a cacheline 1691 * boundary, since the FW will write to them, while the driver 1692 * writes to all other MTT entries. (The variable 1693 * dev->caps.mtt_entry_sz below is really the MTT segment 1694 * size, not the raw entry size) 1695 */ 1696 dev->caps.reserved_mtts = 1697 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1698 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1699 1700 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1701 init_hca->mtt_base, 1702 dev->caps.mtt_entry_sz, 1703 dev->caps.num_mtts, 1704 dev->caps.reserved_mtts, 1, 0); 1705 if (err) { 1706 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1707 goto err_unmap_eq; 1708 } 1709 1710 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1711 init_hca->dmpt_base, 1712 dev_cap->dmpt_entry_sz, 1713 dev->caps.num_mpts, 1714 dev->caps.reserved_mrws, 1, 1); 1715 if (err) { 1716 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1717 goto err_unmap_mtt; 1718 } 1719 1720 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1721 init_hca->qpc_base, 1722 dev_cap->qpc_entry_sz, 1723 dev->caps.num_qps, 1724 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1725 0, 0); 1726 if (err) { 1727 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1728 goto err_unmap_dmpt; 1729 } 1730 1731 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1732 init_hca->auxc_base, 1733 dev_cap->aux_entry_sz, 1734 dev->caps.num_qps, 1735 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1736 0, 0); 1737 if (err) { 1738 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1739 goto err_unmap_qp; 1740 } 1741 1742 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1743 init_hca->altc_base, 1744 dev_cap->altc_entry_sz, 1745 dev->caps.num_qps, 1746 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1747 0, 0); 1748 if (err) { 1749 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1750 goto err_unmap_auxc; 1751 } 1752 1753 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1754 init_hca->rdmarc_base, 1755 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1756 dev->caps.num_qps, 1757 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1758 0, 0); 1759 if (err) { 1760 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1761 goto err_unmap_altc; 1762 } 1763 1764 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1765 init_hca->cqc_base, 1766 dev_cap->cqc_entry_sz, 1767 dev->caps.num_cqs, 1768 dev->caps.reserved_cqs, 0, 0); 1769 if (err) { 1770 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1771 goto err_unmap_rdmarc; 1772 } 1773 1774 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1775 init_hca->srqc_base, 1776 dev_cap->srq_entry_sz, 1777 dev->caps.num_srqs, 1778 dev->caps.reserved_srqs, 0, 0); 1779 if (err) { 1780 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1781 goto err_unmap_cq; 1782 } 1783 1784 /* 1785 * For flow steering device managed mode it is required to use 1786 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1787 * required, but for simplicity just map the whole multicast 1788 * group table now. The table isn't very big and it's a lot 1789 * easier than trying to track ref counts. 1790 */ 1791 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1792 init_hca->mc_base, 1793 mlx4_get_mgm_entry_size(dev), 1794 dev->caps.num_mgms + dev->caps.num_amgms, 1795 dev->caps.num_mgms + dev->caps.num_amgms, 1796 0, 0); 1797 if (err) { 1798 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1799 goto err_unmap_srq; 1800 } 1801 1802 return 0; 1803 1804err_unmap_srq: 1805 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1806 1807err_unmap_cq: 1808 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1809 1810err_unmap_rdmarc: 1811 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1812 1813err_unmap_altc: 1814 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1815 1816err_unmap_auxc: 1817 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1818 1819err_unmap_qp: 1820 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1821 1822err_unmap_dmpt: 1823 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1824 1825err_unmap_mtt: 1826 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1827 1828err_unmap_eq: 1829 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1830 1831err_unmap_cmpt: 1832 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1833 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1834 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1836 1837err_unmap_aux: 1838 mlx4_UNMAP_ICM_AUX(dev); 1839 1840err_free_aux: 1841 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1842 1843 return err; 1844} 1845 1846static void mlx4_free_icms(struct mlx4_dev *dev) 1847{ 1848 struct mlx4_priv *priv = mlx4_priv(dev); 1849 1850 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1851 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1852 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1853 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1854 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1855 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1856 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1857 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1858 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1859 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1860 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1861 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1862 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1863 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1864 1865 mlx4_UNMAP_ICM_AUX(dev); 1866 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1867} 1868 1869static void mlx4_slave_exit(struct mlx4_dev *dev) 1870{ 1871 struct mlx4_priv *priv = mlx4_priv(dev); 1872 1873 mutex_lock(&priv->cmd.slave_cmd_mutex); 1874 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1875 MLX4_COMM_TIME)) 1876 mlx4_warn(dev, "Failed to close slave function\n"); 1877 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1878} 1879 1880static int map_bf_area(struct mlx4_dev *dev) 1881{ 1882 struct mlx4_priv *priv = mlx4_priv(dev); 1883 resource_size_t bf_start; 1884 resource_size_t bf_len; 1885 int err = 0; 1886 1887 if (!dev->caps.bf_reg_size) 1888 return -ENXIO; 1889 1890 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1891 (dev->caps.num_uars << PAGE_SHIFT); 1892 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1893 (dev->caps.num_uars << PAGE_SHIFT); 1894 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1895 if (!priv->bf_mapping) 1896 err = -ENOMEM; 1897 1898 return err; 1899} 1900 1901static void unmap_bf_area(struct mlx4_dev *dev) 1902{ 1903 if (mlx4_priv(dev)->bf_mapping) 1904 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1905} 1906 1907u64 mlx4_read_clock(struct mlx4_dev *dev) 1908{ 1909 u32 clockhi, clocklo, clockhi1; 1910 u64 cycles; 1911 int i; 1912 struct mlx4_priv *priv = mlx4_priv(dev); 1913 1914 for (i = 0; i < 10; i++) { 1915 clockhi = swab32(readl(priv->clock_mapping)); 1916 clocklo = swab32(readl(priv->clock_mapping + 4)); 1917 clockhi1 = swab32(readl(priv->clock_mapping)); 1918 if (clockhi == clockhi1) 1919 break; 1920 } 1921 1922 cycles = (u64) clockhi << 32 | (u64) clocklo; 1923 1924 return cycles; 1925} 1926EXPORT_SYMBOL_GPL(mlx4_read_clock); 1927 1928 1929static int map_internal_clock(struct mlx4_dev *dev) 1930{ 1931 struct mlx4_priv *priv = mlx4_priv(dev); 1932 1933 priv->clock_mapping = 1934 ioremap(pci_resource_start(dev->persist->pdev, 1935 priv->fw.clock_bar) + 1936 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1937 1938 if (!priv->clock_mapping) 1939 return -ENOMEM; 1940 1941 return 0; 1942} 1943 1944int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1945 struct mlx4_clock_params *params) 1946{ 1947 struct mlx4_priv *priv = mlx4_priv(dev); 1948 1949 if (mlx4_is_slave(dev)) 1950 return -EOPNOTSUPP; 1951 1952 if (!dev->caps.map_clock_to_user) { 1953 mlx4_dbg(dev, "Map clock to user is not supported.\n"); 1954 return -EOPNOTSUPP; 1955 } 1956 1957 if (!params) 1958 return -EINVAL; 1959 1960 params->bar = priv->fw.clock_bar; 1961 params->offset = priv->fw.clock_offset; 1962 params->size = MLX4_CLOCK_SIZE; 1963 1964 return 0; 1965} 1966EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1967 1968static void unmap_internal_clock(struct mlx4_dev *dev) 1969{ 1970 struct mlx4_priv *priv = mlx4_priv(dev); 1971 1972 if (priv->clock_mapping) 1973 iounmap(priv->clock_mapping); 1974} 1975 1976static void mlx4_close_hca(struct mlx4_dev *dev) 1977{ 1978 unmap_internal_clock(dev); 1979 unmap_bf_area(dev); 1980 if (mlx4_is_slave(dev)) 1981 mlx4_slave_exit(dev); 1982 else { 1983 mlx4_CLOSE_HCA(dev, 0); 1984 mlx4_free_icms(dev); 1985 } 1986} 1987 1988static void mlx4_close_fw(struct mlx4_dev *dev) 1989{ 1990 if (!mlx4_is_slave(dev)) { 1991 mlx4_UNMAP_FA(dev); 1992 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1993 } 1994} 1995 1996static int mlx4_comm_check_offline(struct mlx4_dev *dev) 1997{ 1998#define COMM_CHAN_OFFLINE_OFFSET 0x09 1999 2000 u32 comm_flags; 2001 u32 offline_bit; 2002 unsigned long end; 2003 struct mlx4_priv *priv = mlx4_priv(dev); 2004 2005 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2006 while (time_before(jiffies, end)) { 2007 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2008 MLX4_COMM_CHAN_FLAGS)); 2009 offline_bit = (comm_flags & 2010 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2011 if (!offline_bit) 2012 return 0; 2013 2014 /* If device removal has been requested, 2015 * do not continue retrying. 2016 */ 2017 if (dev->persist->interface_state & 2018 MLX4_INTERFACE_STATE_NOWAIT) 2019 break; 2020 2021 /* There are cases as part of AER/Reset flow that PF needs 2022 * around 100 msec to load. We therefore sleep for 100 msec 2023 * to allow other tasks to make use of that CPU during this 2024 * time interval. 2025 */ 2026 msleep(100); 2027 } 2028 mlx4_err(dev, "Communication channel is offline.\n"); 2029 return -EIO; 2030} 2031 2032static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2033{ 2034#define COMM_CHAN_RST_OFFSET 0x1e 2035 2036 struct mlx4_priv *priv = mlx4_priv(dev); 2037 u32 comm_rst; 2038 u32 comm_caps; 2039 2040 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2041 MLX4_COMM_CHAN_CAPS)); 2042 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2043 2044 if (comm_rst) 2045 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2046} 2047 2048static int mlx4_init_slave(struct mlx4_dev *dev) 2049{ 2050 struct mlx4_priv *priv = mlx4_priv(dev); 2051 u64 dma = (u64) priv->mfunc.vhcr_dma; 2052 int ret_from_reset = 0; 2053 u32 slave_read; 2054 u32 cmd_channel_ver; 2055 2056 if (atomic_read(&pf_loading)) { 2057 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2058 return -EPROBE_DEFER; 2059 } 2060 2061 mutex_lock(&priv->cmd.slave_cmd_mutex); 2062 priv->cmd.max_cmds = 1; 2063 if (mlx4_comm_check_offline(dev)) { 2064 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2065 goto err_offline; 2066 } 2067 2068 mlx4_reset_vf_support(dev); 2069 mlx4_warn(dev, "Sending reset\n"); 2070 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2071 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2072 /* if we are in the middle of flr the slave will try 2073 * NUM_OF_RESET_RETRIES times before leaving.*/ 2074 if (ret_from_reset) { 2075 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2076 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2077 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2078 return -EPROBE_DEFER; 2079 } else 2080 goto err; 2081 } 2082 2083 /* check the driver version - the slave I/F revision 2084 * must match the master's */ 2085 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2086 cmd_channel_ver = mlx4_comm_get_version(); 2087 2088 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2089 MLX4_COMM_GET_IF_REV(slave_read)) { 2090 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2091 goto err; 2092 } 2093 2094 mlx4_warn(dev, "Sending vhcr0\n"); 2095 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2096 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2097 goto err; 2098 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2099 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2100 goto err; 2101 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2102 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2103 goto err; 2104 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2105 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2106 goto err; 2107 2108 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2109 return 0; 2110 2111err: 2112 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2113err_offline: 2114 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2115 return -EIO; 2116} 2117 2118static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2119{ 2120 int i; 2121 2122 for (i = 1; i <= dev->caps.num_ports; i++) { 2123 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2124 dev->caps.gid_table_len[i] = 2125 mlx4_get_slave_num_gids(dev, 0, i); 2126 else 2127 dev->caps.gid_table_len[i] = 1; 2128 dev->caps.pkey_table_len[i] = 2129 dev->phys_caps.pkey_phys_table_len[i] - 1; 2130 } 2131} 2132 2133static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2134{ 2135 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2136 2137 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2138 i++) { 2139 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2140 break; 2141 } 2142 2143 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2144} 2145 2146static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2147{ 2148 switch (dmfs_high_steer_mode) { 2149 case MLX4_STEERING_DMFS_A0_DEFAULT: 2150 return "default performance"; 2151 2152 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2153 return "dynamic hybrid mode"; 2154 2155 case MLX4_STEERING_DMFS_A0_STATIC: 2156 return "performance optimized for limited rule configuration (static)"; 2157 2158 case MLX4_STEERING_DMFS_A0_DISABLE: 2159 return "disabled performance optimized steering"; 2160 2161 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2162 return "performance optimized steering not supported"; 2163 2164 default: 2165 return "Unrecognized mode"; 2166 } 2167} 2168 2169#define MLX4_DMFS_A0_STEERING (1UL << 2) 2170 2171static void choose_steering_mode(struct mlx4_dev *dev, 2172 struct mlx4_dev_cap *dev_cap) 2173{ 2174 if (mlx4_log_num_mgm_entry_size <= 0) { 2175 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2176 if (dev->caps.dmfs_high_steer_mode == 2177 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2178 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2179 else 2180 dev->caps.dmfs_high_steer_mode = 2181 MLX4_STEERING_DMFS_A0_STATIC; 2182 } 2183 } 2184 2185 if (mlx4_log_num_mgm_entry_size <= 0 && 2186 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2187 (!mlx4_is_mfunc(dev) || 2188 (dev_cap->fs_max_num_qp_per_entry >= 2189 (dev->persist->num_vfs + 1))) && 2190 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2191 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2192 dev->oper_log_mgm_entry_size = 2193 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2194 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2195 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2196 dev->caps.fs_log_max_ucast_qp_range_size = 2197 dev_cap->fs_log_max_ucast_qp_range_size; 2198 } else { 2199 if (dev->caps.dmfs_high_steer_mode != 2200 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2201 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2202 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2203 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2204 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2205 else { 2206 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2207 2208 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2209 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2210 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2211 } 2212 dev->oper_log_mgm_entry_size = 2213 mlx4_log_num_mgm_entry_size > 0 ? 2214 mlx4_log_num_mgm_entry_size : 2215 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2216 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2217 } 2218 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2219 mlx4_steering_mode_str(dev->caps.steering_mode), 2220 dev->oper_log_mgm_entry_size, 2221 mlx4_log_num_mgm_entry_size); 2222} 2223 2224static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2225 struct mlx4_dev_cap *dev_cap) 2226{ 2227 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2228 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2229 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2230 else 2231 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2232 2233 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2234 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2235} 2236 2237static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2238{ 2239 int i; 2240 struct mlx4_port_cap port_cap; 2241 2242 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2243 return -EINVAL; 2244 2245 for (i = 1; i <= dev->caps.num_ports; i++) { 2246 if (mlx4_dev_port(dev, i, &port_cap)) { 2247 mlx4_err(dev, 2248 "QUERY_DEV_CAP command failed, can't verify DMFS high rate steering.\n"); 2249 } else if ((dev->caps.dmfs_high_steer_mode != 2250 MLX4_STEERING_DMFS_A0_DEFAULT) && 2251 (port_cap.dmfs_optimized_state == 2252 !!(dev->caps.dmfs_high_steer_mode == 2253 MLX4_STEERING_DMFS_A0_DISABLE))) { 2254 mlx4_err(dev, 2255 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2256 dmfs_high_rate_steering_mode_str( 2257 dev->caps.dmfs_high_steer_mode), 2258 (port_cap.dmfs_optimized_state ? 2259 "enabled" : "disabled")); 2260 } 2261 } 2262 2263 return 0; 2264} 2265 2266static int mlx4_init_fw(struct mlx4_dev *dev) 2267{ 2268 struct mlx4_mod_stat_cfg mlx4_cfg; 2269 int err = 0; 2270 2271 if (!mlx4_is_slave(dev)) { 2272 err = mlx4_QUERY_FW(dev); 2273 if (err) { 2274 if (err == -EACCES) 2275 mlx4_info(dev, "non-primary physical function, skipping\n"); 2276 else 2277 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2278 return err; 2279 } 2280 2281 err = mlx4_load_fw(dev); 2282 if (err) { 2283 mlx4_err(dev, "Failed to start FW, aborting\n"); 2284 return err; 2285 } 2286 2287 mlx4_cfg.log_pg_sz_m = 1; 2288 mlx4_cfg.log_pg_sz = 0; 2289 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2290 if (err) 2291 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2292 } 2293 2294 return err; 2295} 2296 2297static int mlx4_init_hca(struct mlx4_dev *dev) 2298{ 2299 struct mlx4_priv *priv = mlx4_priv(dev); 2300 struct mlx4_init_hca_param *init_hca = NULL; 2301 struct mlx4_dev_cap *dev_cap = NULL; 2302 struct mlx4_adapter adapter; 2303 struct mlx4_profile profile; 2304 u64 icm_size; 2305 struct mlx4_config_dev_params params; 2306 int err; 2307 2308 if (!mlx4_is_slave(dev)) { 2309 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2310 init_hca = kzalloc(sizeof(*init_hca), GFP_KERNEL); 2311 2312 if (!dev_cap || !init_hca) { 2313 err = -ENOMEM; 2314 goto out_free; 2315 } 2316 2317 err = mlx4_dev_cap(dev, dev_cap); 2318 if (err) { 2319 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2320 goto out_free; 2321 } 2322 2323 choose_steering_mode(dev, dev_cap); 2324 choose_tunnel_offload_mode(dev, dev_cap); 2325 2326 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2327 mlx4_is_master(dev)) 2328 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2329 2330 err = mlx4_get_phys_port_id(dev); 2331 if (err) 2332 mlx4_err(dev, "Fail to get physical port id\n"); 2333 2334 if (mlx4_is_master(dev)) 2335 mlx4_parav_master_pf_caps(dev); 2336 2337 if (mlx4_low_memory_profile()) { 2338 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2339 profile = low_mem_profile; 2340 } else { 2341 profile = default_profile; 2342 } 2343 if (dev->caps.steering_mode == 2344 MLX4_STEERING_MODE_DEVICE_MANAGED) 2345 profile.num_mcg = MLX4_FS_NUM_MCG; 2346 2347 icm_size = mlx4_make_profile(dev, &profile, dev_cap, 2348 init_hca); 2349 if ((long long) icm_size < 0) { 2350 err = icm_size; 2351 goto out_free; 2352 } 2353 2354 if (enable_4k_uar || !dev->persist->num_vfs) { 2355 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) + 2356 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2357 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2358 } else { 2359 init_hca->log_uar_sz = ilog2(dev->caps.num_uars); 2360 init_hca->uar_page_sz = PAGE_SHIFT - 12; 2361 } 2362 2363 init_hca->mw_enabled = 0; 2364 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2365 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2366 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2367 2368 err = mlx4_init_icm(dev, dev_cap, init_hca, icm_size); 2369 if (err) 2370 goto out_free; 2371 2372 err = mlx4_INIT_HCA(dev, init_hca); 2373 if (err) { 2374 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2375 goto err_free_icm; 2376 } 2377 2378 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2379 err = mlx4_query_func(dev, dev_cap); 2380 if (err < 0) { 2381 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2382 goto err_close; 2383 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2384 dev->caps.num_eqs = dev_cap->max_eqs; 2385 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 2386 dev->caps.reserved_uars = dev_cap->reserved_uars; 2387 } 2388 } 2389 2390 /* 2391 * If TS is supported by FW 2392 * read HCA frequency by QUERY_HCA command 2393 */ 2394 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2395 err = mlx4_QUERY_HCA(dev, init_hca); 2396 if (err) { 2397 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2398 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2399 } else { 2400 dev->caps.hca_core_clock = 2401 init_hca->hca_core_clock; 2402 } 2403 2404 /* In case we got HCA frequency 0 - disable timestamping 2405 * to avoid dividing by zero 2406 */ 2407 if (!dev->caps.hca_core_clock) { 2408 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2409 mlx4_err(dev, 2410 "HCA frequency is 0 - timestamping is not supported\n"); 2411 } else if (map_internal_clock(dev)) { 2412 /* 2413 * Map internal clock, 2414 * in case of failure disable timestamping 2415 */ 2416 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2417 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2418 } 2419 } 2420 2421 if (dev->caps.dmfs_high_steer_mode != 2422 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2423 if (mlx4_validate_optimized_steering(dev)) 2424 mlx4_warn(dev, "Optimized steering validation failed\n"); 2425 2426 if (dev->caps.dmfs_high_steer_mode == 2427 MLX4_STEERING_DMFS_A0_DISABLE) { 2428 dev->caps.dmfs_high_rate_qpn_base = 2429 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2430 dev->caps.dmfs_high_rate_qpn_range = 2431 MLX4_A0_STEERING_TABLE_SIZE; 2432 } 2433 2434 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2435 dmfs_high_rate_steering_mode_str( 2436 dev->caps.dmfs_high_steer_mode)); 2437 } 2438 } else { 2439 err = mlx4_init_slave(dev); 2440 if (err) { 2441 if (err != -EPROBE_DEFER) 2442 mlx4_err(dev, "Failed to initialize slave\n"); 2443 return err; 2444 } 2445 2446 err = mlx4_slave_cap(dev); 2447 if (err) { 2448 mlx4_err(dev, "Failed to obtain slave caps\n"); 2449 goto err_close; 2450 } 2451 } 2452 2453 if (map_bf_area(dev)) 2454 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2455 2456 /*Only the master set the ports, all the rest got it from it.*/ 2457 if (!mlx4_is_slave(dev)) 2458 mlx4_set_port_mask(dev); 2459 2460 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2461 if (err) { 2462 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2463 goto unmap_bf; 2464 } 2465 2466 /* Query CONFIG_DEV parameters */ 2467 err = mlx4_config_dev_retrieval(dev, ¶ms); 2468 if (err && err != -EOPNOTSUPP) { 2469 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2470 } else if (!err) { 2471 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2472 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2473 } 2474 priv->eq_table.inta_pin = adapter.inta_pin; 2475 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2476 2477 err = 0; 2478 goto out_free; 2479 2480unmap_bf: 2481 unmap_internal_clock(dev); 2482 unmap_bf_area(dev); 2483 2484 if (mlx4_is_slave(dev)) 2485 mlx4_slave_destroy_special_qp_cap(dev); 2486 2487err_close: 2488 if (mlx4_is_slave(dev)) 2489 mlx4_slave_exit(dev); 2490 else 2491 mlx4_CLOSE_HCA(dev, 0); 2492 2493err_free_icm: 2494 if (!mlx4_is_slave(dev)) 2495 mlx4_free_icms(dev); 2496 2497out_free: 2498 kfree(dev_cap); 2499 kfree(init_hca); 2500 2501 return err; 2502} 2503 2504static int mlx4_init_counters_table(struct mlx4_dev *dev) 2505{ 2506 struct mlx4_priv *priv = mlx4_priv(dev); 2507 int nent_pow2; 2508 2509 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2510 return -ENOENT; 2511 2512 if (!dev->caps.max_counters) 2513 return -ENOSPC; 2514 2515 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2516 /* reserve last counter index for sink counter */ 2517 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2518 nent_pow2 - 1, 0, 2519 nent_pow2 - dev->caps.max_counters + 1); 2520} 2521 2522static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2523{ 2524 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2525 return; 2526 2527 if (!dev->caps.max_counters) 2528 return; 2529 2530 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2531} 2532 2533static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2534{ 2535 struct mlx4_priv *priv = mlx4_priv(dev); 2536 int port; 2537 2538 for (port = 0; port < dev->caps.num_ports; port++) 2539 if (priv->def_counter[port] != -1) 2540 mlx4_counter_free(dev, priv->def_counter[port]); 2541} 2542 2543static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2544{ 2545 struct mlx4_priv *priv = mlx4_priv(dev); 2546 int port, err = 0; 2547 u32 idx; 2548 2549 for (port = 0; port < dev->caps.num_ports; port++) 2550 priv->def_counter[port] = -1; 2551 2552 for (port = 0; port < dev->caps.num_ports; port++) { 2553 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2554 2555 if (!err || err == -ENOSPC) { 2556 priv->def_counter[port] = idx; 2557 err = 0; 2558 } else if (err == -ENOENT) { 2559 err = 0; 2560 continue; 2561 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2562 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2563 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2564 MLX4_SINK_COUNTER_INDEX(dev)); 2565 err = 0; 2566 } else { 2567 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2568 __func__, port + 1, err); 2569 mlx4_cleanup_default_counters(dev); 2570 return err; 2571 } 2572 2573 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2574 __func__, priv->def_counter[port], port + 1); 2575 } 2576 2577 return err; 2578} 2579 2580int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2581{ 2582 struct mlx4_priv *priv = mlx4_priv(dev); 2583 2584 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2585 return -ENOENT; 2586 2587 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2588 if (*idx == -1) { 2589 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2590 return -ENOSPC; 2591 } 2592 2593 return 0; 2594} 2595 2596int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2597{ 2598 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2599 u64 out_param; 2600 int err; 2601 2602 if (mlx4_is_mfunc(dev)) { 2603 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2604 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2605 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2606 if (!err) 2607 *idx = get_param_l(&out_param); 2608 if (WARN_ON(err == -ENOSPC)) 2609 err = -EINVAL; 2610 return err; 2611 } 2612 return __mlx4_counter_alloc(dev, idx); 2613} 2614EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2615 2616static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2617 u8 counter_index) 2618{ 2619 struct mlx4_cmd_mailbox *if_stat_mailbox; 2620 int err; 2621 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2622 2623 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2624 if (IS_ERR(if_stat_mailbox)) 2625 return PTR_ERR(if_stat_mailbox); 2626 2627 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2628 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2629 MLX4_CMD_NATIVE); 2630 2631 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2632 return err; 2633} 2634 2635void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2636{ 2637 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2638 return; 2639 2640 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2641 return; 2642 2643 __mlx4_clear_if_stat(dev, idx); 2644 2645 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2646 return; 2647} 2648 2649void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2650{ 2651 u64 in_param = 0; 2652 2653 if (mlx4_is_mfunc(dev)) { 2654 set_param_l(&in_param, idx); 2655 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2656 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2657 MLX4_CMD_WRAPPED); 2658 return; 2659 } 2660 __mlx4_counter_free(dev, idx); 2661} 2662EXPORT_SYMBOL_GPL(mlx4_counter_free); 2663 2664int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2665{ 2666 struct mlx4_priv *priv = mlx4_priv(dev); 2667 2668 return priv->def_counter[port - 1]; 2669} 2670EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2671 2672void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2673{ 2674 struct mlx4_priv *priv = mlx4_priv(dev); 2675 2676 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2677} 2678EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2679 2680__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2681{ 2682 struct mlx4_priv *priv = mlx4_priv(dev); 2683 2684 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2685} 2686EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2687 2688void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2689{ 2690 struct mlx4_priv *priv = mlx4_priv(dev); 2691 __be64 guid; 2692 2693 /* hw GUID */ 2694 if (entry == 0) 2695 return; 2696 2697 get_random_bytes((char *)&guid, sizeof(guid)); 2698 guid &= ~(cpu_to_be64(1ULL << 56)); 2699 guid |= cpu_to_be64(1ULL << 57); 2700 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2701} 2702 2703static int mlx4_setup_hca(struct mlx4_dev *dev) 2704{ 2705 struct mlx4_priv *priv = mlx4_priv(dev); 2706 int err; 2707 int port; 2708 __be32 ib_port_default_caps; 2709 2710 err = mlx4_init_uar_table(dev); 2711 if (err) { 2712 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2713 return err; 2714 } 2715 2716 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2717 if (err) { 2718 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2719 goto err_uar_table_free; 2720 } 2721 2722 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2723 if (!priv->kar) { 2724 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2725 err = -ENOMEM; 2726 goto err_uar_free; 2727 } 2728 2729 err = mlx4_init_pd_table(dev); 2730 if (err) { 2731 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2732 goto err_kar_unmap; 2733 } 2734 2735 err = mlx4_init_xrcd_table(dev); 2736 if (err) { 2737 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2738 goto err_pd_table_free; 2739 } 2740 2741 err = mlx4_init_mr_table(dev); 2742 if (err) { 2743 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2744 goto err_xrcd_table_free; 2745 } 2746 2747 if (!mlx4_is_slave(dev)) { 2748 err = mlx4_init_mcg_table(dev); 2749 if (err) { 2750 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2751 goto err_mr_table_free; 2752 } 2753 err = mlx4_config_mad_demux(dev); 2754 if (err) { 2755 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2756 goto err_mcg_table_free; 2757 } 2758 } 2759 2760 err = mlx4_init_eq_table(dev); 2761 if (err) { 2762 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2763 goto err_mcg_table_free; 2764 } 2765 2766 err = mlx4_cmd_use_events(dev); 2767 if (err) { 2768 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2769 goto err_eq_table_free; 2770 } 2771 2772 err = mlx4_NOP(dev); 2773 if (err) { 2774 if (dev->flags & MLX4_FLAG_MSI_X) { 2775 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2776 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2777 mlx4_warn(dev, "Trying again without MSI-X\n"); 2778 } else { 2779 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2780 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2781 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2782 } 2783 2784 goto err_cmd_poll; 2785 } 2786 2787 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2788 2789 err = mlx4_init_cq_table(dev); 2790 if (err) { 2791 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2792 goto err_cmd_poll; 2793 } 2794 2795 err = mlx4_init_srq_table(dev); 2796 if (err) { 2797 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2798 goto err_cq_table_free; 2799 } 2800 2801 err = mlx4_init_qp_table(dev); 2802 if (err) { 2803 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2804 goto err_srq_table_free; 2805 } 2806 2807 if (!mlx4_is_slave(dev)) { 2808 err = mlx4_init_counters_table(dev); 2809 if (err && err != -ENOENT) { 2810 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2811 goto err_qp_table_free; 2812 } 2813 } 2814 2815 err = mlx4_allocate_default_counters(dev); 2816 if (err) { 2817 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2818 goto err_counters_table_free; 2819 } 2820 2821 if (!mlx4_is_slave(dev)) { 2822 for (port = 1; port <= dev->caps.num_ports; port++) { 2823 ib_port_default_caps = 0; 2824 err = mlx4_get_port_ib_caps(dev, port, 2825 &ib_port_default_caps); 2826 if (err) 2827 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2828 port, err); 2829 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2830 2831 /* initialize per-slave default ib port capabilities */ 2832 if (mlx4_is_master(dev)) { 2833 int i; 2834 for (i = 0; i < dev->num_slaves; i++) { 2835 if (i == mlx4_master_func_num(dev)) 2836 continue; 2837 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2838 ib_port_default_caps; 2839 } 2840 } 2841 2842 if (mlx4_is_mfunc(dev)) 2843 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2844 else 2845 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2846 2847 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2848 dev->caps.pkey_table_len[port] : -1); 2849 if (err) { 2850 mlx4_err(dev, "Failed to set port %d, aborting\n", 2851 port); 2852 goto err_default_countes_free; 2853 } 2854 } 2855 } 2856 2857 return 0; 2858 2859err_default_countes_free: 2860 mlx4_cleanup_default_counters(dev); 2861 2862err_counters_table_free: 2863 if (!mlx4_is_slave(dev)) 2864 mlx4_cleanup_counters_table(dev); 2865 2866err_qp_table_free: 2867 mlx4_cleanup_qp_table(dev); 2868 2869err_srq_table_free: 2870 mlx4_cleanup_srq_table(dev); 2871 2872err_cq_table_free: 2873 mlx4_cleanup_cq_table(dev); 2874 2875err_cmd_poll: 2876 mlx4_cmd_use_polling(dev); 2877 2878err_eq_table_free: 2879 mlx4_cleanup_eq_table(dev); 2880 2881err_mcg_table_free: 2882 if (!mlx4_is_slave(dev)) 2883 mlx4_cleanup_mcg_table(dev); 2884 2885err_mr_table_free: 2886 mlx4_cleanup_mr_table(dev); 2887 2888err_xrcd_table_free: 2889 mlx4_cleanup_xrcd_table(dev); 2890 2891err_pd_table_free: 2892 mlx4_cleanup_pd_table(dev); 2893 2894err_kar_unmap: 2895 iounmap(priv->kar); 2896 2897err_uar_free: 2898 mlx4_uar_free(dev, &priv->driver_uar); 2899 2900err_uar_table_free: 2901 mlx4_cleanup_uar_table(dev); 2902 return err; 2903} 2904 2905static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2906{ 2907 int requested_cpu = 0; 2908 struct mlx4_priv *priv = mlx4_priv(dev); 2909 struct mlx4_eq *eq; 2910 int off = 0; 2911 int i; 2912 2913 if (eqn > dev->caps.num_comp_vectors) 2914 return -EINVAL; 2915 2916 for (i = 1; i < port; i++) 2917 off += mlx4_get_eqs_per_port(dev, i); 2918 2919 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2920 2921 /* Meaning EQs are shared, and this call comes from the second port */ 2922 if (requested_cpu < 0) 2923 return 0; 2924 2925 eq = &priv->eq_table.eq[eqn]; 2926 2927 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2928 return -ENOMEM; 2929 2930 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2931 2932 return 0; 2933} 2934 2935static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2936{ 2937 struct mlx4_priv *priv = mlx4_priv(dev); 2938 struct msix_entry *entries; 2939 int i; 2940 int port = 0; 2941 2942 if (msi_x) { 2943 int nreq = min3(dev->caps.num_ports * 2944 (int)num_online_cpus() + 1, 2945 dev->caps.num_eqs - dev->caps.reserved_eqs, 2946 MAX_MSIX); 2947 2948 if (msi_x > 1) 2949 nreq = min_t(int, nreq, msi_x); 2950 2951 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2952 if (!entries) 2953 goto no_msi; 2954 2955 for (i = 0; i < nreq; ++i) 2956 entries[i].entry = i; 2957 2958 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2959 nreq); 2960 2961 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2962 kfree(entries); 2963 goto no_msi; 2964 } 2965 /* 1 is reserved for events (asyncrounous EQ) */ 2966 dev->caps.num_comp_vectors = nreq - 1; 2967 2968 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2969 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2970 dev->caps.num_ports); 2971 2972 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 2973 if (i == MLX4_EQ_ASYNC) 2974 continue; 2975 2976 priv->eq_table.eq[i].irq = 2977 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 2978 2979 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 2980 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 2981 dev->caps.num_ports); 2982 /* We don't set affinity hint when there 2983 * aren't enough EQs 2984 */ 2985 } else { 2986 set_bit(port, 2987 priv->eq_table.eq[i].actv_ports.ports); 2988 if (mlx4_init_affinity_hint(dev, port + 1, i)) 2989 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 2990 i); 2991 } 2992 /* We divide the Eqs evenly between the two ports. 2993 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 2994 * refers to the number of Eqs per port 2995 * (i.e eqs_per_port). Theoretically, we would like to 2996 * write something like (i + 1) % eqs_per_port == 0. 2997 * However, since there's an asynchronous Eq, we have 2998 * to skip over it by comparing this condition to 2999 * !!((i + 1) > MLX4_EQ_ASYNC). 3000 */ 3001 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 3002 ((i + 1) % 3003 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 3004 !!((i + 1) > MLX4_EQ_ASYNC)) 3005 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 3006 * everything is shared anyway. 3007 */ 3008 port++; 3009 } 3010 3011 dev->flags |= MLX4_FLAG_MSI_X; 3012 3013 kfree(entries); 3014 return; 3015 } 3016 3017no_msi: 3018 dev->caps.num_comp_vectors = 1; 3019 3020 BUG_ON(MLX4_EQ_ASYNC >= 2); 3021 for (i = 0; i < 2; ++i) { 3022 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3023 if (i != MLX4_EQ_ASYNC) { 3024 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3025 dev->caps.num_ports); 3026 } 3027 } 3028} 3029 3030static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3031{ 3032 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3033 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3034 int err; 3035 3036 err = devlink_port_register(devlink, &info->devlink_port, port); 3037 if (err) 3038 return err; 3039 3040 /* Ethernet and IB drivers will normally set the port type, 3041 * but if they are not built set the type now to prevent 3042 * devlink_port_type_warn() from firing. 3043 */ 3044 if (!IS_ENABLED(CONFIG_MLX4_EN) && 3045 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 3046 devlink_port_type_eth_set(&info->devlink_port, NULL); 3047 else if (!IS_ENABLED(CONFIG_MLX4_INFINIBAND) && 3048 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 3049 devlink_port_type_ib_set(&info->devlink_port, NULL); 3050 3051 info->dev = dev; 3052 info->port = port; 3053 if (!mlx4_is_slave(dev)) { 3054 mlx4_init_mac_table(dev, &info->mac_table); 3055 mlx4_init_vlan_table(dev, &info->vlan_table); 3056 mlx4_init_roce_gid_table(dev, &info->gid_table); 3057 info->base_qpn = mlx4_get_base_qpn(dev, port); 3058 } 3059 3060 sprintf(info->dev_name, "mlx4_port%d", port); 3061 info->port_attr.attr.name = info->dev_name; 3062 if (mlx4_is_mfunc(dev)) { 3063 info->port_attr.attr.mode = 0444; 3064 } else { 3065 info->port_attr.attr.mode = 0644; 3066 info->port_attr.store = set_port_type; 3067 } 3068 info->port_attr.show = show_port_type; 3069 sysfs_attr_init(&info->port_attr.attr); 3070 3071 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3072 if (err) { 3073 mlx4_err(dev, "Failed to create file for port %d\n", port); 3074 devlink_port_unregister(&info->devlink_port); 3075 info->port = -1; 3076 return err; 3077 } 3078 3079 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3080 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3081 if (mlx4_is_mfunc(dev)) { 3082 info->port_mtu_attr.attr.mode = 0444; 3083 } else { 3084 info->port_mtu_attr.attr.mode = 0644; 3085 info->port_mtu_attr.store = set_port_ib_mtu; 3086 } 3087 info->port_mtu_attr.show = show_port_ib_mtu; 3088 sysfs_attr_init(&info->port_mtu_attr.attr); 3089 3090 err = device_create_file(&dev->persist->pdev->dev, 3091 &info->port_mtu_attr); 3092 if (err) { 3093 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3094 device_remove_file(&info->dev->persist->pdev->dev, 3095 &info->port_attr); 3096 devlink_port_unregister(&info->devlink_port); 3097 info->port = -1; 3098 return err; 3099 } 3100 3101 return 0; 3102} 3103 3104static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3105{ 3106 if (info->port < 0) 3107 return; 3108 3109 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3110 device_remove_file(&info->dev->persist->pdev->dev, 3111 &info->port_mtu_attr); 3112 devlink_port_unregister(&info->devlink_port); 3113 3114#ifdef CONFIG_RFS_ACCEL 3115 free_irq_cpu_rmap(info->rmap); 3116 info->rmap = NULL; 3117#endif 3118} 3119 3120static int mlx4_init_steering(struct mlx4_dev *dev) 3121{ 3122 struct mlx4_priv *priv = mlx4_priv(dev); 3123 int num_entries = dev->caps.num_ports; 3124 int i, j; 3125 3126 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3127 GFP_KERNEL); 3128 if (!priv->steer) 3129 return -ENOMEM; 3130 3131 for (i = 0; i < num_entries; i++) 3132 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3133 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3134 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3135 } 3136 return 0; 3137} 3138 3139static void mlx4_clear_steering(struct mlx4_dev *dev) 3140{ 3141 struct mlx4_priv *priv = mlx4_priv(dev); 3142 struct mlx4_steer_index *entry, *tmp_entry; 3143 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3144 int num_entries = dev->caps.num_ports; 3145 int i, j; 3146 3147 for (i = 0; i < num_entries; i++) { 3148 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3149 list_for_each_entry_safe(pqp, tmp_pqp, 3150 &priv->steer[i].promisc_qps[j], 3151 list) { 3152 list_del(&pqp->list); 3153 kfree(pqp); 3154 } 3155 list_for_each_entry_safe(entry, tmp_entry, 3156 &priv->steer[i].steer_entries[j], 3157 list) { 3158 list_del(&entry->list); 3159 list_for_each_entry_safe(pqp, tmp_pqp, 3160 &entry->duplicates, 3161 list) { 3162 list_del(&pqp->list); 3163 kfree(pqp); 3164 } 3165 kfree(entry); 3166 } 3167 } 3168 } 3169 kfree(priv->steer); 3170} 3171 3172static int extended_func_num(struct pci_dev *pdev) 3173{ 3174 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3175} 3176 3177#define MLX4_OWNER_BASE 0x8069c 3178#define MLX4_OWNER_SIZE 4 3179 3180static int mlx4_get_ownership(struct mlx4_dev *dev) 3181{ 3182 void __iomem *owner; 3183 u32 ret; 3184 3185 if (pci_channel_offline(dev->persist->pdev)) 3186 return -EIO; 3187 3188 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3189 MLX4_OWNER_BASE, 3190 MLX4_OWNER_SIZE); 3191 if (!owner) { 3192 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3193 return -ENOMEM; 3194 } 3195 3196 ret = readl(owner); 3197 iounmap(owner); 3198 return (int) !!ret; 3199} 3200 3201static void mlx4_free_ownership(struct mlx4_dev *dev) 3202{ 3203 void __iomem *owner; 3204 3205 if (pci_channel_offline(dev->persist->pdev)) 3206 return; 3207 3208 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3209 MLX4_OWNER_BASE, 3210 MLX4_OWNER_SIZE); 3211 if (!owner) { 3212 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3213 return; 3214 } 3215 writel(0, owner); 3216 msleep(1000); 3217 iounmap(owner); 3218} 3219 3220#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3221 !!((flags) & MLX4_FLAG_MASTER)) 3222 3223static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3224 u8 total_vfs, int existing_vfs, int reset_flow) 3225{ 3226 u64 dev_flags = dev->flags; 3227 int err = 0; 3228 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3229 MLX4_MAX_NUM_VF); 3230 3231 if (reset_flow) { 3232 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3233 GFP_KERNEL); 3234 if (!dev->dev_vfs) 3235 goto free_mem; 3236 return dev_flags; 3237 } 3238 3239 atomic_inc(&pf_loading); 3240 if (dev->flags & MLX4_FLAG_SRIOV) { 3241 if (existing_vfs != total_vfs) { 3242 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3243 existing_vfs, total_vfs); 3244 total_vfs = existing_vfs; 3245 } 3246 } 3247 3248 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3249 if (NULL == dev->dev_vfs) { 3250 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3251 goto disable_sriov; 3252 } 3253 3254 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3255 if (total_vfs > fw_enabled_sriov_vfs) { 3256 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3257 total_vfs, fw_enabled_sriov_vfs); 3258 err = -ENOMEM; 3259 goto disable_sriov; 3260 } 3261 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3262 err = pci_enable_sriov(pdev, total_vfs); 3263 } 3264 if (err) { 3265 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3266 err); 3267 goto disable_sriov; 3268 } else { 3269 mlx4_warn(dev, "Running in master mode\n"); 3270 dev_flags |= MLX4_FLAG_SRIOV | 3271 MLX4_FLAG_MASTER; 3272 dev_flags &= ~MLX4_FLAG_SLAVE; 3273 dev->persist->num_vfs = total_vfs; 3274 } 3275 return dev_flags; 3276 3277disable_sriov: 3278 atomic_dec(&pf_loading); 3279free_mem: 3280 dev->persist->num_vfs = 0; 3281 kfree(dev->dev_vfs); 3282 dev->dev_vfs = NULL; 3283 return dev_flags & ~MLX4_FLAG_MASTER; 3284} 3285 3286enum { 3287 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3288}; 3289 3290static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3291 int *nvfs) 3292{ 3293 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3294 /* Checking for 64 VFs as a limitation of CX2 */ 3295 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3296 requested_vfs >= 64) { 3297 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3298 requested_vfs); 3299 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3300 } 3301 return 0; 3302} 3303 3304static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3305{ 3306 struct pci_dev *pdev = dev->persist->pdev; 3307 int err = 0; 3308 3309 mutex_lock(&dev->persist->pci_status_mutex); 3310 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3311 err = pci_enable_device(pdev); 3312 if (!err) 3313 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3314 } 3315 mutex_unlock(&dev->persist->pci_status_mutex); 3316 3317 return err; 3318} 3319 3320static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3321{ 3322 struct pci_dev *pdev = dev->persist->pdev; 3323 3324 mutex_lock(&dev->persist->pci_status_mutex); 3325 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3326 pci_disable_device(pdev); 3327 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3328 } 3329 mutex_unlock(&dev->persist->pci_status_mutex); 3330} 3331 3332static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3333 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3334 int reset_flow) 3335{ 3336 struct mlx4_dev *dev; 3337 unsigned sum = 0; 3338 int err; 3339 int port; 3340 int i; 3341 struct mlx4_dev_cap *dev_cap = NULL; 3342 int existing_vfs = 0; 3343 3344 dev = &priv->dev; 3345 3346 INIT_LIST_HEAD(&priv->ctx_list); 3347 spin_lock_init(&priv->ctx_lock); 3348 3349 mutex_init(&priv->port_mutex); 3350 mutex_init(&priv->bond_mutex); 3351 3352 INIT_LIST_HEAD(&priv->pgdir_list); 3353 mutex_init(&priv->pgdir_mutex); 3354 spin_lock_init(&priv->cmd.context_lock); 3355 3356 INIT_LIST_HEAD(&priv->bf_list); 3357 mutex_init(&priv->bf_mutex); 3358 3359 dev->rev_id = pdev->revision; 3360 dev->numa_node = dev_to_node(&pdev->dev); 3361 3362 /* Detect if this device is a virtual function */ 3363 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3364 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3365 dev->flags |= MLX4_FLAG_SLAVE; 3366 } else { 3367 /* We reset the device and enable SRIOV only for physical 3368 * devices. Try to claim ownership on the device; 3369 * if already taken, skip -- do not allow multiple PFs */ 3370 err = mlx4_get_ownership(dev); 3371 if (err) { 3372 if (err < 0) 3373 return err; 3374 else { 3375 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3376 return -EINVAL; 3377 } 3378 } 3379 3380 atomic_set(&priv->opreq_count, 0); 3381 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3382 3383 /* 3384 * Now reset the HCA before we touch the PCI capabilities or 3385 * attempt a firmware command, since a boot ROM may have left 3386 * the HCA in an undefined state. 3387 */ 3388 err = mlx4_reset(dev); 3389 if (err) { 3390 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3391 goto err_sriov; 3392 } 3393 3394 if (total_vfs) { 3395 dev->flags = MLX4_FLAG_MASTER; 3396 existing_vfs = pci_num_vf(pdev); 3397 if (existing_vfs) 3398 dev->flags |= MLX4_FLAG_SRIOV; 3399 dev->persist->num_vfs = total_vfs; 3400 } 3401 } 3402 3403 /* on load remove any previous indication of internal error, 3404 * device is up. 3405 */ 3406 dev->persist->state = MLX4_DEVICE_STATE_UP; 3407 3408slave_start: 3409 err = mlx4_cmd_init(dev); 3410 if (err) { 3411 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3412 goto err_sriov; 3413 } 3414 3415 /* In slave functions, the communication channel must be initialized 3416 * before posting commands. Also, init num_slaves before calling 3417 * mlx4_init_hca */ 3418 if (mlx4_is_mfunc(dev)) { 3419 if (mlx4_is_master(dev)) { 3420 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3421 3422 } else { 3423 dev->num_slaves = 0; 3424 err = mlx4_multi_func_init(dev); 3425 if (err) { 3426 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3427 goto err_cmd; 3428 } 3429 } 3430 } 3431 3432 err = mlx4_init_fw(dev); 3433 if (err) { 3434 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3435 goto err_mfunc; 3436 } 3437 3438 if (mlx4_is_master(dev)) { 3439 /* when we hit the goto slave_start below, dev_cap already initialized */ 3440 if (!dev_cap) { 3441 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3442 3443 if (!dev_cap) { 3444 err = -ENOMEM; 3445 goto err_fw; 3446 } 3447 3448 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3449 if (err) { 3450 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3451 goto err_fw; 3452 } 3453 3454 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3455 goto err_fw; 3456 3457 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3458 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3459 total_vfs, 3460 existing_vfs, 3461 reset_flow); 3462 3463 mlx4_close_fw(dev); 3464 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3465 dev->flags = dev_flags; 3466 if (!SRIOV_VALID_STATE(dev->flags)) { 3467 mlx4_err(dev, "Invalid SRIOV state\n"); 3468 goto err_sriov; 3469 } 3470 err = mlx4_reset(dev); 3471 if (err) { 3472 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3473 goto err_sriov; 3474 } 3475 goto slave_start; 3476 } 3477 } else { 3478 /* Legacy mode FW requires SRIOV to be enabled before 3479 * doing QUERY_DEV_CAP, since max_eq's value is different if 3480 * SRIOV is enabled. 3481 */ 3482 memset(dev_cap, 0, sizeof(*dev_cap)); 3483 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3484 if (err) { 3485 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3486 goto err_fw; 3487 } 3488 3489 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3490 goto err_fw; 3491 } 3492 } 3493 3494 err = mlx4_init_hca(dev); 3495 if (err) { 3496 if (err == -EACCES) { 3497 /* Not primary Physical function 3498 * Running in slave mode */ 3499 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3500 /* We're not a PF */ 3501 if (dev->flags & MLX4_FLAG_SRIOV) { 3502 if (!existing_vfs) 3503 pci_disable_sriov(pdev); 3504 if (mlx4_is_master(dev) && !reset_flow) 3505 atomic_dec(&pf_loading); 3506 dev->flags &= ~MLX4_FLAG_SRIOV; 3507 } 3508 if (!mlx4_is_slave(dev)) 3509 mlx4_free_ownership(dev); 3510 dev->flags |= MLX4_FLAG_SLAVE; 3511 dev->flags &= ~MLX4_FLAG_MASTER; 3512 goto slave_start; 3513 } else 3514 goto err_fw; 3515 } 3516 3517 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3518 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3519 existing_vfs, reset_flow); 3520 3521 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3522 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3523 dev->flags = dev_flags; 3524 err = mlx4_cmd_init(dev); 3525 if (err) { 3526 /* Only VHCR is cleaned up, so could still 3527 * send FW commands 3528 */ 3529 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3530 goto err_close; 3531 } 3532 } else { 3533 dev->flags = dev_flags; 3534 } 3535 3536 if (!SRIOV_VALID_STATE(dev->flags)) { 3537 mlx4_err(dev, "Invalid SRIOV state\n"); 3538 err = -EINVAL; 3539 goto err_close; 3540 } 3541 } 3542 3543 /* check if the device is functioning at its maximum possible speed. 3544 * No return code for this call, just warn the user in case of PCI 3545 * express device capabilities are under-satisfied by the bus. 3546 */ 3547 if (!mlx4_is_slave(dev)) 3548 pcie_print_link_status(dev->persist->pdev); 3549 3550 /* In master functions, the communication channel must be initialized 3551 * after obtaining its address from fw */ 3552 if (mlx4_is_master(dev)) { 3553 if (dev->caps.num_ports < 2 && 3554 num_vfs_argc > 1) { 3555 err = -EINVAL; 3556 mlx4_err(dev, 3557 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3558 dev->caps.num_ports); 3559 goto err_close; 3560 } 3561 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3562 3563 for (i = 0; 3564 i < sizeof(dev->persist->nvfs)/ 3565 sizeof(dev->persist->nvfs[0]); i++) { 3566 unsigned j; 3567 3568 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3569 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3570 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3571 dev->caps.num_ports; 3572 } 3573 } 3574 3575 /* In master functions, the communication channel 3576 * must be initialized after obtaining its address from fw 3577 */ 3578 err = mlx4_multi_func_init(dev); 3579 if (err) { 3580 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3581 goto err_close; 3582 } 3583 } 3584 3585 err = mlx4_alloc_eq_table(dev); 3586 if (err) 3587 goto err_master_mfunc; 3588 3589 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3590 mutex_init(&priv->msix_ctl.pool_lock); 3591 3592 mlx4_enable_msi_x(dev); 3593 if ((mlx4_is_mfunc(dev)) && 3594 !(dev->flags & MLX4_FLAG_MSI_X)) { 3595 err = -EOPNOTSUPP; 3596 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3597 goto err_free_eq; 3598 } 3599 3600 if (!mlx4_is_slave(dev)) { 3601 err = mlx4_init_steering(dev); 3602 if (err) 3603 goto err_disable_msix; 3604 } 3605 3606 mlx4_init_quotas(dev); 3607 3608 err = mlx4_setup_hca(dev); 3609 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3610 !mlx4_is_mfunc(dev)) { 3611 dev->flags &= ~MLX4_FLAG_MSI_X; 3612 dev->caps.num_comp_vectors = 1; 3613 pci_disable_msix(pdev); 3614 err = mlx4_setup_hca(dev); 3615 } 3616 3617 if (err) 3618 goto err_steer; 3619 3620 /* When PF resources are ready arm its comm channel to enable 3621 * getting commands 3622 */ 3623 if (mlx4_is_master(dev)) { 3624 err = mlx4_ARM_COMM_CHANNEL(dev); 3625 if (err) { 3626 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3627 err); 3628 goto err_steer; 3629 } 3630 } 3631 3632 for (port = 1; port <= dev->caps.num_ports; port++) { 3633 err = mlx4_init_port_info(dev, port); 3634 if (err) 3635 goto err_port; 3636 } 3637 3638 priv->v2p.port1 = 1; 3639 priv->v2p.port2 = 2; 3640 3641 err = mlx4_register_device(dev); 3642 if (err) 3643 goto err_port; 3644 3645 mlx4_request_modules(dev); 3646 3647 mlx4_sense_init(dev); 3648 mlx4_start_sense(dev); 3649 3650 priv->removed = 0; 3651 3652 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3653 atomic_dec(&pf_loading); 3654 3655 kfree(dev_cap); 3656 return 0; 3657 3658err_port: 3659 for (--port; port >= 1; --port) 3660 mlx4_cleanup_port_info(&priv->port[port]); 3661 3662 mlx4_cleanup_default_counters(dev); 3663 if (!mlx4_is_slave(dev)) 3664 mlx4_cleanup_counters_table(dev); 3665 mlx4_cleanup_qp_table(dev); 3666 mlx4_cleanup_srq_table(dev); 3667 mlx4_cleanup_cq_table(dev); 3668 mlx4_cmd_use_polling(dev); 3669 mlx4_cleanup_eq_table(dev); 3670 mlx4_cleanup_mcg_table(dev); 3671 mlx4_cleanup_mr_table(dev); 3672 mlx4_cleanup_xrcd_table(dev); 3673 mlx4_cleanup_pd_table(dev); 3674 mlx4_cleanup_uar_table(dev); 3675 3676err_steer: 3677 if (!mlx4_is_slave(dev)) 3678 mlx4_clear_steering(dev); 3679 3680err_disable_msix: 3681 if (dev->flags & MLX4_FLAG_MSI_X) 3682 pci_disable_msix(pdev); 3683 3684err_free_eq: 3685 mlx4_free_eq_table(dev); 3686 3687err_master_mfunc: 3688 if (mlx4_is_master(dev)) { 3689 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3690 mlx4_multi_func_cleanup(dev); 3691 } 3692 3693 if (mlx4_is_slave(dev)) 3694 mlx4_slave_destroy_special_qp_cap(dev); 3695 3696err_close: 3697 mlx4_close_hca(dev); 3698 3699err_fw: 3700 mlx4_close_fw(dev); 3701 3702err_mfunc: 3703 if (mlx4_is_slave(dev)) 3704 mlx4_multi_func_cleanup(dev); 3705 3706err_cmd: 3707 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3708 3709err_sriov: 3710 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3711 pci_disable_sriov(pdev); 3712 dev->flags &= ~MLX4_FLAG_SRIOV; 3713 } 3714 3715 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3716 atomic_dec(&pf_loading); 3717 3718 kfree(priv->dev.dev_vfs); 3719 3720 if (!mlx4_is_slave(dev)) 3721 mlx4_free_ownership(dev); 3722 3723 kfree(dev_cap); 3724 return err; 3725} 3726 3727static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3728 struct mlx4_priv *priv) 3729{ 3730 int err; 3731 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3732 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3733 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3734 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3735 unsigned total_vfs = 0; 3736 unsigned int i; 3737 3738 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3739 3740 err = mlx4_pci_enable_device(&priv->dev); 3741 if (err) { 3742 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3743 return err; 3744 } 3745 3746 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3747 * per port, we must limit the number of VFs to 63 (since their are 3748 * 128 MACs) 3749 */ 3750 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3751 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3752 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3753 if (nvfs[i] < 0) { 3754 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3755 err = -EINVAL; 3756 goto err_disable_pdev; 3757 } 3758 } 3759 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3760 i++) { 3761 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3762 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3763 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3764 err = -EINVAL; 3765 goto err_disable_pdev; 3766 } 3767 } 3768 if (total_vfs > MLX4_MAX_NUM_VF) { 3769 dev_err(&pdev->dev, 3770 "Requested more VF's (%d) than allowed by hw (%d)\n", 3771 total_vfs, MLX4_MAX_NUM_VF); 3772 err = -EINVAL; 3773 goto err_disable_pdev; 3774 } 3775 3776 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3777 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3778 dev_err(&pdev->dev, 3779 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3780 nvfs[i] + nvfs[2], i + 1, 3781 MLX4_MAX_NUM_VF_P_PORT); 3782 err = -EINVAL; 3783 goto err_disable_pdev; 3784 } 3785 } 3786 3787 /* Check for BARs. */ 3788 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3789 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3790 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3791 pci_dev_data, pci_resource_flags(pdev, 0)); 3792 err = -ENODEV; 3793 goto err_disable_pdev; 3794 } 3795 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3796 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3797 err = -ENODEV; 3798 goto err_disable_pdev; 3799 } 3800 3801 err = pci_request_regions(pdev, DRV_NAME); 3802 if (err) { 3803 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3804 goto err_disable_pdev; 3805 } 3806 3807 pci_set_master(pdev); 3808 3809 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3810 if (err) { 3811 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3812 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3813 if (err) { 3814 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3815 goto err_release_regions; 3816 } 3817 } 3818 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3819 if (err) { 3820 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3821 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3822 if (err) { 3823 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3824 goto err_release_regions; 3825 } 3826 } 3827 3828 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3829 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3830 /* Detect if this device is a virtual function */ 3831 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3832 /* When acting as pf, we normally skip vfs unless explicitly 3833 * requested to probe them. 3834 */ 3835 if (total_vfs) { 3836 unsigned vfs_offset = 0; 3837 3838 for (i = 0; i < ARRAY_SIZE(nvfs) && 3839 vfs_offset + nvfs[i] < extended_func_num(pdev); 3840 vfs_offset += nvfs[i], i++) 3841 ; 3842 if (i == ARRAY_SIZE(nvfs)) { 3843 err = -ENODEV; 3844 goto err_release_regions; 3845 } 3846 if ((extended_func_num(pdev) - vfs_offset) 3847 > prb_vf[i]) { 3848 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3849 extended_func_num(pdev)); 3850 err = -ENODEV; 3851 goto err_release_regions; 3852 } 3853 } 3854 } 3855 3856 err = mlx4_crdump_init(&priv->dev); 3857 if (err) 3858 goto err_release_regions; 3859 3860 err = mlx4_catas_init(&priv->dev); 3861 if (err) 3862 goto err_crdump; 3863 3864 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3865 if (err) 3866 goto err_catas; 3867 3868 return 0; 3869 3870err_catas: 3871 mlx4_catas_end(&priv->dev); 3872 3873err_crdump: 3874 mlx4_crdump_end(&priv->dev); 3875 3876err_release_regions: 3877 pci_release_regions(pdev); 3878 3879err_disable_pdev: 3880 mlx4_pci_disable_device(&priv->dev); 3881 return err; 3882} 3883 3884static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3885 enum devlink_port_type port_type) 3886{ 3887 struct mlx4_port_info *info = container_of(devlink_port, 3888 struct mlx4_port_info, 3889 devlink_port); 3890 enum mlx4_port_type mlx4_port_type; 3891 3892 switch (port_type) { 3893 case DEVLINK_PORT_TYPE_AUTO: 3894 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3895 break; 3896 case DEVLINK_PORT_TYPE_ETH: 3897 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3898 break; 3899 case DEVLINK_PORT_TYPE_IB: 3900 mlx4_port_type = MLX4_PORT_TYPE_IB; 3901 break; 3902 default: 3903 return -EOPNOTSUPP; 3904 } 3905 3906 return __set_port_type(info, mlx4_port_type); 3907} 3908 3909static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3910{ 3911 struct mlx4_priv *priv = devlink_priv(devlink); 3912 struct mlx4_dev *dev = &priv->dev; 3913 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3914 union devlink_param_value saved_value; 3915 int err; 3916 3917 err = devlink_param_driverinit_value_get(devlink, 3918 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3919 &saved_value); 3920 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3921 mlx4_internal_err_reset = saved_value.vbool; 3922 /* Notify on value changed on runtime configuration mode */ 3923 devlink_param_value_changed(devlink, 3924 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3925 } 3926 err = devlink_param_driverinit_value_get(devlink, 3927 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3928 &saved_value); 3929 if (!err) 3930 log_num_mac = order_base_2(saved_value.vu32); 3931 err = devlink_param_driverinit_value_get(devlink, 3932 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3933 &saved_value); 3934 if (!err) 3935 enable_64b_cqe_eqe = saved_value.vbool; 3936 err = devlink_param_driverinit_value_get(devlink, 3937 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3938 &saved_value); 3939 if (!err) 3940 enable_4k_uar = saved_value.vbool; 3941 err = devlink_param_driverinit_value_get(devlink, 3942 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3943 &saved_value); 3944 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3945 crdump->snapshot_enable = saved_value.vbool; 3946 devlink_param_value_changed(devlink, 3947 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3948 } 3949} 3950 3951static void mlx4_restart_one_down(struct pci_dev *pdev); 3952static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 3953 struct devlink *devlink); 3954 3955static int mlx4_devlink_reload_down(struct devlink *devlink, bool netns_change, 3956 enum devlink_reload_action action, 3957 enum devlink_reload_limit limit, 3958 struct netlink_ext_ack *extack) 3959{ 3960 struct mlx4_priv *priv = devlink_priv(devlink); 3961 struct mlx4_dev *dev = &priv->dev; 3962 struct mlx4_dev_persistent *persist = dev->persist; 3963 3964 if (netns_change) { 3965 NL_SET_ERR_MSG_MOD(extack, "Namespace change is not supported"); 3966 return -EOPNOTSUPP; 3967 } 3968 if (persist->num_vfs) 3969 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 3970 mlx4_restart_one_down(persist->pdev); 3971 return 0; 3972} 3973 3974static int mlx4_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action, 3975 enum devlink_reload_limit limit, u32 *actions_performed, 3976 struct netlink_ext_ack *extack) 3977{ 3978 struct mlx4_priv *priv = devlink_priv(devlink); 3979 struct mlx4_dev *dev = &priv->dev; 3980 struct mlx4_dev_persistent *persist = dev->persist; 3981 int err; 3982 3983 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT); 3984 err = mlx4_restart_one_up(persist->pdev, true, devlink); 3985 if (err) 3986 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n", 3987 err); 3988 3989 return err; 3990} 3991 3992static const struct devlink_ops mlx4_devlink_ops = { 3993 .port_type_set = mlx4_devlink_port_type_set, 3994 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT), 3995 .reload_down = mlx4_devlink_reload_down, 3996 .reload_up = mlx4_devlink_reload_up, 3997}; 3998 3999static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 4000{ 4001 struct devlink *devlink; 4002 struct mlx4_priv *priv; 4003 struct mlx4_dev *dev; 4004 int ret; 4005 4006 printk_once(KERN_INFO "%s", mlx4_version); 4007 4008 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv)); 4009 if (!devlink) 4010 return -ENOMEM; 4011 priv = devlink_priv(devlink); 4012 4013 dev = &priv->dev; 4014 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 4015 if (!dev->persist) { 4016 ret = -ENOMEM; 4017 goto err_devlink_free; 4018 } 4019 dev->persist->pdev = pdev; 4020 dev->persist->dev = dev; 4021 pci_set_drvdata(pdev, dev->persist); 4022 priv->pci_dev_data = id->driver_data; 4023 mutex_init(&dev->persist->device_state_mutex); 4024 mutex_init(&dev->persist->interface_state_mutex); 4025 mutex_init(&dev->persist->pci_status_mutex); 4026 4027 ret = devlink_register(devlink, &pdev->dev); 4028 if (ret) 4029 goto err_persist_free; 4030 ret = devlink_params_register(devlink, mlx4_devlink_params, 4031 ARRAY_SIZE(mlx4_devlink_params)); 4032 if (ret) 4033 goto err_devlink_unregister; 4034 mlx4_devlink_set_params_init_values(devlink); 4035 ret = __mlx4_init_one(pdev, id->driver_data, priv); 4036 if (ret) 4037 goto err_params_unregister; 4038 4039 devlink_params_publish(devlink); 4040 devlink_reload_enable(devlink); 4041 pci_save_state(pdev); 4042 return 0; 4043 4044err_params_unregister: 4045 devlink_params_unregister(devlink, mlx4_devlink_params, 4046 ARRAY_SIZE(mlx4_devlink_params)); 4047err_devlink_unregister: 4048 devlink_unregister(devlink); 4049err_persist_free: 4050 kfree(dev->persist); 4051err_devlink_free: 4052 devlink_free(devlink); 4053 return ret; 4054} 4055 4056static void mlx4_clean_dev(struct mlx4_dev *dev) 4057{ 4058 struct mlx4_dev_persistent *persist = dev->persist; 4059 struct mlx4_priv *priv = mlx4_priv(dev); 4060 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4061 4062 memset(priv, 0, sizeof(*priv)); 4063 priv->dev.persist = persist; 4064 priv->dev.flags = flags; 4065} 4066 4067static void mlx4_unload_one(struct pci_dev *pdev) 4068{ 4069 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4070 struct mlx4_dev *dev = persist->dev; 4071 struct mlx4_priv *priv = mlx4_priv(dev); 4072 int pci_dev_data; 4073 int p, i; 4074 4075 if (priv->removed) 4076 return; 4077 4078 /* saving current ports type for further use */ 4079 for (i = 0; i < dev->caps.num_ports; i++) { 4080 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4081 dev->persist->curr_port_poss_type[i] = dev->caps. 4082 possible_type[i + 1]; 4083 } 4084 4085 pci_dev_data = priv->pci_dev_data; 4086 4087 mlx4_stop_sense(dev); 4088 mlx4_unregister_device(dev); 4089 4090 for (p = 1; p <= dev->caps.num_ports; p++) { 4091 mlx4_cleanup_port_info(&priv->port[p]); 4092 mlx4_CLOSE_PORT(dev, p); 4093 } 4094 4095 if (mlx4_is_master(dev)) 4096 mlx4_free_resource_tracker(dev, 4097 RES_TR_FREE_SLAVES_ONLY); 4098 4099 mlx4_cleanup_default_counters(dev); 4100 if (!mlx4_is_slave(dev)) 4101 mlx4_cleanup_counters_table(dev); 4102 mlx4_cleanup_qp_table(dev); 4103 mlx4_cleanup_srq_table(dev); 4104 mlx4_cleanup_cq_table(dev); 4105 mlx4_cmd_use_polling(dev); 4106 mlx4_cleanup_eq_table(dev); 4107 mlx4_cleanup_mcg_table(dev); 4108 mlx4_cleanup_mr_table(dev); 4109 mlx4_cleanup_xrcd_table(dev); 4110 mlx4_cleanup_pd_table(dev); 4111 4112 if (mlx4_is_master(dev)) 4113 mlx4_free_resource_tracker(dev, 4114 RES_TR_FREE_STRUCTS_ONLY); 4115 4116 iounmap(priv->kar); 4117 mlx4_uar_free(dev, &priv->driver_uar); 4118 mlx4_cleanup_uar_table(dev); 4119 if (!mlx4_is_slave(dev)) 4120 mlx4_clear_steering(dev); 4121 mlx4_free_eq_table(dev); 4122 if (mlx4_is_master(dev)) 4123 mlx4_multi_func_cleanup(dev); 4124 mlx4_close_hca(dev); 4125 mlx4_close_fw(dev); 4126 if (mlx4_is_slave(dev)) 4127 mlx4_multi_func_cleanup(dev); 4128 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4129 4130 if (dev->flags & MLX4_FLAG_MSI_X) 4131 pci_disable_msix(pdev); 4132 4133 if (!mlx4_is_slave(dev)) 4134 mlx4_free_ownership(dev); 4135 4136 mlx4_slave_destroy_special_qp_cap(dev); 4137 kfree(dev->dev_vfs); 4138 4139 mlx4_clean_dev(dev); 4140 priv->pci_dev_data = pci_dev_data; 4141 priv->removed = 1; 4142} 4143 4144static void mlx4_remove_one(struct pci_dev *pdev) 4145{ 4146 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4147 struct mlx4_dev *dev = persist->dev; 4148 struct mlx4_priv *priv = mlx4_priv(dev); 4149 struct devlink *devlink = priv_to_devlink(priv); 4150 int active_vfs = 0; 4151 4152 devlink_reload_disable(devlink); 4153 4154 if (mlx4_is_slave(dev)) 4155 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4156 4157 mutex_lock(&persist->interface_state_mutex); 4158 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4159 mutex_unlock(&persist->interface_state_mutex); 4160 4161 /* Disabling SR-IOV is not allowed while there are active vf's */ 4162 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4163 active_vfs = mlx4_how_many_lives_vf(dev); 4164 if (active_vfs) { 4165 pr_warn("Removing PF when there are active VF's !!\n"); 4166 pr_warn("Will not disable SR-IOV.\n"); 4167 } 4168 } 4169 4170 /* device marked to be under deletion running now without the lock 4171 * letting other tasks to be terminated 4172 */ 4173 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4174 mlx4_unload_one(pdev); 4175 else 4176 mlx4_info(dev, "%s: interface is down\n", __func__); 4177 mlx4_catas_end(dev); 4178 mlx4_crdump_end(dev); 4179 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4180 mlx4_warn(dev, "Disabling SR-IOV\n"); 4181 pci_disable_sriov(pdev); 4182 } 4183 4184 pci_release_regions(pdev); 4185 mlx4_pci_disable_device(dev); 4186 devlink_params_unregister(devlink, mlx4_devlink_params, 4187 ARRAY_SIZE(mlx4_devlink_params)); 4188 devlink_unregister(devlink); 4189 kfree(dev->persist); 4190 devlink_free(devlink); 4191} 4192 4193static int restore_current_port_types(struct mlx4_dev *dev, 4194 enum mlx4_port_type *types, 4195 enum mlx4_port_type *poss_types) 4196{ 4197 struct mlx4_priv *priv = mlx4_priv(dev); 4198 int err, i; 4199 4200 mlx4_stop_sense(dev); 4201 4202 mutex_lock(&priv->port_mutex); 4203 for (i = 0; i < dev->caps.num_ports; i++) 4204 dev->caps.possible_type[i + 1] = poss_types[i]; 4205 err = mlx4_change_port_types(dev, types); 4206 mlx4_start_sense(dev); 4207 mutex_unlock(&priv->port_mutex); 4208 4209 return err; 4210} 4211 4212static void mlx4_restart_one_down(struct pci_dev *pdev) 4213{ 4214 mlx4_unload_one(pdev); 4215} 4216 4217static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 4218 struct devlink *devlink) 4219{ 4220 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4221 struct mlx4_dev *dev = persist->dev; 4222 struct mlx4_priv *priv = mlx4_priv(dev); 4223 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4224 int pci_dev_data, err, total_vfs; 4225 4226 pci_dev_data = priv->pci_dev_data; 4227 total_vfs = dev->persist->num_vfs; 4228 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4229 4230 if (reload) 4231 mlx4_devlink_param_load_driverinit_values(devlink); 4232 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4233 if (err) { 4234 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4235 __func__, pci_name(pdev), err); 4236 return err; 4237 } 4238 4239 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4240 dev->persist->curr_port_poss_type); 4241 if (err) 4242 mlx4_err(dev, "could not restore original port types (%d)\n", 4243 err); 4244 4245 return err; 4246} 4247 4248int mlx4_restart_one(struct pci_dev *pdev) 4249{ 4250 mlx4_restart_one_down(pdev); 4251 return mlx4_restart_one_up(pdev, false, NULL); 4252} 4253 4254#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4255#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4256#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4257 4258static const struct pci_device_id mlx4_pci_table[] = { 4259#ifdef CONFIG_MLX4_CORE_GEN2 4260 /* MT25408 "Hermon" */ 4261 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4262 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4263 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4264 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4265 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4266 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4267 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4268 /* MT25458 ConnectX EN 10GBASE-T */ 4269 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4270 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4271 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4272 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4273 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4274 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4275 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4276 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4277 /* MT25400 Family [ConnectX-2] */ 4278 MLX_VF(0x1002), /* Virtual Function */ 4279#endif /* CONFIG_MLX4_CORE_GEN2 */ 4280 /* MT27500 Family [ConnectX-3] */ 4281 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4282 MLX_VF(0x1004), /* Virtual Function */ 4283 MLX_GN(0x1005), /* MT27510 Family */ 4284 MLX_GN(0x1006), /* MT27511 Family */ 4285 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4286 MLX_GN(0x1008), /* MT27521 Family */ 4287 MLX_GN(0x1009), /* MT27530 Family */ 4288 MLX_GN(0x100a), /* MT27531 Family */ 4289 MLX_GN(0x100b), /* MT27540 Family */ 4290 MLX_GN(0x100c), /* MT27541 Family */ 4291 MLX_GN(0x100d), /* MT27550 Family */ 4292 MLX_GN(0x100e), /* MT27551 Family */ 4293 MLX_GN(0x100f), /* MT27560 Family */ 4294 MLX_GN(0x1010), /* MT27561 Family */ 4295 4296 /* 4297 * See the mellanox_check_broken_intx_masking() quirk when 4298 * adding devices 4299 */ 4300 4301 { 0, } 4302}; 4303 4304MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4305 4306static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4307 pci_channel_state_t state) 4308{ 4309 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4310 4311 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4312 mlx4_enter_error_state(persist); 4313 4314 mutex_lock(&persist->interface_state_mutex); 4315 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4316 mlx4_unload_one(pdev); 4317 4318 mutex_unlock(&persist->interface_state_mutex); 4319 if (state == pci_channel_io_perm_failure) 4320 return PCI_ERS_RESULT_DISCONNECT; 4321 4322 mlx4_pci_disable_device(persist->dev); 4323 return PCI_ERS_RESULT_NEED_RESET; 4324} 4325 4326static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4327{ 4328 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4329 struct mlx4_dev *dev = persist->dev; 4330 int err; 4331 4332 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4333 err = mlx4_pci_enable_device(dev); 4334 if (err) { 4335 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4336 return PCI_ERS_RESULT_DISCONNECT; 4337 } 4338 4339 pci_set_master(pdev); 4340 pci_restore_state(pdev); 4341 pci_save_state(pdev); 4342 return PCI_ERS_RESULT_RECOVERED; 4343} 4344 4345static void mlx4_pci_resume(struct pci_dev *pdev) 4346{ 4347 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4348 struct mlx4_dev *dev = persist->dev; 4349 struct mlx4_priv *priv = mlx4_priv(dev); 4350 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4351 int total_vfs; 4352 int err; 4353 4354 mlx4_err(dev, "%s was called\n", __func__); 4355 total_vfs = dev->persist->num_vfs; 4356 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4357 4358 mutex_lock(&persist->interface_state_mutex); 4359 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4360 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4361 priv, 1); 4362 if (err) { 4363 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4364 __func__, err); 4365 goto end; 4366 } 4367 4368 err = restore_current_port_types(dev, dev->persist-> 4369 curr_port_type, dev->persist-> 4370 curr_port_poss_type); 4371 if (err) 4372 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4373 } 4374end: 4375 mutex_unlock(&persist->interface_state_mutex); 4376 4377} 4378 4379static void mlx4_shutdown(struct pci_dev *pdev) 4380{ 4381 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4382 struct mlx4_dev *dev = persist->dev; 4383 4384 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4385 mutex_lock(&persist->interface_state_mutex); 4386 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4387 mlx4_unload_one(pdev); 4388 mutex_unlock(&persist->interface_state_mutex); 4389 mlx4_pci_disable_device(dev); 4390} 4391 4392static const struct pci_error_handlers mlx4_err_handler = { 4393 .error_detected = mlx4_pci_err_detected, 4394 .slot_reset = mlx4_pci_slot_reset, 4395 .resume = mlx4_pci_resume, 4396}; 4397 4398static int __maybe_unused mlx4_suspend(struct device *dev_d) 4399{ 4400 struct pci_dev *pdev = to_pci_dev(dev_d); 4401 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4402 struct mlx4_dev *dev = persist->dev; 4403 4404 mlx4_err(dev, "suspend was called\n"); 4405 mutex_lock(&persist->interface_state_mutex); 4406 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4407 mlx4_unload_one(pdev); 4408 mutex_unlock(&persist->interface_state_mutex); 4409 4410 return 0; 4411} 4412 4413static int __maybe_unused mlx4_resume(struct device *dev_d) 4414{ 4415 struct pci_dev *pdev = to_pci_dev(dev_d); 4416 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4417 struct mlx4_dev *dev = persist->dev; 4418 struct mlx4_priv *priv = mlx4_priv(dev); 4419 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4420 int total_vfs; 4421 int ret = 0; 4422 4423 mlx4_err(dev, "resume was called\n"); 4424 total_vfs = dev->persist->num_vfs; 4425 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4426 4427 mutex_lock(&persist->interface_state_mutex); 4428 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4429 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4430 nvfs, priv, 1); 4431 if (!ret) { 4432 ret = restore_current_port_types(dev, 4433 dev->persist->curr_port_type, 4434 dev->persist->curr_port_poss_type); 4435 if (ret) 4436 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4437 } 4438 } 4439 mutex_unlock(&persist->interface_state_mutex); 4440 4441 return ret; 4442} 4443 4444static SIMPLE_DEV_PM_OPS(mlx4_pm_ops, mlx4_suspend, mlx4_resume); 4445 4446static struct pci_driver mlx4_driver = { 4447 .name = DRV_NAME, 4448 .id_table = mlx4_pci_table, 4449 .probe = mlx4_init_one, 4450 .shutdown = mlx4_shutdown, 4451 .remove = mlx4_remove_one, 4452 .driver.pm = &mlx4_pm_ops, 4453 .err_handler = &mlx4_err_handler, 4454}; 4455 4456static int __init mlx4_verify_params(void) 4457{ 4458 if (msi_x < 0) { 4459 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4460 return -1; 4461 } 4462 4463 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4464 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4465 return -1; 4466 } 4467 4468 if (log_num_vlan != 0) 4469 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4470 MLX4_LOG_NUM_VLANS); 4471 4472 if (use_prio != 0) 4473 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4474 4475 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 4476 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4477 log_mtts_per_seg); 4478 return -1; 4479 } 4480 4481 /* Check if module param for ports type has legal combination */ 4482 if (port_type_array[0] == false && port_type_array[1] == true) { 4483 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4484 port_type_array[0] = true; 4485 } 4486 4487 if (mlx4_log_num_mgm_entry_size < -7 || 4488 (mlx4_log_num_mgm_entry_size > 0 && 4489 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4490 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4491 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4492 mlx4_log_num_mgm_entry_size, 4493 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4494 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4495 return -1; 4496 } 4497 4498 return 0; 4499} 4500 4501static int __init mlx4_init(void) 4502{ 4503 int ret; 4504 4505 if (mlx4_verify_params()) 4506 return -EINVAL; 4507 4508 4509 mlx4_wq = create_singlethread_workqueue("mlx4"); 4510 if (!mlx4_wq) 4511 return -ENOMEM; 4512 4513 ret = pci_register_driver(&mlx4_driver); 4514 if (ret < 0) 4515 destroy_workqueue(mlx4_wq); 4516 return ret < 0 ? ret : 0; 4517} 4518 4519static void __exit mlx4_cleanup(void) 4520{ 4521 pci_unregister_driver(&mlx4_driver); 4522 destroy_workqueue(mlx4_wq); 4523} 4524 4525module_init(mlx4_init); 4526module_exit(mlx4_cleanup); 4527