1/* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#include <asm/page.h> 35#include <linux/mlx4/cq.h> 36#include <linux/slab.h> 37#include <linux/mlx4/qp.h> 38#include <linux/skbuff.h> 39#include <linux/if_vlan.h> 40#include <linux/prefetch.h> 41#include <linux/vmalloc.h> 42#include <linux/tcp.h> 43#include <linux/ip.h> 44#include <linux/ipv6.h> 45#include <linux/moduleparam.h> 46#include <linux/indirect_call_wrapper.h> 47 48#include "mlx4_en.h" 49 50int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 51 struct mlx4_en_tx_ring **pring, u32 size, 52 u16 stride, int node, int queue_index) 53{ 54 struct mlx4_en_dev *mdev = priv->mdev; 55 struct mlx4_en_tx_ring *ring; 56 int tmp; 57 int err; 58 59 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 60 if (!ring) { 61 en_err(priv, "Failed allocating TX ring\n"); 62 return -ENOMEM; 63 } 64 65 ring->size = size; 66 ring->size_mask = size - 1; 67 ring->sp_stride = stride; 68 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 69 70 tmp = size * sizeof(struct mlx4_en_tx_info); 71 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); 72 if (!ring->tx_info) { 73 err = -ENOMEM; 74 goto err_ring; 75 } 76 77 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 78 ring->tx_info, tmp); 79 80 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 81 if (!ring->bounce_buf) { 82 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 83 if (!ring->bounce_buf) { 84 err = -ENOMEM; 85 goto err_info; 86 } 87 } 88 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); 89 90 /* Allocate HW buffers on provided NUMA node */ 91 set_dev_node(&mdev->dev->persist->pdev->dev, node); 92 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 93 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 94 if (err) { 95 en_err(priv, "Failed allocating hwq resources\n"); 96 goto err_bounce; 97 } 98 99 ring->buf = ring->sp_wqres.buf.direct.buf; 100 101 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 102 ring, ring->buf, ring->size, ring->buf_size, 103 (unsigned long long) ring->sp_wqres.buf.direct.map); 104 105 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 106 MLX4_RESERVE_ETH_BF_QP, 107 MLX4_RES_USAGE_DRIVER); 108 if (err) { 109 en_err(priv, "failed reserving qp for TX ring\n"); 110 goto err_hwq_res; 111 } 112 113 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); 114 if (err) { 115 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 116 goto err_reserve; 117 } 118 ring->sp_qp.event = mlx4_en_sqp_event; 119 120 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 121 if (err) { 122 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 123 ring->bf.uar = &mdev->priv_uar; 124 ring->bf.uar->map = mdev->uar_map; 125 ring->bf_enabled = false; 126 ring->bf_alloced = false; 127 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 128 } else { 129 ring->bf_alloced = true; 130 ring->bf_enabled = !!(priv->pflags & 131 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 132 } 133 134 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 135 ring->queue_index = queue_index; 136 137 if (queue_index < priv->num_tx_rings_p_up) 138 cpumask_set_cpu(cpumask_local_spread(queue_index, 139 priv->mdev->dev->numa_node), 140 &ring->sp_affinity_mask); 141 142 *pring = ring; 143 return 0; 144 145err_reserve: 146 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 147err_hwq_res: 148 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 149err_bounce: 150 kfree(ring->bounce_buf); 151 ring->bounce_buf = NULL; 152err_info: 153 kvfree(ring->tx_info); 154 ring->tx_info = NULL; 155err_ring: 156 kfree(ring); 157 *pring = NULL; 158 return err; 159} 160 161void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 162 struct mlx4_en_tx_ring **pring) 163{ 164 struct mlx4_en_dev *mdev = priv->mdev; 165 struct mlx4_en_tx_ring *ring = *pring; 166 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 167 168 if (ring->bf_alloced) 169 mlx4_bf_free(mdev->dev, &ring->bf); 170 mlx4_qp_remove(mdev->dev, &ring->sp_qp); 171 mlx4_qp_free(mdev->dev, &ring->sp_qp); 172 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 173 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); 174 kfree(ring->bounce_buf); 175 ring->bounce_buf = NULL; 176 kvfree(ring->tx_info); 177 ring->tx_info = NULL; 178 kfree(ring); 179 *pring = NULL; 180} 181 182int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 183 struct mlx4_en_tx_ring *ring, 184 int cq, int user_prio) 185{ 186 struct mlx4_en_dev *mdev = priv->mdev; 187 int err; 188 189 ring->sp_cqn = cq; 190 ring->prod = 0; 191 ring->cons = 0xffffffff; 192 ring->last_nr_txbb = 1; 193 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 194 memset(ring->buf, 0, ring->buf_size); 195 ring->free_tx_desc = mlx4_en_free_tx_desc; 196 197 ring->sp_qp_state = MLX4_QP_STATE_RST; 198 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); 199 ring->mr_key = cpu_to_be32(mdev->mr.key); 200 201 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, 202 ring->sp_cqn, user_prio, &ring->sp_context); 203 if (ring->bf_alloced) 204 ring->sp_context.usr_page = 205 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 206 ring->bf.uar->index)); 207 208 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, 209 &ring->sp_qp, &ring->sp_qp_state); 210 if (!cpumask_empty(&ring->sp_affinity_mask)) 211 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, 212 ring->queue_index); 213 214 return err; 215} 216 217void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 218 struct mlx4_en_tx_ring *ring) 219{ 220 struct mlx4_en_dev *mdev = priv->mdev; 221 222 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, 223 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); 224} 225 226static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 227{ 228 return ring->prod - ring->cons > ring->full_size; 229} 230 231static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 232 struct mlx4_en_tx_ring *ring, int index, 233 u8 owner) 234{ 235 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 236 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 237 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 238 void *end = ring->buf + ring->buf_size; 239 __be32 *ptr = (__be32 *)tx_desc; 240 int i; 241 242 /* Optimize the common case when there are no wraparounds */ 243 if (likely((void *)tx_desc + 244 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 245 /* Stamp the freed descriptor */ 246 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 247 i += STAMP_STRIDE) { 248 *ptr = stamp; 249 ptr += STAMP_DWORDS; 250 } 251 } else { 252 /* Stamp the freed descriptor */ 253 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; 254 i += STAMP_STRIDE) { 255 *ptr = stamp; 256 ptr += STAMP_DWORDS; 257 if ((void *)ptr >= end) { 258 ptr = ring->buf; 259 stamp ^= cpu_to_be32(0x80000000); 260 } 261 } 262 } 263} 264 265INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 266 struct mlx4_en_tx_ring *ring, 267 int index, u64 timestamp, 268 int napi_mode)); 269 270u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 271 struct mlx4_en_tx_ring *ring, 272 int index, u64 timestamp, 273 int napi_mode) 274{ 275 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 276 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 277 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 278 void *end = ring->buf + ring->buf_size; 279 struct sk_buff *skb = tx_info->skb; 280 int nr_maps = tx_info->nr_maps; 281 int i; 282 283 /* We do not touch skb here, so prefetch skb->users location 284 * to speedup consume_skb() 285 */ 286 prefetchw(&skb->users); 287 288 if (unlikely(timestamp)) { 289 struct skb_shared_hwtstamps hwts; 290 291 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 292 skb_tstamp_tx(skb, &hwts); 293 } 294 295 if (!tx_info->inl) { 296 if (tx_info->linear) 297 dma_unmap_single(priv->ddev, 298 tx_info->map0_dma, 299 tx_info->map0_byte_count, 300 PCI_DMA_TODEVICE); 301 else 302 dma_unmap_page(priv->ddev, 303 tx_info->map0_dma, 304 tx_info->map0_byte_count, 305 PCI_DMA_TODEVICE); 306 /* Optimize the common case when there are no wraparounds */ 307 if (likely((void *)tx_desc + 308 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { 309 for (i = 1; i < nr_maps; i++) { 310 data++; 311 dma_unmap_page(priv->ddev, 312 (dma_addr_t)be64_to_cpu(data->addr), 313 be32_to_cpu(data->byte_count), 314 PCI_DMA_TODEVICE); 315 } 316 } else { 317 if ((void *)data >= end) 318 data = ring->buf + ((void *)data - end); 319 320 for (i = 1; i < nr_maps; i++) { 321 data++; 322 /* Check for wraparound before unmapping */ 323 if ((void *) data >= end) 324 data = ring->buf; 325 dma_unmap_page(priv->ddev, 326 (dma_addr_t)be64_to_cpu(data->addr), 327 be32_to_cpu(data->byte_count), 328 PCI_DMA_TODEVICE); 329 } 330 } 331 } 332 napi_consume_skb(skb, napi_mode); 333 334 return tx_info->nr_txbb; 335} 336 337INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 338 struct mlx4_en_tx_ring *ring, 339 int index, u64 timestamp, 340 int napi_mode)); 341 342u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 343 struct mlx4_en_tx_ring *ring, 344 int index, u64 timestamp, 345 int napi_mode) 346{ 347 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 348 struct mlx4_en_rx_alloc frame = { 349 .page = tx_info->page, 350 .dma = tx_info->map0_dma, 351 }; 352 353 if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { 354 dma_unmap_page(priv->ddev, tx_info->map0_dma, 355 PAGE_SIZE, priv->dma_dir); 356 put_page(tx_info->page); 357 } 358 359 return tx_info->nr_txbb; 360} 361 362int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 363{ 364 struct mlx4_en_priv *priv = netdev_priv(dev); 365 int cnt = 0; 366 367 /* Skip last polled descriptor */ 368 ring->cons += ring->last_nr_txbb; 369 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 370 ring->cons, ring->prod); 371 372 if ((u32) (ring->prod - ring->cons) > ring->size) { 373 if (netif_msg_tx_err(priv)) 374 en_warn(priv, "Tx consumer passed producer!\n"); 375 return 0; 376 } 377 378 while (ring->cons != ring->prod) { 379 ring->last_nr_txbb = ring->free_tx_desc(priv, ring, 380 ring->cons & ring->size_mask, 381 0, 0 /* Non-NAPI caller */); 382 ring->cons += ring->last_nr_txbb; 383 cnt++; 384 } 385 386 if (ring->tx_queue) 387 netdev_tx_reset_queue(ring->tx_queue); 388 389 if (cnt) 390 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 391 392 return cnt; 393} 394 395static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe, 396 u16 cqe_index, struct mlx4_en_tx_ring *ring) 397{ 398 struct mlx4_en_dev *mdev = priv->mdev; 399 struct mlx4_en_tx_info *tx_info; 400 struct mlx4_en_tx_desc *tx_desc; 401 u16 wqe_index; 402 int desc_size; 403 404 en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n", 405 ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome); 406 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe), 407 false); 408 409 wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask; 410 tx_info = &ring->tx_info[wqe_index]; 411 desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE; 412 en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn, 413 wqe_index, desc_size); 414 tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE); 415 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false); 416 417 if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state)) 418 return; 419 420 en_err(priv, "Scheduling port restart\n"); 421 queue_work(mdev->workqueue, &priv->restart_task); 422} 423 424int mlx4_en_process_tx_cq(struct net_device *dev, 425 struct mlx4_en_cq *cq, int napi_budget) 426{ 427 struct mlx4_en_priv *priv = netdev_priv(dev); 428 struct mlx4_cq *mcq = &cq->mcq; 429 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; 430 struct mlx4_cqe *cqe; 431 u16 index, ring_index, stamp_index; 432 u32 txbbs_skipped = 0; 433 u32 txbbs_stamp = 0; 434 u32 cons_index = mcq->cons_index; 435 int size = cq->size; 436 u32 size_mask = ring->size_mask; 437 struct mlx4_cqe *buf = cq->buf; 438 u32 packets = 0; 439 u32 bytes = 0; 440 int factor = priv->cqe_factor; 441 int done = 0; 442 int budget = priv->tx_work_limit; 443 u32 last_nr_txbb; 444 u32 ring_cons; 445 446 if (unlikely(!priv->port_up)) 447 return 0; 448 449 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 450 451 index = cons_index & size_mask; 452 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 453 last_nr_txbb = READ_ONCE(ring->last_nr_txbb); 454 ring_cons = READ_ONCE(ring->cons); 455 ring_index = ring_cons & size_mask; 456 stamp_index = ring_index; 457 458 /* Process all completed CQEs */ 459 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 460 cons_index & size) && (done < budget)) { 461 u16 new_index; 462 463 /* 464 * make sure we read the CQE after we read the 465 * ownership bit 466 */ 467 dma_rmb(); 468 469 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 470 MLX4_CQE_OPCODE_ERROR)) 471 if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state)) 472 mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index, 473 ring); 474 475 /* Skip over last polled CQE */ 476 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 477 478 do { 479 u64 timestamp = 0; 480 481 txbbs_skipped += last_nr_txbb; 482 ring_index = (ring_index + last_nr_txbb) & size_mask; 483 484 if (unlikely(ring->tx_info[ring_index].ts_requested)) 485 timestamp = mlx4_en_get_cqe_ts(cqe); 486 487 /* free next descriptor */ 488 last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc, 489 mlx4_en_free_tx_desc, 490 mlx4_en_recycle_tx_desc, 491 priv, ring, ring_index, 492 timestamp, napi_budget); 493 494 mlx4_en_stamp_wqe(priv, ring, stamp_index, 495 !!((ring_cons + txbbs_stamp) & 496 ring->size)); 497 stamp_index = ring_index; 498 txbbs_stamp = txbbs_skipped; 499 packets++; 500 bytes += ring->tx_info[ring_index].nr_bytes; 501 } while ((++done < budget) && (ring_index != new_index)); 502 503 ++cons_index; 504 index = cons_index & size_mask; 505 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 506 } 507 508 /* 509 * To prevent CQ overflow we first update CQ consumer and only then 510 * the ring consumer. 511 */ 512 mcq->cons_index = cons_index; 513 mlx4_cq_set_ci(mcq); 514 wmb(); 515 516 /* we want to dirty this cache line once */ 517 WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); 518 WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); 519 520 if (cq->type == TX_XDP) 521 return done; 522 523 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 524 525 /* Wakeup Tx queue if this stopped, and ring is not full. 526 */ 527 if (netif_tx_queue_stopped(ring->tx_queue) && 528 !mlx4_en_is_tx_ring_full(ring)) { 529 netif_tx_wake_queue(ring->tx_queue); 530 ring->wake_queue++; 531 } 532 533 return done; 534} 535 536void mlx4_en_tx_irq(struct mlx4_cq *mcq) 537{ 538 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 539 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 540 541 if (likely(priv->port_up)) 542 napi_schedule_irqoff(&cq->napi); 543 else 544 mlx4_en_arm_cq(priv, cq); 545} 546 547/* TX CQ polling - called by NAPI */ 548int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 549{ 550 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 551 struct net_device *dev = cq->dev; 552 struct mlx4_en_priv *priv = netdev_priv(dev); 553 int work_done; 554 555 work_done = mlx4_en_process_tx_cq(dev, cq, budget); 556 if (work_done >= budget) 557 return budget; 558 559 if (napi_complete_done(napi, work_done)) 560 mlx4_en_arm_cq(priv, cq); 561 562 return 0; 563} 564 565static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 566 struct mlx4_en_tx_ring *ring, 567 u32 index, 568 unsigned int desc_size) 569{ 570 u32 copy = (ring->size - index) << LOG_TXBB_SIZE; 571 int i; 572 573 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 574 if ((i & (TXBB_SIZE - 1)) == 0) 575 wmb(); 576 577 *((u32 *) (ring->buf + i)) = 578 *((u32 *) (ring->bounce_buf + copy + i)); 579 } 580 581 for (i = copy - 4; i >= 4 ; i -= 4) { 582 if ((i & (TXBB_SIZE - 1)) == 0) 583 wmb(); 584 585 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = 586 *((u32 *) (ring->bounce_buf + i)); 587 } 588 589 /* Return real descriptor location */ 590 return ring->buf + (index << LOG_TXBB_SIZE); 591} 592 593/* Decide if skb can be inlined in tx descriptor to avoid dma mapping 594 * 595 * It seems strange we do not simply use skb_copy_bits(). 596 * This would allow to inline all skbs iff skb->len <= inline_thold 597 * 598 * Note that caller already checked skb was not a gso packet 599 */ 600static bool is_inline(int inline_thold, const struct sk_buff *skb, 601 const struct skb_shared_info *shinfo, 602 void **pfrag) 603{ 604 void *ptr; 605 606 if (skb->len > inline_thold || !inline_thold) 607 return false; 608 609 if (shinfo->nr_frags == 1) { 610 ptr = skb_frag_address_safe(&shinfo->frags[0]); 611 if (unlikely(!ptr)) 612 return false; 613 *pfrag = ptr; 614 return true; 615 } 616 if (shinfo->nr_frags) 617 return false; 618 return true; 619} 620 621static int inline_size(const struct sk_buff *skb) 622{ 623 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 624 <= MLX4_INLINE_ALIGN) 625 return ALIGN(skb->len + CTRL_SIZE + 626 sizeof(struct mlx4_wqe_inline_seg), 16); 627 else 628 return ALIGN(skb->len + CTRL_SIZE + 2 * 629 sizeof(struct mlx4_wqe_inline_seg), 16); 630} 631 632static int get_real_size(const struct sk_buff *skb, 633 const struct skb_shared_info *shinfo, 634 struct net_device *dev, 635 int *lso_header_size, 636 bool *inline_ok, 637 void **pfrag) 638{ 639 struct mlx4_en_priv *priv = netdev_priv(dev); 640 int real_size; 641 642 if (shinfo->gso_size) { 643 *inline_ok = false; 644 if (skb->encapsulation) 645 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 646 else 647 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 648 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 649 ALIGN(*lso_header_size + 4, DS_SIZE); 650 if (unlikely(*lso_header_size != skb_headlen(skb))) { 651 /* We add a segment for the skb linear buffer only if 652 * it contains data */ 653 if (*lso_header_size < skb_headlen(skb)) 654 real_size += DS_SIZE; 655 else { 656 if (netif_msg_tx_err(priv)) 657 en_warn(priv, "Non-linear headers\n"); 658 return 0; 659 } 660 } 661 } else { 662 *lso_header_size = 0; 663 *inline_ok = is_inline(priv->prof->inline_thold, skb, 664 shinfo, pfrag); 665 666 if (*inline_ok) 667 real_size = inline_size(skb); 668 else 669 real_size = CTRL_SIZE + 670 (shinfo->nr_frags + 1) * DS_SIZE; 671 } 672 673 return real_size; 674} 675 676static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 677 const struct sk_buff *skb, 678 const struct skb_shared_info *shinfo, 679 void *fragptr) 680{ 681 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 682 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); 683 unsigned int hlen = skb_headlen(skb); 684 685 if (skb->len <= spc) { 686 if (likely(skb->len >= MIN_PKT_LEN)) { 687 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 688 } else { 689 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 690 memset(((void *)(inl + 1)) + skb->len, 0, 691 MIN_PKT_LEN - skb->len); 692 } 693 skb_copy_from_linear_data(skb, inl + 1, hlen); 694 if (shinfo->nr_frags) 695 memcpy(((void *)(inl + 1)) + hlen, fragptr, 696 skb_frag_size(&shinfo->frags[0])); 697 698 } else { 699 inl->byte_count = cpu_to_be32(1 << 31 | spc); 700 if (hlen <= spc) { 701 skb_copy_from_linear_data(skb, inl + 1, hlen); 702 if (hlen < spc) { 703 memcpy(((void *)(inl + 1)) + hlen, 704 fragptr, spc - hlen); 705 fragptr += spc - hlen; 706 } 707 inl = (void *) (inl + 1) + spc; 708 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 709 } else { 710 skb_copy_from_linear_data(skb, inl + 1, spc); 711 inl = (void *) (inl + 1) + spc; 712 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 713 hlen - spc); 714 if (shinfo->nr_frags) 715 memcpy(((void *)(inl + 1)) + hlen - spc, 716 fragptr, 717 skb_frag_size(&shinfo->frags[0])); 718 } 719 720 dma_wmb(); 721 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 722 } 723} 724 725u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 726 struct net_device *sb_dev) 727{ 728 struct mlx4_en_priv *priv = netdev_priv(dev); 729 u16 rings_p_up = priv->num_tx_rings_p_up; 730 731 if (netdev_get_num_tc(dev)) 732 return netdev_pick_tx(dev, skb, NULL); 733 734 return netdev_pick_tx(dev, skb, NULL) % rings_p_up; 735} 736 737static void mlx4_bf_copy(void __iomem *dst, const void *src, 738 unsigned int bytecnt) 739{ 740 __iowrite64_copy(dst, src, bytecnt / 8); 741} 742 743void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) 744{ 745 wmb(); 746 /* Since there is no iowrite*_native() that writes the 747 * value as is, without byteswapping - using the one 748 * the doesn't do byteswapping in the relevant arch 749 * endianness. 750 */ 751#if defined(__LITTLE_ENDIAN) 752 iowrite32( 753#else 754 iowrite32be( 755#endif 756 (__force u32)ring->doorbell_qpn, 757 ring->bf.uar->map + MLX4_SEND_DOORBELL); 758} 759 760static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, 761 struct mlx4_en_tx_desc *tx_desc, 762 union mlx4_wqe_qpn_vlan qpn_vlan, 763 int desc_size, int bf_index, 764 __be32 op_own, bool bf_ok, 765 bool send_doorbell) 766{ 767 tx_desc->ctrl.qpn_vlan = qpn_vlan; 768 769 if (bf_ok) { 770 op_own |= htonl((bf_index & 0xffff) << 8); 771 /* Ensure new descriptor hits memory 772 * before setting ownership of this descriptor to HW 773 */ 774 dma_wmb(); 775 tx_desc->ctrl.owner_opcode = op_own; 776 777 wmb(); 778 779 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 780 desc_size); 781 782 wmb(); 783 784 ring->bf.offset ^= ring->bf.buf_size; 785 } else { 786 /* Ensure new descriptor hits memory 787 * before setting ownership of this descriptor to HW 788 */ 789 dma_wmb(); 790 tx_desc->ctrl.owner_opcode = op_own; 791 if (send_doorbell) 792 mlx4_en_xmit_doorbell(ring); 793 else 794 ring->xmit_more++; 795 } 796} 797 798static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, 799 struct skb_shared_info *shinfo, 800 struct mlx4_wqe_data_seg *data, 801 struct sk_buff *skb, 802 int lso_header_size, 803 __be32 mr_key, 804 struct mlx4_en_tx_info *tx_info) 805{ 806 struct device *ddev = priv->ddev; 807 dma_addr_t dma = 0; 808 u32 byte_count = 0; 809 int i_frag; 810 811 /* Map fragments if any */ 812 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 813 const skb_frag_t *frag = &shinfo->frags[i_frag]; 814 byte_count = skb_frag_size(frag); 815 dma = skb_frag_dma_map(ddev, frag, 816 0, byte_count, 817 DMA_TO_DEVICE); 818 if (dma_mapping_error(ddev, dma)) 819 goto tx_drop_unmap; 820 821 data->addr = cpu_to_be64(dma); 822 data->lkey = mr_key; 823 dma_wmb(); 824 data->byte_count = cpu_to_be32(byte_count); 825 --data; 826 } 827 828 /* Map linear part if needed */ 829 if (tx_info->linear) { 830 byte_count = skb_headlen(skb) - lso_header_size; 831 832 dma = dma_map_single(ddev, skb->data + 833 lso_header_size, byte_count, 834 PCI_DMA_TODEVICE); 835 if (dma_mapping_error(ddev, dma)) 836 goto tx_drop_unmap; 837 838 data->addr = cpu_to_be64(dma); 839 data->lkey = mr_key; 840 dma_wmb(); 841 data->byte_count = cpu_to_be32(byte_count); 842 } 843 /* tx completion can avoid cache line miss for common cases */ 844 tx_info->map0_dma = dma; 845 tx_info->map0_byte_count = byte_count; 846 847 return true; 848 849tx_drop_unmap: 850 en_err(priv, "DMA mapping error\n"); 851 852 while (++i_frag < shinfo->nr_frags) { 853 ++data; 854 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), 855 be32_to_cpu(data->byte_count), 856 PCI_DMA_TODEVICE); 857 } 858 859 return false; 860} 861 862netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 863{ 864 struct skb_shared_info *shinfo = skb_shinfo(skb); 865 struct mlx4_en_priv *priv = netdev_priv(dev); 866 union mlx4_wqe_qpn_vlan qpn_vlan = {}; 867 struct mlx4_en_tx_ring *ring; 868 struct mlx4_en_tx_desc *tx_desc; 869 struct mlx4_wqe_data_seg *data; 870 struct mlx4_en_tx_info *tx_info; 871 u32 __maybe_unused ring_cons; 872 int tx_ind; 873 int nr_txbb; 874 int desc_size; 875 int real_size; 876 u32 index, bf_index; 877 __be32 op_own; 878 int lso_header_size; 879 void *fragptr = NULL; 880 bool bounce = false; 881 bool send_doorbell; 882 bool stop_queue; 883 bool inline_ok; 884 u8 data_offset; 885 bool bf_ok; 886 887 tx_ind = skb_get_queue_mapping(skb); 888 ring = priv->tx_ring[TX][tx_ind]; 889 890 if (unlikely(!priv->port_up)) 891 goto tx_drop; 892 893 /* fetch ring->cons far ahead before needing it to avoid stall */ 894 ring_cons = READ_ONCE(ring->cons); 895 896 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 897 &inline_ok, &fragptr); 898 if (unlikely(!real_size)) 899 goto tx_drop_count; 900 901 /* Align descriptor to TXBB size */ 902 desc_size = ALIGN(real_size, TXBB_SIZE); 903 nr_txbb = desc_size >> LOG_TXBB_SIZE; 904 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 905 if (netif_msg_tx_err(priv)) 906 en_warn(priv, "Oversized header or SG list\n"); 907 goto tx_drop_count; 908 } 909 910 bf_ok = ring->bf_enabled; 911 if (skb_vlan_tag_present(skb)) { 912 u16 vlan_proto; 913 914 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); 915 vlan_proto = be16_to_cpu(skb->vlan_proto); 916 if (vlan_proto == ETH_P_8021AD) 917 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 918 else if (vlan_proto == ETH_P_8021Q) 919 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 920 else 921 qpn_vlan.ins_vlan = 0; 922 bf_ok = false; 923 } 924 925 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 926 927 /* Track current inflight packets for performance analysis */ 928 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 929 (u32)(ring->prod - ring_cons - 1)); 930 931 /* Packet is good - grab an index and transmit it */ 932 index = ring->prod & ring->size_mask; 933 bf_index = ring->prod; 934 935 /* See if we have enough space for whole descriptor TXBB for setting 936 * SW ownership on next descriptor; if not, use a bounce buffer. */ 937 if (likely(index + nr_txbb <= ring->size)) 938 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 939 else { 940 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 941 bounce = true; 942 bf_ok = false; 943 } 944 945 /* Save skb in tx_info ring */ 946 tx_info = &ring->tx_info[index]; 947 tx_info->skb = skb; 948 tx_info->nr_txbb = nr_txbb; 949 950 if (!lso_header_size) { 951 data = &tx_desc->data; 952 data_offset = offsetof(struct mlx4_en_tx_desc, data); 953 } else { 954 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE); 955 956 data = (void *)&tx_desc->lso + lso_align; 957 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; 958 } 959 960 /* valid only for none inline segments */ 961 tx_info->data_offset = data_offset; 962 963 tx_info->inl = inline_ok; 964 965 tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; 966 967 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 968 data += tx_info->nr_maps - 1; 969 970 if (!tx_info->inl) 971 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, 972 lso_header_size, ring->mr_key, 973 tx_info)) 974 goto tx_drop_count; 975 976 /* 977 * For timestamping add flag to skb_shinfo and 978 * set flag for further reference 979 */ 980 tx_info->ts_requested = 0; 981 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 982 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 983 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 984 tx_info->ts_requested = 1; 985 } 986 987 /* Prepare ctrl segement apart opcode+ownership, which depends on 988 * whether LSO is used */ 989 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 990 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 991 if (!skb->encapsulation) 992 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 993 MLX4_WQE_CTRL_TCP_UDP_CSUM); 994 else 995 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 996 ring->tx_csum++; 997 } 998 999 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 1000 struct ethhdr *ethh; 1001 1002 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 1003 * so that VFs and PF can communicate with each other 1004 */ 1005 ethh = (struct ethhdr *)skb->data; 1006 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 1007 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 1008 } 1009 1010 /* Handle LSO (TSO) packets */ 1011 if (lso_header_size) { 1012 int i; 1013 1014 /* Mark opcode as LSO */ 1015 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 1016 ((ring->prod & ring->size) ? 1017 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1018 1019 /* Fill in the LSO prefix */ 1020 tx_desc->lso.mss_hdr_size = cpu_to_be32( 1021 shinfo->gso_size << 16 | lso_header_size); 1022 1023 /* Copy headers; 1024 * note that we already verified that it is linear */ 1025 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 1026 1027 ring->tso_packets++; 1028 1029 i = shinfo->gso_segs; 1030 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 1031 ring->packets += i; 1032 } else { 1033 /* Normal (Non LSO) packet */ 1034 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1035 ((ring->prod & ring->size) ? 1036 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1037 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 1038 ring->packets++; 1039 } 1040 ring->bytes += tx_info->nr_bytes; 1041 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 1042 1043 if (tx_info->inl) 1044 build_inline_wqe(tx_desc, skb, shinfo, fragptr); 1045 1046 if (skb->encapsulation) { 1047 union { 1048 struct iphdr *v4; 1049 struct ipv6hdr *v6; 1050 unsigned char *hdr; 1051 } ip; 1052 u8 proto; 1053 1054 ip.hdr = skb_inner_network_header(skb); 1055 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1056 ip.v6->nexthdr; 1057 1058 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 1059 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 1060 else 1061 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 1062 } 1063 1064 ring->prod += nr_txbb; 1065 1066 /* If we used a bounce buffer then copy descriptor back into place */ 1067 if (unlikely(bounce)) 1068 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 1069 1070 skb_tx_timestamp(skb); 1071 1072 /* Check available TXBBs And 2K spare for prefetch */ 1073 stop_queue = mlx4_en_is_tx_ring_full(ring); 1074 if (unlikely(stop_queue)) { 1075 netif_tx_stop_queue(ring->tx_queue); 1076 ring->queue_stopped++; 1077 } 1078 1079 send_doorbell = __netdev_tx_sent_queue(ring->tx_queue, 1080 tx_info->nr_bytes, 1081 netdev_xmit_more()); 1082 1083 real_size = (real_size / 16) & 0x3f; 1084 1085 bf_ok &= desc_size <= MAX_BF && send_doorbell; 1086 1087 if (bf_ok) 1088 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); 1089 else 1090 qpn_vlan.fence_size = real_size; 1091 1092 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, 1093 op_own, bf_ok, send_doorbell); 1094 1095 if (unlikely(stop_queue)) { 1096 /* If queue was emptied after the if (stop_queue) , and before 1097 * the netif_tx_stop_queue() - need to wake the queue, 1098 * or else it will remain stopped forever. 1099 * Need a memory barrier to make sure ring->cons was not 1100 * updated before queue was stopped. 1101 */ 1102 smp_rmb(); 1103 1104 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1105 netif_tx_wake_queue(ring->tx_queue); 1106 ring->wake_queue++; 1107 } 1108 } 1109 return NETDEV_TX_OK; 1110 1111tx_drop_count: 1112 ring->tx_dropped++; 1113tx_drop: 1114 dev_kfree_skb_any(skb); 1115 return NETDEV_TX_OK; 1116} 1117 1118#define MLX4_EN_XDP_TX_NRTXBB 1 1119#define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ 1120 / 16) & 0x3f) 1121 1122void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 1123 struct mlx4_en_tx_ring *ring) 1124{ 1125 int i; 1126 1127 for (i = 0; i < ring->size; i++) { 1128 struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; 1129 struct mlx4_en_tx_desc *tx_desc = ring->buf + 1130 (i << LOG_TXBB_SIZE); 1131 1132 tx_info->map0_byte_count = PAGE_SIZE; 1133 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; 1134 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); 1135 tx_info->ts_requested = 0; 1136 tx_info->nr_maps = 1; 1137 tx_info->linear = 1; 1138 tx_info->inl = 0; 1139 1140 tx_desc->data.lkey = ring->mr_key; 1141 tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; 1142 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 1143 } 1144} 1145 1146netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 1147 struct mlx4_en_rx_alloc *frame, 1148 struct mlx4_en_priv *priv, unsigned int length, 1149 int tx_ind, bool *doorbell_pending) 1150{ 1151 struct mlx4_en_tx_desc *tx_desc; 1152 struct mlx4_en_tx_info *tx_info; 1153 struct mlx4_wqe_data_seg *data; 1154 struct mlx4_en_tx_ring *ring; 1155 dma_addr_t dma; 1156 __be32 op_own; 1157 int index; 1158 1159 if (unlikely(!priv->port_up)) 1160 goto tx_drop; 1161 1162 ring = priv->tx_ring[TX_XDP][tx_ind]; 1163 1164 if (unlikely(mlx4_en_is_tx_ring_full(ring))) 1165 goto tx_drop_count; 1166 1167 index = ring->prod & ring->size_mask; 1168 tx_info = &ring->tx_info[index]; 1169 1170 /* Track current inflight packets for performance analysis */ 1171 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 1172 (u32)(ring->prod - READ_ONCE(ring->cons) - 1)); 1173 1174 tx_desc = ring->buf + (index << LOG_TXBB_SIZE); 1175 data = &tx_desc->data; 1176 1177 dma = frame->dma; 1178 1179 tx_info->page = frame->page; 1180 frame->page = NULL; 1181 tx_info->map0_dma = dma; 1182 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); 1183 1184 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, 1185 length, PCI_DMA_TODEVICE); 1186 1187 data->addr = cpu_to_be64(dma + frame->page_offset); 1188 dma_wmb(); 1189 data->byte_count = cpu_to_be32(length); 1190 1191 /* tx completion can avoid cache line miss for common cases */ 1192 1193 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 1194 ((ring->prod & ring->size) ? 1195 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 1196 1197 rx_ring->xdp_tx++; 1198 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); 1199 1200 ring->prod += MLX4_EN_XDP_TX_NRTXBB; 1201 1202 /* Ensure new descriptor hits memory 1203 * before setting ownership of this descriptor to HW 1204 */ 1205 dma_wmb(); 1206 tx_desc->ctrl.owner_opcode = op_own; 1207 ring->xmit_more++; 1208 1209 *doorbell_pending = true; 1210 1211 return NETDEV_TX_OK; 1212 1213tx_drop_count: 1214 rx_ring->xdp_tx_full++; 1215 *doorbell_pending = true; 1216tx_drop: 1217 return NETDEV_TX_BUSY; 1218} 1219