1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef RVU_H 12#define RVU_H 13 14#include <linux/pci.h> 15#include "rvu_struct.h" 16#include "common.h" 17#include "mbox.h" 18 19/* PCI device IDs */ 20#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 21 22/* Subsystem Device ID */ 23#define PCI_SUBSYS_DEVID_98XX 0xB100 24#define PCI_SUBSYS_DEVID_96XX 0xB200 25 26/* PCI BAR nos */ 27#define PCI_AF_REG_BAR_NUM 0 28#define PCI_PF_REG_BAR_NUM 2 29#define PCI_MBOX_BAR_NUM 4 30 31#define NAME_SIZE 32 32 33/* PF_FUNC */ 34#define RVU_PFVF_PF_SHIFT 10 35#define RVU_PFVF_PF_MASK 0x3F 36#define RVU_PFVF_FUNC_SHIFT 0 37#define RVU_PFVF_FUNC_MASK 0x3FF 38 39#ifdef CONFIG_DEBUG_FS 40struct dump_ctx { 41 int lf; 42 int id; 43 bool all; 44}; 45 46struct rvu_debugfs { 47 struct dentry *root; 48 struct dentry *cgx_root; 49 struct dentry *cgx; 50 struct dentry *lmac; 51 struct dentry *npa; 52 struct dentry *nix; 53 struct dentry *npc; 54 struct dump_ctx npa_aura_ctx; 55 struct dump_ctx npa_pool_ctx; 56 struct dump_ctx nix_cq_ctx; 57 struct dump_ctx nix_rq_ctx; 58 struct dump_ctx nix_sq_ctx; 59 int npa_qsize_id; 60 int nix_qsize_id; 61}; 62#endif 63 64struct rvu_work { 65 struct work_struct work; 66 struct rvu *rvu; 67 int num_msgs; 68 int up_num_msgs; 69}; 70 71struct rsrc_bmap { 72 unsigned long *bmap; /* Pointer to resource bitmap */ 73 u16 max; /* Max resource id or count */ 74}; 75 76struct rvu_block { 77 struct rsrc_bmap lf; 78 struct admin_queue *aq; /* NIX/NPA AQ */ 79 u16 *fn_map; /* LF to pcifunc mapping */ 80 bool multislot; 81 bool implemented; 82 u8 addr; /* RVU_BLOCK_ADDR_E */ 83 u8 type; /* RVU_BLOCK_TYPE_E */ 84 u8 lfshift; 85 u64 lookup_reg; 86 u64 pf_lfcnt_reg; 87 u64 vf_lfcnt_reg; 88 u64 lfcfg_reg; 89 u64 msixcfg_reg; 90 u64 lfreset_reg; 91 unsigned char name[NAME_SIZE]; 92}; 93 94struct nix_mcast { 95 struct qmem *mce_ctx; 96 struct qmem *mcast_buf; 97 int replay_pkind; 98 int next_free_mce; 99 struct mutex mce_lock; /* Serialize MCE updates */ 100}; 101 102struct nix_mce_list { 103 struct hlist_head head; 104 int count; 105 int max; 106}; 107 108struct npc_mcam { 109 struct rsrc_bmap counters; 110 struct mutex lock; /* MCAM entries and counters update lock */ 111 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 112 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 113 u16 bmap_entries; /* Number of unreserved MCAM entries */ 114 u16 bmap_fcnt; /* MCAM entries free count */ 115 u16 *entry2pfvf_map; 116 u16 *entry2cntr_map; 117 u16 *cntr2pfvf_map; 118 u16 *cntr_refcnt; 119 u8 keysize; /* MCAM keysize 112/224/448 bits */ 120 u8 banks; /* Number of MCAM banks */ 121 u8 banks_per_entry;/* Number of keywords in key */ 122 u16 banksize; /* Number of MCAM entries in each bank */ 123 u16 total_entries; /* Total number of MCAM entries */ 124 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 125 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 126 u16 lprio_count; 127 u16 lprio_start; 128 u16 hprio_count; 129 u16 hprio_end; 130 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 131}; 132 133/* Structure for per RVU func info ie PF/VF */ 134struct rvu_pfvf { 135 bool npalf; /* Only one NPALF per RVU_FUNC */ 136 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 137 u16 sso; 138 u16 ssow; 139 u16 cptlfs; 140 u16 timlfs; 141 u16 cpt1_lfs; 142 u8 cgx_lmac; 143 144 /* Block LF's MSIX vector info */ 145 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 146#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 147 u16 *msix_lfmap; /* Vector to block LF mapping */ 148 149 /* NPA contexts */ 150 struct qmem *aura_ctx; 151 struct qmem *pool_ctx; 152 struct qmem *npa_qints_ctx; 153 unsigned long *aura_bmap; 154 unsigned long *pool_bmap; 155 156 /* NIX contexts */ 157 struct qmem *rq_ctx; 158 struct qmem *sq_ctx; 159 struct qmem *cq_ctx; 160 struct qmem *rss_ctx; 161 struct qmem *cq_ints_ctx; 162 struct qmem *nix_qints_ctx; 163 unsigned long *sq_bmap; 164 unsigned long *rq_bmap; 165 unsigned long *cq_bmap; 166 167 u16 rx_chan_base; 168 u16 tx_chan_base; 169 u8 rx_chan_cnt; /* total number of RX channels */ 170 u8 tx_chan_cnt; /* total number of TX channels */ 171 u16 maxlen; 172 u16 minlen; 173 174 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 175 176 /* Broadcast pkt replication info */ 177 u16 bcast_mce_idx; 178 struct nix_mce_list bcast_mce_list; 179 180 /* VLAN offload */ 181 struct mcam_entry entry; 182 int rxvlan_index; 183 bool rxvlan; 184 185 bool cgx_in_use; /* this PF/VF using CGX? */ 186 int cgx_users; /* number of cgx users - used only by PFs */ 187 188 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 189}; 190 191struct nix_txsch { 192 struct rsrc_bmap schq; 193 u8 lvl; 194#define NIX_TXSCHQ_FREE BIT_ULL(1) 195#define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 196#define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 197#define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 198#define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 199#define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 200 u32 *pfvf_map; 201}; 202 203struct nix_mark_format { 204 u8 total; 205 u8 in_use; 206 u32 *cfg; 207}; 208 209struct npc_pkind { 210 struct rsrc_bmap rsrc; 211 u32 *pfchan_map; 212}; 213 214struct nix_flowkey { 215#define NIX_FLOW_KEY_ALG_MAX 32 216 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 217 int in_use; 218}; 219 220struct nix_lso { 221 u8 total; 222 u8 in_use; 223}; 224 225struct nix_hw { 226 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 227 struct nix_mcast mcast; 228 struct nix_flowkey flowkey; 229 struct nix_mark_format mark_format; 230 struct nix_lso lso; 231}; 232 233/* RVU block's capabilities or functionality, 234 * which vary by silicon version/skew. 235 */ 236struct hw_cap { 237 /* Transmit side supported functionality */ 238 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 239 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 240 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 241 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 242 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 243 bool nix_shaping; /* Is shaping and coloring supported */ 244 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 245 bool nix_rx_multicast; /* Rx packet replication support */ 246}; 247 248struct rvu_hwinfo { 249 u8 total_pfs; /* MAX RVU PFs HW supports */ 250 u16 total_vfs; /* Max RVU VFs HW supports */ 251 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 252 u8 cgx; 253 u8 lmac_per_cgx; 254 u8 cgx_links; 255 u8 lbk_links; 256 u8 sdp_links; 257 u8 npc_kpus; /* No of parser units */ 258 259 struct hw_cap cap; 260 struct rvu_block block[BLK_COUNT]; /* Block info */ 261 struct nix_hw *nix0; 262 struct npc_pkind pkind; 263 struct npc_mcam mcam; 264}; 265 266struct mbox_wq_info { 267 struct otx2_mbox mbox; 268 struct rvu_work *mbox_wrk; 269 270 struct otx2_mbox mbox_up; 271 struct rvu_work *mbox_wrk_up; 272 273 struct workqueue_struct *mbox_wq; 274}; 275 276struct rvu_fwdata { 277#define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 278#define RVU_FWDATA_VERSION 0x0001 279 u32 header_magic; 280 u32 version; /* version id */ 281 282 /* MAC address */ 283#define PF_MACNUM_MAX 32 284#define VF_MACNUM_MAX 256 285 u64 pf_macs[PF_MACNUM_MAX]; 286 u64 vf_macs[VF_MACNUM_MAX]; 287 u64 sclk; 288 u64 rclk; 289 u64 mcam_addr; 290 u64 mcam_sz; 291 u64 msixtr_base; 292#define FWDATA_RESERVED_MEM 1023 293 u64 reserved[FWDATA_RESERVED_MEM]; 294}; 295 296struct ptp; 297 298/* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 299 * source where it came from. 300 */ 301struct npc_kpu_profile_adapter { 302 const char *name; 303 u64 version; 304 const struct npc_lt_def_cfg *lt_def; 305 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 306 const struct npc_kpu_profile *kpu; /* array[kpus] */ 307 const struct npc_mcam_kex *mkex; 308 size_t pkinds; 309 size_t kpus; 310}; 311 312struct rvu { 313 void __iomem *afreg_base; 314 void __iomem *pfreg_base; 315 struct pci_dev *pdev; 316 struct device *dev; 317 struct rvu_hwinfo *hw; 318 struct rvu_pfvf *pf; 319 struct rvu_pfvf *hwvf; 320 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 321 int vfs; /* Number of VFs attached to RVU */ 322 323 /* Mbox */ 324 struct mbox_wq_info afpf_wq_info; 325 struct mbox_wq_info afvf_wq_info; 326 327 /* PF FLR */ 328 struct rvu_work *flr_wrk; 329 struct workqueue_struct *flr_wq; 330 struct mutex flr_lock; /* Serialize FLRs */ 331 332 /* MSI-X */ 333 u16 num_vec; 334 char *irq_name; 335 bool *irq_allocated; 336 dma_addr_t msix_base_iova; 337 u64 msixtr_base_phy; /* Register reset value */ 338 339 /* CGX */ 340#define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 341 u8 cgx_mapped_pfs; 342 u8 cgx_cnt_max; /* CGX port count max */ 343 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 344 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 345 * every cgx lmac port 346 */ 347 unsigned long pf_notify_bmap; /* Flags for PF notification */ 348 void **cgx_idmap; /* cgx id to cgx data map table */ 349 struct work_struct cgx_evh_work; 350 struct workqueue_struct *cgx_evh_wq; 351 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 352 struct list_head cgx_evq_head; /* cgx event queue head */ 353 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 354 355 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 356 357 /* Firmware data */ 358 struct rvu_fwdata *fwdata; 359 360 /* NPC KPU data */ 361 struct npc_kpu_profile_adapter kpu; 362 363 struct ptp *ptp; 364 365#ifdef CONFIG_DEBUG_FS 366 struct rvu_debugfs rvu_dbg; 367#endif 368}; 369 370static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 371{ 372 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 373} 374 375static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 376{ 377 return readq(rvu->afreg_base + ((block << 28) | offset)); 378} 379 380static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 381{ 382 writeq(val, rvu->pfreg_base + offset); 383} 384 385static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 386{ 387 return readq(rvu->pfreg_base + offset); 388} 389 390/* Silicon revisions */ 391static inline bool is_rvu_96xx_A0(struct rvu *rvu) 392{ 393 struct pci_dev *pdev = rvu->pdev; 394 395 return (pdev->revision == 0x00) && 396 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 397} 398 399static inline bool is_rvu_96xx_B0(struct rvu *rvu) 400{ 401 struct pci_dev *pdev = rvu->pdev; 402 403 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 404 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 405} 406 407static inline bool is_rvu_supports_nix1(struct rvu *rvu) 408{ 409 struct pci_dev *pdev = rvu->pdev; 410 411 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 412 return true; 413 414 return false; 415} 416 417/* Function Prototypes 418 * RVU 419 */ 420static inline int is_afvf(u16 pcifunc) 421{ 422 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 423} 424 425static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 426{ 427 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 428 (rvu->fwdata->version == RVU_FWDATA_VERSION); 429} 430 431int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 432int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 433void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 434int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 435int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 436bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 437u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 438int rvu_get_pf(u16 pcifunc); 439struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 440void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 441bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 442bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 443int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 444int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 445int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 446int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 447 448/* RVU HW reg validation */ 449enum regmap_block { 450 TXSCHQ_HWREGMAP = 0, 451 MAX_HWREGMAP, 452}; 453 454bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 455 456/* NPA/NIX AQ APIs */ 457int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 458 int qsize, int inst_size, int res_size); 459void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 460 461/* CGX APIs */ 462static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 463{ 464 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 465} 466 467static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 468{ 469 *cgx_id = (map >> 4) & 0xF; 470 *lmac_id = (map & 0xF); 471} 472 473#define M(_name, _id, fn_name, req, rsp) \ 474int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 475MBOX_MESSAGES 476#undef M 477 478int rvu_cgx_init(struct rvu *rvu); 479int rvu_cgx_exit(struct rvu *rvu); 480void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 481int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 482void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 483int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 484int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 485 int rxtxflag, u64 *stat); 486/* NPA APIs */ 487int rvu_npa_init(struct rvu *rvu); 488void rvu_npa_freemem(struct rvu *rvu); 489void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 490int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 491 struct npa_aq_enq_rsp *rsp); 492 493/* NIX APIs */ 494bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 495int rvu_nix_init(struct rvu *rvu); 496int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 497 int blkaddr, u32 cfg); 498void rvu_nix_freemem(struct rvu *rvu); 499int rvu_get_nixlf_count(struct rvu *rvu); 500void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 501int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 502int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); 503 504/* NPC APIs */ 505int rvu_npc_init(struct rvu *rvu); 506void rvu_npc_freemem(struct rvu *rvu); 507int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 508void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 509int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 510void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 511 int nixlf, u64 chan, u8 *mac_addr); 512void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 513 int nixlf, u64 chan, bool allmulti); 514void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 515void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 516void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 517 int nixlf, u64 chan); 518void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable); 519int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf); 520void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 521void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 522void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 523void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 524 int group, int alg_idx, int mcam_index); 525void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 526 int blkaddr, int *alloc_cnt, 527 int *enable_cnt); 528void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 529 int blkaddr, int *alloc_cnt, 530 int *enable_cnt); 531 532#ifdef CONFIG_DEBUG_FS 533void rvu_dbg_init(struct rvu *rvu); 534void rvu_dbg_exit(struct rvu *rvu); 535#else 536static inline void rvu_dbg_init(struct rvu *rvu) {} 537static inline void rvu_dbg_exit(struct rvu *rvu) {} 538#endif 539#endif /* RVU_H */ 540