1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef MBOX_H 12#define MBOX_H 13 14#include <linux/etherdevice.h> 15#include <linux/sizes.h> 16 17#include "rvu_struct.h" 18#include "common.h" 19 20#define MBOX_SIZE SZ_64K 21 22/* AF/PF: PF initiated, PF/VF VF initiated */ 23#define MBOX_DOWN_RX_START 0 24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27/* AF/PF: AF initiated, PF/VF PF initiated */ 28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29#define MBOX_UP_RX_SIZE SZ_1K 30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31#define MBOX_UP_TX_SIZE SZ_1K 32 33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34# error "incorrect mailbox area sizes" 35#endif 36 37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39#define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */ 40 41#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43/* Mailbox directions */ 44#define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46#define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60}; 61 62struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74}; 75 76/* Header which preceeds all mbox messages */ 77struct mbox_hdr { 78 u64 msg_size; /* Total msgs size embedded */ 79 u16 num_msgs; /* No of msgs embedded */ 80}; 81 82/* Header which preceeds every msg and is also part of it */ 83struct mbox_msghdr { 84 u16 pcifunc; /* Who's sending this msg */ 85 u16 id; /* Mbox message ID */ 86#define OTX2_MBOX_REQ_SIG (0xdead) 87#define OTX2_MBOX_RSP_SIG (0xbeef) 88 u16 sig; /* Signature, for validating corrupted msgs */ 89#define OTX2_MBOX_VERSION (0x0001) 90 u16 ver; /* Version of msg's structure for this ID */ 91 u16 next_msgoff; /* Offset of next msg within mailbox region */ 92 int rc; /* Msg process'ed response code */ 93}; 94 95void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 96void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97void otx2_mbox_destroy(struct otx2_mbox *mbox); 98int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 99 struct pci_dev *pdev, void __force *reg_base, 100 int direction, int ndevs); 101void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 102int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 103int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 104struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 105 int size, int size_rsp); 106struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 107 struct mbox_msghdr *msg); 108int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 109int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 110 u16 pcifunc, u16 id); 111bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 112const char *otx2_mbox_id2name(u16 id); 113static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 114 int devid, int size) 115{ 116 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 117} 118 119/* Mailbox message types */ 120#define MBOX_MSG_MASK 0xFFFF 121#define MBOX_MSG_INVALID 0xFFFE 122#define MBOX_MSG_MAX 0xFFFF 123 124#define MBOX_MESSAGES \ 125/* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 126M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 127M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 128M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 129M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 130M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 131M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 132M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 133/* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 134M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 135M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 136M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 137M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 138 cgx_mac_addr_set_or_get) \ 139M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 140 cgx_mac_addr_set_or_get) \ 141M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 142M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 143M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 144M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 145M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 146M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 147M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 148M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 149M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 150M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 151 cgx_pause_frm_cfg) \ 152/* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 153M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 154 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 155M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 156M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 157M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 158/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 159/* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 160/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 161/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 162M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 163 npc_mcam_alloc_entry_rsp) \ 164M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 165 npc_mcam_free_entry_req, msg_rsp) \ 166M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 167 npc_mcam_write_entry_req, msg_rsp) \ 168M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 169 npc_mcam_ena_dis_entry_req, msg_rsp) \ 170M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 171 npc_mcam_ena_dis_entry_req, msg_rsp) \ 172M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 173 npc_mcam_shift_entry_rsp) \ 174M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 175 npc_mcam_alloc_counter_req, \ 176 npc_mcam_alloc_counter_rsp) \ 177M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 178 npc_mcam_oper_counter_req, msg_rsp) \ 179M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 180 npc_mcam_unmap_counter_req, msg_rsp) \ 181M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 182 npc_mcam_oper_counter_req, msg_rsp) \ 183M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 184 npc_mcam_oper_counter_req, \ 185 npc_mcam_oper_counter_rsp) \ 186M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 187 npc_mcam_alloc_and_write_entry_req, \ 188 npc_mcam_alloc_and_write_entry_rsp) \ 189M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 190 msg_req, npc_get_kex_cfg_rsp) \ 191/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 192M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 193 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 194M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \ 195M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 196M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 197 hwctx_disable_req, msg_rsp) \ 198M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 199 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 200M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 201M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 202M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 203M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \ 204M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 205 nix_rss_flowkey_cfg, \ 206 nix_rss_flowkey_cfg_rsp) \ 207M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 208M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 209M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 210M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 211M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 212M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 213 nix_mark_format_cfg, \ 214 nix_mark_format_cfg_rsp) \ 215M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 216M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 217 nix_lso_format_cfg, \ 218 nix_lso_format_cfg_rsp) \ 219M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \ 220M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 221M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 222M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 223 nix_bp_cfg_rsp) \ 224M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 225M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 226 227/* Messages initiated by AF (range 0xC00 - 0xDFF) */ 228#define MBOX_UP_CGX_MESSAGES \ 229M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 230 231enum { 232#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 233MBOX_MESSAGES 234MBOX_UP_CGX_MESSAGES 235#undef M 236}; 237 238/* Mailbox message formats */ 239 240#define RVU_DEFAULT_PF_FUNC 0xFFFF 241 242/* Generic request msg used for those mbox messages which 243 * don't send any data in the request. 244 */ 245struct msg_req { 246 struct mbox_msghdr hdr; 247}; 248 249/* Generic rsponse msg used a ack or response for those mbox 250 * messages which doesn't have a specific rsp msg format. 251 */ 252struct msg_rsp { 253 struct mbox_msghdr hdr; 254}; 255 256/* RVU mailbox error codes 257 * Range 256 - 300. 258 */ 259enum rvu_af_status { 260 RVU_INVALID_VF_ID = -256, 261}; 262 263struct ready_msg_rsp { 264 struct mbox_msghdr hdr; 265 u16 sclk_freq; /* SCLK frequency (in MHz) */ 266 u16 rclk_freq; /* RCLK frequency (in MHz) */ 267}; 268 269/* Structure for requesting resource provisioning. 270 * 'modify' flag to be used when either requesting more 271 * or to detach partial of a cetain resource type. 272 * Rest of the fields specify how many of what type to 273 * be attached. 274 */ 275struct rsrc_attach { 276 struct mbox_msghdr hdr; 277 u8 modify:1; 278 u8 npalf:1; 279 u8 nixlf:1; 280 u16 sso; 281 u16 ssow; 282 u16 timlfs; 283 u16 cptlfs; 284}; 285 286/* Structure for relinquishing resources. 287 * 'partial' flag to be used when relinquishing all resources 288 * but only of a certain type. If not set, all resources of all 289 * types provisioned to the RVU function will be detached. 290 */ 291struct rsrc_detach { 292 struct mbox_msghdr hdr; 293 u8 partial:1; 294 u8 npalf:1; 295 u8 nixlf:1; 296 u8 sso:1; 297 u8 ssow:1; 298 u8 timlfs:1; 299 u8 cptlfs:1; 300}; 301 302#define MSIX_VECTOR_INVALID 0xFFFF 303#define MAX_RVU_BLKLF_CNT 256 304 305struct msix_offset_rsp { 306 struct mbox_msghdr hdr; 307 u16 npa_msixoff; 308 u16 nix_msixoff; 309 u8 sso; 310 u8 ssow; 311 u8 timlfs; 312 u8 cptlfs; 313 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 314 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 315 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 316 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 317}; 318 319struct get_hw_cap_rsp { 320 struct mbox_msghdr hdr; 321 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 322 u8 nix_shaping; /* Is shaping and coloring supported */ 323}; 324 325/* CGX mbox message formats */ 326 327struct cgx_stats_rsp { 328 struct mbox_msghdr hdr; 329#define CGX_RX_STATS_COUNT 13 330#define CGX_TX_STATS_COUNT 18 331 u64 rx_stats[CGX_RX_STATS_COUNT]; 332 u64 tx_stats[CGX_TX_STATS_COUNT]; 333}; 334 335/* Structure for requesting the operation for 336 * setting/getting mac address in the CGX interface 337 */ 338struct cgx_mac_addr_set_or_get { 339 struct mbox_msghdr hdr; 340 u8 mac_addr[ETH_ALEN]; 341}; 342 343struct cgx_link_user_info { 344 uint64_t link_up:1; 345 uint64_t full_duplex:1; 346 uint64_t lmac_type_id:4; 347 uint64_t speed:20; /* speed in Mbps */ 348#define LMACTYPE_STR_LEN 16 349 char lmac_type[LMACTYPE_STR_LEN]; 350}; 351 352struct cgx_link_info_msg { 353 struct mbox_msghdr hdr; 354 struct cgx_link_user_info link_info; 355}; 356 357struct cgx_pause_frm_cfg { 358 struct mbox_msghdr hdr; 359 u8 set; 360 /* set = 1 if the request is to config pause frames */ 361 /* set = 0 if the request is to fetch pause frames config */ 362 u8 rx_pause; 363 u8 tx_pause; 364}; 365 366/* NPA mbox message formats */ 367 368/* NPA mailbox error codes 369 * Range 301 - 400. 370 */ 371enum npa_af_status { 372 NPA_AF_ERR_PARAM = -301, 373 NPA_AF_ERR_AQ_FULL = -302, 374 NPA_AF_ERR_AQ_ENQUEUE = -303, 375 NPA_AF_ERR_AF_LF_INVALID = -304, 376 NPA_AF_ERR_AF_LF_ALLOC = -305, 377 NPA_AF_ERR_LF_RESET = -306, 378}; 379 380/* For NPA LF context alloc and init */ 381struct npa_lf_alloc_req { 382 struct mbox_msghdr hdr; 383 int node; 384 int aura_sz; /* No of auras */ 385 u32 nr_pools; /* No of pools */ 386 u64 way_mask; 387}; 388 389struct npa_lf_alloc_rsp { 390 struct mbox_msghdr hdr; 391 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 392 u32 stack_pg_bytes; /* Size of stack page */ 393 u16 qints; /* NPA_AF_CONST::QINTS */ 394}; 395 396/* NPA AQ enqueue msg */ 397struct npa_aq_enq_req { 398 struct mbox_msghdr hdr; 399 u32 aura_id; 400 u8 ctype; 401 u8 op; 402 union { 403 /* Valid when op == WRITE/INIT and ctype == AURA. 404 * LF fills the pool_id in aura.pool_addr. AF will translate 405 * the pool_id to pool context pointer. 406 */ 407 struct npa_aura_s aura; 408 /* Valid when op == WRITE/INIT and ctype == POOL */ 409 struct npa_pool_s pool; 410 }; 411 /* Mask data when op == WRITE (1=write, 0=don't write) */ 412 union { 413 /* Valid when op == WRITE and ctype == AURA */ 414 struct npa_aura_s aura_mask; 415 /* Valid when op == WRITE and ctype == POOL */ 416 struct npa_pool_s pool_mask; 417 }; 418}; 419 420struct npa_aq_enq_rsp { 421 struct mbox_msghdr hdr; 422 union { 423 /* Valid when op == READ and ctype == AURA */ 424 struct npa_aura_s aura; 425 /* Valid when op == READ and ctype == POOL */ 426 struct npa_pool_s pool; 427 }; 428}; 429 430/* Disable all contexts of type 'ctype' */ 431struct hwctx_disable_req { 432 struct mbox_msghdr hdr; 433 u8 ctype; 434}; 435 436/* NIX mbox message formats */ 437 438/* NIX mailbox error codes 439 * Range 401 - 500. 440 */ 441enum nix_af_status { 442 NIX_AF_ERR_PARAM = -401, 443 NIX_AF_ERR_AQ_FULL = -402, 444 NIX_AF_ERR_AQ_ENQUEUE = -403, 445 NIX_AF_ERR_AF_LF_INVALID = -404, 446 NIX_AF_ERR_AF_LF_ALLOC = -405, 447 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 448 NIX_AF_ERR_TLX_INVALID = -407, 449 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 450 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 451 NIX_AF_ERR_FRS_INVALID = -410, 452 NIX_AF_ERR_RX_LINK_INVALID = -411, 453 NIX_AF_INVAL_TXSCHQ_CFG = -412, 454 NIX_AF_SMQ_FLUSH_FAILED = -413, 455 NIX_AF_ERR_LF_RESET = -414, 456 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 457 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 458 NIX_AF_ERR_MARK_CFG_FAIL = -417, 459 NIX_AF_ERR_LSO_CFG_FAIL = -418, 460 NIX_AF_INVAL_NPA_PF_FUNC = -419, 461 NIX_AF_INVAL_SSO_PF_FUNC = -420, 462}; 463 464/* For NIX LF context alloc and init */ 465struct nix_lf_alloc_req { 466 struct mbox_msghdr hdr; 467 int node; 468 u32 rq_cnt; /* No of receive queues */ 469 u32 sq_cnt; /* No of send queues */ 470 u32 cq_cnt; /* No of completion queues */ 471 u8 xqe_sz; 472 u16 rss_sz; 473 u8 rss_grps; 474 u16 npa_func; 475 u16 sso_func; 476 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 477 u64 way_mask; 478}; 479 480struct nix_lf_alloc_rsp { 481 struct mbox_msghdr hdr; 482 u16 sqb_size; 483 u16 rx_chan_base; 484 u16 tx_chan_base; 485 u8 rx_chan_cnt; /* total number of RX channels */ 486 u8 tx_chan_cnt; /* total number of TX channels */ 487 u8 lso_tsov4_idx; 488 u8 lso_tsov6_idx; 489 u8 mac_addr[ETH_ALEN]; 490 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 491 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 492 u16 cints; /* NIX_AF_CONST2::CINTS */ 493 u16 qints; /* NIX_AF_CONST2::QINTS */ 494}; 495 496/* NIX AQ enqueue msg */ 497struct nix_aq_enq_req { 498 struct mbox_msghdr hdr; 499 u32 qidx; 500 u8 ctype; 501 u8 op; 502 union { 503 struct nix_rq_ctx_s rq; 504 struct nix_sq_ctx_s sq; 505 struct nix_cq_ctx_s cq; 506 struct nix_rsse_s rss; 507 struct nix_rx_mce_s mce; 508 }; 509 union { 510 struct nix_rq_ctx_s rq_mask; 511 struct nix_sq_ctx_s sq_mask; 512 struct nix_cq_ctx_s cq_mask; 513 struct nix_rsse_s rss_mask; 514 struct nix_rx_mce_s mce_mask; 515 }; 516}; 517 518struct nix_aq_enq_rsp { 519 struct mbox_msghdr hdr; 520 union { 521 struct nix_rq_ctx_s rq; 522 struct nix_sq_ctx_s sq; 523 struct nix_cq_ctx_s cq; 524 struct nix_rsse_s rss; 525 struct nix_rx_mce_s mce; 526 }; 527}; 528 529/* Tx scheduler/shaper mailbox messages */ 530 531#define MAX_TXSCHQ_PER_FUNC 128 532 533struct nix_txsch_alloc_req { 534 struct mbox_msghdr hdr; 535 /* Scheduler queue count request at each level */ 536 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 537 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 538}; 539 540struct nix_txsch_alloc_rsp { 541 struct mbox_msghdr hdr; 542 /* Scheduler queue count allocated at each level */ 543 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 544 u16 schq[NIX_TXSCH_LVL_CNT]; 545 /* Scheduler queue list allocated at each level */ 546 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 547 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 548 u8 aggr_level; /* Traffic aggregation scheduler level */ 549 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 550 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 551}; 552 553struct nix_txsch_free_req { 554 struct mbox_msghdr hdr; 555#define TXSCHQ_FREE_ALL BIT_ULL(0) 556 u16 flags; 557 /* Scheduler queue level to be freed */ 558 u16 schq_lvl; 559 /* List of scheduler queues to be freed */ 560 u16 schq; 561}; 562 563struct nix_txschq_config { 564 struct mbox_msghdr hdr; 565 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 566#define TXSCHQ_IDX_SHIFT 16 567#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 568#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 569 u8 num_regs; 570#define MAX_REGS_PER_MBOX_MSG 20 571 u64 reg[MAX_REGS_PER_MBOX_MSG]; 572 u64 regval[MAX_REGS_PER_MBOX_MSG]; 573}; 574 575struct nix_vtag_config { 576 struct mbox_msghdr hdr; 577 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 578 u8 vtag_size; 579 /* cfg_type is '0' for tx vlan cfg 580 * cfg_type is '1' for rx vlan cfg 581 */ 582 u8 cfg_type; 583 union { 584 /* valid when cfg_type is '0' */ 585 struct { 586 /* tx vlan0 tag(C-VLAN) */ 587 u64 vlan0; 588 /* tx vlan1 tag(S-VLAN) */ 589 u64 vlan1; 590 /* insert tx vlan tag */ 591 u8 insert_vlan :1; 592 /* insert tx double vlan tag */ 593 u8 double_vlan :1; 594 } tx; 595 596 /* valid when cfg_type is '1' */ 597 struct { 598 /* rx vtag type index, valid values are in 0..7 range */ 599 u8 vtag_type; 600 /* rx vtag strip */ 601 u8 strip_vtag :1; 602 /* rx vtag capture */ 603 u8 capture_vtag :1; 604 } rx; 605 }; 606}; 607 608struct nix_rss_flowkey_cfg { 609 struct mbox_msghdr hdr; 610 int mcam_index; /* MCAM entry index to modify */ 611#define NIX_FLOW_KEY_TYPE_PORT BIT(0) 612#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 613#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 614#define NIX_FLOW_KEY_TYPE_TCP BIT(3) 615#define NIX_FLOW_KEY_TYPE_UDP BIT(4) 616#define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 617#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 618#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 619#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 620#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 621#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 622#define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 623#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 624#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 625#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 626#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 627#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 628#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 629#define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 630 u32 flowkey_cfg; /* Flowkey types selected */ 631 u8 group; /* RSS context or group */ 632}; 633 634struct nix_rss_flowkey_cfg_rsp { 635 struct mbox_msghdr hdr; 636 u8 alg_idx; /* Selected algo index */ 637}; 638 639struct nix_set_mac_addr { 640 struct mbox_msghdr hdr; 641 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 642}; 643 644struct nix_get_mac_addr_rsp { 645 struct mbox_msghdr hdr; 646 u8 mac_addr[ETH_ALEN]; 647}; 648 649struct nix_mark_format_cfg { 650 struct mbox_msghdr hdr; 651 u8 offset; 652 u8 y_mask; 653 u8 y_val; 654 u8 r_mask; 655 u8 r_val; 656}; 657 658struct nix_mark_format_cfg_rsp { 659 struct mbox_msghdr hdr; 660 u8 mark_format_idx; 661}; 662 663struct nix_rx_mode { 664 struct mbox_msghdr hdr; 665#define NIX_RX_MODE_UCAST BIT(0) 666#define NIX_RX_MODE_PROMISC BIT(1) 667#define NIX_RX_MODE_ALLMULTI BIT(2) 668 u16 mode; 669}; 670 671struct nix_rx_cfg { 672 struct mbox_msghdr hdr; 673#define NIX_RX_OL3_VERIFY BIT(0) 674#define NIX_RX_OL4_VERIFY BIT(1) 675 u8 len_verify; /* Outer L3/L4 len check */ 676#define NIX_RX_CSUM_OL4_VERIFY BIT(0) 677 u8 csum_verify; /* Outer L4 checksum verification */ 678}; 679 680struct nix_frs_cfg { 681 struct mbox_msghdr hdr; 682 u8 update_smq; /* Update SMQ's min/max lens */ 683 u8 update_minlen; /* Set minlen also */ 684 u8 sdp_link; /* Set SDP RX link */ 685 u16 maxlen; 686 u16 minlen; 687}; 688 689struct nix_lso_format_cfg { 690 struct mbox_msghdr hdr; 691 u64 field_mask; 692#define NIX_LSO_FIELD_MAX 8 693 u64 fields[NIX_LSO_FIELD_MAX]; 694}; 695 696struct nix_lso_format_cfg_rsp { 697 struct mbox_msghdr hdr; 698 u8 lso_format_idx; 699}; 700 701struct nix_bp_cfg_req { 702 struct mbox_msghdr hdr; 703 u16 chan_base; /* Starting channel number */ 704 u8 chan_cnt; /* Number of channels */ 705 u8 bpid_per_chan; 706 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 707 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 708}; 709 710/* PF can be mapped to either CGX or LBK interface, 711 * so maximum 64 channels are possible. 712 */ 713#define NIX_MAX_BPID_CHAN 64 714struct nix_bp_cfg_rsp { 715 struct mbox_msghdr hdr; 716 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 717 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 718}; 719 720/* NPC mbox message structs */ 721 722#define NPC_MCAM_ENTRY_INVALID 0xFFFF 723#define NPC_MCAM_INVALID_MAP 0xFFFF 724 725/* NPC mailbox error codes 726 * Range 701 - 800. 727 */ 728enum npc_af_status { 729 NPC_MCAM_INVALID_REQ = -701, 730 NPC_MCAM_ALLOC_DENIED = -702, 731 NPC_MCAM_ALLOC_FAILED = -703, 732 NPC_MCAM_PERM_DENIED = -704, 733}; 734 735struct npc_mcam_alloc_entry_req { 736 struct mbox_msghdr hdr; 737#define NPC_MAX_NONCONTIG_ENTRIES 256 738 u8 contig; /* Contiguous entries ? */ 739#define NPC_MCAM_ANY_PRIO 0 740#define NPC_MCAM_LOWER_PRIO 1 741#define NPC_MCAM_HIGHER_PRIO 2 742 u8 priority; /* Lower or higher w.r.t ref_entry */ 743 u16 ref_entry; 744 u16 count; /* Number of entries requested */ 745}; 746 747struct npc_mcam_alloc_entry_rsp { 748 struct mbox_msghdr hdr; 749 u16 entry; /* Entry allocated or start index if contiguous. 750 * Invalid incase of non-contiguous. 751 */ 752 u16 count; /* Number of entries allocated */ 753 u16 free_count; /* Number of entries available */ 754 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 755}; 756 757struct npc_mcam_free_entry_req { 758 struct mbox_msghdr hdr; 759 u16 entry; /* Entry index to be freed */ 760 u8 all; /* If all entries allocated to this PFVF to be freed */ 761}; 762 763struct mcam_entry { 764#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 765 u64 kw[NPC_MAX_KWS_IN_KEY]; 766 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 767 u64 action; 768 u64 vtag_action; 769}; 770 771struct npc_mcam_write_entry_req { 772 struct mbox_msghdr hdr; 773 struct mcam_entry entry_data; 774 u16 entry; /* MCAM entry to write this match key */ 775 u16 cntr; /* Counter for this MCAM entry */ 776 u8 intf; /* Rx or Tx interface */ 777 u8 enable_entry;/* Enable this MCAM entry ? */ 778 u8 set_cntr; /* Set counter for this entry ? */ 779}; 780 781/* Enable/Disable a given entry */ 782struct npc_mcam_ena_dis_entry_req { 783 struct mbox_msghdr hdr; 784 u16 entry; 785}; 786 787struct npc_mcam_shift_entry_req { 788 struct mbox_msghdr hdr; 789#define NPC_MCAM_MAX_SHIFTS 64 790 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 791 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 792 u16 shift_count; /* Number of entries to shift */ 793}; 794 795struct npc_mcam_shift_entry_rsp { 796 struct mbox_msghdr hdr; 797 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 798}; 799 800struct npc_mcam_alloc_counter_req { 801 struct mbox_msghdr hdr; 802 u8 contig; /* Contiguous counters ? */ 803#define NPC_MAX_NONCONTIG_COUNTERS 64 804 u16 count; /* Number of counters requested */ 805}; 806 807struct npc_mcam_alloc_counter_rsp { 808 struct mbox_msghdr hdr; 809 u16 cntr; /* Counter allocated or start index if contiguous. 810 * Invalid incase of non-contiguous. 811 */ 812 u16 count; /* Number of counters allocated */ 813 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 814}; 815 816struct npc_mcam_oper_counter_req { 817 struct mbox_msghdr hdr; 818 u16 cntr; /* Free a counter or clear/fetch it's stats */ 819}; 820 821struct npc_mcam_oper_counter_rsp { 822 struct mbox_msghdr hdr; 823 u64 stat; /* valid only while fetching counter's stats */ 824}; 825 826struct npc_mcam_unmap_counter_req { 827 struct mbox_msghdr hdr; 828 u16 cntr; 829 u16 entry; /* Entry and counter to be unmapped */ 830 u8 all; /* Unmap all entries using this counter ? */ 831}; 832 833struct npc_mcam_alloc_and_write_entry_req { 834 struct mbox_msghdr hdr; 835 struct mcam_entry entry_data; 836 u16 ref_entry; 837 u8 priority; /* Lower or higher w.r.t ref_entry */ 838 u8 intf; /* Rx or Tx interface */ 839 u8 enable_entry;/* Enable this MCAM entry ? */ 840 u8 alloc_cntr; /* Allocate counter and map ? */ 841}; 842 843struct npc_mcam_alloc_and_write_entry_rsp { 844 struct mbox_msghdr hdr; 845 u16 entry; 846 u16 cntr; 847}; 848 849struct npc_get_kex_cfg_rsp { 850 struct mbox_msghdr hdr; 851 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 852 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 853#define NPC_MAX_INTF 2 854#define NPC_MAX_LID 8 855#define NPC_MAX_LT 16 856#define NPC_MAX_LD 2 857#define NPC_MAX_LFL 16 858 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 859 u64 kex_ld_flags[NPC_MAX_LD]; 860 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 861 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 862 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 863 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 864#define MKEX_NAME_LEN 128 865 u8 mkex_pfl_name[MKEX_NAME_LEN]; 866}; 867 868enum ptp_op { 869 PTP_OP_ADJFINE = 0, 870 PTP_OP_GET_CLOCK = 1, 871}; 872 873struct ptp_req { 874 struct mbox_msghdr hdr; 875 u8 op; 876 s64 scaled_ppm; 877}; 878 879struct ptp_rsp { 880 struct mbox_msghdr hdr; 881 u64 clk; 882}; 883 884#endif /* MBOX_H */ 885