1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef CGX_H 12#define CGX_H 13 14#include "mbox.h" 15#include "cgx_fw_if.h" 16 17 /* PCI device IDs */ 18#define PCI_DEVID_OCTEONTX2_CGX 0xA059 19 20/* PCI BAR nos */ 21#define PCI_CFG_REG_BAR_NUM 0 22 23#define CGX_ID_MASK 0x7 24#define MAX_LMAC_PER_CGX 4 25#define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */ 26#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX) 27 28/* Registers */ 29#define CGXX_CMRX_CFG 0x00 30#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59) 31#define CMR_P2X_SEL_SHIFT 59ULL 32#define CMR_P2X_SEL_NIX0 1ULL 33#define CMR_P2X_SEL_NIX1 2ULL 34#define DATA_PKT_TX_EN BIT_ULL(53) 35#define DATA_PKT_RX_EN BIT_ULL(54) 36#define CGX_LMAC_TYPE_SHIFT 40 37#define CGX_LMAC_TYPE_MASK 0xF 38#define CGXX_CMRX_INT 0x040 39#define FW_CGX_INT BIT_ULL(1) 40#define CGXX_CMRX_INT_ENA_W1S 0x058 41#define CGXX_CMRX_RX_ID_MAP 0x060 42#define CGXX_CMRX_RX_STAT0 0x070 43#define CGXX_CMRX_RX_LMACS 0x128 44#define CGXX_CMRX_RX_DMAC_CTL0 0x1F8 45#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) 46#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3) 47#define CGX_DMAC_MCAST_MODE BIT_ULL(1) 48#define CGX_DMAC_BCAST_MODE BIT_ULL(0) 49#define CGXX_CMRX_RX_DMAC_CAM0 0x200 50#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48) 51#define CGXX_CMRX_RX_DMAC_CAM1 0x400 52#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) 53#define CGXX_CMRX_TX_STAT0 0x700 54#define CGXX_SCRATCH0_REG 0x1050 55#define CGXX_SCRATCH1_REG 0x1058 56#define CGX_CONST 0x2000 57#define CGXX_SPUX_CONTROL1 0x10000 58#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14) 59#define CGXX_GMP_PCS_MRX_CTL 0x30000 60#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14) 61 62#define CGXX_SMUX_RX_FRM_CTL 0x20020 63#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3) 64#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12) 65#define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028 66#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3) 67#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12) 68#define CGXX_SMUX_TX_CTL 0x20178 69#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110 70#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120 71#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230 72#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248 73#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7) 74#define CGXX_CMR_RX_OVR_BP 0x130 75#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8)) 76#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4)) 77 78#define CGX_COMMAND_REG CGXX_SCRATCH1_REG 79#define CGX_EVENT_REG CGXX_SCRATCH0_REG 80#define CGX_CMD_TIMEOUT 2200 /* msecs */ 81#define DEFAULT_PAUSE_TIME 0x7FF 82 83#define CGX_NVEC 37 84#define CGX_LMAC_FWI 0 85 86enum cgx_nix_stat_type { 87 NIX_STATS_RX, 88 NIX_STATS_TX, 89}; 90 91enum LMAC_TYPE { 92 LMAC_MODE_SGMII = 0, 93 LMAC_MODE_XAUI = 1, 94 LMAC_MODE_RXAUI = 2, 95 LMAC_MODE_10G_R = 3, 96 LMAC_MODE_40G_R = 4, 97 LMAC_MODE_QSGMII = 6, 98 LMAC_MODE_25G_R = 7, 99 LMAC_MODE_50G_R = 8, 100 LMAC_MODE_100G_R = 9, 101 LMAC_MODE_USXGMII = 10, 102 LMAC_MODE_MAX, 103}; 104 105struct cgx_link_event { 106 struct cgx_link_user_info link_uinfo; 107 u8 cgx_id; 108 u8 lmac_id; 109}; 110 111/** 112 * struct cgx_event_cb 113 * @notify_link_chg: callback for link change notification 114 * @data: data passed to callback function 115 */ 116struct cgx_event_cb { 117 int (*notify_link_chg)(struct cgx_link_event *event, void *data); 118 void *data; 119}; 120 121extern struct pci_driver cgx_driver; 122 123int cgx_get_cgxcnt_max(void); 124int cgx_get_cgxid(void *cgxd); 125int cgx_get_lmac_cnt(void *cgxd); 126void *cgx_get_pdata(int cgx_id); 127int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind); 128int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); 129int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); 130int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); 131int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); 132int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); 133int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable); 134int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 135u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); 136void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); 137void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable); 138int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); 139int cgx_get_link_info(void *cgxd, int lmac_id, 140 struct cgx_link_user_info *linfo); 141int cgx_lmac_linkup_start(void *cgxd); 142int cgx_get_fwdata_base(u64 *base); 143int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id, 144 u8 *tx_pause, u8 *rx_pause); 145int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id, 146 u8 tx_pause, u8 rx_pause); 147void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable); 148u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id); 149 150#endif /* CGX_H */ 151