1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Header Parser definitions for Marvell PPv2 Network Controller
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
8 */
9#ifndef _MVPP2_PRS_H_
10#define _MVPP2_PRS_H_
11
12#include <linux/kernel.h>
13#include <linux/netdevice.h>
14#include <linux/platform_device.h>
15
16#include "mvpp2.h"
17
18/* Parser constants */
19#define MVPP2_PRS_TCAM_SRAM_SIZE	256
20#define MVPP2_PRS_TCAM_WORDS		6
21#define MVPP2_PRS_SRAM_WORDS		4
22#define MVPP2_PRS_FLOW_ID_SIZE		64
23#define MVPP2_PRS_FLOW_ID_MASK		0x3f
24#define MVPP2_PRS_TCAM_ENTRY_INVALID	1
25#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT	BIT(5)
26#define MVPP2_PRS_IPV4_HEAD		0x40
27#define MVPP2_PRS_IPV4_HEAD_MASK	0xf0
28#define MVPP2_PRS_IPV4_MC		0xe0
29#define MVPP2_PRS_IPV4_MC_MASK		0xf0
30#define MVPP2_PRS_IPV4_BC_MASK		0xff
31#define MVPP2_PRS_IPV4_IHL		0x5
32#define MVPP2_PRS_IPV4_IHL_MASK		0xf
33#define MVPP2_PRS_IPV6_MC		0xff
34#define MVPP2_PRS_IPV6_MC_MASK		0xff
35#define MVPP2_PRS_IPV6_HOP_MASK		0xff
36#define MVPP2_PRS_TCAM_PROTO_MASK	0xff
37#define MVPP2_PRS_TCAM_PROTO_MASK_L	0x3f
38#define MVPP2_PRS_DBL_VLANS_MAX		100
39#define MVPP2_PRS_CAST_MASK		BIT(0)
40#define MVPP2_PRS_MCAST_VAL		BIT(0)
41#define MVPP2_PRS_UCAST_VAL		0x0
42
43/* Tcam structure:
44 * - lookup ID - 4 bits
45 * - port ID - 1 byte
46 * - additional information - 1 byte
47 * - header data - 8 bytes
48 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
49 */
50#define MVPP2_PRS_AI_BITS			8
51#define MVPP2_PRS_AI_MASK			0xff
52#define MVPP2_PRS_PORT_MASK			0xff
53#define MVPP2_PRS_LU_MASK			0xf
54
55/* TCAM entries in registers are accessed using 16 data bits + 16 enable bits */
56#define MVPP2_PRS_BYTE_TO_WORD(byte)	((byte) / 2)
57#define MVPP2_PRS_BYTE_IN_WORD(byte)	((byte) % 2)
58
59#define MVPP2_PRS_TCAM_EN(data)		((data) << 16)
60#define MVPP2_PRS_TCAM_AI_WORD		4
61#define MVPP2_PRS_TCAM_AI(ai)		(ai)
62#define MVPP2_PRS_TCAM_AI_EN(ai)	MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_AI(ai))
63#define MVPP2_PRS_TCAM_PORT_WORD	4
64#define MVPP2_PRS_TCAM_PORT(p)		((p) << 8)
65#define MVPP2_PRS_TCAM_PORT_EN(p)	MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_PORT(p))
66#define MVPP2_PRS_TCAM_LU_WORD		5
67#define MVPP2_PRS_TCAM_LU(lu)		(lu)
68#define MVPP2_PRS_TCAM_LU_EN(lu)	MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_LU(lu))
69#define MVPP2_PRS_TCAM_INV_WORD		5
70
71#define MVPP2_PRS_VID_TCAM_BYTE         2
72
73/* TCAM range for unicast and multicast filtering. We have 25 entries per port,
74 * with 4 dedicated to UC filtering and the rest to multicast filtering.
75 * Additionnally we reserve one entry for the broadcast address, and one for
76 * each port's own address.
77 */
78#define MVPP2_PRS_MAC_UC_MC_FILT_MAX	25
79#define MVPP2_PRS_MAC_RANGE_SIZE	80
80
81/* Number of entries per port dedicated to UC and MC filtering */
82#define MVPP2_PRS_MAC_UC_FILT_MAX	4
83#define MVPP2_PRS_MAC_MC_FILT_MAX	(MVPP2_PRS_MAC_UC_MC_FILT_MAX - \
84					 MVPP2_PRS_MAC_UC_FILT_MAX)
85
86/* There is a TCAM range reserved for VLAN filtering entries, range size is 33
87 * 10 VLAN ID filter entries per port
88 * 1 default VLAN filter entry per port
89 * It is assumed that there are 3 ports for filter, not including loopback port
90 */
91#define MVPP2_PRS_VLAN_FILT_MAX		11
92#define MVPP2_PRS_VLAN_FILT_RANGE_SIZE	33
93
94#define MVPP2_PRS_VLAN_FILT_MAX_ENTRY   (MVPP2_PRS_VLAN_FILT_MAX - 2)
95#define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY  (MVPP2_PRS_VLAN_FILT_MAX - 1)
96
97/* Tcam entries ID */
98#define MVPP2_PE_DROP_ALL		0
99#define MVPP2_PE_FIRST_FREE_TID		1
100
101/* MAC filtering range */
102#define MVPP2_PE_MAC_RANGE_END		(MVPP2_PE_VID_FILT_RANGE_START - 1)
103#define MVPP2_PE_MAC_RANGE_START	(MVPP2_PE_MAC_RANGE_END - \
104						MVPP2_PRS_MAC_RANGE_SIZE + 1)
105/* VLAN filtering range */
106#define MVPP2_PE_VID_FILT_RANGE_END     (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
107#define MVPP2_PE_VID_FILT_RANGE_START   (MVPP2_PE_VID_FILT_RANGE_END - \
108					 MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1)
109#define MVPP2_PE_LAST_FREE_TID          (MVPP2_PE_MAC_RANGE_START - 1)
110#define MVPP2_PE_IP6_EXT_PROTO_UN	(MVPP2_PRS_TCAM_SRAM_SIZE - 30)
111#define MVPP2_PE_IP6_ADDR_UN		(MVPP2_PRS_TCAM_SRAM_SIZE - 29)
112#define MVPP2_PE_IP4_ADDR_UN		(MVPP2_PRS_TCAM_SRAM_SIZE - 28)
113#define MVPP2_PE_LAST_DEFAULT_FLOW	(MVPP2_PRS_TCAM_SRAM_SIZE - 27)
114#define MVPP2_PE_FIRST_DEFAULT_FLOW	(MVPP2_PRS_TCAM_SRAM_SIZE - 22)
115#define MVPP2_PE_EDSA_TAGGED		(MVPP2_PRS_TCAM_SRAM_SIZE - 21)
116#define MVPP2_PE_EDSA_UNTAGGED		(MVPP2_PRS_TCAM_SRAM_SIZE - 20)
117#define MVPP2_PE_DSA_TAGGED		(MVPP2_PRS_TCAM_SRAM_SIZE - 19)
118#define MVPP2_PE_DSA_UNTAGGED		(MVPP2_PRS_TCAM_SRAM_SIZE - 18)
119#define MVPP2_PE_ETYPE_EDSA_TAGGED	(MVPP2_PRS_TCAM_SRAM_SIZE - 17)
120#define MVPP2_PE_ETYPE_EDSA_UNTAGGED	(MVPP2_PRS_TCAM_SRAM_SIZE - 16)
121#define MVPP2_PE_ETYPE_DSA_TAGGED	(MVPP2_PRS_TCAM_SRAM_SIZE - 15)
122#define MVPP2_PE_ETYPE_DSA_UNTAGGED	(MVPP2_PRS_TCAM_SRAM_SIZE - 14)
123#define MVPP2_PE_MH_DEFAULT		(MVPP2_PRS_TCAM_SRAM_SIZE - 13)
124#define MVPP2_PE_DSA_DEFAULT		(MVPP2_PRS_TCAM_SRAM_SIZE - 12)
125#define MVPP2_PE_IP6_PROTO_UN		(MVPP2_PRS_TCAM_SRAM_SIZE - 11)
126#define MVPP2_PE_IP4_PROTO_UN		(MVPP2_PRS_TCAM_SRAM_SIZE - 10)
127#define MVPP2_PE_ETH_TYPE_UN		(MVPP2_PRS_TCAM_SRAM_SIZE - 9)
128#define MVPP2_PE_VID_FLTR_DEFAULT	(MVPP2_PRS_TCAM_SRAM_SIZE - 8)
129#define MVPP2_PE_VID_EDSA_FLTR_DEFAULT	(MVPP2_PRS_TCAM_SRAM_SIZE - 7)
130#define MVPP2_PE_VLAN_DBL		(MVPP2_PRS_TCAM_SRAM_SIZE - 6)
131#define MVPP2_PE_VLAN_NONE		(MVPP2_PRS_TCAM_SRAM_SIZE - 5)
132#define MVPP2_PE_FC_DROP		(MVPP2_PRS_TCAM_SRAM_SIZE - 4)
133#define MVPP2_PE_MAC_MC_PROMISCUOUS	(MVPP2_PRS_TCAM_SRAM_SIZE - 3)
134#define MVPP2_PE_MAC_UC_PROMISCUOUS	(MVPP2_PRS_TCAM_SRAM_SIZE - 2)
135#define MVPP2_PE_MAC_NON_PROMISCUOUS	(MVPP2_PRS_TCAM_SRAM_SIZE - 1)
136
137#define MVPP2_PRS_VID_PORT_FIRST(port)	(MVPP2_PE_VID_FILT_RANGE_START + \
138					 ((port) * MVPP2_PRS_VLAN_FILT_MAX))
139#define MVPP2_PRS_VID_PORT_LAST(port)	(MVPP2_PRS_VID_PORT_FIRST(port) \
140					 + MVPP2_PRS_VLAN_FILT_MAX_ENTRY)
141/* Index of default vid filter for given port */
142#define MVPP2_PRS_VID_PORT_DFLT(port)	(MVPP2_PRS_VID_PORT_FIRST(port) \
143					 + MVPP2_PRS_VLAN_FILT_DFLT_ENTRY)
144
145/* Sram structure
146 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
147 */
148#define MVPP2_PRS_SRAM_RI_OFFS			0
149#define MVPP2_PRS_SRAM_RI_WORD			0
150#define MVPP2_PRS_SRAM_RI_CTRL_OFFS		32
151#define MVPP2_PRS_SRAM_RI_CTRL_WORD		1
152#define MVPP2_PRS_SRAM_RI_CTRL_BITS		32
153#define MVPP2_PRS_SRAM_SHIFT_OFFS		64
154#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT		72
155#define MVPP2_PRS_SRAM_SHIFT_MASK		0xff
156#define MVPP2_PRS_SRAM_UDF_OFFS			73
157#define MVPP2_PRS_SRAM_UDF_BITS			8
158#define MVPP2_PRS_SRAM_UDF_MASK			0xff
159#define MVPP2_PRS_SRAM_UDF_SIGN_BIT		81
160#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS		82
161#define MVPP2_PRS_SRAM_UDF_TYPE_MASK		0x7
162#define MVPP2_PRS_SRAM_UDF_TYPE_L3		1
163#define MVPP2_PRS_SRAM_UDF_TYPE_L4		4
164#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS	85
165#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK	0x3
166#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD		1
167#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD	2
168#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD	3
169#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS		87
170#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS		2
171#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK		0x3
172#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD		0
173#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD	2
174#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD	3
175#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS		89
176#define MVPP2_PRS_SRAM_AI_OFFS			90
177#define MVPP2_PRS_SRAM_AI_CTRL_OFFS		98
178#define MVPP2_PRS_SRAM_AI_CTRL_BITS		8
179#define MVPP2_PRS_SRAM_AI_MASK			0xff
180#define MVPP2_PRS_SRAM_NEXT_LU_OFFS		106
181#define MVPP2_PRS_SRAM_NEXT_LU_MASK		0xf
182#define MVPP2_PRS_SRAM_LU_DONE_BIT		110
183#define MVPP2_PRS_SRAM_LU_GEN_BIT		111
184
185/* Sram result info bits assignment */
186#define MVPP2_PRS_RI_MAC_ME_MASK		0x1
187#define MVPP2_PRS_RI_DSA_MASK			0x2
188#define MVPP2_PRS_RI_VLAN_MASK			(BIT(2) | BIT(3))
189#define MVPP2_PRS_RI_VLAN_NONE			0x0
190#define MVPP2_PRS_RI_VLAN_SINGLE		BIT(2)
191#define MVPP2_PRS_RI_VLAN_DOUBLE		BIT(3)
192#define MVPP2_PRS_RI_VLAN_TRIPLE		(BIT(2) | BIT(3))
193#define MVPP2_PRS_RI_CPU_CODE_MASK		0x70
194#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC		BIT(4)
195#define MVPP2_PRS_RI_L2_CAST_MASK		(BIT(9) | BIT(10))
196#define MVPP2_PRS_RI_L2_UCAST			0x0
197#define MVPP2_PRS_RI_L2_MCAST			BIT(9)
198#define MVPP2_PRS_RI_L2_BCAST			BIT(10)
199#define MVPP2_PRS_RI_PPPOE_MASK			0x800
200#define MVPP2_PRS_RI_L3_PROTO_MASK		(BIT(12) | BIT(13) | BIT(14))
201#define MVPP2_PRS_RI_L3_UN			0x0
202#define MVPP2_PRS_RI_L3_IP4			BIT(12)
203#define MVPP2_PRS_RI_L3_IP4_OPT			BIT(13)
204#define MVPP2_PRS_RI_L3_IP4_OTHER		(BIT(12) | BIT(13))
205#define MVPP2_PRS_RI_L3_IP6			BIT(14)
206#define MVPP2_PRS_RI_L3_IP6_EXT			(BIT(12) | BIT(14))
207#define MVPP2_PRS_RI_L3_ARP			(BIT(13) | BIT(14))
208#define MVPP2_PRS_RI_L3_ADDR_MASK		(BIT(15) | BIT(16))
209#define MVPP2_PRS_RI_L3_UCAST			0x0
210#define MVPP2_PRS_RI_L3_MCAST			BIT(15)
211#define MVPP2_PRS_RI_L3_BCAST			(BIT(15) | BIT(16))
212#define MVPP2_PRS_RI_IP_FRAG_MASK		0x20000
213#define MVPP2_PRS_RI_IP_FRAG_TRUE		BIT(17)
214#define MVPP2_PRS_RI_UDF3_MASK			0x300000
215#define MVPP2_PRS_RI_UDF3_RX_SPECIAL		BIT(21)
216#define MVPP2_PRS_RI_L4_PROTO_MASK		0x1c00000
217#define MVPP2_PRS_RI_L4_TCP			BIT(22)
218#define MVPP2_PRS_RI_L4_UDP			BIT(23)
219#define MVPP2_PRS_RI_L4_OTHER			(BIT(22) | BIT(23))
220#define MVPP2_PRS_RI_UDF7_MASK			0x60000000
221#define MVPP2_PRS_RI_UDF7_IP6_LITE		BIT(29)
222#define MVPP2_PRS_RI_DROP_MASK			0x80000000
223
224#define MVPP2_PRS_IP_MASK			(MVPP2_PRS_RI_L3_PROTO_MASK | \
225						MVPP2_PRS_RI_IP_FRAG_MASK | \
226						MVPP2_PRS_RI_L4_PROTO_MASK)
227
228/* Sram additional info bits assignment */
229#define MVPP2_PRS_IPV4_DIP_AI_BIT		BIT(0)
230#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT		BIT(0)
231#define MVPP2_PRS_IPV6_EXT_AI_BIT		BIT(1)
232#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT		BIT(2)
233#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT	BIT(3)
234#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT		BIT(4)
235#define MVPP2_PRS_SINGLE_VLAN_AI		0
236#define MVPP2_PRS_DBL_VLAN_AI_BIT		BIT(7)
237#define MVPP2_PRS_EDSA_VID_AI_BIT		BIT(0)
238
239/* DSA/EDSA type */
240#define MVPP2_PRS_TAGGED		true
241#define MVPP2_PRS_UNTAGGED		false
242#define MVPP2_PRS_EDSA			true
243#define MVPP2_PRS_DSA			false
244
245/* MAC entries, shadow udf */
246enum mvpp2_prs_udf {
247	MVPP2_PRS_UDF_MAC_DEF,
248	MVPP2_PRS_UDF_MAC_RANGE,
249	MVPP2_PRS_UDF_L2_DEF,
250	MVPP2_PRS_UDF_L2_DEF_COPY,
251	MVPP2_PRS_UDF_L2_USER,
252};
253
254/* Lookup ID */
255enum mvpp2_prs_lookup {
256	MVPP2_PRS_LU_MH,
257	MVPP2_PRS_LU_MAC,
258	MVPP2_PRS_LU_DSA,
259	MVPP2_PRS_LU_VLAN,
260	MVPP2_PRS_LU_VID,
261	MVPP2_PRS_LU_L2,
262	MVPP2_PRS_LU_PPPOE,
263	MVPP2_PRS_LU_IP4,
264	MVPP2_PRS_LU_IP6,
265	MVPP2_PRS_LU_FLOWS,
266	MVPP2_PRS_LU_LAST,
267};
268
269struct mvpp2_prs_entry {
270	u32 index;
271	u32 tcam[MVPP2_PRS_TCAM_WORDS];
272	u32 sram[MVPP2_PRS_SRAM_WORDS];
273};
274
275struct mvpp2_prs_result_info {
276	u32 ri;
277	u32 ri_mask;
278};
279
280struct mvpp2_prs_shadow {
281	bool valid;
282	bool finish;
283
284	/* Lookup ID */
285	int lu;
286
287	/* User defined offset */
288	int udf;
289
290	/* Result info */
291	u32 ri;
292	u32 ri_mask;
293};
294
295int mvpp2_prs_default_init(struct platform_device *pdev, struct mvpp2 *priv);
296
297int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
298			   int tid);
299
300unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe);
301
302void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
303				  unsigned int offs, unsigned char *byte,
304				  unsigned char *enable);
305
306int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, bool add);
307
308int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type);
309
310int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask);
311
312int mvpp2_prs_def_flow(struct mvpp2_port *port);
313
314void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port);
315
316void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port);
317
318int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid);
319
320void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid);
321
322void mvpp2_prs_vid_remove_all(struct mvpp2_port *port);
323
324void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port,
325			       enum mvpp2_prs_l2_cast l2_cast, bool add);
326
327void mvpp2_prs_mac_del_all(struct mvpp2_port *port);
328
329int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da);
330
331int mvpp2_prs_hits(struct mvpp2 *priv, int index);
332
333#endif
334