1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/kernel.h> 12#include <linux/netdevice.h> 13#include <linux/etherdevice.h> 14#include <linux/platform_device.h> 15#include <linux/skbuff.h> 16#include <linux/inetdevice.h> 17#include <linux/mbus.h> 18#include <linux/module.h> 19#include <linux/mfd/syscon.h> 20#include <linux/interrupt.h> 21#include <linux/cpumask.h> 22#include <linux/of.h> 23#include <linux/of_irq.h> 24#include <linux/of_mdio.h> 25#include <linux/of_net.h> 26#include <linux/of_address.h> 27#include <linux/of_device.h> 28#include <linux/phy.h> 29#include <linux/phylink.h> 30#include <linux/phy/phy.h> 31#include <linux/ptp_classify.h> 32#include <linux/clk.h> 33#include <linux/hrtimer.h> 34#include <linux/ktime.h> 35#include <linux/regmap.h> 36#include <uapi/linux/ppp_defs.h> 37#include <net/ip.h> 38#include <net/ipv6.h> 39#include <net/tso.h> 40#include <linux/bpf_trace.h> 41 42#include "mvpp2.h" 43#include "mvpp2_prs.h" 44#include "mvpp2_cls.h" 45 46enum mvpp2_bm_pool_log_num { 47 MVPP2_BM_SHORT, 48 MVPP2_BM_LONG, 49 MVPP2_BM_JUMBO, 50 MVPP2_BM_POOLS_NUM 51}; 52 53static struct { 54 int pkt_size; 55 int buf_num; 56} mvpp2_pools[MVPP2_BM_POOLS_NUM]; 57 58/* The prototype is added here to be used in start_dev when using ACPI. This 59 * will be removed once phylink is used for all modes (dt+ACPI). 60 */ 61static void mvpp2_acpi_start(struct mvpp2_port *port); 62 63/* Queue modes */ 64#define MVPP2_QDIST_SINGLE_MODE 0 65#define MVPP2_QDIST_MULTI_MODE 1 66 67static int queue_mode = MVPP2_QDIST_MULTI_MODE; 68 69module_param(queue_mode, int, 0444); 70MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 71 72/* Utility/helper methods */ 73 74void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 75{ 76 writel(data, priv->swth_base[0] + offset); 77} 78 79u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 80{ 81 return readl(priv->swth_base[0] + offset); 82} 83 84static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 85{ 86 return readl_relaxed(priv->swth_base[0] + offset); 87} 88 89static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 90{ 91 return cpu % priv->nthreads; 92} 93 94static struct page_pool * 95mvpp2_create_page_pool(struct device *dev, int num, int len, 96 enum dma_data_direction dma_dir) 97{ 98 struct page_pool_params pp_params = { 99 /* internal DMA mapping in page_pool */ 100 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 101 .pool_size = num, 102 .nid = NUMA_NO_NODE, 103 .dev = dev, 104 .dma_dir = dma_dir, 105 .offset = MVPP2_SKB_HEADROOM, 106 .max_len = len, 107 }; 108 109 return page_pool_create(&pp_params); 110} 111 112/* These accessors should be used to access: 113 * 114 * - per-thread registers, where each thread has its own copy of the 115 * register. 116 * 117 * MVPP2_BM_VIRT_ALLOC_REG 118 * MVPP2_BM_ADDR_HIGH_ALLOC 119 * MVPP22_BM_ADDR_HIGH_RLS_REG 120 * MVPP2_BM_VIRT_RLS_REG 121 * MVPP2_ISR_RX_TX_CAUSE_REG 122 * MVPP2_ISR_RX_TX_MASK_REG 123 * MVPP2_TXQ_NUM_REG 124 * MVPP2_AGGR_TXQ_UPDATE_REG 125 * MVPP2_TXQ_RSVD_REQ_REG 126 * MVPP2_TXQ_RSVD_RSLT_REG 127 * MVPP2_TXQ_SENT_REG 128 * MVPP2_RXQ_NUM_REG 129 * 130 * - global registers that must be accessed through a specific thread 131 * window, because they are related to an access to a per-thread 132 * register 133 * 134 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 135 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 136 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 137 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 138 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 139 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 140 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 141 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 142 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 143 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 144 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 145 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 146 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 147 */ 148static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 149 u32 offset, u32 data) 150{ 151 writel(data, priv->swth_base[thread] + offset); 152} 153 154static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 155 u32 offset) 156{ 157 return readl(priv->swth_base[thread] + offset); 158} 159 160static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 161 u32 offset, u32 data) 162{ 163 writel_relaxed(data, priv->swth_base[thread] + offset); 164} 165 166static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 167 u32 offset) 168{ 169 return readl_relaxed(priv->swth_base[thread] + offset); 170} 171 172static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 173 struct mvpp2_tx_desc *tx_desc) 174{ 175 if (port->priv->hw_version == MVPP21) 176 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 177 else 178 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 179 MVPP2_DESC_DMA_MASK; 180} 181 182static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 183 struct mvpp2_tx_desc *tx_desc, 184 dma_addr_t dma_addr) 185{ 186 dma_addr_t addr, offset; 187 188 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 189 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 190 191 if (port->priv->hw_version == MVPP21) { 192 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 193 tx_desc->pp21.packet_offset = offset; 194 } else { 195 __le64 val = cpu_to_le64(addr); 196 197 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 198 tx_desc->pp22.buf_dma_addr_ptp |= val; 199 tx_desc->pp22.packet_offset = offset; 200 } 201} 202 203static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 204 struct mvpp2_tx_desc *tx_desc) 205{ 206 if (port->priv->hw_version == MVPP21) 207 return le16_to_cpu(tx_desc->pp21.data_size); 208 else 209 return le16_to_cpu(tx_desc->pp22.data_size); 210} 211 212static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 213 struct mvpp2_tx_desc *tx_desc, 214 size_t size) 215{ 216 if (port->priv->hw_version == MVPP21) 217 tx_desc->pp21.data_size = cpu_to_le16(size); 218 else 219 tx_desc->pp22.data_size = cpu_to_le16(size); 220} 221 222static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 223 struct mvpp2_tx_desc *tx_desc, 224 unsigned int txq) 225{ 226 if (port->priv->hw_version == MVPP21) 227 tx_desc->pp21.phys_txq = txq; 228 else 229 tx_desc->pp22.phys_txq = txq; 230} 231 232static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 233 struct mvpp2_tx_desc *tx_desc, 234 unsigned int command) 235{ 236 if (port->priv->hw_version == MVPP21) 237 tx_desc->pp21.command = cpu_to_le32(command); 238 else 239 tx_desc->pp22.command = cpu_to_le32(command); 240} 241 242static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 243 struct mvpp2_tx_desc *tx_desc) 244{ 245 if (port->priv->hw_version == MVPP21) 246 return tx_desc->pp21.packet_offset; 247 else 248 return tx_desc->pp22.packet_offset; 249} 250 251static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 252 struct mvpp2_rx_desc *rx_desc) 253{ 254 if (port->priv->hw_version == MVPP21) 255 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 256 else 257 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 258 MVPP2_DESC_DMA_MASK; 259} 260 261static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 262 struct mvpp2_rx_desc *rx_desc) 263{ 264 if (port->priv->hw_version == MVPP21) 265 return le32_to_cpu(rx_desc->pp21.buf_cookie); 266 else 267 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 268 MVPP2_DESC_DMA_MASK; 269} 270 271static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 272 struct mvpp2_rx_desc *rx_desc) 273{ 274 if (port->priv->hw_version == MVPP21) 275 return le16_to_cpu(rx_desc->pp21.data_size); 276 else 277 return le16_to_cpu(rx_desc->pp22.data_size); 278} 279 280static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 281 struct mvpp2_rx_desc *rx_desc) 282{ 283 if (port->priv->hw_version == MVPP21) 284 return le32_to_cpu(rx_desc->pp21.status); 285 else 286 return le32_to_cpu(rx_desc->pp22.status); 287} 288 289static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 290{ 291 txq_pcpu->txq_get_index++; 292 if (txq_pcpu->txq_get_index == txq_pcpu->size) 293 txq_pcpu->txq_get_index = 0; 294} 295 296static void mvpp2_txq_inc_put(struct mvpp2_port *port, 297 struct mvpp2_txq_pcpu *txq_pcpu, 298 void *data, 299 struct mvpp2_tx_desc *tx_desc, 300 enum mvpp2_tx_buf_type buf_type) 301{ 302 struct mvpp2_txq_pcpu_buf *tx_buf = 303 txq_pcpu->buffs + txq_pcpu->txq_put_index; 304 tx_buf->type = buf_type; 305 if (buf_type == MVPP2_TYPE_SKB) 306 tx_buf->skb = data; 307 else 308 tx_buf->xdpf = data; 309 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 310 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 311 mvpp2_txdesc_offset_get(port, tx_desc); 312 txq_pcpu->txq_put_index++; 313 if (txq_pcpu->txq_put_index == txq_pcpu->size) 314 txq_pcpu->txq_put_index = 0; 315} 316 317/* Get number of maximum RXQ */ 318static int mvpp2_get_nrxqs(struct mvpp2 *priv) 319{ 320 unsigned int nrxqs; 321 322 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) 323 return 1; 324 325 /* According to the PPv2.2 datasheet and our experiments on 326 * PPv2.1, RX queues have an allocation granularity of 4 (when 327 * more than a single one on PPv2.2). 328 * Round up to nearest multiple of 4. 329 */ 330 nrxqs = (num_possible_cpus() + 3) & ~0x3; 331 if (nrxqs > MVPP2_PORT_MAX_RXQ) 332 nrxqs = MVPP2_PORT_MAX_RXQ; 333 334 return nrxqs; 335} 336 337/* Get number of physical egress port */ 338static inline int mvpp2_egress_port(struct mvpp2_port *port) 339{ 340 return MVPP2_MAX_TCONT + port->id; 341} 342 343/* Get number of physical TXQ */ 344static inline int mvpp2_txq_phys(int port, int txq) 345{ 346 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 347} 348 349/* Returns a struct page if page_pool is set, otherwise a buffer */ 350static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool, 351 struct page_pool *page_pool) 352{ 353 if (page_pool) 354 return page_pool_dev_alloc_pages(page_pool); 355 356 if (likely(pool->frag_size <= PAGE_SIZE)) 357 return netdev_alloc_frag(pool->frag_size); 358 359 return kmalloc(pool->frag_size, GFP_ATOMIC); 360} 361 362static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, 363 struct page_pool *page_pool, void *data) 364{ 365 if (page_pool) 366 page_pool_put_full_page(page_pool, virt_to_head_page(data), false); 367 else if (likely(pool->frag_size <= PAGE_SIZE)) 368 skb_free_frag(data); 369 else 370 kfree(data); 371} 372 373/* Buffer Manager configuration routines */ 374 375/* Create pool */ 376static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, 377 struct mvpp2_bm_pool *bm_pool, int size) 378{ 379 u32 val; 380 381 /* Number of buffer pointers must be a multiple of 16, as per 382 * hardware constraints 383 */ 384 if (!IS_ALIGNED(size, 16)) 385 return -EINVAL; 386 387 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 388 * bytes per buffer pointer 389 */ 390 if (priv->hw_version == MVPP21) 391 bm_pool->size_bytes = 2 * sizeof(u32) * size; 392 else 393 bm_pool->size_bytes = 2 * sizeof(u64) * size; 394 395 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, 396 &bm_pool->dma_addr, 397 GFP_KERNEL); 398 if (!bm_pool->virt_addr) 399 return -ENOMEM; 400 401 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 402 MVPP2_BM_POOL_PTR_ALIGN)) { 403 dma_free_coherent(dev, bm_pool->size_bytes, 404 bm_pool->virt_addr, bm_pool->dma_addr); 405 dev_err(dev, "BM pool %d is not %d bytes aligned\n", 406 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 407 return -ENOMEM; 408 } 409 410 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 411 lower_32_bits(bm_pool->dma_addr)); 412 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 413 414 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 415 val |= MVPP2_BM_START_MASK; 416 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 417 418 bm_pool->size = size; 419 bm_pool->pkt_size = 0; 420 bm_pool->buf_num = 0; 421 422 return 0; 423} 424 425/* Set pool buffer size */ 426static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 427 struct mvpp2_bm_pool *bm_pool, 428 int buf_size) 429{ 430 u32 val; 431 432 bm_pool->buf_size = buf_size; 433 434 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 435 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 436} 437 438static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 439 struct mvpp2_bm_pool *bm_pool, 440 dma_addr_t *dma_addr, 441 phys_addr_t *phys_addr) 442{ 443 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 444 445 *dma_addr = mvpp2_thread_read(priv, thread, 446 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 447 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 448 449 if (priv->hw_version == MVPP22) { 450 u32 val; 451 u32 dma_addr_highbits, phys_addr_highbits; 452 453 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 454 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 455 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 456 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 457 458 if (sizeof(dma_addr_t) == 8) 459 *dma_addr |= (u64)dma_addr_highbits << 32; 460 461 if (sizeof(phys_addr_t) == 8) 462 *phys_addr |= (u64)phys_addr_highbits << 32; 463 } 464 465 put_cpu(); 466} 467 468/* Free all buffers from the pool */ 469static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 470 struct mvpp2_bm_pool *bm_pool, int buf_num) 471{ 472 struct page_pool *pp = NULL; 473 int i; 474 475 if (buf_num > bm_pool->buf_num) { 476 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 477 bm_pool->id, buf_num); 478 buf_num = bm_pool->buf_num; 479 } 480 481 if (priv->percpu_pools) 482 pp = priv->page_pool[bm_pool->id]; 483 484 for (i = 0; i < buf_num; i++) { 485 dma_addr_t buf_dma_addr; 486 phys_addr_t buf_phys_addr; 487 void *data; 488 489 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 490 &buf_dma_addr, &buf_phys_addr); 491 492 if (!pp) 493 dma_unmap_single(dev, buf_dma_addr, 494 bm_pool->buf_size, DMA_FROM_DEVICE); 495 496 data = (void *)phys_to_virt(buf_phys_addr); 497 if (!data) 498 break; 499 500 mvpp2_frag_free(bm_pool, pp, data); 501 } 502 503 /* Update BM driver with number of buffers removed from pool */ 504 bm_pool->buf_num -= i; 505} 506 507/* Check number of buffers in BM pool */ 508static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 509{ 510 int buf_num = 0; 511 512 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 513 MVPP22_BM_POOL_PTRS_NUM_MASK; 514 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 515 MVPP2_BM_BPPI_PTR_NUM_MASK; 516 517 /* HW has one buffer ready which is not reflected in the counters */ 518 if (buf_num) 519 buf_num += 1; 520 521 return buf_num; 522} 523 524/* Cleanup pool */ 525static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv, 526 struct mvpp2_bm_pool *bm_pool) 527{ 528 int buf_num; 529 u32 val; 530 531 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 532 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num); 533 534 /* Check buffer counters after free */ 535 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 536 if (buf_num) { 537 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 538 bm_pool->id, bm_pool->buf_num); 539 return 0; 540 } 541 542 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 543 val |= MVPP2_BM_STOP_MASK; 544 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 545 546 if (priv->percpu_pools) { 547 page_pool_destroy(priv->page_pool[bm_pool->id]); 548 priv->page_pool[bm_pool->id] = NULL; 549 } 550 551 dma_free_coherent(dev, bm_pool->size_bytes, 552 bm_pool->virt_addr, 553 bm_pool->dma_addr); 554 return 0; 555} 556 557static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) 558{ 559 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM; 560 struct mvpp2_bm_pool *bm_pool; 561 562 if (priv->percpu_pools) 563 poolnum = mvpp2_get_nrxqs(priv) * 2; 564 565 /* Create all pools with maximum size */ 566 size = MVPP2_BM_POOL_SIZE_MAX; 567 for (i = 0; i < poolnum; i++) { 568 bm_pool = &priv->bm_pools[i]; 569 bm_pool->id = i; 570 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); 571 if (err) 572 goto err_unroll_pools; 573 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 574 } 575 return 0; 576 577err_unroll_pools: 578 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size); 579 for (i = i - 1; i >= 0; i--) 580 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); 581 return err; 582} 583 584/* Cleanup pool before actual initialization in the OS */ 585static void mvpp2_bm_pool_cleanup(struct mvpp2 *priv, int pool_id) 586{ 587 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 588 u32 val; 589 int i; 590 591 /* Drain the BM from all possible residues left by firmware */ 592 for (i = 0; i < MVPP2_BM_POOL_SIZE_MAX; i++) 593 mvpp2_thread_read(priv, thread, MVPP2_BM_PHY_ALLOC_REG(pool_id)); 594 595 put_cpu(); 596 597 /* Stop the BM pool */ 598 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id)); 599 val |= MVPP2_BM_STOP_MASK; 600 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val); 601} 602 603static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) 604{ 605 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 606 int i, err, poolnum = MVPP2_BM_POOLS_NUM; 607 struct mvpp2_port *port; 608 609 if (priv->percpu_pools) 610 poolnum = mvpp2_get_nrxqs(priv) * 2; 611 612 /* Clean up the pool state in case it contains stale state */ 613 for (i = 0; i < poolnum; i++) 614 mvpp2_bm_pool_cleanup(priv, i); 615 616 if (priv->percpu_pools) { 617 for (i = 0; i < priv->port_count; i++) { 618 port = priv->port_list[i]; 619 if (port->xdp_prog) { 620 dma_dir = DMA_BIDIRECTIONAL; 621 break; 622 } 623 } 624 625 for (i = 0; i < poolnum; i++) { 626 /* the pool in use */ 627 int pn = i / (poolnum / 2); 628 629 priv->page_pool[i] = 630 mvpp2_create_page_pool(dev, 631 mvpp2_pools[pn].buf_num, 632 mvpp2_pools[pn].pkt_size, 633 dma_dir); 634 if (IS_ERR(priv->page_pool[i])) { 635 int j; 636 637 for (j = 0; j < i; j++) { 638 page_pool_destroy(priv->page_pool[j]); 639 priv->page_pool[j] = NULL; 640 } 641 return PTR_ERR(priv->page_pool[i]); 642 } 643 } 644 } 645 646 dev_info(dev, "using %d %s buffers\n", poolnum, 647 priv->percpu_pools ? "per-cpu" : "shared"); 648 649 for (i = 0; i < poolnum; i++) { 650 /* Mask BM all interrupts */ 651 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 652 /* Clear BM cause register */ 653 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 654 } 655 656 /* Allocate and initialize BM pools */ 657 priv->bm_pools = devm_kcalloc(dev, poolnum, 658 sizeof(*priv->bm_pools), GFP_KERNEL); 659 if (!priv->bm_pools) 660 return -ENOMEM; 661 662 err = mvpp2_bm_pools_init(dev, priv); 663 if (err < 0) 664 return err; 665 return 0; 666} 667 668static void mvpp2_setup_bm_pool(void) 669{ 670 /* Short pool */ 671 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 672 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 673 674 /* Long pool */ 675 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 676 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 677 678 /* Jumbo pool */ 679 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 680 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 681} 682 683/* Attach long pool to rxq */ 684static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 685 int lrxq, int long_pool) 686{ 687 u32 val, mask; 688 int prxq; 689 690 /* Get queue physical ID */ 691 prxq = port->rxqs[lrxq]->id; 692 693 if (port->priv->hw_version == MVPP21) 694 mask = MVPP21_RXQ_POOL_LONG_MASK; 695 else 696 mask = MVPP22_RXQ_POOL_LONG_MASK; 697 698 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 699 val &= ~mask; 700 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 701 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 702} 703 704/* Attach short pool to rxq */ 705static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 706 int lrxq, int short_pool) 707{ 708 u32 val, mask; 709 int prxq; 710 711 /* Get queue physical ID */ 712 prxq = port->rxqs[lrxq]->id; 713 714 if (port->priv->hw_version == MVPP21) 715 mask = MVPP21_RXQ_POOL_SHORT_MASK; 716 else 717 mask = MVPP22_RXQ_POOL_SHORT_MASK; 718 719 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 720 val &= ~mask; 721 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 722 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 723} 724 725static void *mvpp2_buf_alloc(struct mvpp2_port *port, 726 struct mvpp2_bm_pool *bm_pool, 727 struct page_pool *page_pool, 728 dma_addr_t *buf_dma_addr, 729 phys_addr_t *buf_phys_addr, 730 gfp_t gfp_mask) 731{ 732 dma_addr_t dma_addr; 733 struct page *page; 734 void *data; 735 736 data = mvpp2_frag_alloc(bm_pool, page_pool); 737 if (!data) 738 return NULL; 739 740 if (page_pool) { 741 page = (struct page *)data; 742 dma_addr = page_pool_get_dma_addr(page); 743 data = page_to_virt(page); 744 } else { 745 dma_addr = dma_map_single(port->dev->dev.parent, data, 746 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 747 DMA_FROM_DEVICE); 748 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 749 mvpp2_frag_free(bm_pool, NULL, data); 750 return NULL; 751 } 752 } 753 *buf_dma_addr = dma_addr; 754 *buf_phys_addr = virt_to_phys(data); 755 756 return data; 757} 758 759/* Release buffer to BM */ 760static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 761 dma_addr_t buf_dma_addr, 762 phys_addr_t buf_phys_addr) 763{ 764 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 765 unsigned long flags = 0; 766 767 if (test_bit(thread, &port->priv->lock_map)) 768 spin_lock_irqsave(&port->bm_lock[thread], flags); 769 770 if (port->priv->hw_version == MVPP22) { 771 u32 val = 0; 772 773 if (sizeof(dma_addr_t) == 8) 774 val |= upper_32_bits(buf_dma_addr) & 775 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 776 777 if (sizeof(phys_addr_t) == 8) 778 val |= (upper_32_bits(buf_phys_addr) 779 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 780 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 781 782 mvpp2_thread_write_relaxed(port->priv, thread, 783 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 784 } 785 786 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 787 * returned in the "cookie" field of the RX 788 * descriptor. Instead of storing the virtual address, we 789 * store the physical address 790 */ 791 mvpp2_thread_write_relaxed(port->priv, thread, 792 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 793 mvpp2_thread_write_relaxed(port->priv, thread, 794 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 795 796 if (test_bit(thread, &port->priv->lock_map)) 797 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 798 799 put_cpu(); 800} 801 802/* Allocate buffers for the pool */ 803static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 804 struct mvpp2_bm_pool *bm_pool, int buf_num) 805{ 806 int i, buf_size, total_size; 807 dma_addr_t dma_addr; 808 phys_addr_t phys_addr; 809 struct page_pool *pp = NULL; 810 void *buf; 811 812 if (port->priv->percpu_pools && 813 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 814 netdev_err(port->dev, 815 "attempted to use jumbo frames with per-cpu pools"); 816 return 0; 817 } 818 819 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 820 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 821 822 if (buf_num < 0 || 823 (buf_num + bm_pool->buf_num > bm_pool->size)) { 824 netdev_err(port->dev, 825 "cannot allocate %d buffers for pool %d\n", 826 buf_num, bm_pool->id); 827 return 0; 828 } 829 830 if (port->priv->percpu_pools) 831 pp = port->priv->page_pool[bm_pool->id]; 832 for (i = 0; i < buf_num; i++) { 833 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, 834 &phys_addr, GFP_KERNEL); 835 if (!buf) 836 break; 837 838 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 839 phys_addr); 840 } 841 842 /* Update BM driver with number of buffers added to pool */ 843 bm_pool->buf_num += i; 844 845 netdev_dbg(port->dev, 846 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 847 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 848 849 netdev_dbg(port->dev, 850 "pool %d: %d of %d buffers added\n", 851 bm_pool->id, i, buf_num); 852 return i; 853} 854 855/* Notify the driver that BM pool is being used as specific type and return the 856 * pool pointer on success 857 */ 858static struct mvpp2_bm_pool * 859mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 860{ 861 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 862 int num; 863 864 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || 865 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { 866 netdev_err(port->dev, "Invalid pool %d\n", pool); 867 return NULL; 868 } 869 870 /* Allocate buffers in case BM pool is used as long pool, but packet 871 * size doesn't match MTU or BM pool hasn't being used yet 872 */ 873 if (new_pool->pkt_size == 0) { 874 int pkts_num; 875 876 /* Set default buffer number or free all the buffers in case 877 * the pool is not empty 878 */ 879 pkts_num = new_pool->buf_num; 880 if (pkts_num == 0) { 881 if (port->priv->percpu_pools) { 882 if (pool < port->nrxqs) 883 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num; 884 else 885 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num; 886 } else { 887 pkts_num = mvpp2_pools[pool].buf_num; 888 } 889 } else { 890 mvpp2_bm_bufs_free(port->dev->dev.parent, 891 port->priv, new_pool, pkts_num); 892 } 893 894 new_pool->pkt_size = pkt_size; 895 new_pool->frag_size = 896 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 897 MVPP2_SKB_SHINFO_SIZE; 898 899 /* Allocate buffers for this pool */ 900 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 901 if (num != pkts_num) { 902 WARN(1, "pool %d: %d of %d allocated\n", 903 new_pool->id, num, pkts_num); 904 return NULL; 905 } 906 } 907 908 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 909 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 910 911 return new_pool; 912} 913 914static struct mvpp2_bm_pool * 915mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, 916 unsigned int pool, int pkt_size) 917{ 918 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 919 int num; 920 921 if (pool > port->nrxqs * 2) { 922 netdev_err(port->dev, "Invalid pool %d\n", pool); 923 return NULL; 924 } 925 926 /* Allocate buffers in case BM pool is used as long pool, but packet 927 * size doesn't match MTU or BM pool hasn't being used yet 928 */ 929 if (new_pool->pkt_size == 0) { 930 int pkts_num; 931 932 /* Set default buffer number or free all the buffers in case 933 * the pool is not empty 934 */ 935 pkts_num = new_pool->buf_num; 936 if (pkts_num == 0) 937 pkts_num = mvpp2_pools[type].buf_num; 938 else 939 mvpp2_bm_bufs_free(port->dev->dev.parent, 940 port->priv, new_pool, pkts_num); 941 942 new_pool->pkt_size = pkt_size; 943 new_pool->frag_size = 944 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 945 MVPP2_SKB_SHINFO_SIZE; 946 947 /* Allocate buffers for this pool */ 948 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 949 if (num != pkts_num) { 950 WARN(1, "pool %d: %d of %d allocated\n", 951 new_pool->id, num, pkts_num); 952 return NULL; 953 } 954 } 955 956 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 957 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 958 959 return new_pool; 960} 961 962/* Initialize pools for swf, shared buffers variant */ 963static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) 964{ 965 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 966 int rxq; 967 968 /* If port pkt_size is higher than 1518B: 969 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 970 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 971 */ 972 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 973 long_log_pool = MVPP2_BM_JUMBO; 974 short_log_pool = MVPP2_BM_LONG; 975 } else { 976 long_log_pool = MVPP2_BM_LONG; 977 short_log_pool = MVPP2_BM_SHORT; 978 } 979 980 if (!port->pool_long) { 981 port->pool_long = 982 mvpp2_bm_pool_use(port, long_log_pool, 983 mvpp2_pools[long_log_pool].pkt_size); 984 if (!port->pool_long) 985 return -ENOMEM; 986 987 port->pool_long->port_map |= BIT(port->id); 988 989 for (rxq = 0; rxq < port->nrxqs; rxq++) 990 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 991 } 992 993 if (!port->pool_short) { 994 port->pool_short = 995 mvpp2_bm_pool_use(port, short_log_pool, 996 mvpp2_pools[short_log_pool].pkt_size); 997 if (!port->pool_short) 998 return -ENOMEM; 999 1000 port->pool_short->port_map |= BIT(port->id); 1001 1002 for (rxq = 0; rxq < port->nrxqs; rxq++) 1003 mvpp2_rxq_short_pool_set(port, rxq, 1004 port->pool_short->id); 1005 } 1006 1007 return 0; 1008} 1009 1010/* Initialize pools for swf, percpu buffers variant */ 1011static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) 1012{ 1013 struct mvpp2_bm_pool *bm_pool; 1014 int i; 1015 1016 for (i = 0; i < port->nrxqs; i++) { 1017 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, 1018 mvpp2_pools[MVPP2_BM_SHORT].pkt_size); 1019 if (!bm_pool) 1020 return -ENOMEM; 1021 1022 bm_pool->port_map |= BIT(port->id); 1023 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); 1024 } 1025 1026 for (i = 0; i < port->nrxqs; i++) { 1027 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, 1028 mvpp2_pools[MVPP2_BM_LONG].pkt_size); 1029 if (!bm_pool) 1030 return -ENOMEM; 1031 1032 bm_pool->port_map |= BIT(port->id); 1033 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); 1034 } 1035 1036 port->pool_long = NULL; 1037 port->pool_short = NULL; 1038 1039 return 0; 1040} 1041 1042static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 1043{ 1044 if (port->priv->percpu_pools) 1045 return mvpp2_swf_bm_pool_init_percpu(port); 1046 else 1047 return mvpp2_swf_bm_pool_init_shared(port); 1048} 1049 1050static void mvpp2_set_hw_csum(struct mvpp2_port *port, 1051 enum mvpp2_bm_pool_log_num new_long_pool) 1052{ 1053 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1054 1055 /* Update L4 checksum when jumbo enable/disable on port. 1056 * Only port 0 supports hardware checksum offload due to 1057 * the Tx FIFO size limitation. 1058 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 1059 * has 7 bits, so the maximum L3 offset is 128. 1060 */ 1061 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1062 port->dev->features &= ~csums; 1063 port->dev->hw_features &= ~csums; 1064 } else { 1065 port->dev->features |= csums; 1066 port->dev->hw_features |= csums; 1067 } 1068} 1069 1070static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 1071{ 1072 struct mvpp2_port *port = netdev_priv(dev); 1073 enum mvpp2_bm_pool_log_num new_long_pool; 1074 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 1075 1076 if (port->priv->percpu_pools) 1077 goto out_set; 1078 1079 /* If port MTU is higher than 1518B: 1080 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1081 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1082 */ 1083 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1084 new_long_pool = MVPP2_BM_JUMBO; 1085 else 1086 new_long_pool = MVPP2_BM_LONG; 1087 1088 if (new_long_pool != port->pool_long->id) { 1089 /* Remove port from old short & long pool */ 1090 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 1091 port->pool_long->pkt_size); 1092 port->pool_long->port_map &= ~BIT(port->id); 1093 port->pool_long = NULL; 1094 1095 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 1096 port->pool_short->pkt_size); 1097 port->pool_short->port_map &= ~BIT(port->id); 1098 port->pool_short = NULL; 1099 1100 port->pkt_size = pkt_size; 1101 1102 /* Add port to new short & long pool */ 1103 mvpp2_swf_bm_pool_init(port); 1104 1105 mvpp2_set_hw_csum(port, new_long_pool); 1106 } 1107 1108out_set: 1109 dev->mtu = mtu; 1110 dev->wanted_features = dev->features; 1111 1112 netdev_update_features(dev); 1113 return 0; 1114} 1115 1116static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 1117{ 1118 int i, sw_thread_mask = 0; 1119 1120 for (i = 0; i < port->nqvecs; i++) 1121 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1122 1123 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1124 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 1125} 1126 1127static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 1128{ 1129 int i, sw_thread_mask = 0; 1130 1131 for (i = 0; i < port->nqvecs; i++) 1132 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1133 1134 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1135 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 1136} 1137 1138static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 1139{ 1140 struct mvpp2_port *port = qvec->port; 1141 1142 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1143 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 1144} 1145 1146static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 1147{ 1148 struct mvpp2_port *port = qvec->port; 1149 1150 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1151 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 1152} 1153 1154/* Mask the current thread's Rx/Tx interrupts 1155 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1156 * using smp_processor_id() is OK. 1157 */ 1158static void mvpp2_interrupts_mask(void *arg) 1159{ 1160 struct mvpp2_port *port = arg; 1161 1162 /* If the thread isn't used, don't do anything */ 1163 if (smp_processor_id() > port->priv->nthreads) 1164 return; 1165 1166 mvpp2_thread_write(port->priv, 1167 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1168 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 1169} 1170 1171/* Unmask the current thread's Rx/Tx interrupts. 1172 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1173 * using smp_processor_id() is OK. 1174 */ 1175static void mvpp2_interrupts_unmask(void *arg) 1176{ 1177 struct mvpp2_port *port = arg; 1178 u32 val; 1179 1180 /* If the thread isn't used, don't do anything */ 1181 if (smp_processor_id() >= port->priv->nthreads) 1182 return; 1183 1184 val = MVPP2_CAUSE_MISC_SUM_MASK | 1185 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 1186 if (port->has_tx_irqs) 1187 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 1188 1189 mvpp2_thread_write(port->priv, 1190 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1191 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1192} 1193 1194static void 1195mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 1196{ 1197 u32 val; 1198 int i; 1199 1200 if (port->priv->hw_version != MVPP22) 1201 return; 1202 1203 if (mask) 1204 val = 0; 1205 else 1206 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 1207 1208 for (i = 0; i < port->nqvecs; i++) { 1209 struct mvpp2_queue_vector *v = port->qvecs + i; 1210 1211 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 1212 continue; 1213 1214 mvpp2_thread_write(port->priv, v->sw_thread_id, 1215 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1216 } 1217} 1218 1219/* Only GOP port 0 has an XLG MAC */ 1220static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) 1221{ 1222 return port->gop_id == 0; 1223} 1224 1225static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 1226{ 1227 return !(port->priv->hw_version == MVPP22 && port->gop_id == 0); 1228} 1229 1230/* Port configuration routines */ 1231static bool mvpp2_is_xlg(phy_interface_t interface) 1232{ 1233 return interface == PHY_INTERFACE_MODE_10GBASER || 1234 interface == PHY_INTERFACE_MODE_XAUI; 1235} 1236 1237static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set) 1238{ 1239 u32 old, val; 1240 1241 old = val = readl(ptr); 1242 val &= ~mask; 1243 val |= set; 1244 if (old != val) 1245 writel(val, ptr); 1246} 1247 1248static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 1249{ 1250 struct mvpp2 *priv = port->priv; 1251 u32 val; 1252 1253 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1254 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 1255 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1256 1257 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1258 if (port->gop_id == 2) 1259 val |= GENCONF_CTRL0_PORT0_RGMII; 1260 else if (port->gop_id == 3) 1261 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 1262 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1263} 1264 1265static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1266{ 1267 struct mvpp2 *priv = port->priv; 1268 u32 val; 1269 1270 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1271 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1272 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1273 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1274 1275 if (port->gop_id > 1) { 1276 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1277 if (port->gop_id == 2) 1278 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1279 else if (port->gop_id == 3) 1280 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1281 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1282 } 1283} 1284 1285static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1286{ 1287 struct mvpp2 *priv = port->priv; 1288 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1289 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1290 u32 val; 1291 1292 val = readl(xpcs + MVPP22_XPCS_CFG0); 1293 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1294 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1295 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1296 writel(val, xpcs + MVPP22_XPCS_CFG0); 1297 1298 val = readl(mpcs + MVPP22_MPCS_CTRL); 1299 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1300 writel(val, mpcs + MVPP22_MPCS_CTRL); 1301 1302 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1303 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1304 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1305 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1306} 1307 1308static int mvpp22_gop_init(struct mvpp2_port *port) 1309{ 1310 struct mvpp2 *priv = port->priv; 1311 u32 val; 1312 1313 if (!priv->sysctrl_base) 1314 return 0; 1315 1316 switch (port->phy_interface) { 1317 case PHY_INTERFACE_MODE_RGMII: 1318 case PHY_INTERFACE_MODE_RGMII_ID: 1319 case PHY_INTERFACE_MODE_RGMII_RXID: 1320 case PHY_INTERFACE_MODE_RGMII_TXID: 1321 if (!mvpp2_port_supports_rgmii(port)) 1322 goto invalid_conf; 1323 mvpp22_gop_init_rgmii(port); 1324 break; 1325 case PHY_INTERFACE_MODE_SGMII: 1326 case PHY_INTERFACE_MODE_1000BASEX: 1327 case PHY_INTERFACE_MODE_2500BASEX: 1328 mvpp22_gop_init_sgmii(port); 1329 break; 1330 case PHY_INTERFACE_MODE_10GBASER: 1331 if (!mvpp2_port_supports_xlg(port)) 1332 goto invalid_conf; 1333 mvpp22_gop_init_10gkr(port); 1334 break; 1335 default: 1336 goto unsupported_conf; 1337 } 1338 1339 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1340 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1341 GENCONF_PORT_CTRL1_EN(port->gop_id); 1342 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1343 1344 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1345 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1346 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1347 1348 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1349 val |= GENCONF_SOFT_RESET1_GOP; 1350 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1351 1352unsupported_conf: 1353 return 0; 1354 1355invalid_conf: 1356 netdev_err(port->dev, "Invalid port configuration\n"); 1357 return -EINVAL; 1358} 1359 1360static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1361{ 1362 u32 val; 1363 1364 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1365 phy_interface_mode_is_8023z(port->phy_interface) || 1366 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1367 /* Enable the GMAC link status irq for this port */ 1368 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1369 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1370 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1371 } 1372 1373 if (mvpp2_port_supports_xlg(port)) { 1374 /* Enable the XLG/GIG irqs for this port */ 1375 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1376 if (mvpp2_is_xlg(port->phy_interface)) 1377 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1378 else 1379 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1380 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1381 } 1382} 1383 1384static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1385{ 1386 u32 val; 1387 1388 if (mvpp2_port_supports_xlg(port)) { 1389 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1390 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1391 MVPP22_XLG_EXT_INT_MASK_GIG); 1392 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1393 } 1394 1395 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1396 phy_interface_mode_is_8023z(port->phy_interface) || 1397 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1398 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1399 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1400 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1401 } 1402} 1403 1404static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1405{ 1406 u32 val; 1407 1408 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, 1409 MVPP22_GMAC_INT_SUM_MASK_PTP, 1410 MVPP22_GMAC_INT_SUM_MASK_PTP); 1411 1412 if (port->phylink || 1413 phy_interface_mode_is_rgmii(port->phy_interface) || 1414 phy_interface_mode_is_8023z(port->phy_interface) || 1415 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1416 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1417 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1418 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1419 } 1420 1421 if (mvpp2_port_supports_xlg(port)) { 1422 val = readl(port->base + MVPP22_XLG_INT_MASK); 1423 val |= MVPP22_XLG_INT_MASK_LINK; 1424 writel(val, port->base + MVPP22_XLG_INT_MASK); 1425 1426 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, 1427 MVPP22_XLG_EXT_INT_MASK_PTP, 1428 MVPP22_XLG_EXT_INT_MASK_PTP); 1429 } 1430 1431 mvpp22_gop_unmask_irq(port); 1432} 1433 1434/* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1435 * 1436 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1437 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1438 * differ. 1439 * 1440 * The COMPHY configures the serdes lanes regardless of the actual use of the 1441 * lanes by the physical layer. This is why configurations like 1442 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1443 */ 1444static int mvpp22_comphy_init(struct mvpp2_port *port) 1445{ 1446 int ret; 1447 1448 if (!port->comphy) 1449 return 0; 1450 1451 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1452 port->phy_interface); 1453 if (ret) 1454 return ret; 1455 1456 return phy_power_on(port->comphy); 1457} 1458 1459static void mvpp2_port_enable(struct mvpp2_port *port) 1460{ 1461 u32 val; 1462 1463 if (mvpp2_port_supports_xlg(port) && 1464 mvpp2_is_xlg(port->phy_interface)) { 1465 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1466 val |= MVPP22_XLG_CTRL0_PORT_EN; 1467 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1468 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1469 } else { 1470 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1471 val |= MVPP2_GMAC_PORT_EN_MASK; 1472 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1473 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1474 } 1475} 1476 1477static void mvpp2_port_disable(struct mvpp2_port *port) 1478{ 1479 u32 val; 1480 1481 if (mvpp2_port_supports_xlg(port) && 1482 mvpp2_is_xlg(port->phy_interface)) { 1483 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1484 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1485 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1486 } 1487 1488 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1489 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1490 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1491} 1492 1493/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1494static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1495{ 1496 u32 val; 1497 1498 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1499 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1500 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1501} 1502 1503/* Configure loopback port */ 1504static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1505 const struct phylink_link_state *state) 1506{ 1507 u32 val; 1508 1509 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1510 1511 if (state->speed == 1000) 1512 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1513 else 1514 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1515 1516 if (phy_interface_mode_is_8023z(state->interface) || 1517 state->interface == PHY_INTERFACE_MODE_SGMII) 1518 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1519 else 1520 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1521 1522 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1523} 1524 1525enum { 1526 ETHTOOL_XDP_REDIRECT, 1527 ETHTOOL_XDP_PASS, 1528 ETHTOOL_XDP_DROP, 1529 ETHTOOL_XDP_TX, 1530 ETHTOOL_XDP_TX_ERR, 1531 ETHTOOL_XDP_XMIT, 1532 ETHTOOL_XDP_XMIT_ERR, 1533}; 1534 1535struct mvpp2_ethtool_counter { 1536 unsigned int offset; 1537 const char string[ETH_GSTRING_LEN]; 1538 bool reg_is_64b; 1539}; 1540 1541static u64 mvpp2_read_count(struct mvpp2_port *port, 1542 const struct mvpp2_ethtool_counter *counter) 1543{ 1544 u64 val; 1545 1546 val = readl(port->stats_base + counter->offset); 1547 if (counter->reg_is_64b) 1548 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1549 1550 return val; 1551} 1552 1553/* Some counters are accessed indirectly by first writing an index to 1554 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1555 * register we access, it can be a hit counter for some classification tables, 1556 * a counter specific to a rxq, a txq or a buffer pool. 1557 */ 1558static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1559{ 1560 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1561 return mvpp2_read(priv, reg); 1562} 1563 1564/* Due to the fact that software statistics and hardware statistics are, by 1565 * design, incremented at different moments in the chain of packet processing, 1566 * it is very likely that incoming packets could have been dropped after being 1567 * counted by hardware but before reaching software statistics (most probably 1568 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1569 * are added in between as well as TSO skb will be split and header bytes added. 1570 * Hence, statistics gathered from userspace with ifconfig (software) and 1571 * ethtool (hardware) cannot be compared. 1572 */ 1573static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1574 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1575 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1576 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1577 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1578 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1579 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1580 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1581 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1582 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1583 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1584 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1585 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1586 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1587 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1588 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1589 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1590 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1591 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1592 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1593 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1594 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1595 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1596 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1597 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1598 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1599 { MVPP2_MIB_COLLISION, "collision" }, 1600 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1601}; 1602 1603static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1604 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1605 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1606}; 1607 1608static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1609 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1610 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1611 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1612 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1613 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1614 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1615 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1616 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1617 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1618}; 1619 1620static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1621 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1622 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1623 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1624 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1625}; 1626 1627static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = { 1628 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", }, 1629 { ETHTOOL_XDP_PASS, "rx_xdp_pass", }, 1630 { ETHTOOL_XDP_DROP, "rx_xdp_drop", }, 1631 { ETHTOOL_XDP_TX, "rx_xdp_tx", }, 1632 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", }, 1633 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", }, 1634 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", }, 1635}; 1636 1637#define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1638 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1639 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1640 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \ 1641 ARRAY_SIZE(mvpp2_ethtool_xdp)) 1642 1643static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1644 u8 *data) 1645{ 1646 struct mvpp2_port *port = netdev_priv(netdev); 1647 int i, q; 1648 1649 if (sset != ETH_SS_STATS) 1650 return; 1651 1652 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1653 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1654 ETH_GSTRING_LEN); 1655 data += ETH_GSTRING_LEN; 1656 } 1657 1658 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1659 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1660 ETH_GSTRING_LEN); 1661 data += ETH_GSTRING_LEN; 1662 } 1663 1664 for (q = 0; q < port->ntxqs; q++) { 1665 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1666 snprintf(data, ETH_GSTRING_LEN, 1667 mvpp2_ethtool_txq_regs[i].string, q); 1668 data += ETH_GSTRING_LEN; 1669 } 1670 } 1671 1672 for (q = 0; q < port->nrxqs; q++) { 1673 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1674 snprintf(data, ETH_GSTRING_LEN, 1675 mvpp2_ethtool_rxq_regs[i].string, 1676 q); 1677 data += ETH_GSTRING_LEN; 1678 } 1679 } 1680 1681 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) { 1682 strscpy(data, mvpp2_ethtool_xdp[i].string, 1683 ETH_GSTRING_LEN); 1684 data += ETH_GSTRING_LEN; 1685 } 1686} 1687 1688static void 1689mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) 1690{ 1691 unsigned int start; 1692 unsigned int cpu; 1693 1694 /* Gather XDP Statistics */ 1695 for_each_possible_cpu(cpu) { 1696 struct mvpp2_pcpu_stats *cpu_stats; 1697 u64 xdp_redirect; 1698 u64 xdp_pass; 1699 u64 xdp_drop; 1700 u64 xdp_xmit; 1701 u64 xdp_xmit_err; 1702 u64 xdp_tx; 1703 u64 xdp_tx_err; 1704 1705 cpu_stats = per_cpu_ptr(port->stats, cpu); 1706 do { 1707 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1708 xdp_redirect = cpu_stats->xdp_redirect; 1709 xdp_pass = cpu_stats->xdp_pass; 1710 xdp_drop = cpu_stats->xdp_drop; 1711 xdp_xmit = cpu_stats->xdp_xmit; 1712 xdp_xmit_err = cpu_stats->xdp_xmit_err; 1713 xdp_tx = cpu_stats->xdp_tx; 1714 xdp_tx_err = cpu_stats->xdp_tx_err; 1715 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1716 1717 xdp_stats->xdp_redirect += xdp_redirect; 1718 xdp_stats->xdp_pass += xdp_pass; 1719 xdp_stats->xdp_drop += xdp_drop; 1720 xdp_stats->xdp_xmit += xdp_xmit; 1721 xdp_stats->xdp_xmit_err += xdp_xmit_err; 1722 xdp_stats->xdp_tx += xdp_tx; 1723 xdp_stats->xdp_tx_err += xdp_tx_err; 1724 } 1725} 1726 1727static void mvpp2_read_stats(struct mvpp2_port *port) 1728{ 1729 struct mvpp2_pcpu_stats xdp_stats = {}; 1730 const struct mvpp2_ethtool_counter *s; 1731 u64 *pstats; 1732 int i, q; 1733 1734 pstats = port->ethtool_stats; 1735 1736 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 1737 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 1738 1739 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 1740 *pstats++ += mvpp2_read(port->priv, 1741 mvpp2_ethtool_port_regs[i].offset + 1742 4 * port->id); 1743 1744 for (q = 0; q < port->ntxqs; q++) 1745 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 1746 *pstats++ += mvpp2_read_index(port->priv, 1747 MVPP22_CTRS_TX_CTR(port->id, q), 1748 mvpp2_ethtool_txq_regs[i].offset); 1749 1750 /* Rxqs are numbered from 0 from the user standpoint, but not from the 1751 * driver's. We need to add the port->first_rxq offset. 1752 */ 1753 for (q = 0; q < port->nrxqs; q++) 1754 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 1755 *pstats++ += mvpp2_read_index(port->priv, 1756 port->first_rxq + q, 1757 mvpp2_ethtool_rxq_regs[i].offset); 1758 1759 /* Gather XDP Statistics */ 1760 mvpp2_get_xdp_stats(port, &xdp_stats); 1761 1762 for (i = 0, s = mvpp2_ethtool_xdp; 1763 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp); 1764 s++, i++) { 1765 switch (s->offset) { 1766 case ETHTOOL_XDP_REDIRECT: 1767 *pstats++ = xdp_stats.xdp_redirect; 1768 break; 1769 case ETHTOOL_XDP_PASS: 1770 *pstats++ = xdp_stats.xdp_pass; 1771 break; 1772 case ETHTOOL_XDP_DROP: 1773 *pstats++ = xdp_stats.xdp_drop; 1774 break; 1775 case ETHTOOL_XDP_TX: 1776 *pstats++ = xdp_stats.xdp_tx; 1777 break; 1778 case ETHTOOL_XDP_TX_ERR: 1779 *pstats++ = xdp_stats.xdp_tx_err; 1780 break; 1781 case ETHTOOL_XDP_XMIT: 1782 *pstats++ = xdp_stats.xdp_xmit; 1783 break; 1784 case ETHTOOL_XDP_XMIT_ERR: 1785 *pstats++ = xdp_stats.xdp_xmit_err; 1786 break; 1787 } 1788 } 1789} 1790 1791static void mvpp2_gather_hw_statistics(struct work_struct *work) 1792{ 1793 struct delayed_work *del_work = to_delayed_work(work); 1794 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1795 stats_work); 1796 1797 mutex_lock(&port->gather_stats_lock); 1798 1799 mvpp2_read_stats(port); 1800 1801 /* No need to read again the counters right after this function if it 1802 * was called asynchronously by the user (ie. use of ethtool). 1803 */ 1804 cancel_delayed_work(&port->stats_work); 1805 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1806 MVPP2_MIB_COUNTERS_STATS_DELAY); 1807 1808 mutex_unlock(&port->gather_stats_lock); 1809} 1810 1811static void mvpp2_ethtool_get_stats(struct net_device *dev, 1812 struct ethtool_stats *stats, u64 *data) 1813{ 1814 struct mvpp2_port *port = netdev_priv(dev); 1815 1816 /* Update statistics for the given port, then take the lock to avoid 1817 * concurrent accesses on the ethtool_stats structure during its copy. 1818 */ 1819 mvpp2_gather_hw_statistics(&port->stats_work.work); 1820 1821 mutex_lock(&port->gather_stats_lock); 1822 memcpy(data, port->ethtool_stats, 1823 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 1824 mutex_unlock(&port->gather_stats_lock); 1825} 1826 1827static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1828{ 1829 struct mvpp2_port *port = netdev_priv(dev); 1830 1831 if (sset == ETH_SS_STATS) 1832 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 1833 1834 return -EOPNOTSUPP; 1835} 1836 1837static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 1838{ 1839 u32 val; 1840 1841 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1842 MVPP2_GMAC_PORT_RESET_MASK; 1843 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1844 1845 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 1846 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 1847 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1848 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1849 } 1850} 1851 1852static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 1853{ 1854 struct mvpp2 *priv = port->priv; 1855 void __iomem *mpcs, *xpcs; 1856 u32 val; 1857 1858 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1859 return; 1860 1861 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1862 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1863 1864 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1865 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1866 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 1867 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1868 1869 val = readl(xpcs + MVPP22_XPCS_CFG0); 1870 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1871} 1872 1873static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 1874{ 1875 struct mvpp2 *priv = port->priv; 1876 void __iomem *mpcs, *xpcs; 1877 u32 val; 1878 1879 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1880 return; 1881 1882 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1883 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1884 1885 switch (port->phy_interface) { 1886 case PHY_INTERFACE_MODE_10GBASER: 1887 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1888 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 1889 MAC_CLK_RESET_SD_TX; 1890 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1891 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1892 break; 1893 case PHY_INTERFACE_MODE_XAUI: 1894 case PHY_INTERFACE_MODE_RXAUI: 1895 val = readl(xpcs + MVPP22_XPCS_CFG0); 1896 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1897 break; 1898 default: 1899 break; 1900 } 1901} 1902 1903/* Change maximum receive size of the port */ 1904static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1905{ 1906 u32 val; 1907 1908 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1909 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1910 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1911 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1912 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1913} 1914 1915/* Change maximum receive size of the port */ 1916static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1917{ 1918 u32 val; 1919 1920 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1921 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1922 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1923 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1924 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1925} 1926 1927/* Set defaults to the MVPP2 port */ 1928static void mvpp2_defaults_set(struct mvpp2_port *port) 1929{ 1930 int tx_port_num, val, queue, lrxq; 1931 1932 if (port->priv->hw_version == MVPP21) { 1933 /* Update TX FIFO MIN Threshold */ 1934 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1935 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1936 /* Min. TX threshold must be less than minimal packet length */ 1937 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1938 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1939 } 1940 1941 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1942 tx_port_num = mvpp2_egress_port(port); 1943 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1944 tx_port_num); 1945 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1946 1947 /* Set TXQ scheduling to Round-Robin */ 1948 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1949 1950 /* Close bandwidth for all queues */ 1951 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 1952 mvpp2_write(port->priv, 1953 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 1954 1955 /* Set refill period to 1 usec, refill tokens 1956 * and bucket size to maximum 1957 */ 1958 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1959 port->priv->tclk / USEC_PER_SEC); 1960 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1961 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1962 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1963 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1964 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1965 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1966 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1967 1968 /* Set MaximumLowLatencyPacketSize value to 256 */ 1969 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1970 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1971 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1972 1973 /* Enable Rx cache snoop */ 1974 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1975 queue = port->rxqs[lrxq]->id; 1976 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1977 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1978 MVPP2_SNOOP_BUF_HDR_MASK; 1979 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1980 } 1981 1982 /* At default, mask all interrupts to all present cpus */ 1983 mvpp2_interrupts_disable(port); 1984} 1985 1986/* Enable/disable receiving packets */ 1987static void mvpp2_ingress_enable(struct mvpp2_port *port) 1988{ 1989 u32 val; 1990 int lrxq, queue; 1991 1992 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1993 queue = port->rxqs[lrxq]->id; 1994 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1995 val &= ~MVPP2_RXQ_DISABLE_MASK; 1996 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1997 } 1998} 1999 2000static void mvpp2_ingress_disable(struct mvpp2_port *port) 2001{ 2002 u32 val; 2003 int lrxq, queue; 2004 2005 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2006 queue = port->rxqs[lrxq]->id; 2007 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2008 val |= MVPP2_RXQ_DISABLE_MASK; 2009 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2010 } 2011} 2012 2013/* Enable transmit via physical egress queue 2014 * - HW starts take descriptors from DRAM 2015 */ 2016static void mvpp2_egress_enable(struct mvpp2_port *port) 2017{ 2018 u32 qmap; 2019 int queue; 2020 int tx_port_num = mvpp2_egress_port(port); 2021 2022 /* Enable all initialized TXs. */ 2023 qmap = 0; 2024 for (queue = 0; queue < port->ntxqs; queue++) { 2025 struct mvpp2_tx_queue *txq = port->txqs[queue]; 2026 2027 if (txq->descs) 2028 qmap |= (1 << queue); 2029 } 2030 2031 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2032 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 2033} 2034 2035/* Disable transmit via physical egress queue 2036 * - HW doesn't take descriptors from DRAM 2037 */ 2038static void mvpp2_egress_disable(struct mvpp2_port *port) 2039{ 2040 u32 reg_data; 2041 int delay; 2042 int tx_port_num = mvpp2_egress_port(port); 2043 2044 /* Issue stop command for active channels only */ 2045 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2046 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 2047 MVPP2_TXP_SCHED_ENQ_MASK; 2048 if (reg_data != 0) 2049 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 2050 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 2051 2052 /* Wait for all Tx activity to terminate. */ 2053 delay = 0; 2054 do { 2055 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 2056 netdev_warn(port->dev, 2057 "Tx stop timed out, status=0x%08x\n", 2058 reg_data); 2059 break; 2060 } 2061 mdelay(1); 2062 delay++; 2063 2064 /* Check port TX Command register that all 2065 * Tx queues are stopped 2066 */ 2067 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 2068 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 2069} 2070 2071/* Rx descriptors helper methods */ 2072 2073/* Get number of Rx descriptors occupied by received packets */ 2074static inline int 2075mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 2076{ 2077 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 2078 2079 return val & MVPP2_RXQ_OCCUPIED_MASK; 2080} 2081 2082/* Update Rx queue status with the number of occupied and available 2083 * Rx descriptor slots. 2084 */ 2085static inline void 2086mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 2087 int used_count, int free_count) 2088{ 2089 /* Decrement the number of used descriptors and increment count 2090 * increment the number of free descriptors. 2091 */ 2092 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 2093 2094 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 2095} 2096 2097/* Get pointer to next RX descriptor to be processed by SW */ 2098static inline struct mvpp2_rx_desc * 2099mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 2100{ 2101 int rx_desc = rxq->next_desc_to_proc; 2102 2103 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 2104 prefetch(rxq->descs + rxq->next_desc_to_proc); 2105 return rxq->descs + rx_desc; 2106} 2107 2108/* Set rx queue offset */ 2109static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 2110 int prxq, int offset) 2111{ 2112 u32 val; 2113 2114 /* Convert offset from bytes to units of 32 bytes */ 2115 offset = offset >> 5; 2116 2117 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 2118 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 2119 2120 /* Offset is in */ 2121 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 2122 MVPP2_RXQ_PACKET_OFFSET_MASK); 2123 2124 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 2125} 2126 2127/* Tx descriptors helper methods */ 2128 2129/* Get pointer to next Tx descriptor to be processed (send) by HW */ 2130static struct mvpp2_tx_desc * 2131mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 2132{ 2133 int tx_desc = txq->next_desc_to_proc; 2134 2135 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 2136 return txq->descs + tx_desc; 2137} 2138 2139/* Update HW with number of aggregated Tx descriptors to be sent 2140 * 2141 * Called only from mvpp2_tx(), so migration is disabled, using 2142 * smp_processor_id() is OK. 2143 */ 2144static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 2145{ 2146 /* aggregated access - relevant TXQ number is written in TX desc */ 2147 mvpp2_thread_write(port->priv, 2148 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2149 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 2150} 2151 2152/* Check if there are enough free descriptors in aggregated txq. 2153 * If not, update the number of occupied descriptors and repeat the check. 2154 * 2155 * Called only from mvpp2_tx(), so migration is disabled, using 2156 * smp_processor_id() is OK. 2157 */ 2158static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 2159 struct mvpp2_tx_queue *aggr_txq, int num) 2160{ 2161 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 2162 /* Update number of occupied aggregated Tx descriptors */ 2163 unsigned int thread = 2164 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2165 u32 val = mvpp2_read_relaxed(port->priv, 2166 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 2167 2168 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 2169 2170 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 2171 return -ENOMEM; 2172 } 2173 return 0; 2174} 2175 2176/* Reserved Tx descriptors allocation request 2177 * 2178 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 2179 * only by mvpp2_tx(), so migration is disabled, using 2180 * smp_processor_id() is OK. 2181 */ 2182static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 2183 struct mvpp2_tx_queue *txq, int num) 2184{ 2185 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2186 struct mvpp2 *priv = port->priv; 2187 u32 val; 2188 2189 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 2190 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 2191 2192 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 2193 2194 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 2195} 2196 2197/* Check if there are enough reserved descriptors for transmission. 2198 * If not, request chunk of reserved descriptors and check again. 2199 */ 2200static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 2201 struct mvpp2_tx_queue *txq, 2202 struct mvpp2_txq_pcpu *txq_pcpu, 2203 int num) 2204{ 2205 int req, desc_count; 2206 unsigned int thread; 2207 2208 if (txq_pcpu->reserved_num >= num) 2209 return 0; 2210 2211 /* Not enough descriptors reserved! Update the reserved descriptor 2212 * count and check again. 2213 */ 2214 2215 desc_count = 0; 2216 /* Compute total of used descriptors */ 2217 for (thread = 0; thread < port->priv->nthreads; thread++) { 2218 struct mvpp2_txq_pcpu *txq_pcpu_aux; 2219 2220 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 2221 desc_count += txq_pcpu_aux->count; 2222 desc_count += txq_pcpu_aux->reserved_num; 2223 } 2224 2225 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 2226 desc_count += req; 2227 2228 if (desc_count > 2229 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 2230 return -ENOMEM; 2231 2232 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 2233 2234 /* OK, the descriptor could have been updated: check again. */ 2235 if (txq_pcpu->reserved_num < num) 2236 return -ENOMEM; 2237 return 0; 2238} 2239 2240/* Release the last allocated Tx descriptor. Useful to handle DMA 2241 * mapping failures in the Tx path. 2242 */ 2243static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 2244{ 2245 if (txq->next_desc_to_proc == 0) 2246 txq->next_desc_to_proc = txq->last_desc - 1; 2247 else 2248 txq->next_desc_to_proc--; 2249} 2250 2251/* Set Tx descriptors fields relevant for CSUM calculation */ 2252static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 2253 int ip_hdr_len, int l4_proto) 2254{ 2255 u32 command; 2256 2257 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 2258 * G_L4_chk, L4_type required only for checksum calculation 2259 */ 2260 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 2261 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 2262 command |= MVPP2_TXD_IP_CSUM_DISABLE; 2263 2264 if (l3_proto == htons(ETH_P_IP)) { 2265 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 2266 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 2267 } else { 2268 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 2269 } 2270 2271 if (l4_proto == IPPROTO_TCP) { 2272 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 2273 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2274 } else if (l4_proto == IPPROTO_UDP) { 2275 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 2276 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2277 } else { 2278 command |= MVPP2_TXD_L4_CSUM_NOT; 2279 } 2280 2281 return command; 2282} 2283 2284/* Get number of sent descriptors and decrement counter. 2285 * The number of sent descriptors is returned. 2286 * Per-thread access 2287 * 2288 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 2289 * (migration disabled) and from the TX completion tasklet (migration 2290 * disabled) so using smp_processor_id() is OK. 2291 */ 2292static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 2293 struct mvpp2_tx_queue *txq) 2294{ 2295 u32 val; 2296 2297 /* Reading status reg resets transmitted descriptor counter */ 2298 val = mvpp2_thread_read_relaxed(port->priv, 2299 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2300 MVPP2_TXQ_SENT_REG(txq->id)); 2301 2302 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 2303 MVPP2_TRANSMITTED_COUNT_OFFSET; 2304} 2305 2306/* Called through on_each_cpu(), so runs on all CPUs, with migration 2307 * disabled, therefore using smp_processor_id() is OK. 2308 */ 2309static void mvpp2_txq_sent_counter_clear(void *arg) 2310{ 2311 struct mvpp2_port *port = arg; 2312 int queue; 2313 2314 /* If the thread isn't used, don't do anything */ 2315 if (smp_processor_id() >= port->priv->nthreads) 2316 return; 2317 2318 for (queue = 0; queue < port->ntxqs; queue++) { 2319 int id = port->txqs[queue]->id; 2320 2321 mvpp2_thread_read(port->priv, 2322 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2323 MVPP2_TXQ_SENT_REG(id)); 2324 } 2325} 2326 2327/* Set max sizes for Tx queues */ 2328static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 2329{ 2330 u32 val, size, mtu; 2331 int txq, tx_port_num; 2332 2333 mtu = port->pkt_size * 8; 2334 if (mtu > MVPP2_TXP_MTU_MAX) 2335 mtu = MVPP2_TXP_MTU_MAX; 2336 2337 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 2338 mtu = 3 * mtu; 2339 2340 /* Indirect access to registers */ 2341 tx_port_num = mvpp2_egress_port(port); 2342 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2343 2344 /* Set MTU */ 2345 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 2346 val &= ~MVPP2_TXP_MTU_MAX; 2347 val |= mtu; 2348 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 2349 2350 /* TXP token size and all TXQs token size must be larger that MTU */ 2351 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 2352 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 2353 if (size < mtu) { 2354 size = mtu; 2355 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 2356 val |= size; 2357 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2358 } 2359 2360 for (txq = 0; txq < port->ntxqs; txq++) { 2361 val = mvpp2_read(port->priv, 2362 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 2363 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 2364 2365 if (size < mtu) { 2366 size = mtu; 2367 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 2368 val |= size; 2369 mvpp2_write(port->priv, 2370 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2371 val); 2372 } 2373 } 2374} 2375 2376/* Set the number of packets that will be received before Rx interrupt 2377 * will be generated by HW. 2378 */ 2379static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2380 struct mvpp2_rx_queue *rxq) 2381{ 2382 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2383 2384 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2385 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2386 2387 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2388 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2389 rxq->pkts_coal); 2390 2391 put_cpu(); 2392} 2393 2394/* For some reason in the LSP this is done on each CPU. Why ? */ 2395static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2396 struct mvpp2_tx_queue *txq) 2397{ 2398 unsigned int thread; 2399 u32 val; 2400 2401 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2402 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2403 2404 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2405 /* PKT-coalescing registers are per-queue + per-thread */ 2406 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) { 2407 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2408 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2409 } 2410} 2411 2412static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2413{ 2414 u64 tmp = (u64)clk_hz * usec; 2415 2416 do_div(tmp, USEC_PER_SEC); 2417 2418 return tmp > U32_MAX ? U32_MAX : tmp; 2419} 2420 2421static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2422{ 2423 u64 tmp = (u64)cycles * USEC_PER_SEC; 2424 2425 do_div(tmp, clk_hz); 2426 2427 return tmp > U32_MAX ? U32_MAX : tmp; 2428} 2429 2430/* Set the time delay in usec before Rx interrupt */ 2431static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2432 struct mvpp2_rx_queue *rxq) 2433{ 2434 unsigned long freq = port->priv->tclk; 2435 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2436 2437 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2438 rxq->time_coal = 2439 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2440 2441 /* re-evaluate to get actual register value */ 2442 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2443 } 2444 2445 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2446} 2447 2448static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2449{ 2450 unsigned long freq = port->priv->tclk; 2451 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2452 2453 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2454 port->tx_time_coal = 2455 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2456 2457 /* re-evaluate to get actual register value */ 2458 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2459 } 2460 2461 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2462} 2463 2464/* Free Tx queue skbuffs */ 2465static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2466 struct mvpp2_tx_queue *txq, 2467 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2468{ 2469 int i; 2470 2471 for (i = 0; i < num; i++) { 2472 struct mvpp2_txq_pcpu_buf *tx_buf = 2473 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2474 2475 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && 2476 tx_buf->type != MVPP2_TYPE_XDP_TX) 2477 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2478 tx_buf->size, DMA_TO_DEVICE); 2479 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) 2480 dev_kfree_skb_any(tx_buf->skb); 2481 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || 2482 tx_buf->type == MVPP2_TYPE_XDP_NDO) 2483 xdp_return_frame(tx_buf->xdpf); 2484 2485 mvpp2_txq_inc_get(txq_pcpu); 2486 } 2487} 2488 2489static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2490 u32 cause) 2491{ 2492 int queue = fls(cause) - 1; 2493 2494 return port->rxqs[queue]; 2495} 2496 2497static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2498 u32 cause) 2499{ 2500 int queue = fls(cause) - 1; 2501 2502 return port->txqs[queue]; 2503} 2504 2505/* Handle end of transmission */ 2506static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2507 struct mvpp2_txq_pcpu *txq_pcpu) 2508{ 2509 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2510 int tx_done; 2511 2512 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2513 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2514 2515 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2516 if (!tx_done) 2517 return; 2518 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2519 2520 txq_pcpu->count -= tx_done; 2521 2522 if (netif_tx_queue_stopped(nq)) 2523 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2524 netif_tx_wake_queue(nq); 2525} 2526 2527static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2528 unsigned int thread) 2529{ 2530 struct mvpp2_tx_queue *txq; 2531 struct mvpp2_txq_pcpu *txq_pcpu; 2532 unsigned int tx_todo = 0; 2533 2534 while (cause) { 2535 txq = mvpp2_get_tx_queue(port, cause); 2536 if (!txq) 2537 break; 2538 2539 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2540 2541 if (txq_pcpu->count) { 2542 mvpp2_txq_done(port, txq, txq_pcpu); 2543 tx_todo += txq_pcpu->count; 2544 } 2545 2546 cause &= ~(1 << txq->log_id); 2547 } 2548 return tx_todo; 2549} 2550 2551/* Rx/Tx queue initialization/cleanup methods */ 2552 2553/* Allocate and initialize descriptors for aggr TXQ */ 2554static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2555 struct mvpp2_tx_queue *aggr_txq, 2556 unsigned int thread, struct mvpp2 *priv) 2557{ 2558 u32 txq_dma; 2559 2560 /* Allocate memory for TX descriptors */ 2561 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2562 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2563 &aggr_txq->descs_dma, GFP_KERNEL); 2564 if (!aggr_txq->descs) 2565 return -ENOMEM; 2566 2567 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2568 2569 /* Aggr TXQ no reset WA */ 2570 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2571 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2572 2573 /* Set Tx descriptors queue starting address indirect 2574 * access 2575 */ 2576 if (priv->hw_version == MVPP21) 2577 txq_dma = aggr_txq->descs_dma; 2578 else 2579 txq_dma = aggr_txq->descs_dma >> 2580 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2581 2582 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2583 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2584 MVPP2_AGGR_TXQ_SIZE); 2585 2586 return 0; 2587} 2588 2589/* Create a specified Rx queue */ 2590static int mvpp2_rxq_init(struct mvpp2_port *port, 2591 struct mvpp2_rx_queue *rxq) 2592{ 2593 struct mvpp2 *priv = port->priv; 2594 unsigned int thread; 2595 u32 rxq_dma; 2596 int err; 2597 2598 rxq->size = port->rx_ring_size; 2599 2600 /* Allocate memory for RX descriptors */ 2601 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2602 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2603 &rxq->descs_dma, GFP_KERNEL); 2604 if (!rxq->descs) 2605 return -ENOMEM; 2606 2607 rxq->last_desc = rxq->size - 1; 2608 2609 /* Zero occupied and non-occupied counters - direct access */ 2610 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2611 2612 /* Set Rx descriptors queue starting address - indirect access */ 2613 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2614 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2615 if (port->priv->hw_version == MVPP21) 2616 rxq_dma = rxq->descs_dma; 2617 else 2618 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2619 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2620 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2621 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2622 put_cpu(); 2623 2624 /* Set Offset */ 2625 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); 2626 2627 /* Set coalescing pkts and time */ 2628 mvpp2_rx_pkts_coal_set(port, rxq); 2629 mvpp2_rx_time_coal_set(port, rxq); 2630 2631 /* Add number of descriptors ready for receiving packets */ 2632 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2633 2634 if (priv->percpu_pools) { 2635 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq); 2636 if (err < 0) 2637 goto err_free_dma; 2638 2639 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq); 2640 if (err < 0) 2641 goto err_unregister_rxq_short; 2642 2643 /* Every RXQ has a pool for short and another for long packets */ 2644 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, 2645 MEM_TYPE_PAGE_POOL, 2646 priv->page_pool[rxq->logic_rxq]); 2647 if (err < 0) 2648 goto err_unregister_rxq_long; 2649 2650 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, 2651 MEM_TYPE_PAGE_POOL, 2652 priv->page_pool[rxq->logic_rxq + 2653 port->nrxqs]); 2654 if (err < 0) 2655 goto err_unregister_mem_rxq_short; 2656 } 2657 2658 return 0; 2659 2660err_unregister_mem_rxq_short: 2661 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); 2662err_unregister_rxq_long: 2663 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2664err_unregister_rxq_short: 2665 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2666err_free_dma: 2667 dma_free_coherent(port->dev->dev.parent, 2668 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2669 rxq->descs, rxq->descs_dma); 2670 return err; 2671} 2672 2673/* Push packets received by the RXQ to BM pool */ 2674static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2675 struct mvpp2_rx_queue *rxq) 2676{ 2677 int rx_received, i; 2678 2679 rx_received = mvpp2_rxq_received(port, rxq->id); 2680 if (!rx_received) 2681 return; 2682 2683 for (i = 0; i < rx_received; i++) { 2684 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2685 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2686 int pool; 2687 2688 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2689 MVPP2_RXD_BM_POOL_ID_OFFS; 2690 2691 mvpp2_bm_pool_put(port, pool, 2692 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2693 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2694 } 2695 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2696} 2697 2698/* Cleanup Rx queue */ 2699static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2700 struct mvpp2_rx_queue *rxq) 2701{ 2702 unsigned int thread; 2703 2704 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) 2705 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2706 2707 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) 2708 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2709 2710 mvpp2_rxq_drop_pkts(port, rxq); 2711 2712 if (rxq->descs) 2713 dma_free_coherent(port->dev->dev.parent, 2714 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2715 rxq->descs, 2716 rxq->descs_dma); 2717 2718 rxq->descs = NULL; 2719 rxq->last_desc = 0; 2720 rxq->next_desc_to_proc = 0; 2721 rxq->descs_dma = 0; 2722 2723 /* Clear Rx descriptors queue starting address and size; 2724 * free descriptor number 2725 */ 2726 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2727 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2728 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2729 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2730 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2731 put_cpu(); 2732} 2733 2734/* Create and initialize a Tx queue */ 2735static int mvpp2_txq_init(struct mvpp2_port *port, 2736 struct mvpp2_tx_queue *txq) 2737{ 2738 u32 val; 2739 unsigned int thread; 2740 int desc, desc_per_txq, tx_port_num; 2741 struct mvpp2_txq_pcpu *txq_pcpu; 2742 2743 txq->size = port->tx_ring_size; 2744 2745 /* Allocate memory for Tx descriptors */ 2746 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2747 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2748 &txq->descs_dma, GFP_KERNEL); 2749 if (!txq->descs) 2750 return -ENOMEM; 2751 2752 txq->last_desc = txq->size - 1; 2753 2754 /* Set Tx descriptors queue starting address - indirect access */ 2755 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2756 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2757 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2758 txq->descs_dma); 2759 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2760 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2761 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2762 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2763 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2764 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2765 val &= ~MVPP2_TXQ_PENDING_MASK; 2766 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2767 2768 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2769 * for each existing TXQ. 2770 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2771 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2772 */ 2773 desc_per_txq = 16; 2774 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2775 (txq->log_id * desc_per_txq); 2776 2777 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2778 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2779 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2780 put_cpu(); 2781 2782 /* WRR / EJP configuration - indirect access */ 2783 tx_port_num = mvpp2_egress_port(port); 2784 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2785 2786 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2787 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2788 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2789 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2790 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2791 2792 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2793 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2794 val); 2795 2796 for (thread = 0; thread < port->priv->nthreads; thread++) { 2797 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2798 txq_pcpu->size = txq->size; 2799 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2800 sizeof(*txq_pcpu->buffs), 2801 GFP_KERNEL); 2802 if (!txq_pcpu->buffs) 2803 return -ENOMEM; 2804 2805 txq_pcpu->count = 0; 2806 txq_pcpu->reserved_num = 0; 2807 txq_pcpu->txq_put_index = 0; 2808 txq_pcpu->txq_get_index = 0; 2809 txq_pcpu->tso_headers = NULL; 2810 2811 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2812 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2813 2814 txq_pcpu->tso_headers = 2815 dma_alloc_coherent(port->dev->dev.parent, 2816 txq_pcpu->size * TSO_HEADER_SIZE, 2817 &txq_pcpu->tso_headers_dma, 2818 GFP_KERNEL); 2819 if (!txq_pcpu->tso_headers) 2820 return -ENOMEM; 2821 } 2822 2823 return 0; 2824} 2825 2826/* Free allocated TXQ resources */ 2827static void mvpp2_txq_deinit(struct mvpp2_port *port, 2828 struct mvpp2_tx_queue *txq) 2829{ 2830 struct mvpp2_txq_pcpu *txq_pcpu; 2831 unsigned int thread; 2832 2833 for (thread = 0; thread < port->priv->nthreads; thread++) { 2834 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2835 kfree(txq_pcpu->buffs); 2836 2837 if (txq_pcpu->tso_headers) 2838 dma_free_coherent(port->dev->dev.parent, 2839 txq_pcpu->size * TSO_HEADER_SIZE, 2840 txq_pcpu->tso_headers, 2841 txq_pcpu->tso_headers_dma); 2842 2843 txq_pcpu->tso_headers = NULL; 2844 } 2845 2846 if (txq->descs) 2847 dma_free_coherent(port->dev->dev.parent, 2848 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2849 txq->descs, txq->descs_dma); 2850 2851 txq->descs = NULL; 2852 txq->last_desc = 0; 2853 txq->next_desc_to_proc = 0; 2854 txq->descs_dma = 0; 2855 2856 /* Set minimum bandwidth for disabled TXQs */ 2857 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 2858 2859 /* Set Tx descriptors queue starting address and size */ 2860 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2861 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2862 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2863 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2864 put_cpu(); 2865} 2866 2867/* Cleanup Tx ports */ 2868static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2869{ 2870 struct mvpp2_txq_pcpu *txq_pcpu; 2871 int delay, pending; 2872 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2873 u32 val; 2874 2875 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2876 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2877 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2878 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2879 2880 /* The napi queue has been stopped so wait for all packets 2881 * to be transmitted. 2882 */ 2883 delay = 0; 2884 do { 2885 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2886 netdev_warn(port->dev, 2887 "port %d: cleaning queue %d timed out\n", 2888 port->id, txq->log_id); 2889 break; 2890 } 2891 mdelay(1); 2892 delay++; 2893 2894 pending = mvpp2_thread_read(port->priv, thread, 2895 MVPP2_TXQ_PENDING_REG); 2896 pending &= MVPP2_TXQ_PENDING_MASK; 2897 } while (pending); 2898 2899 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2900 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2901 put_cpu(); 2902 2903 for (thread = 0; thread < port->priv->nthreads; thread++) { 2904 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2905 2906 /* Release all packets */ 2907 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2908 2909 /* Reset queue */ 2910 txq_pcpu->count = 0; 2911 txq_pcpu->txq_put_index = 0; 2912 txq_pcpu->txq_get_index = 0; 2913 } 2914} 2915 2916/* Cleanup all Tx queues */ 2917static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2918{ 2919 struct mvpp2_tx_queue *txq; 2920 int queue; 2921 u32 val; 2922 2923 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2924 2925 /* Reset Tx ports and delete Tx queues */ 2926 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2927 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2928 2929 for (queue = 0; queue < port->ntxqs; queue++) { 2930 txq = port->txqs[queue]; 2931 mvpp2_txq_clean(port, txq); 2932 mvpp2_txq_deinit(port, txq); 2933 } 2934 2935 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2936 2937 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2938 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2939} 2940 2941/* Cleanup all Rx queues */ 2942static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2943{ 2944 int queue; 2945 2946 for (queue = 0; queue < port->nrxqs; queue++) 2947 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2948} 2949 2950/* Init all Rx queues for port */ 2951static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2952{ 2953 int queue, err; 2954 2955 for (queue = 0; queue < port->nrxqs; queue++) { 2956 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2957 if (err) 2958 goto err_cleanup; 2959 } 2960 return 0; 2961 2962err_cleanup: 2963 mvpp2_cleanup_rxqs(port); 2964 return err; 2965} 2966 2967/* Init all tx queues for port */ 2968static int mvpp2_setup_txqs(struct mvpp2_port *port) 2969{ 2970 struct mvpp2_tx_queue *txq; 2971 int queue, err; 2972 2973 for (queue = 0; queue < port->ntxqs; queue++) { 2974 txq = port->txqs[queue]; 2975 err = mvpp2_txq_init(port, txq); 2976 if (err) 2977 goto err_cleanup; 2978 2979 /* Assign this queue to a CPU */ 2980 if (queue < num_possible_cpus()) 2981 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); 2982 } 2983 2984 if (port->has_tx_irqs) { 2985 mvpp2_tx_time_coal_set(port); 2986 for (queue = 0; queue < port->ntxqs; queue++) { 2987 txq = port->txqs[queue]; 2988 mvpp2_tx_pkts_coal_set(port, txq); 2989 } 2990 } 2991 2992 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2993 return 0; 2994 2995err_cleanup: 2996 mvpp2_cleanup_txqs(port); 2997 return err; 2998} 2999 3000/* The callback for per-port interrupt */ 3001static irqreturn_t mvpp2_isr(int irq, void *dev_id) 3002{ 3003 struct mvpp2_queue_vector *qv = dev_id; 3004 3005 mvpp2_qvec_interrupt_disable(qv); 3006 3007 napi_schedule(&qv->napi); 3008 3009 return IRQ_HANDLED; 3010} 3011 3012static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) 3013{ 3014 struct skb_shared_hwtstamps shhwtstamps; 3015 struct mvpp2_hwtstamp_queue *queue; 3016 struct sk_buff *skb; 3017 void __iomem *ptp_q; 3018 unsigned int id; 3019 u32 r0, r1, r2; 3020 3021 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3022 if (nq) 3023 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; 3024 3025 queue = &port->tx_hwtstamp_queue[nq]; 3026 3027 while (1) { 3028 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff; 3029 if (!r0) 3030 break; 3031 3032 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff; 3033 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff; 3034 3035 id = (r0 >> 1) & 31; 3036 3037 skb = queue->skb[id]; 3038 queue->skb[id] = NULL; 3039 if (skb) { 3040 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13; 3041 3042 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); 3043 skb_tstamp_tx(skb, &shhwtstamps); 3044 dev_kfree_skb_any(skb); 3045 } 3046 } 3047} 3048 3049static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) 3050{ 3051 void __iomem *ptp; 3052 u32 val; 3053 3054 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3055 val = readl(ptp + MVPP22_PTP_INT_CAUSE); 3056 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0) 3057 mvpp2_isr_handle_ptp_queue(port, 0); 3058 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1) 3059 mvpp2_isr_handle_ptp_queue(port, 1); 3060} 3061 3062static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) 3063{ 3064 struct net_device *dev = port->dev; 3065 3066 if (port->phylink) { 3067 phylink_mac_change(port->phylink, link); 3068 return; 3069 } 3070 3071 if (!netif_running(dev)) 3072 return; 3073 3074 if (link) { 3075 mvpp2_interrupts_enable(port); 3076 3077 mvpp2_egress_enable(port); 3078 mvpp2_ingress_enable(port); 3079 netif_carrier_on(dev); 3080 netif_tx_wake_all_queues(dev); 3081 } else { 3082 netif_tx_stop_all_queues(dev); 3083 netif_carrier_off(dev); 3084 mvpp2_ingress_disable(port); 3085 mvpp2_egress_disable(port); 3086 3087 mvpp2_interrupts_disable(port); 3088 } 3089} 3090 3091static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) 3092{ 3093 bool link; 3094 u32 val; 3095 3096 val = readl(port->base + MVPP22_XLG_INT_STAT); 3097 if (val & MVPP22_XLG_INT_STAT_LINK) { 3098 val = readl(port->base + MVPP22_XLG_STATUS); 3099 link = (val & MVPP22_XLG_STATUS_LINK_UP); 3100 mvpp2_isr_handle_link(port, link); 3101 } 3102} 3103 3104static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) 3105{ 3106 bool link; 3107 u32 val; 3108 3109 if (phy_interface_mode_is_rgmii(port->phy_interface) || 3110 phy_interface_mode_is_8023z(port->phy_interface) || 3111 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 3112 val = readl(port->base + MVPP22_GMAC_INT_STAT); 3113 if (val & MVPP22_GMAC_INT_STAT_LINK) { 3114 val = readl(port->base + MVPP2_GMAC_STATUS0); 3115 link = (val & MVPP2_GMAC_STATUS0_LINK_UP); 3116 mvpp2_isr_handle_link(port, link); 3117 } 3118 } 3119} 3120 3121/* Per-port interrupt for link status changes */ 3122static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) 3123{ 3124 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 3125 u32 val; 3126 3127 mvpp22_gop_mask_irq(port); 3128 3129 if (mvpp2_port_supports_xlg(port) && 3130 mvpp2_is_xlg(port->phy_interface)) { 3131 /* Check the external status register */ 3132 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); 3133 if (val & MVPP22_XLG_EXT_INT_STAT_XLG) 3134 mvpp2_isr_handle_xlg(port); 3135 if (val & MVPP22_XLG_EXT_INT_STAT_PTP) 3136 mvpp2_isr_handle_ptp(port); 3137 } else { 3138 /* If it's not the XLG, we must be using the GMAC. 3139 * Check the summary status. 3140 */ 3141 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); 3142 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) 3143 mvpp2_isr_handle_gmac_internal(port); 3144 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP) 3145 mvpp2_isr_handle_ptp(port); 3146 } 3147 3148 mvpp22_gop_unmask_irq(port); 3149 return IRQ_HANDLED; 3150} 3151 3152static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 3153{ 3154 struct net_device *dev; 3155 struct mvpp2_port *port; 3156 struct mvpp2_port_pcpu *port_pcpu; 3157 unsigned int tx_todo, cause; 3158 3159 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer); 3160 dev = port_pcpu->dev; 3161 3162 if (!netif_running(dev)) 3163 return HRTIMER_NORESTART; 3164 3165 port_pcpu->timer_scheduled = false; 3166 port = netdev_priv(dev); 3167 3168 /* Process all the Tx queues */ 3169 cause = (1 << port->ntxqs) - 1; 3170 tx_todo = mvpp2_tx_done(port, cause, 3171 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 3172 3173 /* Set the timer in case not all the packets were processed */ 3174 if (tx_todo && !port_pcpu->timer_scheduled) { 3175 port_pcpu->timer_scheduled = true; 3176 hrtimer_forward_now(&port_pcpu->tx_done_timer, 3177 MVPP2_TXDONE_HRTIMER_PERIOD_NS); 3178 3179 return HRTIMER_RESTART; 3180 } 3181 return HRTIMER_NORESTART; 3182} 3183 3184/* Main RX/TX processing routines */ 3185 3186/* Display more error info */ 3187static void mvpp2_rx_error(struct mvpp2_port *port, 3188 struct mvpp2_rx_desc *rx_desc) 3189{ 3190 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3191 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 3192 char *err_str = NULL; 3193 3194 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 3195 case MVPP2_RXD_ERR_CRC: 3196 err_str = "crc"; 3197 break; 3198 case MVPP2_RXD_ERR_OVERRUN: 3199 err_str = "overrun"; 3200 break; 3201 case MVPP2_RXD_ERR_RESOURCE: 3202 err_str = "resource"; 3203 break; 3204 } 3205 if (err_str && net_ratelimit()) 3206 netdev_err(port->dev, 3207 "bad rx status %08x (%s error), size=%zu\n", 3208 status, err_str, sz); 3209} 3210 3211/* Handle RX checksum offload */ 3212static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 3213 struct sk_buff *skb) 3214{ 3215 if (((status & MVPP2_RXD_L3_IP4) && 3216 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 3217 (status & MVPP2_RXD_L3_IP6)) 3218 if (((status & MVPP2_RXD_L4_UDP) || 3219 (status & MVPP2_RXD_L4_TCP)) && 3220 (status & MVPP2_RXD_L4_CSUM_OK)) { 3221 skb->csum = 0; 3222 skb->ip_summed = CHECKSUM_UNNECESSARY; 3223 return; 3224 } 3225 3226 skb->ip_summed = CHECKSUM_NONE; 3227} 3228 3229/* Allocate a new skb and add it to BM pool */ 3230static int mvpp2_rx_refill(struct mvpp2_port *port, 3231 struct mvpp2_bm_pool *bm_pool, 3232 struct page_pool *page_pool, int pool) 3233{ 3234 dma_addr_t dma_addr; 3235 phys_addr_t phys_addr; 3236 void *buf; 3237 3238 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, 3239 &dma_addr, &phys_addr, GFP_ATOMIC); 3240 if (!buf) 3241 return -ENOMEM; 3242 3243 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3244 3245 return 0; 3246} 3247 3248/* Handle tx checksum */ 3249static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 3250{ 3251 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3252 int ip_hdr_len = 0; 3253 u8 l4_proto; 3254 __be16 l3_proto = vlan_get_protocol(skb); 3255 3256 if (l3_proto == htons(ETH_P_IP)) { 3257 struct iphdr *ip4h = ip_hdr(skb); 3258 3259 /* Calculate IPv4 checksum and L4 checksum */ 3260 ip_hdr_len = ip4h->ihl; 3261 l4_proto = ip4h->protocol; 3262 } else if (l3_proto == htons(ETH_P_IPV6)) { 3263 struct ipv6hdr *ip6h = ipv6_hdr(skb); 3264 3265 /* Read l4_protocol from one of IPv6 extra headers */ 3266 if (skb_network_header_len(skb) > 0) 3267 ip_hdr_len = (skb_network_header_len(skb) >> 2); 3268 l4_proto = ip6h->nexthdr; 3269 } else { 3270 return MVPP2_TXD_L4_CSUM_NOT; 3271 } 3272 3273 return mvpp2_txq_desc_csum(skb_network_offset(skb), 3274 l3_proto, ip_hdr_len, l4_proto); 3275 } 3276 3277 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 3278} 3279 3280static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) 3281{ 3282 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3283 struct mvpp2_tx_queue *aggr_txq; 3284 struct mvpp2_txq_pcpu *txq_pcpu; 3285 struct mvpp2_tx_queue *txq; 3286 struct netdev_queue *nq; 3287 3288 txq = port->txqs[txq_id]; 3289 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3290 nq = netdev_get_tx_queue(port->dev, txq_id); 3291 aggr_txq = &port->priv->aggr_txqs[thread]; 3292 3293 txq_pcpu->reserved_num -= nxmit; 3294 txq_pcpu->count += nxmit; 3295 aggr_txq->count += nxmit; 3296 3297 /* Enable transmit */ 3298 wmb(); 3299 mvpp2_aggr_txq_pend_desc_add(port, nxmit); 3300 3301 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3302 netif_tx_stop_queue(nq); 3303 3304 /* Finalize TX processing */ 3305 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3306 mvpp2_txq_done(port, txq, txq_pcpu); 3307} 3308 3309static int 3310mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, 3311 struct xdp_frame *xdpf, bool dma_map) 3312{ 3313 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3314 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | 3315 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3316 enum mvpp2_tx_buf_type buf_type; 3317 struct mvpp2_txq_pcpu *txq_pcpu; 3318 struct mvpp2_tx_queue *aggr_txq; 3319 struct mvpp2_tx_desc *tx_desc; 3320 struct mvpp2_tx_queue *txq; 3321 int ret = MVPP2_XDP_TX; 3322 dma_addr_t dma_addr; 3323 3324 txq = port->txqs[txq_id]; 3325 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3326 aggr_txq = &port->priv->aggr_txqs[thread]; 3327 3328 /* Check number of available descriptors */ 3329 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || 3330 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { 3331 ret = MVPP2_XDP_DROPPED; 3332 goto out; 3333 } 3334 3335 /* Get a descriptor for the first part of the packet */ 3336 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3337 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3338 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); 3339 3340 if (dma_map) { 3341 /* XDP_REDIRECT or AF_XDP */ 3342 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, 3343 xdpf->len, DMA_TO_DEVICE); 3344 3345 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 3346 mvpp2_txq_desc_put(txq); 3347 ret = MVPP2_XDP_DROPPED; 3348 goto out; 3349 } 3350 3351 buf_type = MVPP2_TYPE_XDP_NDO; 3352 } else { 3353 /* XDP_TX */ 3354 struct page *page = virt_to_page(xdpf->data); 3355 3356 dma_addr = page_pool_get_dma_addr(page) + 3357 sizeof(*xdpf) + xdpf->headroom; 3358 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, 3359 xdpf->len, DMA_BIDIRECTIONAL); 3360 3361 buf_type = MVPP2_TYPE_XDP_TX; 3362 } 3363 3364 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); 3365 3366 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3367 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); 3368 3369out: 3370 return ret; 3371} 3372 3373static int 3374mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) 3375{ 3376 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3377 struct xdp_frame *xdpf; 3378 u16 txq_id; 3379 int ret; 3380 3381 xdpf = xdp_convert_buff_to_frame(xdp); 3382 if (unlikely(!xdpf)) 3383 return MVPP2_XDP_DROPPED; 3384 3385 /* The first of the TX queues are used for XPS, 3386 * the second half for XDP_TX 3387 */ 3388 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3389 3390 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); 3391 if (ret == MVPP2_XDP_TX) { 3392 u64_stats_update_begin(&stats->syncp); 3393 stats->tx_bytes += xdpf->len; 3394 stats->tx_packets++; 3395 stats->xdp_tx++; 3396 u64_stats_update_end(&stats->syncp); 3397 3398 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); 3399 } else { 3400 u64_stats_update_begin(&stats->syncp); 3401 stats->xdp_tx_err++; 3402 u64_stats_update_end(&stats->syncp); 3403 } 3404 3405 return ret; 3406} 3407 3408static int 3409mvpp2_xdp_xmit(struct net_device *dev, int num_frame, 3410 struct xdp_frame **frames, u32 flags) 3411{ 3412 struct mvpp2_port *port = netdev_priv(dev); 3413 int i, nxmit_byte = 0, nxmit = num_frame; 3414 struct mvpp2_pcpu_stats *stats; 3415 u16 txq_id; 3416 u32 ret; 3417 3418 if (unlikely(test_bit(0, &port->state))) 3419 return -ENETDOWN; 3420 3421 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3422 return -EINVAL; 3423 3424 /* The first of the TX queues are used for XPS, 3425 * the second half for XDP_TX 3426 */ 3427 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3428 3429 for (i = 0; i < num_frame; i++) { 3430 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); 3431 if (ret == MVPP2_XDP_TX) { 3432 nxmit_byte += frames[i]->len; 3433 } else { 3434 xdp_return_frame_rx_napi(frames[i]); 3435 nxmit--; 3436 } 3437 } 3438 3439 if (likely(nxmit > 0)) 3440 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); 3441 3442 stats = this_cpu_ptr(port->stats); 3443 u64_stats_update_begin(&stats->syncp); 3444 stats->tx_bytes += nxmit_byte; 3445 stats->tx_packets += nxmit; 3446 stats->xdp_xmit += nxmit; 3447 stats->xdp_xmit_err += num_frame - nxmit; 3448 u64_stats_update_end(&stats->syncp); 3449 3450 return nxmit; 3451} 3452 3453static int 3454mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq, 3455 struct bpf_prog *prog, struct xdp_buff *xdp, 3456 struct page_pool *pp, struct mvpp2_pcpu_stats *stats) 3457{ 3458 unsigned int len, sync, err; 3459 struct page *page; 3460 u32 ret, act; 3461 3462 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3463 act = bpf_prog_run_xdp(prog, xdp); 3464 3465 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 3466 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3467 sync = max(sync, len); 3468 3469 switch (act) { 3470 case XDP_PASS: 3471 stats->xdp_pass++; 3472 ret = MVPP2_XDP_PASS; 3473 break; 3474 case XDP_REDIRECT: 3475 err = xdp_do_redirect(port->dev, xdp, prog); 3476 if (unlikely(err)) { 3477 ret = MVPP2_XDP_DROPPED; 3478 page = virt_to_head_page(xdp->data); 3479 page_pool_put_page(pp, page, sync, true); 3480 } else { 3481 ret = MVPP2_XDP_REDIR; 3482 stats->xdp_redirect++; 3483 } 3484 break; 3485 case XDP_TX: 3486 ret = mvpp2_xdp_xmit_back(port, xdp); 3487 if (ret != MVPP2_XDP_TX) { 3488 page = virt_to_head_page(xdp->data); 3489 page_pool_put_page(pp, page, sync, true); 3490 } 3491 break; 3492 default: 3493 bpf_warn_invalid_xdp_action(act); 3494 fallthrough; 3495 case XDP_ABORTED: 3496 trace_xdp_exception(port->dev, prog, act); 3497 fallthrough; 3498 case XDP_DROP: 3499 page = virt_to_head_page(xdp->data); 3500 page_pool_put_page(pp, page, sync, true); 3501 ret = MVPP2_XDP_DROPPED; 3502 stats->xdp_drop++; 3503 break; 3504 } 3505 3506 return ret; 3507} 3508 3509static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc, 3510 int pool, u32 rx_status) 3511{ 3512 phys_addr_t phys_addr, phys_addr_next; 3513 dma_addr_t dma_addr, dma_addr_next; 3514 struct mvpp2_buff_hdr *buff_hdr; 3515 3516 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3517 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3518 3519 do { 3520 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr); 3521 3522 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr); 3523 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr); 3524 3525 if (port->priv->hw_version >= MVPP22) { 3526 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32); 3527 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32); 3528 } 3529 3530 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3531 3532 phys_addr = phys_addr_next; 3533 dma_addr = dma_addr_next; 3534 3535 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info))); 3536} 3537 3538/* Main rx processing */ 3539static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 3540 int rx_todo, struct mvpp2_rx_queue *rxq) 3541{ 3542 struct net_device *dev = port->dev; 3543 struct mvpp2_pcpu_stats ps = {}; 3544 enum dma_data_direction dma_dir; 3545 struct bpf_prog *xdp_prog; 3546 struct xdp_buff xdp; 3547 int rx_received; 3548 int rx_done = 0; 3549 u32 xdp_ret = 0; 3550 3551 rcu_read_lock(); 3552 3553 xdp_prog = READ_ONCE(port->xdp_prog); 3554 3555 /* Get number of received packets and clamp the to-do */ 3556 rx_received = mvpp2_rxq_received(port, rxq->id); 3557 if (rx_todo > rx_received) 3558 rx_todo = rx_received; 3559 3560 while (rx_done < rx_todo) { 3561 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3562 struct mvpp2_bm_pool *bm_pool; 3563 struct page_pool *pp = NULL; 3564 struct sk_buff *skb; 3565 unsigned int frag_size; 3566 dma_addr_t dma_addr; 3567 phys_addr_t phys_addr; 3568 u32 rx_status, timestamp; 3569 int pool, rx_bytes, err, ret; 3570 void *data; 3571 3572 rx_done++; 3573 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 3574 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 3575 rx_bytes -= MVPP2_MH_SIZE; 3576 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3577 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3578 data = (void *)phys_to_virt(phys_addr); 3579 3580 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3581 MVPP2_RXD_BM_POOL_ID_OFFS; 3582 bm_pool = &port->priv->bm_pools[pool]; 3583 3584 if (port->priv->percpu_pools) { 3585 pp = port->priv->page_pool[pool]; 3586 dma_dir = page_pool_get_dma_dir(pp); 3587 } else { 3588 dma_dir = DMA_FROM_DEVICE; 3589 } 3590 3591 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, 3592 rx_bytes + MVPP2_MH_SIZE, 3593 dma_dir); 3594 3595 /* Buffer header not supported */ 3596 if (rx_status & MVPP2_RXD_BUF_HDR) 3597 goto err_drop_frame; 3598 3599 /* In case of an error, release the requested buffer pointer 3600 * to the Buffer Manager. This request process is controlled 3601 * by the hardware, and the information about the buffer is 3602 * comprised by the RX descriptor. 3603 */ 3604 if (rx_status & MVPP2_RXD_ERR_SUMMARY) 3605 goto err_drop_frame; 3606 3607 /* Prefetch header */ 3608 prefetch(data); 3609 3610 if (bm_pool->frag_size > PAGE_SIZE) 3611 frag_size = 0; 3612 else 3613 frag_size = bm_pool->frag_size; 3614 3615 if (xdp_prog) { 3616 xdp.data_hard_start = data; 3617 xdp.data = data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM; 3618 xdp.data_end = xdp.data + rx_bytes; 3619 xdp.frame_sz = PAGE_SIZE; 3620 3621 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) 3622 xdp.rxq = &rxq->xdp_rxq_short; 3623 else 3624 xdp.rxq = &rxq->xdp_rxq_long; 3625 3626 xdp_set_data_meta_invalid(&xdp); 3627 3628 ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps); 3629 3630 if (ret) { 3631 xdp_ret |= ret; 3632 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3633 if (err) { 3634 netdev_err(port->dev, "failed to refill BM pools\n"); 3635 goto err_drop_frame; 3636 } 3637 3638 ps.rx_packets++; 3639 ps.rx_bytes += rx_bytes; 3640 continue; 3641 } 3642 } 3643 3644 skb = build_skb(data, frag_size); 3645 if (!skb) { 3646 netdev_warn(port->dev, "skb build failed\n"); 3647 goto err_drop_frame; 3648 } 3649 3650 /* If we have RX hardware timestamping enabled, grab the 3651 * timestamp from the queue and convert. 3652 */ 3653 if (mvpp22_rx_hwtstamping(port)) { 3654 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); 3655 mvpp22_tai_tstamp(port->priv->tai, timestamp, 3656 skb_hwtstamps(skb)); 3657 } 3658 3659 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3660 if (err) { 3661 netdev_err(port->dev, "failed to refill BM pools\n"); 3662 dev_kfree_skb_any(skb); 3663 goto err_drop_frame; 3664 } 3665 3666 if (pp) 3667 page_pool_release_page(pp, virt_to_page(data)); 3668 else 3669 dma_unmap_single_attrs(dev->dev.parent, dma_addr, 3670 bm_pool->buf_size, DMA_FROM_DEVICE, 3671 DMA_ATTR_SKIP_CPU_SYNC); 3672 3673 ps.rx_packets++; 3674 ps.rx_bytes += rx_bytes; 3675 3676 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 3677 skb_put(skb, rx_bytes); 3678 skb->protocol = eth_type_trans(skb, dev); 3679 mvpp2_rx_csum(port, rx_status, skb); 3680 3681 napi_gro_receive(napi, skb); 3682 continue; 3683 3684err_drop_frame: 3685 dev->stats.rx_errors++; 3686 mvpp2_rx_error(port, rx_desc); 3687 /* Return the buffer to the pool */ 3688 if (rx_status & MVPP2_RXD_BUF_HDR) 3689 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status); 3690 else 3691 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3692 } 3693 3694 rcu_read_unlock(); 3695 3696 if (xdp_ret & MVPP2_XDP_REDIR) 3697 xdp_do_flush_map(); 3698 3699 if (ps.rx_packets) { 3700 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3701 3702 u64_stats_update_begin(&stats->syncp); 3703 stats->rx_packets += ps.rx_packets; 3704 stats->rx_bytes += ps.rx_bytes; 3705 /* xdp */ 3706 stats->xdp_redirect += ps.xdp_redirect; 3707 stats->xdp_pass += ps.xdp_pass; 3708 stats->xdp_drop += ps.xdp_drop; 3709 u64_stats_update_end(&stats->syncp); 3710 } 3711 3712 /* Update Rx queue management counters */ 3713 wmb(); 3714 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 3715 3716 return rx_todo; 3717} 3718 3719static inline void 3720tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 3721 struct mvpp2_tx_desc *desc) 3722{ 3723 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3724 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3725 3726 dma_addr_t buf_dma_addr = 3727 mvpp2_txdesc_dma_addr_get(port, desc); 3728 size_t buf_sz = 3729 mvpp2_txdesc_size_get(port, desc); 3730 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 3731 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 3732 buf_sz, DMA_TO_DEVICE); 3733 mvpp2_txq_desc_put(txq); 3734} 3735 3736static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, 3737 struct mvpp2_tx_desc *desc) 3738{ 3739 /* We only need to clear the low bits */ 3740 if (port->priv->hw_version != MVPP21) 3741 desc->pp22.ptp_descriptor &= 3742 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 3743} 3744 3745static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, 3746 struct mvpp2_tx_desc *tx_desc, 3747 struct sk_buff *skb) 3748{ 3749 struct mvpp2_hwtstamp_queue *queue; 3750 unsigned int mtype, type, i; 3751 struct ptp_header *hdr; 3752 u64 ptpdesc; 3753 3754 if (port->priv->hw_version == MVPP21 || 3755 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) 3756 return false; 3757 3758 type = ptp_classify_raw(skb); 3759 if (!type) 3760 return false; 3761 3762 hdr = ptp_parse_header(skb, type); 3763 if (!hdr) 3764 return false; 3765 3766 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3767 3768 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN | 3769 MVPP22_PTP_ACTION_CAPTURE; 3770 queue = &port->tx_hwtstamp_queue[0]; 3771 3772 switch (type & PTP_CLASS_VMASK) { 3773 case PTP_CLASS_V1: 3774 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1); 3775 break; 3776 3777 case PTP_CLASS_V2: 3778 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2); 3779 mtype = hdr->tsmt & 15; 3780 /* Direct PTP Sync messages to queue 1 */ 3781 if (mtype == 0) { 3782 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT; 3783 queue = &port->tx_hwtstamp_queue[1]; 3784 } 3785 break; 3786 } 3787 3788 /* Take a reference on the skb and insert into our queue */ 3789 i = queue->next; 3790 queue->next = (i + 1) & 31; 3791 if (queue->skb[i]) 3792 dev_kfree_skb_any(queue->skb[i]); 3793 queue->skb[i] = skb_get(skb); 3794 3795 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i); 3796 3797 /* 3798 * 3:0 - PTPAction 3799 * 6:4 - PTPPacketFormat 3800 * 7 - PTP_CF_WraparoundCheckEn 3801 * 9:8 - IngressTimestampSeconds[1:0] 3802 * 10 - Reserved 3803 * 11 - MACTimestampingEn 3804 * 17:12 - PTP_TimestampQueueEntryID[5:0] 3805 * 18 - PTPTimestampQueueSelect 3806 * 19 - UDPChecksumUpdateEn 3807 * 27:20 - TimestampOffset 3808 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header 3809 * NTPTs, Y.1731 - L3 to timestamp entry 3810 * 35:28 - UDP Checksum Offset 3811 * 3812 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12) 3813 */ 3814 tx_desc->pp22.ptp_descriptor &= 3815 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 3816 tx_desc->pp22.ptp_descriptor |= 3817 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW); 3818 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); 3819 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); 3820 3821 return true; 3822} 3823 3824/* Handle tx fragmentation processing */ 3825static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 3826 struct mvpp2_tx_queue *aggr_txq, 3827 struct mvpp2_tx_queue *txq) 3828{ 3829 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3830 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3831 struct mvpp2_tx_desc *tx_desc; 3832 int i; 3833 dma_addr_t buf_dma_addr; 3834 3835 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3836 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3837 void *addr = skb_frag_address(frag); 3838 3839 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3840 mvpp2_txdesc_clear_ptp(port, tx_desc); 3841 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3842 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 3843 3844 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 3845 skb_frag_size(frag), 3846 DMA_TO_DEVICE); 3847 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 3848 mvpp2_txq_desc_put(txq); 3849 goto cleanup; 3850 } 3851 3852 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3853 3854 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 3855 /* Last descriptor */ 3856 mvpp2_txdesc_cmd_set(port, tx_desc, 3857 MVPP2_TXD_L_DESC); 3858 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 3859 } else { 3860 /* Descriptor in the middle: Not First, Not Last */ 3861 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3862 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3863 } 3864 } 3865 3866 return 0; 3867cleanup: 3868 /* Release all descriptors that were used to map fragments of 3869 * this packet, as well as the corresponding DMA mappings 3870 */ 3871 for (i = i - 1; i >= 0; i--) { 3872 tx_desc = txq->descs + i; 3873 tx_desc_unmap_put(port, txq, tx_desc); 3874 } 3875 3876 return -ENOMEM; 3877} 3878 3879static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 3880 struct net_device *dev, 3881 struct mvpp2_tx_queue *txq, 3882 struct mvpp2_tx_queue *aggr_txq, 3883 struct mvpp2_txq_pcpu *txq_pcpu, 3884 int hdr_sz) 3885{ 3886 struct mvpp2_port *port = netdev_priv(dev); 3887 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3888 dma_addr_t addr; 3889 3890 mvpp2_txdesc_clear_ptp(port, tx_desc); 3891 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3892 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 3893 3894 addr = txq_pcpu->tso_headers_dma + 3895 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3896 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 3897 3898 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 3899 MVPP2_TXD_F_DESC | 3900 MVPP2_TXD_PADDING_DISABLE); 3901 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3902} 3903 3904static inline int mvpp2_tso_put_data(struct sk_buff *skb, 3905 struct net_device *dev, struct tso_t *tso, 3906 struct mvpp2_tx_queue *txq, 3907 struct mvpp2_tx_queue *aggr_txq, 3908 struct mvpp2_txq_pcpu *txq_pcpu, 3909 int sz, bool left, bool last) 3910{ 3911 struct mvpp2_port *port = netdev_priv(dev); 3912 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3913 dma_addr_t buf_dma_addr; 3914 3915 mvpp2_txdesc_clear_ptp(port, tx_desc); 3916 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3917 mvpp2_txdesc_size_set(port, tx_desc, sz); 3918 3919 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 3920 DMA_TO_DEVICE); 3921 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3922 mvpp2_txq_desc_put(txq); 3923 return -ENOMEM; 3924 } 3925 3926 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3927 3928 if (!left) { 3929 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 3930 if (last) { 3931 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 3932 return 0; 3933 } 3934 } else { 3935 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3936 } 3937 3938 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3939 return 0; 3940} 3941 3942static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 3943 struct mvpp2_tx_queue *txq, 3944 struct mvpp2_tx_queue *aggr_txq, 3945 struct mvpp2_txq_pcpu *txq_pcpu) 3946{ 3947 struct mvpp2_port *port = netdev_priv(dev); 3948 int hdr_sz, i, len, descs = 0; 3949 struct tso_t tso; 3950 3951 /* Check number of available descriptors */ 3952 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 3953 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 3954 tso_count_descs(skb))) 3955 return 0; 3956 3957 hdr_sz = tso_start(skb, &tso); 3958 3959 len = skb->len - hdr_sz; 3960 while (len > 0) { 3961 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 3962 char *hdr = txq_pcpu->tso_headers + 3963 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3964 3965 len -= left; 3966 descs++; 3967 3968 tso_build_hdr(skb, hdr, &tso, left, len == 0); 3969 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 3970 3971 while (left > 0) { 3972 int sz = min_t(int, tso.size, left); 3973 left -= sz; 3974 descs++; 3975 3976 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 3977 txq_pcpu, sz, left, len == 0)) 3978 goto release; 3979 tso_build_data(skb, &tso, sz); 3980 } 3981 } 3982 3983 return descs; 3984 3985release: 3986 for (i = descs - 1; i >= 0; i--) { 3987 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 3988 tx_desc_unmap_put(port, txq, tx_desc); 3989 } 3990 return 0; 3991} 3992 3993/* Main tx processing */ 3994static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 3995{ 3996 struct mvpp2_port *port = netdev_priv(dev); 3997 struct mvpp2_tx_queue *txq, *aggr_txq; 3998 struct mvpp2_txq_pcpu *txq_pcpu; 3999 struct mvpp2_tx_desc *tx_desc; 4000 dma_addr_t buf_dma_addr; 4001 unsigned long flags = 0; 4002 unsigned int thread; 4003 int frags = 0; 4004 u16 txq_id; 4005 u32 tx_cmd; 4006 4007 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4008 4009 txq_id = skb_get_queue_mapping(skb); 4010 txq = port->txqs[txq_id]; 4011 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4012 aggr_txq = &port->priv->aggr_txqs[thread]; 4013 4014 if (test_bit(thread, &port->priv->lock_map)) 4015 spin_lock_irqsave(&port->tx_lock[thread], flags); 4016 4017 if (skb_is_gso(skb)) { 4018 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 4019 goto out; 4020 } 4021 frags = skb_shinfo(skb)->nr_frags + 1; 4022 4023 /* Check number of available descriptors */ 4024 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 4025 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 4026 frags = 0; 4027 goto out; 4028 } 4029 4030 /* Get a descriptor for the first part of the packet */ 4031 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4032 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || 4033 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) 4034 mvpp2_txdesc_clear_ptp(port, tx_desc); 4035 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4036 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 4037 4038 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 4039 skb_headlen(skb), DMA_TO_DEVICE); 4040 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4041 mvpp2_txq_desc_put(txq); 4042 frags = 0; 4043 goto out; 4044 } 4045 4046 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4047 4048 tx_cmd = mvpp2_skb_tx_csum(port, skb); 4049 4050 if (frags == 1) { 4051 /* First and Last descriptor */ 4052 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 4053 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4054 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4055 } else { 4056 /* First but not Last */ 4057 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 4058 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4059 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4060 4061 /* Continue with other skb fragments */ 4062 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 4063 tx_desc_unmap_put(port, txq, tx_desc); 4064 frags = 0; 4065 } 4066 } 4067 4068out: 4069 if (frags > 0) { 4070 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 4071 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 4072 4073 txq_pcpu->reserved_num -= frags; 4074 txq_pcpu->count += frags; 4075 aggr_txq->count += frags; 4076 4077 /* Enable transmit */ 4078 wmb(); 4079 mvpp2_aggr_txq_pend_desc_add(port, frags); 4080 4081 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 4082 netif_tx_stop_queue(nq); 4083 4084 u64_stats_update_begin(&stats->syncp); 4085 stats->tx_packets++; 4086 stats->tx_bytes += skb->len; 4087 u64_stats_update_end(&stats->syncp); 4088 } else { 4089 dev->stats.tx_dropped++; 4090 dev_kfree_skb_any(skb); 4091 } 4092 4093 /* Finalize TX processing */ 4094 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 4095 mvpp2_txq_done(port, txq, txq_pcpu); 4096 4097 /* Set the timer in case not all frags were processed */ 4098 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 4099 txq_pcpu->count > 0) { 4100 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 4101 4102 if (!port_pcpu->timer_scheduled) { 4103 port_pcpu->timer_scheduled = true; 4104 hrtimer_start(&port_pcpu->tx_done_timer, 4105 MVPP2_TXDONE_HRTIMER_PERIOD_NS, 4106 HRTIMER_MODE_REL_PINNED_SOFT); 4107 } 4108 } 4109 4110 if (test_bit(thread, &port->priv->lock_map)) 4111 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 4112 4113 return NETDEV_TX_OK; 4114} 4115 4116static inline void mvpp2_cause_error(struct net_device *dev, int cause) 4117{ 4118 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 4119 netdev_err(dev, "FCS error\n"); 4120 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 4121 netdev_err(dev, "rx fifo overrun error\n"); 4122 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 4123 netdev_err(dev, "tx fifo underrun error\n"); 4124} 4125 4126static int mvpp2_poll(struct napi_struct *napi, int budget) 4127{ 4128 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 4129 int rx_done = 0; 4130 struct mvpp2_port *port = netdev_priv(napi->dev); 4131 struct mvpp2_queue_vector *qv; 4132 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4133 4134 qv = container_of(napi, struct mvpp2_queue_vector, napi); 4135 4136 /* Rx/Tx cause register 4137 * 4138 * Bits 0-15: each bit indicates received packets on the Rx queue 4139 * (bit 0 is for Rx queue 0). 4140 * 4141 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 4142 * (bit 16 is for Tx queue 0). 4143 * 4144 * Each CPU has its own Rx/Tx cause register 4145 */ 4146 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 4147 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 4148 4149 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 4150 if (cause_misc) { 4151 mvpp2_cause_error(port->dev, cause_misc); 4152 4153 /* Clear the cause register */ 4154 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 4155 mvpp2_thread_write(port->priv, thread, 4156 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 4157 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 4158 } 4159 4160 if (port->has_tx_irqs) { 4161 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 4162 if (cause_tx) { 4163 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 4164 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 4165 } 4166 } 4167 4168 /* Process RX packets */ 4169 cause_rx = cause_rx_tx & 4170 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 4171 cause_rx <<= qv->first_rxq; 4172 cause_rx |= qv->pending_cause_rx; 4173 while (cause_rx && budget > 0) { 4174 int count; 4175 struct mvpp2_rx_queue *rxq; 4176 4177 rxq = mvpp2_get_rx_queue(port, cause_rx); 4178 if (!rxq) 4179 break; 4180 4181 count = mvpp2_rx(port, napi, budget, rxq); 4182 rx_done += count; 4183 budget -= count; 4184 if (budget > 0) { 4185 /* Clear the bit associated to this Rx queue 4186 * so that next iteration will continue from 4187 * the next Rx queue. 4188 */ 4189 cause_rx &= ~(1 << rxq->logic_rxq); 4190 } 4191 } 4192 4193 if (budget > 0) { 4194 cause_rx = 0; 4195 napi_complete_done(napi, rx_done); 4196 4197 mvpp2_qvec_interrupt_enable(qv); 4198 } 4199 qv->pending_cause_rx = cause_rx; 4200 return rx_done; 4201} 4202 4203static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 4204{ 4205 u32 ctrl3; 4206 4207 /* Set the GMAC & XLG MAC in reset */ 4208 mvpp2_mac_reset_assert(port); 4209 4210 /* Set the MPCS and XPCS in reset */ 4211 mvpp22_pcs_reset_assert(port); 4212 4213 /* comphy reconfiguration */ 4214 mvpp22_comphy_init(port); 4215 4216 /* gop reconfiguration */ 4217 mvpp22_gop_init(port); 4218 4219 mvpp22_pcs_reset_deassert(port); 4220 4221 if (mvpp2_port_supports_xlg(port)) { 4222 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 4223 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4224 4225 if (mvpp2_is_xlg(port->phy_interface)) 4226 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 4227 else 4228 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 4229 4230 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 4231 } 4232 4233 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface)) 4234 mvpp2_xlg_max_rx_size_set(port); 4235 else 4236 mvpp2_gmac_max_rx_size_set(port); 4237} 4238 4239/* Set hw internals when starting port */ 4240static void mvpp2_start_dev(struct mvpp2_port *port) 4241{ 4242 int i; 4243 4244 mvpp2_txp_max_tx_size_set(port); 4245 4246 for (i = 0; i < port->nqvecs; i++) 4247 napi_enable(&port->qvecs[i].napi); 4248 4249 /* Enable interrupts on all threads */ 4250 mvpp2_interrupts_enable(port); 4251 4252 if (port->priv->hw_version == MVPP22) 4253 mvpp22_mode_reconfigure(port); 4254 4255 if (port->phylink) { 4256 phylink_start(port->phylink); 4257 } else { 4258 mvpp2_acpi_start(port); 4259 } 4260 4261 netif_tx_start_all_queues(port->dev); 4262 4263 clear_bit(0, &port->state); 4264} 4265 4266/* Set hw internals when stopping port */ 4267static void mvpp2_stop_dev(struct mvpp2_port *port) 4268{ 4269 int i; 4270 4271 set_bit(0, &port->state); 4272 4273 /* Disable interrupts on all threads */ 4274 mvpp2_interrupts_disable(port); 4275 4276 for (i = 0; i < port->nqvecs; i++) 4277 napi_disable(&port->qvecs[i].napi); 4278 4279 if (port->phylink) 4280 phylink_stop(port->phylink); 4281 phy_power_off(port->comphy); 4282} 4283 4284static int mvpp2_check_ringparam_valid(struct net_device *dev, 4285 struct ethtool_ringparam *ring) 4286{ 4287 u16 new_rx_pending = ring->rx_pending; 4288 u16 new_tx_pending = ring->tx_pending; 4289 4290 if (ring->rx_pending == 0 || ring->tx_pending == 0) 4291 return -EINVAL; 4292 4293 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 4294 new_rx_pending = MVPP2_MAX_RXD_MAX; 4295 else if (!IS_ALIGNED(ring->rx_pending, 16)) 4296 new_rx_pending = ALIGN(ring->rx_pending, 16); 4297 4298 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 4299 new_tx_pending = MVPP2_MAX_TXD_MAX; 4300 else if (!IS_ALIGNED(ring->tx_pending, 32)) 4301 new_tx_pending = ALIGN(ring->tx_pending, 32); 4302 4303 /* The Tx ring size cannot be smaller than the minimum number of 4304 * descriptors needed for TSO. 4305 */ 4306 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 4307 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 4308 4309 if (ring->rx_pending != new_rx_pending) { 4310 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 4311 ring->rx_pending, new_rx_pending); 4312 ring->rx_pending = new_rx_pending; 4313 } 4314 4315 if (ring->tx_pending != new_tx_pending) { 4316 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 4317 ring->tx_pending, new_tx_pending); 4318 ring->tx_pending = new_tx_pending; 4319 } 4320 4321 return 0; 4322} 4323 4324static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 4325{ 4326 u32 mac_addr_l, mac_addr_m, mac_addr_h; 4327 4328 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 4329 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 4330 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 4331 addr[0] = (mac_addr_h >> 24) & 0xFF; 4332 addr[1] = (mac_addr_h >> 16) & 0xFF; 4333 addr[2] = (mac_addr_h >> 8) & 0xFF; 4334 addr[3] = mac_addr_h & 0xFF; 4335 addr[4] = mac_addr_m & 0xFF; 4336 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 4337} 4338 4339static int mvpp2_irqs_init(struct mvpp2_port *port) 4340{ 4341 int err, i; 4342 4343 for (i = 0; i < port->nqvecs; i++) { 4344 struct mvpp2_queue_vector *qv = port->qvecs + i; 4345 4346 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4347 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 4348 if (!qv->mask) { 4349 err = -ENOMEM; 4350 goto err; 4351 } 4352 4353 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 4354 } 4355 4356 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 4357 if (err) 4358 goto err; 4359 4360 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4361 unsigned int cpu; 4362 4363 for_each_present_cpu(cpu) { 4364 if (mvpp2_cpu_to_thread(port->priv, cpu) == 4365 qv->sw_thread_id) 4366 cpumask_set_cpu(cpu, qv->mask); 4367 } 4368 4369 irq_set_affinity_hint(qv->irq, qv->mask); 4370 } 4371 } 4372 4373 return 0; 4374err: 4375 for (i = 0; i < port->nqvecs; i++) { 4376 struct mvpp2_queue_vector *qv = port->qvecs + i; 4377 4378 irq_set_affinity_hint(qv->irq, NULL); 4379 kfree(qv->mask); 4380 qv->mask = NULL; 4381 free_irq(qv->irq, qv); 4382 } 4383 4384 return err; 4385} 4386 4387static void mvpp2_irqs_deinit(struct mvpp2_port *port) 4388{ 4389 int i; 4390 4391 for (i = 0; i < port->nqvecs; i++) { 4392 struct mvpp2_queue_vector *qv = port->qvecs + i; 4393 4394 irq_set_affinity_hint(qv->irq, NULL); 4395 kfree(qv->mask); 4396 qv->mask = NULL; 4397 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 4398 free_irq(qv->irq, qv); 4399 } 4400} 4401 4402static bool mvpp22_rss_is_supported(void) 4403{ 4404 return queue_mode == MVPP2_QDIST_MULTI_MODE; 4405} 4406 4407static int mvpp2_open(struct net_device *dev) 4408{ 4409 struct mvpp2_port *port = netdev_priv(dev); 4410 struct mvpp2 *priv = port->priv; 4411 unsigned char mac_bcast[ETH_ALEN] = { 4412 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4413 bool valid = false; 4414 int err; 4415 4416 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 4417 if (err) { 4418 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 4419 return err; 4420 } 4421 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 4422 if (err) { 4423 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 4424 return err; 4425 } 4426 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 4427 if (err) { 4428 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 4429 return err; 4430 } 4431 err = mvpp2_prs_def_flow(port); 4432 if (err) { 4433 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 4434 return err; 4435 } 4436 4437 /* Allocate the Rx/Tx queues */ 4438 err = mvpp2_setup_rxqs(port); 4439 if (err) { 4440 netdev_err(port->dev, "cannot allocate Rx queues\n"); 4441 return err; 4442 } 4443 4444 err = mvpp2_setup_txqs(port); 4445 if (err) { 4446 netdev_err(port->dev, "cannot allocate Tx queues\n"); 4447 goto err_cleanup_rxqs; 4448 } 4449 4450 err = mvpp2_irqs_init(port); 4451 if (err) { 4452 netdev_err(port->dev, "cannot init IRQs\n"); 4453 goto err_cleanup_txqs; 4454 } 4455 4456 /* Phylink isn't supported yet in ACPI mode */ 4457 if (port->of_node) { 4458 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 4459 if (err) { 4460 netdev_err(port->dev, "could not attach PHY (%d)\n", 4461 err); 4462 goto err_free_irq; 4463 } 4464 4465 valid = true; 4466 } 4467 4468 if (priv->hw_version == MVPP22 && port->port_irq) { 4469 err = request_irq(port->port_irq, mvpp2_port_isr, 0, 4470 dev->name, port); 4471 if (err) { 4472 netdev_err(port->dev, 4473 "cannot request port link/ptp IRQ %d\n", 4474 port->port_irq); 4475 goto err_free_irq; 4476 } 4477 4478 mvpp22_gop_setup_irq(port); 4479 4480 /* In default link is down */ 4481 netif_carrier_off(port->dev); 4482 4483 valid = true; 4484 } else { 4485 port->port_irq = 0; 4486 } 4487 4488 if (!valid) { 4489 netdev_err(port->dev, 4490 "invalid configuration: no dt or link IRQ"); 4491 err = -ENOENT; 4492 goto err_free_irq; 4493 } 4494 4495 /* Unmask interrupts on all CPUs */ 4496 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 4497 mvpp2_shared_interrupt_mask_unmask(port, false); 4498 4499 mvpp2_start_dev(port); 4500 4501 /* Start hardware statistics gathering */ 4502 queue_delayed_work(priv->stats_queue, &port->stats_work, 4503 MVPP2_MIB_COUNTERS_STATS_DELAY); 4504 4505 return 0; 4506 4507err_free_irq: 4508 mvpp2_irqs_deinit(port); 4509err_cleanup_txqs: 4510 mvpp2_cleanup_txqs(port); 4511err_cleanup_rxqs: 4512 mvpp2_cleanup_rxqs(port); 4513 return err; 4514} 4515 4516static int mvpp2_stop(struct net_device *dev) 4517{ 4518 struct mvpp2_port *port = netdev_priv(dev); 4519 struct mvpp2_port_pcpu *port_pcpu; 4520 unsigned int thread; 4521 4522 mvpp2_stop_dev(port); 4523 4524 /* Mask interrupts on all threads */ 4525 on_each_cpu(mvpp2_interrupts_mask, port, 1); 4526 mvpp2_shared_interrupt_mask_unmask(port, true); 4527 4528 if (port->phylink) 4529 phylink_disconnect_phy(port->phylink); 4530 if (port->port_irq) 4531 free_irq(port->port_irq, port); 4532 4533 mvpp2_irqs_deinit(port); 4534 if (!port->has_tx_irqs) { 4535 for (thread = 0; thread < port->priv->nthreads; thread++) { 4536 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4537 4538 hrtimer_cancel(&port_pcpu->tx_done_timer); 4539 port_pcpu->timer_scheduled = false; 4540 } 4541 } 4542 mvpp2_cleanup_rxqs(port); 4543 mvpp2_cleanup_txqs(port); 4544 4545 cancel_delayed_work_sync(&port->stats_work); 4546 4547 mvpp2_mac_reset_assert(port); 4548 mvpp22_pcs_reset_assert(port); 4549 4550 return 0; 4551} 4552 4553static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 4554 struct netdev_hw_addr_list *list) 4555{ 4556 struct netdev_hw_addr *ha; 4557 int ret; 4558 4559 netdev_hw_addr_list_for_each(ha, list) { 4560 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 4561 if (ret) 4562 return ret; 4563 } 4564 4565 return 0; 4566} 4567 4568static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 4569{ 4570 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 4571 mvpp2_prs_vid_enable_filtering(port); 4572 else 4573 mvpp2_prs_vid_disable_filtering(port); 4574 4575 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4576 MVPP2_PRS_L2_UNI_CAST, enable); 4577 4578 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4579 MVPP2_PRS_L2_MULTI_CAST, enable); 4580} 4581 4582static void mvpp2_set_rx_mode(struct net_device *dev) 4583{ 4584 struct mvpp2_port *port = netdev_priv(dev); 4585 4586 /* Clear the whole UC and MC list */ 4587 mvpp2_prs_mac_del_all(port); 4588 4589 if (dev->flags & IFF_PROMISC) { 4590 mvpp2_set_rx_promisc(port, true); 4591 return; 4592 } 4593 4594 mvpp2_set_rx_promisc(port, false); 4595 4596 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 4597 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 4598 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4599 MVPP2_PRS_L2_UNI_CAST, true); 4600 4601 if (dev->flags & IFF_ALLMULTI) { 4602 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4603 MVPP2_PRS_L2_MULTI_CAST, true); 4604 return; 4605 } 4606 4607 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 4608 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 4609 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4610 MVPP2_PRS_L2_MULTI_CAST, true); 4611} 4612 4613static int mvpp2_set_mac_address(struct net_device *dev, void *p) 4614{ 4615 const struct sockaddr *addr = p; 4616 int err; 4617 4618 if (!is_valid_ether_addr(addr->sa_data)) 4619 return -EADDRNOTAVAIL; 4620 4621 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 4622 if (err) { 4623 /* Reconfigure parser accept the original MAC address */ 4624 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 4625 netdev_err(dev, "failed to change MAC address\n"); 4626 } 4627 return err; 4628} 4629 4630/* Shut down all the ports, reconfigure the pools as percpu or shared, 4631 * then bring up again all ports. 4632 */ 4633static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu) 4634{ 4635 int numbufs = MVPP2_BM_POOLS_NUM, i; 4636 struct mvpp2_port *port = NULL; 4637 bool status[MVPP2_MAX_PORTS]; 4638 4639 for (i = 0; i < priv->port_count; i++) { 4640 port = priv->port_list[i]; 4641 status[i] = netif_running(port->dev); 4642 if (status[i]) 4643 mvpp2_stop(port->dev); 4644 } 4645 4646 /* nrxqs is the same for all ports */ 4647 if (priv->percpu_pools) 4648 numbufs = port->nrxqs * 2; 4649 4650 for (i = 0; i < numbufs; i++) 4651 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); 4652 4653 devm_kfree(port->dev->dev.parent, priv->bm_pools); 4654 priv->percpu_pools = percpu; 4655 mvpp2_bm_init(port->dev->dev.parent, priv); 4656 4657 for (i = 0; i < priv->port_count; i++) { 4658 port = priv->port_list[i]; 4659 mvpp2_swf_bm_pool_init(port); 4660 if (status[i]) 4661 mvpp2_open(port->dev); 4662 } 4663 4664 return 0; 4665} 4666 4667static int mvpp2_change_mtu(struct net_device *dev, int mtu) 4668{ 4669 struct mvpp2_port *port = netdev_priv(dev); 4670 bool running = netif_running(dev); 4671 struct mvpp2 *priv = port->priv; 4672 int err; 4673 4674 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 4675 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 4676 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 4677 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 4678 } 4679 4680 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) { 4681 netdev_err(dev, "Illegal MTU value %d (> %d) for XDP mode\n", 4682 mtu, (int)MVPP2_MAX_RX_BUF_SIZE); 4683 return -EINVAL; 4684 } 4685 4686 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) { 4687 if (priv->percpu_pools) { 4688 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu); 4689 mvpp2_bm_switch_buffers(priv, false); 4690 } 4691 } else { 4692 bool jumbo = false; 4693 int i; 4694 4695 for (i = 0; i < priv->port_count; i++) 4696 if (priv->port_list[i] != port && 4697 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > 4698 MVPP2_BM_LONG_PKT_SIZE) { 4699 jumbo = true; 4700 break; 4701 } 4702 4703 /* No port is using jumbo frames */ 4704 if (!jumbo) { 4705 dev_info(port->dev->dev.parent, 4706 "all ports have a low MTU, switching to per-cpu buffers"); 4707 mvpp2_bm_switch_buffers(priv, true); 4708 } 4709 } 4710 4711 if (running) 4712 mvpp2_stop_dev(port); 4713 4714 err = mvpp2_bm_update_mtu(dev, mtu); 4715 if (err) { 4716 netdev_err(dev, "failed to change MTU\n"); 4717 /* Reconfigure BM to the original MTU */ 4718 mvpp2_bm_update_mtu(dev, dev->mtu); 4719 } else { 4720 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 4721 } 4722 4723 if (running) { 4724 mvpp2_start_dev(port); 4725 mvpp2_egress_enable(port); 4726 mvpp2_ingress_enable(port); 4727 } 4728 4729 return err; 4730} 4731 4732static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) 4733{ 4734 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 4735 struct mvpp2 *priv = port->priv; 4736 int err = -1, i; 4737 4738 if (!priv->percpu_pools) 4739 return err; 4740 4741 if (!priv->page_pool[0]) 4742 return -ENOMEM; 4743 4744 for (i = 0; i < priv->port_count; i++) { 4745 port = priv->port_list[i]; 4746 if (port->xdp_prog) { 4747 dma_dir = DMA_BIDIRECTIONAL; 4748 break; 4749 } 4750 } 4751 4752 /* All pools are equal in terms of DMA direction */ 4753 if (priv->page_pool[0]->p.dma_dir != dma_dir) 4754 err = mvpp2_bm_switch_buffers(priv, true); 4755 4756 return err; 4757} 4758 4759static void 4760mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4761{ 4762 struct mvpp2_port *port = netdev_priv(dev); 4763 unsigned int start; 4764 unsigned int cpu; 4765 4766 for_each_possible_cpu(cpu) { 4767 struct mvpp2_pcpu_stats *cpu_stats; 4768 u64 rx_packets; 4769 u64 rx_bytes; 4770 u64 tx_packets; 4771 u64 tx_bytes; 4772 4773 cpu_stats = per_cpu_ptr(port->stats, cpu); 4774 do { 4775 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 4776 rx_packets = cpu_stats->rx_packets; 4777 rx_bytes = cpu_stats->rx_bytes; 4778 tx_packets = cpu_stats->tx_packets; 4779 tx_bytes = cpu_stats->tx_bytes; 4780 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 4781 4782 stats->rx_packets += rx_packets; 4783 stats->rx_bytes += rx_bytes; 4784 stats->tx_packets += tx_packets; 4785 stats->tx_bytes += tx_bytes; 4786 } 4787 4788 stats->rx_errors = dev->stats.rx_errors; 4789 stats->rx_dropped = dev->stats.rx_dropped; 4790 stats->tx_dropped = dev->stats.tx_dropped; 4791} 4792 4793static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 4794{ 4795 struct hwtstamp_config config; 4796 void __iomem *ptp; 4797 u32 gcr, int_mask; 4798 4799 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 4800 return -EFAULT; 4801 4802 if (config.flags) 4803 return -EINVAL; 4804 4805 if (config.tx_type != HWTSTAMP_TX_OFF && 4806 config.tx_type != HWTSTAMP_TX_ON) 4807 return -ERANGE; 4808 4809 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 4810 4811 int_mask = gcr = 0; 4812 if (config.tx_type != HWTSTAMP_TX_OFF) { 4813 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET; 4814 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 | 4815 MVPP22_PTP_INT_MASK_QUEUE0; 4816 } 4817 4818 /* It seems we must also release the TX reset when enabling the TSU */ 4819 if (config.rx_filter != HWTSTAMP_FILTER_NONE) 4820 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET | 4821 MVPP22_PTP_GCR_TX_RESET; 4822 4823 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE) 4824 mvpp22_tai_start(port->priv->tai); 4825 4826 if (config.rx_filter != HWTSTAMP_FILTER_NONE) { 4827 config.rx_filter = HWTSTAMP_FILTER_ALL; 4828 mvpp2_modify(ptp + MVPP22_PTP_GCR, 4829 MVPP22_PTP_GCR_RX_RESET | 4830 MVPP22_PTP_GCR_TX_RESET | 4831 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 4832 port->rx_hwtstamp = true; 4833 } else { 4834 port->rx_hwtstamp = false; 4835 mvpp2_modify(ptp + MVPP22_PTP_GCR, 4836 MVPP22_PTP_GCR_RX_RESET | 4837 MVPP22_PTP_GCR_TX_RESET | 4838 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 4839 } 4840 4841 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK, 4842 MVPP22_PTP_INT_MASK_QUEUE1 | 4843 MVPP22_PTP_INT_MASK_QUEUE0, int_mask); 4844 4845 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE)) 4846 mvpp22_tai_stop(port->priv->tai); 4847 4848 port->tx_hwtstamp_type = config.tx_type; 4849 4850 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 4851 return -EFAULT; 4852 4853 return 0; 4854} 4855 4856static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 4857{ 4858 struct hwtstamp_config config; 4859 4860 memset(&config, 0, sizeof(config)); 4861 4862 config.tx_type = port->tx_hwtstamp_type; 4863 config.rx_filter = port->rx_hwtstamp ? 4864 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 4865 4866 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 4867 return -EFAULT; 4868 4869 return 0; 4870} 4871 4872static int mvpp2_ethtool_get_ts_info(struct net_device *dev, 4873 struct ethtool_ts_info *info) 4874{ 4875 struct mvpp2_port *port = netdev_priv(dev); 4876 4877 if (!port->hwtstamp) 4878 return -EOPNOTSUPP; 4879 4880 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); 4881 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 4882 SOF_TIMESTAMPING_RX_SOFTWARE | 4883 SOF_TIMESTAMPING_SOFTWARE | 4884 SOF_TIMESTAMPING_TX_HARDWARE | 4885 SOF_TIMESTAMPING_RX_HARDWARE | 4886 SOF_TIMESTAMPING_RAW_HARDWARE; 4887 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 4888 BIT(HWTSTAMP_TX_ON); 4889 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 4890 BIT(HWTSTAMP_FILTER_ALL); 4891 4892 return 0; 4893} 4894 4895static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4896{ 4897 struct mvpp2_port *port = netdev_priv(dev); 4898 4899 switch (cmd) { 4900 case SIOCSHWTSTAMP: 4901 if (port->hwtstamp) 4902 return mvpp2_set_ts_config(port, ifr); 4903 break; 4904 4905 case SIOCGHWTSTAMP: 4906 if (port->hwtstamp) 4907 return mvpp2_get_ts_config(port, ifr); 4908 break; 4909 } 4910 4911 if (!port->phylink) 4912 return -ENOTSUPP; 4913 4914 return phylink_mii_ioctl(port->phylink, ifr, cmd); 4915} 4916 4917static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 4918{ 4919 struct mvpp2_port *port = netdev_priv(dev); 4920 int ret; 4921 4922 ret = mvpp2_prs_vid_entry_add(port, vid); 4923 if (ret) 4924 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 4925 MVPP2_PRS_VLAN_FILT_MAX - 1); 4926 return ret; 4927} 4928 4929static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 4930{ 4931 struct mvpp2_port *port = netdev_priv(dev); 4932 4933 mvpp2_prs_vid_entry_remove(port, vid); 4934 return 0; 4935} 4936 4937static int mvpp2_set_features(struct net_device *dev, 4938 netdev_features_t features) 4939{ 4940 netdev_features_t changed = dev->features ^ features; 4941 struct mvpp2_port *port = netdev_priv(dev); 4942 4943 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 4944 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 4945 mvpp2_prs_vid_enable_filtering(port); 4946 } else { 4947 /* Invalidate all registered VID filters for this 4948 * port 4949 */ 4950 mvpp2_prs_vid_remove_all(port); 4951 4952 mvpp2_prs_vid_disable_filtering(port); 4953 } 4954 } 4955 4956 if (changed & NETIF_F_RXHASH) { 4957 if (features & NETIF_F_RXHASH) 4958 mvpp22_port_rss_enable(port); 4959 else 4960 mvpp22_port_rss_disable(port); 4961 } 4962 4963 return 0; 4964} 4965 4966static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) 4967{ 4968 struct bpf_prog *prog = bpf->prog, *old_prog; 4969 bool running = netif_running(port->dev); 4970 bool reset = !prog != !port->xdp_prog; 4971 4972 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) { 4973 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP"); 4974 return -EOPNOTSUPP; 4975 } 4976 4977 if (!port->priv->percpu_pools) { 4978 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); 4979 return -EOPNOTSUPP; 4980 } 4981 4982 if (port->ntxqs < num_possible_cpus() * 2) { 4983 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); 4984 return -EOPNOTSUPP; 4985 } 4986 4987 /* device is up and bpf is added/removed, must setup the RX queues */ 4988 if (running && reset) 4989 mvpp2_stop(port->dev); 4990 4991 old_prog = xchg(&port->xdp_prog, prog); 4992 if (old_prog) 4993 bpf_prog_put(old_prog); 4994 4995 /* bpf is just replaced, RXQ and MTU are already setup */ 4996 if (!reset) 4997 return 0; 4998 4999 /* device was up, restore the link */ 5000 if (running) 5001 mvpp2_open(port->dev); 5002 5003 /* Check Page Pool DMA Direction */ 5004 mvpp2_check_pagepool_dma(port); 5005 5006 return 0; 5007} 5008 5009static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp) 5010{ 5011 struct mvpp2_port *port = netdev_priv(dev); 5012 5013 switch (xdp->command) { 5014 case XDP_SETUP_PROG: 5015 return mvpp2_xdp_setup(port, xdp); 5016 default: 5017 return -EINVAL; 5018 } 5019} 5020 5021/* Ethtool methods */ 5022 5023static int mvpp2_ethtool_nway_reset(struct net_device *dev) 5024{ 5025 struct mvpp2_port *port = netdev_priv(dev); 5026 5027 if (!port->phylink) 5028 return -ENOTSUPP; 5029 5030 return phylink_ethtool_nway_reset(port->phylink); 5031} 5032 5033/* Set interrupt coalescing for ethtools */ 5034static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 5035 struct ethtool_coalesce *c) 5036{ 5037 struct mvpp2_port *port = netdev_priv(dev); 5038 int queue; 5039 5040 for (queue = 0; queue < port->nrxqs; queue++) { 5041 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5042 5043 rxq->time_coal = c->rx_coalesce_usecs; 5044 rxq->pkts_coal = c->rx_max_coalesced_frames; 5045 mvpp2_rx_pkts_coal_set(port, rxq); 5046 mvpp2_rx_time_coal_set(port, rxq); 5047 } 5048 5049 if (port->has_tx_irqs) { 5050 port->tx_time_coal = c->tx_coalesce_usecs; 5051 mvpp2_tx_time_coal_set(port); 5052 } 5053 5054 for (queue = 0; queue < port->ntxqs; queue++) { 5055 struct mvpp2_tx_queue *txq = port->txqs[queue]; 5056 5057 txq->done_pkts_coal = c->tx_max_coalesced_frames; 5058 5059 if (port->has_tx_irqs) 5060 mvpp2_tx_pkts_coal_set(port, txq); 5061 } 5062 5063 return 0; 5064} 5065 5066/* get coalescing for ethtools */ 5067static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 5068 struct ethtool_coalesce *c) 5069{ 5070 struct mvpp2_port *port = netdev_priv(dev); 5071 5072 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 5073 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 5074 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 5075 c->tx_coalesce_usecs = port->tx_time_coal; 5076 return 0; 5077} 5078 5079static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 5080 struct ethtool_drvinfo *drvinfo) 5081{ 5082 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 5083 sizeof(drvinfo->driver)); 5084 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 5085 sizeof(drvinfo->version)); 5086 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 5087 sizeof(drvinfo->bus_info)); 5088} 5089 5090static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 5091 struct ethtool_ringparam *ring) 5092{ 5093 struct mvpp2_port *port = netdev_priv(dev); 5094 5095 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 5096 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 5097 ring->rx_pending = port->rx_ring_size; 5098 ring->tx_pending = port->tx_ring_size; 5099} 5100 5101static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 5102 struct ethtool_ringparam *ring) 5103{ 5104 struct mvpp2_port *port = netdev_priv(dev); 5105 u16 prev_rx_ring_size = port->rx_ring_size; 5106 u16 prev_tx_ring_size = port->tx_ring_size; 5107 int err; 5108 5109 err = mvpp2_check_ringparam_valid(dev, ring); 5110 if (err) 5111 return err; 5112 5113 if (!netif_running(dev)) { 5114 port->rx_ring_size = ring->rx_pending; 5115 port->tx_ring_size = ring->tx_pending; 5116 return 0; 5117 } 5118 5119 /* The interface is running, so we have to force a 5120 * reallocation of the queues 5121 */ 5122 mvpp2_stop_dev(port); 5123 mvpp2_cleanup_rxqs(port); 5124 mvpp2_cleanup_txqs(port); 5125 5126 port->rx_ring_size = ring->rx_pending; 5127 port->tx_ring_size = ring->tx_pending; 5128 5129 err = mvpp2_setup_rxqs(port); 5130 if (err) { 5131 /* Reallocate Rx queues with the original ring size */ 5132 port->rx_ring_size = prev_rx_ring_size; 5133 ring->rx_pending = prev_rx_ring_size; 5134 err = mvpp2_setup_rxqs(port); 5135 if (err) 5136 goto err_out; 5137 } 5138 err = mvpp2_setup_txqs(port); 5139 if (err) { 5140 /* Reallocate Tx queues with the original ring size */ 5141 port->tx_ring_size = prev_tx_ring_size; 5142 ring->tx_pending = prev_tx_ring_size; 5143 err = mvpp2_setup_txqs(port); 5144 if (err) 5145 goto err_clean_rxqs; 5146 } 5147 5148 mvpp2_start_dev(port); 5149 mvpp2_egress_enable(port); 5150 mvpp2_ingress_enable(port); 5151 5152 return 0; 5153 5154err_clean_rxqs: 5155 mvpp2_cleanup_rxqs(port); 5156err_out: 5157 netdev_err(dev, "failed to change ring parameters"); 5158 return err; 5159} 5160 5161static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 5162 struct ethtool_pauseparam *pause) 5163{ 5164 struct mvpp2_port *port = netdev_priv(dev); 5165 5166 if (!port->phylink) 5167 return; 5168 5169 phylink_ethtool_get_pauseparam(port->phylink, pause); 5170} 5171 5172static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 5173 struct ethtool_pauseparam *pause) 5174{ 5175 struct mvpp2_port *port = netdev_priv(dev); 5176 5177 if (!port->phylink) 5178 return -ENOTSUPP; 5179 5180 return phylink_ethtool_set_pauseparam(port->phylink, pause); 5181} 5182 5183static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 5184 struct ethtool_link_ksettings *cmd) 5185{ 5186 struct mvpp2_port *port = netdev_priv(dev); 5187 5188 if (!port->phylink) 5189 return -ENOTSUPP; 5190 5191 return phylink_ethtool_ksettings_get(port->phylink, cmd); 5192} 5193 5194static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 5195 const struct ethtool_link_ksettings *cmd) 5196{ 5197 struct mvpp2_port *port = netdev_priv(dev); 5198 5199 if (!port->phylink) 5200 return -ENOTSUPP; 5201 5202 return phylink_ethtool_ksettings_set(port->phylink, cmd); 5203} 5204 5205static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 5206 struct ethtool_rxnfc *info, u32 *rules) 5207{ 5208 struct mvpp2_port *port = netdev_priv(dev); 5209 int ret = 0, i, loc = 0; 5210 5211 if (!mvpp22_rss_is_supported()) 5212 return -EOPNOTSUPP; 5213 5214 switch (info->cmd) { 5215 case ETHTOOL_GRXFH: 5216 ret = mvpp2_ethtool_rxfh_get(port, info); 5217 break; 5218 case ETHTOOL_GRXRINGS: 5219 info->data = port->nrxqs; 5220 break; 5221 case ETHTOOL_GRXCLSRLCNT: 5222 info->rule_cnt = port->n_rfs_rules; 5223 break; 5224 case ETHTOOL_GRXCLSRULE: 5225 ret = mvpp2_ethtool_cls_rule_get(port, info); 5226 break; 5227 case ETHTOOL_GRXCLSRLALL: 5228 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 5229 if (loc == info->rule_cnt) { 5230 ret = -EMSGSIZE; 5231 break; 5232 } 5233 5234 if (port->rfs_rules[i]) 5235 rules[loc++] = i; 5236 } 5237 break; 5238 default: 5239 return -ENOTSUPP; 5240 } 5241 5242 return ret; 5243} 5244 5245static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 5246 struct ethtool_rxnfc *info) 5247{ 5248 struct mvpp2_port *port = netdev_priv(dev); 5249 int ret = 0; 5250 5251 if (!mvpp22_rss_is_supported()) 5252 return -EOPNOTSUPP; 5253 5254 switch (info->cmd) { 5255 case ETHTOOL_SRXFH: 5256 ret = mvpp2_ethtool_rxfh_set(port, info); 5257 break; 5258 case ETHTOOL_SRXCLSRLINS: 5259 ret = mvpp2_ethtool_cls_rule_ins(port, info); 5260 break; 5261 case ETHTOOL_SRXCLSRLDEL: 5262 ret = mvpp2_ethtool_cls_rule_del(port, info); 5263 break; 5264 default: 5265 return -EOPNOTSUPP; 5266 } 5267 return ret; 5268} 5269 5270static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 5271{ 5272 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 5273} 5274 5275static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 5276 u8 *hfunc) 5277{ 5278 struct mvpp2_port *port = netdev_priv(dev); 5279 int ret = 0; 5280 5281 if (!mvpp22_rss_is_supported()) 5282 return -EOPNOTSUPP; 5283 5284 if (indir) 5285 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 5286 5287 if (hfunc) 5288 *hfunc = ETH_RSS_HASH_CRC32; 5289 5290 return ret; 5291} 5292 5293static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 5294 const u8 *key, const u8 hfunc) 5295{ 5296 struct mvpp2_port *port = netdev_priv(dev); 5297 int ret = 0; 5298 5299 if (!mvpp22_rss_is_supported()) 5300 return -EOPNOTSUPP; 5301 5302 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5303 return -EOPNOTSUPP; 5304 5305 if (key) 5306 return -EOPNOTSUPP; 5307 5308 if (indir) 5309 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 5310 5311 return ret; 5312} 5313 5314static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 5315 u8 *key, u8 *hfunc, u32 rss_context) 5316{ 5317 struct mvpp2_port *port = netdev_priv(dev); 5318 int ret = 0; 5319 5320 if (!mvpp22_rss_is_supported()) 5321 return -EOPNOTSUPP; 5322 if (rss_context >= MVPP22_N_RSS_TABLES) 5323 return -EINVAL; 5324 5325 if (hfunc) 5326 *hfunc = ETH_RSS_HASH_CRC32; 5327 5328 if (indir) 5329 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 5330 5331 return ret; 5332} 5333 5334static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 5335 const u32 *indir, const u8 *key, 5336 const u8 hfunc, u32 *rss_context, 5337 bool delete) 5338{ 5339 struct mvpp2_port *port = netdev_priv(dev); 5340 int ret; 5341 5342 if (!mvpp22_rss_is_supported()) 5343 return -EOPNOTSUPP; 5344 5345 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5346 return -EOPNOTSUPP; 5347 5348 if (key) 5349 return -EOPNOTSUPP; 5350 5351 if (delete) 5352 return mvpp22_port_rss_ctx_delete(port, *rss_context); 5353 5354 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 5355 ret = mvpp22_port_rss_ctx_create(port, rss_context); 5356 if (ret) 5357 return ret; 5358 } 5359 5360 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 5361} 5362/* Device ops */ 5363 5364static const struct net_device_ops mvpp2_netdev_ops = { 5365 .ndo_open = mvpp2_open, 5366 .ndo_stop = mvpp2_stop, 5367 .ndo_start_xmit = mvpp2_tx, 5368 .ndo_set_rx_mode = mvpp2_set_rx_mode, 5369 .ndo_set_mac_address = mvpp2_set_mac_address, 5370 .ndo_change_mtu = mvpp2_change_mtu, 5371 .ndo_get_stats64 = mvpp2_get_stats64, 5372 .ndo_do_ioctl = mvpp2_ioctl, 5373 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 5374 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 5375 .ndo_set_features = mvpp2_set_features, 5376 .ndo_bpf = mvpp2_xdp, 5377 .ndo_xdp_xmit = mvpp2_xdp_xmit, 5378}; 5379 5380static const struct ethtool_ops mvpp2_eth_tool_ops = { 5381 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5382 ETHTOOL_COALESCE_MAX_FRAMES, 5383 .nway_reset = mvpp2_ethtool_nway_reset, 5384 .get_link = ethtool_op_get_link, 5385 .get_ts_info = mvpp2_ethtool_get_ts_info, 5386 .set_coalesce = mvpp2_ethtool_set_coalesce, 5387 .get_coalesce = mvpp2_ethtool_get_coalesce, 5388 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 5389 .get_ringparam = mvpp2_ethtool_get_ringparam, 5390 .set_ringparam = mvpp2_ethtool_set_ringparam, 5391 .get_strings = mvpp2_ethtool_get_strings, 5392 .get_ethtool_stats = mvpp2_ethtool_get_stats, 5393 .get_sset_count = mvpp2_ethtool_get_sset_count, 5394 .get_pauseparam = mvpp2_ethtool_get_pause_param, 5395 .set_pauseparam = mvpp2_ethtool_set_pause_param, 5396 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 5397 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 5398 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 5399 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 5400 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 5401 .get_rxfh = mvpp2_ethtool_get_rxfh, 5402 .set_rxfh = mvpp2_ethtool_set_rxfh, 5403 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 5404 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 5405}; 5406 5407/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 5408 * had a single IRQ defined per-port. 5409 */ 5410static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 5411 struct device_node *port_node) 5412{ 5413 struct mvpp2_queue_vector *v = &port->qvecs[0]; 5414 5415 v->first_rxq = 0; 5416 v->nrxqs = port->nrxqs; 5417 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5418 v->sw_thread_id = 0; 5419 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 5420 v->port = port; 5421 v->irq = irq_of_parse_and_map(port_node, 0); 5422 if (v->irq <= 0) 5423 return -EINVAL; 5424 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5425 NAPI_POLL_WEIGHT); 5426 5427 port->nqvecs = 1; 5428 5429 return 0; 5430} 5431 5432static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 5433 struct device_node *port_node) 5434{ 5435 struct mvpp2 *priv = port->priv; 5436 struct mvpp2_queue_vector *v; 5437 int i, ret; 5438 5439 switch (queue_mode) { 5440 case MVPP2_QDIST_SINGLE_MODE: 5441 port->nqvecs = priv->nthreads + 1; 5442 break; 5443 case MVPP2_QDIST_MULTI_MODE: 5444 port->nqvecs = priv->nthreads; 5445 break; 5446 } 5447 5448 for (i = 0; i < port->nqvecs; i++) { 5449 char irqname[16]; 5450 5451 v = port->qvecs + i; 5452 5453 v->port = port; 5454 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 5455 v->sw_thread_id = i; 5456 v->sw_thread_mask = BIT(i); 5457 5458 if (port->flags & MVPP2_F_DT_COMPAT) 5459 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 5460 else 5461 snprintf(irqname, sizeof(irqname), "hif%d", i); 5462 5463 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 5464 v->first_rxq = i; 5465 v->nrxqs = 1; 5466 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 5467 i == (port->nqvecs - 1)) { 5468 v->first_rxq = 0; 5469 v->nrxqs = port->nrxqs; 5470 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5471 5472 if (port->flags & MVPP2_F_DT_COMPAT) 5473 strncpy(irqname, "rx-shared", sizeof(irqname)); 5474 } 5475 5476 if (port_node) 5477 v->irq = of_irq_get_byname(port_node, irqname); 5478 else 5479 v->irq = fwnode_irq_get(port->fwnode, i); 5480 if (v->irq <= 0) { 5481 ret = -EINVAL; 5482 goto err; 5483 } 5484 5485 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5486 NAPI_POLL_WEIGHT); 5487 } 5488 5489 return 0; 5490 5491err: 5492 for (i = 0; i < port->nqvecs; i++) 5493 irq_dispose_mapping(port->qvecs[i].irq); 5494 return ret; 5495} 5496 5497static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 5498 struct device_node *port_node) 5499{ 5500 if (port->has_tx_irqs) 5501 return mvpp2_multi_queue_vectors_init(port, port_node); 5502 else 5503 return mvpp2_simple_queue_vectors_init(port, port_node); 5504} 5505 5506static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 5507{ 5508 int i; 5509 5510 for (i = 0; i < port->nqvecs; i++) 5511 irq_dispose_mapping(port->qvecs[i].irq); 5512} 5513 5514/* Configure Rx queue group interrupt for this port */ 5515static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 5516{ 5517 struct mvpp2 *priv = port->priv; 5518 u32 val; 5519 int i; 5520 5521 if (priv->hw_version == MVPP21) { 5522 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 5523 port->nrxqs); 5524 return; 5525 } 5526 5527 /* Handle the more complicated PPv2.2 case */ 5528 for (i = 0; i < port->nqvecs; i++) { 5529 struct mvpp2_queue_vector *qv = port->qvecs + i; 5530 5531 if (!qv->nrxqs) 5532 continue; 5533 5534 val = qv->sw_thread_id; 5535 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 5536 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 5537 5538 val = qv->first_rxq; 5539 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 5540 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 5541 } 5542} 5543 5544/* Initialize port HW */ 5545static int mvpp2_port_init(struct mvpp2_port *port) 5546{ 5547 struct device *dev = port->dev->dev.parent; 5548 struct mvpp2 *priv = port->priv; 5549 struct mvpp2_txq_pcpu *txq_pcpu; 5550 unsigned int thread; 5551 int queue, err, val; 5552 5553 /* Checks for hardware constraints */ 5554 if (port->first_rxq + port->nrxqs > 5555 MVPP2_MAX_PORTS * priv->max_port_rxqs) 5556 return -EINVAL; 5557 5558 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 5559 return -EINVAL; 5560 5561 /* Disable port */ 5562 mvpp2_egress_disable(port); 5563 mvpp2_port_disable(port); 5564 5565 if (mvpp2_is_xlg(port->phy_interface)) { 5566 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5567 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 5568 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 5569 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 5570 } else { 5571 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5572 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 5573 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 5574 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5575 } 5576 5577 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 5578 5579 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 5580 GFP_KERNEL); 5581 if (!port->txqs) 5582 return -ENOMEM; 5583 5584 /* Associate physical Tx queues to this port and initialize. 5585 * The mapping is predefined. 5586 */ 5587 for (queue = 0; queue < port->ntxqs; queue++) { 5588 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 5589 struct mvpp2_tx_queue *txq; 5590 5591 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 5592 if (!txq) { 5593 err = -ENOMEM; 5594 goto err_free_percpu; 5595 } 5596 5597 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 5598 if (!txq->pcpu) { 5599 err = -ENOMEM; 5600 goto err_free_percpu; 5601 } 5602 5603 txq->id = queue_phy_id; 5604 txq->log_id = queue; 5605 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 5606 for (thread = 0; thread < priv->nthreads; thread++) { 5607 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 5608 txq_pcpu->thread = thread; 5609 } 5610 5611 port->txqs[queue] = txq; 5612 } 5613 5614 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 5615 GFP_KERNEL); 5616 if (!port->rxqs) { 5617 err = -ENOMEM; 5618 goto err_free_percpu; 5619 } 5620 5621 /* Allocate and initialize Rx queue for this port */ 5622 for (queue = 0; queue < port->nrxqs; queue++) { 5623 struct mvpp2_rx_queue *rxq; 5624 5625 /* Map physical Rx queue to port's logical Rx queue */ 5626 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 5627 if (!rxq) { 5628 err = -ENOMEM; 5629 goto err_free_percpu; 5630 } 5631 /* Map this Rx queue to a physical queue */ 5632 rxq->id = port->first_rxq + queue; 5633 rxq->port = port->id; 5634 rxq->logic_rxq = queue; 5635 5636 port->rxqs[queue] = rxq; 5637 } 5638 5639 mvpp2_rx_irqs_setup(port); 5640 5641 /* Create Rx descriptor rings */ 5642 for (queue = 0; queue < port->nrxqs; queue++) { 5643 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5644 5645 rxq->size = port->rx_ring_size; 5646 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 5647 rxq->time_coal = MVPP2_RX_COAL_USEC; 5648 } 5649 5650 mvpp2_ingress_disable(port); 5651 5652 /* Port default configuration */ 5653 mvpp2_defaults_set(port); 5654 5655 /* Port's classifier configuration */ 5656 mvpp2_cls_oversize_rxq_set(port); 5657 mvpp2_cls_port_config(port); 5658 5659 if (mvpp22_rss_is_supported()) 5660 mvpp22_port_rss_init(port); 5661 5662 /* Provide an initial Rx packet size */ 5663 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 5664 5665 /* Initialize pools for swf */ 5666 err = mvpp2_swf_bm_pool_init(port); 5667 if (err) 5668 goto err_free_percpu; 5669 5670 /* Clear all port stats */ 5671 mvpp2_read_stats(port); 5672 memset(port->ethtool_stats, 0, 5673 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 5674 5675 return 0; 5676 5677err_free_percpu: 5678 for (queue = 0; queue < port->ntxqs; queue++) { 5679 if (!port->txqs[queue]) 5680 continue; 5681 free_percpu(port->txqs[queue]->pcpu); 5682 } 5683 return err; 5684} 5685 5686static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 5687 unsigned long *flags) 5688{ 5689 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 5690 "tx-cpu3" }; 5691 int i; 5692 5693 for (i = 0; i < 5; i++) 5694 if (of_property_match_string(port_node, "interrupt-names", 5695 irqs[i]) < 0) 5696 return false; 5697 5698 *flags |= MVPP2_F_DT_COMPAT; 5699 return true; 5700} 5701 5702/* Checks if the port dt description has the required Tx interrupts: 5703 * - PPv2.1: there are no such interrupts. 5704 * - PPv2.2: 5705 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 5706 * - The new ones have: "hifX" with X in [0..8] 5707 * 5708 * All those variants are supported to keep the backward compatibility. 5709 */ 5710static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 5711 struct device_node *port_node, 5712 unsigned long *flags) 5713{ 5714 char name[5]; 5715 int i; 5716 5717 /* ACPI */ 5718 if (!port_node) 5719 return true; 5720 5721 if (priv->hw_version == MVPP21) 5722 return false; 5723 5724 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 5725 return true; 5726 5727 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5728 snprintf(name, 5, "hif%d", i); 5729 if (of_property_match_string(port_node, "interrupt-names", 5730 name) < 0) 5731 return false; 5732 } 5733 5734 return true; 5735} 5736 5737static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 5738 struct fwnode_handle *fwnode, 5739 char **mac_from) 5740{ 5741 struct mvpp2_port *port = netdev_priv(dev); 5742 char hw_mac_addr[ETH_ALEN] = {0}; 5743 char fw_mac_addr[ETH_ALEN]; 5744 5745 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 5746 *mac_from = "firmware node"; 5747 ether_addr_copy(dev->dev_addr, fw_mac_addr); 5748 return; 5749 } 5750 5751 if (priv->hw_version == MVPP21) { 5752 mvpp21_get_mac_address(port, hw_mac_addr); 5753 if (is_valid_ether_addr(hw_mac_addr)) { 5754 *mac_from = "hardware"; 5755 ether_addr_copy(dev->dev_addr, hw_mac_addr); 5756 return; 5757 } 5758 } 5759 5760 *mac_from = "random"; 5761 eth_hw_addr_random(dev); 5762} 5763 5764static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config) 5765{ 5766 return container_of(config, struct mvpp2_port, phylink_config); 5767} 5768 5769static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs) 5770{ 5771 return container_of(pcs, struct mvpp2_port, phylink_pcs); 5772} 5773 5774static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 5775 struct phylink_link_state *state) 5776{ 5777 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5778 u32 val; 5779 5780 state->speed = SPEED_10000; 5781 state->duplex = 1; 5782 state->an_complete = 1; 5783 5784 val = readl(port->base + MVPP22_XLG_STATUS); 5785 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 5786 5787 state->pause = 0; 5788 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5789 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 5790 state->pause |= MLO_PAUSE_TX; 5791 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 5792 state->pause |= MLO_PAUSE_RX; 5793} 5794 5795static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, 5796 unsigned int mode, 5797 phy_interface_t interface, 5798 const unsigned long *advertising, 5799 bool permit_pause_to_mac) 5800{ 5801 return 0; 5802} 5803 5804static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = { 5805 .pcs_get_state = mvpp2_xlg_pcs_get_state, 5806 .pcs_config = mvpp2_xlg_pcs_config, 5807}; 5808 5809static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, 5810 struct phylink_link_state *state) 5811{ 5812 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5813 u32 val; 5814 5815 val = readl(port->base + MVPP2_GMAC_STATUS0); 5816 5817 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 5818 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 5819 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 5820 5821 switch (port->phy_interface) { 5822 case PHY_INTERFACE_MODE_1000BASEX: 5823 state->speed = SPEED_1000; 5824 break; 5825 case PHY_INTERFACE_MODE_2500BASEX: 5826 state->speed = SPEED_2500; 5827 break; 5828 default: 5829 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 5830 state->speed = SPEED_1000; 5831 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 5832 state->speed = SPEED_100; 5833 else 5834 state->speed = SPEED_10; 5835 } 5836 5837 state->pause = 0; 5838 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 5839 state->pause |= MLO_PAUSE_RX; 5840 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 5841 state->pause |= MLO_PAUSE_TX; 5842} 5843 5844static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 5845 phy_interface_t interface, 5846 const unsigned long *advertising, 5847 bool permit_pause_to_mac) 5848{ 5849 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5850 u32 mask, val, an, old_an, changed; 5851 5852 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | 5853 MVPP2_GMAC_IN_BAND_AUTONEG | 5854 MVPP2_GMAC_AN_SPEED_EN | 5855 MVPP2_GMAC_FLOW_CTRL_AUTONEG | 5856 MVPP2_GMAC_AN_DUPLEX_EN; 5857 5858 if (phylink_autoneg_inband(mode)) { 5859 mask |= MVPP2_GMAC_CONFIG_MII_SPEED | 5860 MVPP2_GMAC_CONFIG_GMII_SPEED | 5861 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 5862 val = MVPP2_GMAC_IN_BAND_AUTONEG; 5863 5864 if (interface == PHY_INTERFACE_MODE_SGMII) { 5865 /* SGMII mode receives the speed and duplex from PHY */ 5866 val |= MVPP2_GMAC_AN_SPEED_EN | 5867 MVPP2_GMAC_AN_DUPLEX_EN; 5868 } else { 5869 /* 802.3z mode has fixed speed and duplex */ 5870 val |= MVPP2_GMAC_CONFIG_GMII_SPEED | 5871 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 5872 5873 /* The FLOW_CTRL_AUTONEG bit selects either the hardware 5874 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG 5875 * manually controls the GMAC pause modes. 5876 */ 5877 if (permit_pause_to_mac) 5878 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 5879 5880 /* Configure advertisement bits */ 5881 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN; 5882 if (phylink_test(advertising, Pause)) 5883 val |= MVPP2_GMAC_FC_ADV_EN; 5884 if (phylink_test(advertising, Asym_Pause)) 5885 val |= MVPP2_GMAC_FC_ADV_ASM_EN; 5886 } 5887 } else { 5888 val = 0; 5889 } 5890 5891 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5892 an = (an & ~mask) | val; 5893 changed = an ^ old_an; 5894 if (changed) 5895 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5896 5897 /* We are only interested in the advertisement bits changing */ 5898 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN); 5899} 5900 5901static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs) 5902{ 5903 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5904 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5905 5906 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 5907 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5908 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 5909 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5910} 5911 5912static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { 5913 .pcs_get_state = mvpp2_gmac_pcs_get_state, 5914 .pcs_config = mvpp2_gmac_pcs_config, 5915 .pcs_an_restart = mvpp2_gmac_pcs_an_restart, 5916}; 5917 5918static void mvpp2_phylink_validate(struct phylink_config *config, 5919 unsigned long *supported, 5920 struct phylink_link_state *state) 5921{ 5922 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 5923 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 5924 5925 /* Invalid combinations */ 5926 switch (state->interface) { 5927 case PHY_INTERFACE_MODE_10GBASER: 5928 case PHY_INTERFACE_MODE_XAUI: 5929 if (!mvpp2_port_supports_xlg(port)) 5930 goto empty_set; 5931 break; 5932 case PHY_INTERFACE_MODE_RGMII: 5933 case PHY_INTERFACE_MODE_RGMII_ID: 5934 case PHY_INTERFACE_MODE_RGMII_RXID: 5935 case PHY_INTERFACE_MODE_RGMII_TXID: 5936 if (!mvpp2_port_supports_rgmii(port)) 5937 goto empty_set; 5938 break; 5939 default: 5940 break; 5941 } 5942 5943 phylink_set(mask, Autoneg); 5944 phylink_set_port_modes(mask); 5945 5946 switch (state->interface) { 5947 case PHY_INTERFACE_MODE_10GBASER: 5948 case PHY_INTERFACE_MODE_XAUI: 5949 case PHY_INTERFACE_MODE_NA: 5950 if (mvpp2_port_supports_xlg(port)) { 5951 phylink_set(mask, 10000baseT_Full); 5952 phylink_set(mask, 10000baseCR_Full); 5953 phylink_set(mask, 10000baseSR_Full); 5954 phylink_set(mask, 10000baseLR_Full); 5955 phylink_set(mask, 10000baseLRM_Full); 5956 phylink_set(mask, 10000baseER_Full); 5957 phylink_set(mask, 10000baseKR_Full); 5958 } 5959 if (state->interface != PHY_INTERFACE_MODE_NA) 5960 break; 5961 fallthrough; 5962 case PHY_INTERFACE_MODE_RGMII: 5963 case PHY_INTERFACE_MODE_RGMII_ID: 5964 case PHY_INTERFACE_MODE_RGMII_RXID: 5965 case PHY_INTERFACE_MODE_RGMII_TXID: 5966 case PHY_INTERFACE_MODE_SGMII: 5967 phylink_set(mask, 10baseT_Half); 5968 phylink_set(mask, 10baseT_Full); 5969 phylink_set(mask, 100baseT_Half); 5970 phylink_set(mask, 100baseT_Full); 5971 phylink_set(mask, 1000baseT_Full); 5972 phylink_set(mask, 1000baseX_Full); 5973 if (state->interface != PHY_INTERFACE_MODE_NA) 5974 break; 5975 fallthrough; 5976 case PHY_INTERFACE_MODE_1000BASEX: 5977 case PHY_INTERFACE_MODE_2500BASEX: 5978 if (port->comphy || 5979 state->interface != PHY_INTERFACE_MODE_2500BASEX) { 5980 phylink_set(mask, 1000baseT_Full); 5981 phylink_set(mask, 1000baseX_Full); 5982 } 5983 if (port->comphy || 5984 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 5985 phylink_set(mask, 2500baseT_Full); 5986 phylink_set(mask, 2500baseX_Full); 5987 } 5988 break; 5989 default: 5990 goto empty_set; 5991 } 5992 5993 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 5994 bitmap_and(state->advertising, state->advertising, mask, 5995 __ETHTOOL_LINK_MODE_MASK_NBITS); 5996 5997 phylink_helper_basex_speed(state); 5998 return; 5999 6000empty_set: 6001 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 6002} 6003 6004static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 6005 const struct phylink_link_state *state) 6006{ 6007 u32 val; 6008 6009 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6010 MVPP22_XLG_CTRL0_MAC_RESET_DIS, 6011 MVPP22_XLG_CTRL0_MAC_RESET_DIS); 6012 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, 6013 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 6014 MVPP22_XLG_CTRL4_EN_IDLE_CHECK | 6015 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC, 6016 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC); 6017 6018 /* Wait for reset to deassert */ 6019 do { 6020 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6021 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS)); 6022} 6023 6024static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 6025 const struct phylink_link_state *state) 6026{ 6027 u32 old_ctrl0, ctrl0; 6028 u32 old_ctrl2, ctrl2; 6029 u32 old_ctrl4, ctrl4; 6030 6031 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 6032 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 6033 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 6034 6035 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 6036 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); 6037 6038 /* Configure port type */ 6039 if (phy_interface_mode_is_8023z(state->interface)) { 6040 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 6041 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6042 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6043 MVPP22_CTRL4_DP_CLK_SEL | 6044 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6045 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6046 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 6047 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6048 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6049 MVPP22_CTRL4_DP_CLK_SEL | 6050 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6051 } else if (phy_interface_mode_is_rgmii(state->interface)) { 6052 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 6053 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 6054 MVPP22_CTRL4_SYNC_BYPASS_DIS | 6055 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6056 } 6057 6058 /* Configure negotiation style */ 6059 if (!phylink_autoneg_inband(mode)) { 6060 /* Phy or fixed speed - no in-band AN, nothing to do, leave the 6061 * configured speed, duplex and flow control as-is. 6062 */ 6063 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6064 /* SGMII in-band mode receives the speed and duplex from 6065 * the PHY. Flow control information is not received. */ 6066 } else if (phy_interface_mode_is_8023z(state->interface)) { 6067 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 6068 * they negotiate duplex: they are always operating with a fixed 6069 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 6070 * speed and full duplex here. 6071 */ 6072 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 6073 } 6074 6075 if (old_ctrl0 != ctrl0) 6076 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 6077 if (old_ctrl2 != ctrl2) 6078 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 6079 if (old_ctrl4 != ctrl4) 6080 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 6081} 6082 6083static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode, 6084 phy_interface_t interface) 6085{ 6086 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6087 6088 /* Check for invalid configuration */ 6089 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { 6090 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); 6091 return -EINVAL; 6092 } 6093 6094 if (port->phy_interface != interface || 6095 phylink_autoneg_inband(mode)) { 6096 /* Force the link down when changing the interface or if in 6097 * in-band mode to ensure we do not change the configuration 6098 * while the hardware is indicating link is up. We force both 6099 * XLG and GMAC down to ensure that they're both in a known 6100 * state. 6101 */ 6102 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6103 MVPP2_GMAC_FORCE_LINK_PASS | 6104 MVPP2_GMAC_FORCE_LINK_DOWN, 6105 MVPP2_GMAC_FORCE_LINK_DOWN); 6106 6107 if (mvpp2_port_supports_xlg(port)) 6108 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6109 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6110 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 6111 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN); 6112 } 6113 6114 /* Make sure the port is disabled when reconfiguring the mode */ 6115 mvpp2_port_disable(port); 6116 6117 if (port->phy_interface != interface) { 6118 /* Place GMAC into reset */ 6119 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6120 MVPP2_GMAC_PORT_RESET_MASK, 6121 MVPP2_GMAC_PORT_RESET_MASK); 6122 6123 if (port->priv->hw_version == MVPP22) { 6124 mvpp22_gop_mask_irq(port); 6125 6126 phy_power_off(port->comphy); 6127 } 6128 } 6129 6130 /* Select the appropriate PCS operations depending on the 6131 * configured interface mode. We will only switch to a mode 6132 * that the validate() checks have already passed. 6133 */ 6134 if (mvpp2_is_xlg(interface)) 6135 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops; 6136 else 6137 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops; 6138 6139 return 0; 6140} 6141 6142static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, 6143 phy_interface_t interface) 6144{ 6145 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6146 int ret; 6147 6148 ret = mvpp2__mac_prepare(config, mode, interface); 6149 if (ret == 0) 6150 phylink_set_pcs(port->phylink, &port->phylink_pcs); 6151 6152 return ret; 6153} 6154 6155static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 6156 const struct phylink_link_state *state) 6157{ 6158 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6159 6160 /* mac (re)configuration */ 6161 if (mvpp2_is_xlg(state->interface)) 6162 mvpp2_xlg_config(port, mode, state); 6163 else if (phy_interface_mode_is_rgmii(state->interface) || 6164 phy_interface_mode_is_8023z(state->interface) || 6165 state->interface == PHY_INTERFACE_MODE_SGMII) 6166 mvpp2_gmac_config(port, mode, state); 6167 6168 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 6169 mvpp2_port_loopback_set(port, state); 6170} 6171 6172static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode, 6173 phy_interface_t interface) 6174{ 6175 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6176 6177 if (port->priv->hw_version == MVPP22 && 6178 port->phy_interface != interface) { 6179 port->phy_interface = interface; 6180 6181 /* Reconfigure the serdes lanes */ 6182 mvpp22_mode_reconfigure(port); 6183 6184 /* Unmask interrupts */ 6185 mvpp22_gop_unmask_irq(port); 6186 } 6187 6188 if (!mvpp2_is_xlg(interface)) { 6189 /* Release GMAC reset and wait */ 6190 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6191 MVPP2_GMAC_PORT_RESET_MASK, 0); 6192 6193 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 6194 MVPP2_GMAC_PORT_RESET_MASK) 6195 continue; 6196 } 6197 6198 mvpp2_port_enable(port); 6199 6200 /* Allow the link to come up if in in-band mode, otherwise the 6201 * link is forced via mac_link_down()/mac_link_up() 6202 */ 6203 if (phylink_autoneg_inband(mode)) { 6204 if (mvpp2_is_xlg(interface)) 6205 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6206 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6207 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0); 6208 else 6209 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6210 MVPP2_GMAC_FORCE_LINK_PASS | 6211 MVPP2_GMAC_FORCE_LINK_DOWN, 0); 6212 } 6213 6214 return 0; 6215} 6216 6217static void mvpp2_mac_link_up(struct phylink_config *config, 6218 struct phy_device *phy, 6219 unsigned int mode, phy_interface_t interface, 6220 int speed, int duplex, 6221 bool tx_pause, bool rx_pause) 6222{ 6223 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6224 u32 val; 6225 6226 if (mvpp2_is_xlg(interface)) { 6227 if (!phylink_autoneg_inband(mode)) { 6228 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6229 if (tx_pause) 6230 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 6231 if (rx_pause) 6232 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 6233 6234 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6235 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | 6236 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6237 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | 6238 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val); 6239 } 6240 } else { 6241 if (!phylink_autoneg_inband(mode)) { 6242 val = MVPP2_GMAC_FORCE_LINK_PASS; 6243 6244 if (speed == SPEED_1000 || speed == SPEED_2500) 6245 val |= MVPP2_GMAC_CONFIG_GMII_SPEED; 6246 else if (speed == SPEED_100) 6247 val |= MVPP2_GMAC_CONFIG_MII_SPEED; 6248 6249 if (duplex == DUPLEX_FULL) 6250 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6251 6252 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6253 MVPP2_GMAC_FORCE_LINK_DOWN | 6254 MVPP2_GMAC_FORCE_LINK_PASS | 6255 MVPP2_GMAC_CONFIG_MII_SPEED | 6256 MVPP2_GMAC_CONFIG_GMII_SPEED | 6257 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val); 6258 } 6259 6260 /* We can always update the flow control enable bits; 6261 * these will only be effective if flow control AN 6262 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled. 6263 */ 6264 val = 0; 6265 if (tx_pause) 6266 val |= MVPP22_CTRL4_TX_FC_EN; 6267 if (rx_pause) 6268 val |= MVPP22_CTRL4_RX_FC_EN; 6269 6270 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, 6271 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN, 6272 val); 6273 } 6274 6275 mvpp2_port_enable(port); 6276 6277 mvpp2_egress_enable(port); 6278 mvpp2_ingress_enable(port); 6279 netif_tx_wake_all_queues(port->dev); 6280} 6281 6282static void mvpp2_mac_link_down(struct phylink_config *config, 6283 unsigned int mode, phy_interface_t interface) 6284{ 6285 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6286 u32 val; 6287 6288 if (!phylink_autoneg_inband(mode)) { 6289 if (mvpp2_is_xlg(interface)) { 6290 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6291 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6292 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 6293 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 6294 } else { 6295 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6296 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 6297 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 6298 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6299 } 6300 } 6301 6302 netif_tx_stop_all_queues(port->dev); 6303 mvpp2_egress_disable(port); 6304 mvpp2_ingress_disable(port); 6305 6306 mvpp2_port_disable(port); 6307} 6308 6309static const struct phylink_mac_ops mvpp2_phylink_ops = { 6310 .validate = mvpp2_phylink_validate, 6311 .mac_prepare = mvpp2_mac_prepare, 6312 .mac_config = mvpp2_mac_config, 6313 .mac_finish = mvpp2_mac_finish, 6314 .mac_link_up = mvpp2_mac_link_up, 6315 .mac_link_down = mvpp2_mac_link_down, 6316}; 6317 6318/* Work-around for ACPI */ 6319static void mvpp2_acpi_start(struct mvpp2_port *port) 6320{ 6321 /* Phylink isn't used as of now for ACPI, so the MAC has to be 6322 * configured manually when the interface is started. This will 6323 * be removed as soon as the phylink ACPI support lands in. 6324 */ 6325 struct phylink_link_state state = { 6326 .interface = port->phy_interface, 6327 }; 6328 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND, 6329 port->phy_interface); 6330 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 6331 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND, 6332 port->phy_interface, 6333 state.advertising, false); 6334 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, 6335 port->phy_interface); 6336 mvpp2_mac_link_up(&port->phylink_config, NULL, 6337 MLO_AN_INBAND, port->phy_interface, 6338 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false); 6339} 6340 6341/* Ports initialization */ 6342static int mvpp2_port_probe(struct platform_device *pdev, 6343 struct fwnode_handle *port_fwnode, 6344 struct mvpp2 *priv) 6345{ 6346 struct phy *comphy = NULL; 6347 struct mvpp2_port *port; 6348 struct mvpp2_port_pcpu *port_pcpu; 6349 struct device_node *port_node = to_of_node(port_fwnode); 6350 netdev_features_t features; 6351 struct net_device *dev; 6352 struct phylink *phylink; 6353 char *mac_from = ""; 6354 unsigned int ntxqs, nrxqs, thread; 6355 unsigned long flags = 0; 6356 bool has_tx_irqs; 6357 u32 id; 6358 int phy_mode; 6359 int err, i; 6360 6361 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 6362 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 6363 dev_err(&pdev->dev, 6364 "not enough IRQs to support multi queue mode\n"); 6365 return -EINVAL; 6366 } 6367 6368 ntxqs = MVPP2_MAX_TXQ; 6369 nrxqs = mvpp2_get_nrxqs(priv); 6370 6371 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 6372 if (!dev) 6373 return -ENOMEM; 6374 6375 phy_mode = fwnode_get_phy_mode(port_fwnode); 6376 if (phy_mode < 0) { 6377 dev_err(&pdev->dev, "incorrect phy mode\n"); 6378 err = phy_mode; 6379 goto err_free_netdev; 6380 } 6381 6382 /* 6383 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. 6384 * Existing usage of 10GBASE-KR is not correct; no backplane 6385 * negotiation is done, and this driver does not actually support 6386 * 10GBASE-KR. 6387 */ 6388 if (phy_mode == PHY_INTERFACE_MODE_10GKR) 6389 phy_mode = PHY_INTERFACE_MODE_10GBASER; 6390 6391 if (port_node) { 6392 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 6393 if (IS_ERR(comphy)) { 6394 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 6395 err = -EPROBE_DEFER; 6396 goto err_free_netdev; 6397 } 6398 comphy = NULL; 6399 } 6400 } 6401 6402 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 6403 err = -EINVAL; 6404 dev_err(&pdev->dev, "missing port-id value\n"); 6405 goto err_free_netdev; 6406 } 6407 6408 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 6409 dev->watchdog_timeo = 5 * HZ; 6410 dev->netdev_ops = &mvpp2_netdev_ops; 6411 dev->ethtool_ops = &mvpp2_eth_tool_ops; 6412 6413 port = netdev_priv(dev); 6414 port->dev = dev; 6415 port->fwnode = port_fwnode; 6416 port->has_phy = !!of_find_property(port_node, "phy", NULL); 6417 port->ntxqs = ntxqs; 6418 port->nrxqs = nrxqs; 6419 port->priv = priv; 6420 port->has_tx_irqs = has_tx_irqs; 6421 port->flags = flags; 6422 6423 err = mvpp2_queue_vectors_init(port, port_node); 6424 if (err) 6425 goto err_free_netdev; 6426 6427 if (port_node) 6428 port->port_irq = of_irq_get_byname(port_node, "link"); 6429 else 6430 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 6431 if (port->port_irq == -EPROBE_DEFER) { 6432 err = -EPROBE_DEFER; 6433 goto err_deinit_qvecs; 6434 } 6435 if (port->port_irq <= 0) 6436 /* the link irq is optional */ 6437 port->port_irq = 0; 6438 6439 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 6440 port->flags |= MVPP2_F_LOOPBACK; 6441 6442 port->id = id; 6443 if (priv->hw_version == MVPP21) 6444 port->first_rxq = port->id * port->nrxqs; 6445 else 6446 port->first_rxq = port->id * priv->max_port_rxqs; 6447 6448 port->of_node = port_node; 6449 port->phy_interface = phy_mode; 6450 port->comphy = comphy; 6451 6452 if (priv->hw_version == MVPP21) { 6453 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 6454 if (IS_ERR(port->base)) { 6455 err = PTR_ERR(port->base); 6456 goto err_free_irq; 6457 } 6458 6459 port->stats_base = port->priv->lms_base + 6460 MVPP21_MIB_COUNTERS_OFFSET + 6461 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 6462 } else { 6463 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 6464 &port->gop_id)) { 6465 err = -EINVAL; 6466 dev_err(&pdev->dev, "missing gop-port-id value\n"); 6467 goto err_deinit_qvecs; 6468 } 6469 6470 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 6471 port->stats_base = port->priv->iface_base + 6472 MVPP22_MIB_COUNTERS_OFFSET + 6473 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 6474 6475 /* We may want a property to describe whether we should use 6476 * MAC hardware timestamping. 6477 */ 6478 if (priv->tai) 6479 port->hwtstamp = true; 6480 } 6481 6482 /* Alloc per-cpu and ethtool stats */ 6483 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 6484 if (!port->stats) { 6485 err = -ENOMEM; 6486 goto err_free_irq; 6487 } 6488 6489 port->ethtool_stats = devm_kcalloc(&pdev->dev, 6490 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 6491 sizeof(u64), GFP_KERNEL); 6492 if (!port->ethtool_stats) { 6493 err = -ENOMEM; 6494 goto err_free_stats; 6495 } 6496 6497 mutex_init(&port->gather_stats_lock); 6498 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 6499 6500 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 6501 6502 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 6503 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 6504 SET_NETDEV_DEV(dev, &pdev->dev); 6505 6506 err = mvpp2_port_init(port); 6507 if (err < 0) { 6508 dev_err(&pdev->dev, "failed to init port %d\n", id); 6509 goto err_free_stats; 6510 } 6511 6512 mvpp2_port_periodic_xon_disable(port); 6513 6514 mvpp2_mac_reset_assert(port); 6515 mvpp22_pcs_reset_assert(port); 6516 6517 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 6518 if (!port->pcpu) { 6519 err = -ENOMEM; 6520 goto err_free_txq_pcpu; 6521 } 6522 6523 if (!port->has_tx_irqs) { 6524 for (thread = 0; thread < priv->nthreads; thread++) { 6525 port_pcpu = per_cpu_ptr(port->pcpu, thread); 6526 6527 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 6528 HRTIMER_MODE_REL_PINNED_SOFT); 6529 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 6530 port_pcpu->timer_scheduled = false; 6531 port_pcpu->dev = dev; 6532 } 6533 } 6534 6535 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6536 NETIF_F_TSO; 6537 dev->features = features | NETIF_F_RXCSUM; 6538 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 6539 NETIF_F_HW_VLAN_CTAG_FILTER; 6540 6541 if (mvpp22_rss_is_supported()) { 6542 dev->hw_features |= NETIF_F_RXHASH; 6543 dev->features |= NETIF_F_NTUPLE; 6544 } 6545 6546 if (!port->priv->percpu_pools) 6547 mvpp2_set_hw_csum(port, port->pool_long->id); 6548 6549 dev->vlan_features |= features; 6550 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 6551 dev->priv_flags |= IFF_UNICAST_FLT; 6552 6553 /* MTU range: 68 - 9704 */ 6554 dev->min_mtu = ETH_MIN_MTU; 6555 /* 9704 == 9728 - 20 and rounding to 8 */ 6556 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 6557 dev->dev.of_node = port_node; 6558 6559 /* Phylink isn't used w/ ACPI as of now */ 6560 if (port_node) { 6561 port->phylink_config.dev = &dev->dev; 6562 port->phylink_config.type = PHYLINK_NETDEV; 6563 6564 phylink = phylink_create(&port->phylink_config, port_fwnode, 6565 phy_mode, &mvpp2_phylink_ops); 6566 if (IS_ERR(phylink)) { 6567 err = PTR_ERR(phylink); 6568 goto err_free_port_pcpu; 6569 } 6570 port->phylink = phylink; 6571 } else { 6572 port->phylink = NULL; 6573 } 6574 6575 /* Cycle the comphy to power it down, saving 270mW per port - 6576 * don't worry about an error powering it up. When the comphy 6577 * driver does this, we can remove this code. 6578 */ 6579 if (port->comphy) { 6580 err = mvpp22_comphy_init(port); 6581 if (err == 0) 6582 phy_power_off(port->comphy); 6583 } 6584 6585 err = register_netdev(dev); 6586 if (err < 0) { 6587 dev_err(&pdev->dev, "failed to register netdev\n"); 6588 goto err_phylink; 6589 } 6590 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 6591 6592 priv->port_list[priv->port_count++] = port; 6593 6594 return 0; 6595 6596err_phylink: 6597 if (port->phylink) 6598 phylink_destroy(port->phylink); 6599err_free_port_pcpu: 6600 free_percpu(port->pcpu); 6601err_free_txq_pcpu: 6602 for (i = 0; i < port->ntxqs; i++) 6603 free_percpu(port->txqs[i]->pcpu); 6604err_free_stats: 6605 free_percpu(port->stats); 6606err_free_irq: 6607 if (port->port_irq) 6608 irq_dispose_mapping(port->port_irq); 6609err_deinit_qvecs: 6610 mvpp2_queue_vectors_deinit(port); 6611err_free_netdev: 6612 free_netdev(dev); 6613 return err; 6614} 6615 6616/* Ports removal routine */ 6617static void mvpp2_port_remove(struct mvpp2_port *port) 6618{ 6619 int i; 6620 6621 unregister_netdev(port->dev); 6622 if (port->phylink) 6623 phylink_destroy(port->phylink); 6624 free_percpu(port->pcpu); 6625 free_percpu(port->stats); 6626 for (i = 0; i < port->ntxqs; i++) 6627 free_percpu(port->txqs[i]->pcpu); 6628 mvpp2_queue_vectors_deinit(port); 6629 if (port->port_irq) 6630 irq_dispose_mapping(port->port_irq); 6631 free_netdev(port->dev); 6632} 6633 6634/* Initialize decoding windows */ 6635static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 6636 struct mvpp2 *priv) 6637{ 6638 u32 win_enable; 6639 int i; 6640 6641 for (i = 0; i < 6; i++) { 6642 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 6643 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 6644 6645 if (i < 4) 6646 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 6647 } 6648 6649 win_enable = 0; 6650 6651 for (i = 0; i < dram->num_cs; i++) { 6652 const struct mbus_dram_window *cs = dram->cs + i; 6653 6654 mvpp2_write(priv, MVPP2_WIN_BASE(i), 6655 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 6656 dram->mbus_dram_target_id); 6657 6658 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 6659 (cs->size - 1) & 0xffff0000); 6660 6661 win_enable |= (1 << i); 6662 } 6663 6664 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 6665} 6666 6667/* Initialize Rx FIFO's */ 6668static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 6669{ 6670 int port; 6671 6672 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 6673 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 6674 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 6675 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 6676 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 6677 } 6678 6679 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 6680 MVPP2_RX_FIFO_PORT_MIN_PKT); 6681 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 6682} 6683 6684static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 6685{ 6686 int port; 6687 6688 /* The FIFO size parameters are set depending on the maximum speed a 6689 * given port can handle: 6690 * - Port 0: 10Gbps 6691 * - Port 1: 2.5Gbps 6692 * - Ports 2 and 3: 1Gbps 6693 */ 6694 6695 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 6696 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 6697 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 6698 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 6699 6700 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 6701 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 6702 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 6703 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 6704 6705 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 6706 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 6707 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 6708 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 6709 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 6710 } 6711 6712 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 6713 MVPP2_RX_FIFO_PORT_MIN_PKT); 6714 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 6715} 6716 6717/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 6718 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 6719 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 6720 */ 6721static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 6722{ 6723 int port, size, thrs; 6724 6725 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 6726 if (port == 0) { 6727 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 6728 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 6729 } else { 6730 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 6731 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 6732 } 6733 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 6734 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 6735 } 6736} 6737 6738static void mvpp2_axi_init(struct mvpp2 *priv) 6739{ 6740 u32 val, rdval, wrval; 6741 6742 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 6743 6744 /* AXI Bridge Configuration */ 6745 6746 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 6747 << MVPP22_AXI_ATTR_CACHE_OFFS; 6748 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6749 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 6750 6751 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 6752 << MVPP22_AXI_ATTR_CACHE_OFFS; 6753 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6754 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 6755 6756 /* BM */ 6757 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 6758 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 6759 6760 /* Descriptors */ 6761 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 6762 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 6763 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 6764 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 6765 6766 /* Buffer Data */ 6767 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 6768 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 6769 6770 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 6771 << MVPP22_AXI_CODE_CACHE_OFFS; 6772 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 6773 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6774 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 6775 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 6776 6777 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 6778 << MVPP22_AXI_CODE_CACHE_OFFS; 6779 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6780 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6781 6782 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 6783 6784 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 6785 << MVPP22_AXI_CODE_CACHE_OFFS; 6786 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6787 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6788 6789 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 6790} 6791 6792/* Initialize network controller common part HW */ 6793static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 6794{ 6795 const struct mbus_dram_target_info *dram_target_info; 6796 int err, i; 6797 u32 val; 6798 6799 /* MBUS windows configuration */ 6800 dram_target_info = mv_mbus_dram_info(); 6801 if (dram_target_info) 6802 mvpp2_conf_mbus_windows(dram_target_info, priv); 6803 6804 if (priv->hw_version == MVPP22) 6805 mvpp2_axi_init(priv); 6806 6807 /* Disable HW PHY polling */ 6808 if (priv->hw_version == MVPP21) { 6809 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 6810 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 6811 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 6812 } else { 6813 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 6814 val &= ~MVPP22_SMI_POLLING_EN; 6815 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 6816 } 6817 6818 /* Allocate and initialize aggregated TXQs */ 6819 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 6820 sizeof(*priv->aggr_txqs), 6821 GFP_KERNEL); 6822 if (!priv->aggr_txqs) 6823 return -ENOMEM; 6824 6825 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6826 priv->aggr_txqs[i].id = i; 6827 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 6828 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 6829 if (err < 0) 6830 return err; 6831 } 6832 6833 /* Fifo Init */ 6834 if (priv->hw_version == MVPP21) { 6835 mvpp2_rx_fifo_init(priv); 6836 } else { 6837 mvpp22_rx_fifo_init(priv); 6838 mvpp22_tx_fifo_init(priv); 6839 } 6840 6841 if (priv->hw_version == MVPP21) 6842 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 6843 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 6844 6845 /* Allow cache snoop when transmiting packets */ 6846 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 6847 6848 /* Buffer Manager initialization */ 6849 err = mvpp2_bm_init(&pdev->dev, priv); 6850 if (err < 0) 6851 return err; 6852 6853 /* Parser default initialization */ 6854 err = mvpp2_prs_default_init(pdev, priv); 6855 if (err < 0) 6856 return err; 6857 6858 /* Classifier default initialization */ 6859 mvpp2_cls_init(priv); 6860 6861 return 0; 6862} 6863 6864static int mvpp2_probe(struct platform_device *pdev) 6865{ 6866 const struct acpi_device_id *acpi_id; 6867 struct fwnode_handle *fwnode = pdev->dev.fwnode; 6868 struct fwnode_handle *port_fwnode; 6869 struct mvpp2 *priv; 6870 struct resource *res; 6871 void __iomem *base; 6872 int i, shared; 6873 int err; 6874 6875 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 6876 if (!priv) 6877 return -ENOMEM; 6878 6879 if (has_acpi_companion(&pdev->dev)) { 6880 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 6881 &pdev->dev); 6882 if (!acpi_id) 6883 return -EINVAL; 6884 priv->hw_version = (unsigned long)acpi_id->driver_data; 6885 } else { 6886 priv->hw_version = 6887 (unsigned long)of_device_get_match_data(&pdev->dev); 6888 } 6889 6890 /* multi queue mode isn't supported on PPV2.1, fallback to single 6891 * mode 6892 */ 6893 if (priv->hw_version == MVPP21) 6894 queue_mode = MVPP2_QDIST_SINGLE_MODE; 6895 6896 base = devm_platform_ioremap_resource(pdev, 0); 6897 if (IS_ERR(base)) 6898 return PTR_ERR(base); 6899 6900 if (priv->hw_version == MVPP21) { 6901 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 6902 if (IS_ERR(priv->lms_base)) 6903 return PTR_ERR(priv->lms_base); 6904 } else { 6905 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 6906 if (!res) { 6907 dev_err(&pdev->dev, "Invalid resource\n"); 6908 return -EINVAL; 6909 } 6910 if (has_acpi_companion(&pdev->dev)) { 6911 /* In case the MDIO memory region is declared in 6912 * the ACPI, it can already appear as 'in-use' 6913 * in the OS. Because it is overlapped by second 6914 * region of the network controller, make 6915 * sure it is released, before requesting it again. 6916 * The care is taken by mvpp2 driver to avoid 6917 * concurrent access to this memory region. 6918 */ 6919 release_resource(res); 6920 } 6921 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 6922 if (IS_ERR(priv->iface_base)) 6923 return PTR_ERR(priv->iface_base); 6924 } 6925 6926 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 6927 priv->sysctrl_base = 6928 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 6929 "marvell,system-controller"); 6930 if (IS_ERR(priv->sysctrl_base)) 6931 /* The system controller regmap is optional for dt 6932 * compatibility reasons. When not provided, the 6933 * configuration of the GoP relies on the 6934 * firmware/bootloader. 6935 */ 6936 priv->sysctrl_base = NULL; 6937 } 6938 6939 if (priv->hw_version == MVPP22 && 6940 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS) 6941 priv->percpu_pools = 1; 6942 6943 mvpp2_setup_bm_pool(); 6944 6945 6946 priv->nthreads = min_t(unsigned int, num_present_cpus(), 6947 MVPP2_MAX_THREADS); 6948 6949 shared = num_present_cpus() - priv->nthreads; 6950 if (shared > 0) 6951 bitmap_set(&priv->lock_map, 0, 6952 min_t(int, shared, MVPP2_MAX_THREADS)); 6953 6954 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6955 u32 addr_space_sz; 6956 6957 addr_space_sz = (priv->hw_version == MVPP21 ? 6958 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 6959 priv->swth_base[i] = base + i * addr_space_sz; 6960 } 6961 6962 if (priv->hw_version == MVPP21) 6963 priv->max_port_rxqs = 8; 6964 else 6965 priv->max_port_rxqs = 32; 6966 6967 if (dev_of_node(&pdev->dev)) { 6968 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 6969 if (IS_ERR(priv->pp_clk)) 6970 return PTR_ERR(priv->pp_clk); 6971 err = clk_prepare_enable(priv->pp_clk); 6972 if (err < 0) 6973 return err; 6974 6975 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 6976 if (IS_ERR(priv->gop_clk)) { 6977 err = PTR_ERR(priv->gop_clk); 6978 goto err_pp_clk; 6979 } 6980 err = clk_prepare_enable(priv->gop_clk); 6981 if (err < 0) 6982 goto err_pp_clk; 6983 6984 if (priv->hw_version == MVPP22) { 6985 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 6986 if (IS_ERR(priv->mg_clk)) { 6987 err = PTR_ERR(priv->mg_clk); 6988 goto err_gop_clk; 6989 } 6990 6991 err = clk_prepare_enable(priv->mg_clk); 6992 if (err < 0) 6993 goto err_gop_clk; 6994 6995 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 6996 if (IS_ERR(priv->mg_core_clk)) { 6997 priv->mg_core_clk = NULL; 6998 } else { 6999 err = clk_prepare_enable(priv->mg_core_clk); 7000 if (err < 0) 7001 goto err_mg_clk; 7002 } 7003 } 7004 7005 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 7006 if (IS_ERR(priv->axi_clk)) { 7007 err = PTR_ERR(priv->axi_clk); 7008 if (err == -EPROBE_DEFER) 7009 goto err_mg_core_clk; 7010 priv->axi_clk = NULL; 7011 } else { 7012 err = clk_prepare_enable(priv->axi_clk); 7013 if (err < 0) 7014 goto err_mg_core_clk; 7015 } 7016 7017 /* Get system's tclk rate */ 7018 priv->tclk = clk_get_rate(priv->pp_clk); 7019 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 7020 &priv->tclk)) { 7021 dev_err(&pdev->dev, "missing clock-frequency value\n"); 7022 return -EINVAL; 7023 } 7024 7025 if (priv->hw_version == MVPP22) { 7026 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 7027 if (err) 7028 goto err_axi_clk; 7029 /* Sadly, the BM pools all share the same register to 7030 * store the high 32 bits of their address. So they 7031 * must all have the same high 32 bits, which forces 7032 * us to restrict coherent memory to DMA_BIT_MASK(32). 7033 */ 7034 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 7035 if (err) 7036 goto err_axi_clk; 7037 } 7038 7039 /* Initialize network controller */ 7040 err = mvpp2_init(pdev, priv); 7041 if (err < 0) { 7042 dev_err(&pdev->dev, "failed to initialize controller\n"); 7043 goto err_axi_clk; 7044 } 7045 7046 err = mvpp22_tai_probe(&pdev->dev, priv); 7047 if (err < 0) 7048 goto err_axi_clk; 7049 7050 /* Initialize ports */ 7051 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7052 err = mvpp2_port_probe(pdev, port_fwnode, priv); 7053 if (err < 0) 7054 goto err_port_probe; 7055 } 7056 7057 if (priv->port_count == 0) { 7058 dev_err(&pdev->dev, "no ports enabled\n"); 7059 err = -ENODEV; 7060 goto err_axi_clk; 7061 } 7062 7063 /* Statistics must be gathered regularly because some of them (like 7064 * packets counters) are 32-bit registers and could overflow quite 7065 * quickly. For instance, a 10Gb link used at full bandwidth with the 7066 * smallest packets (64B) will overflow a 32-bit counter in less than 7067 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 7068 */ 7069 snprintf(priv->queue_name, sizeof(priv->queue_name), 7070 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 7071 priv->port_count > 1 ? "+" : ""); 7072 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 7073 if (!priv->stats_queue) { 7074 err = -ENOMEM; 7075 goto err_port_probe; 7076 } 7077 7078 mvpp2_dbgfs_init(priv, pdev->name); 7079 7080 platform_set_drvdata(pdev, priv); 7081 return 0; 7082 7083err_port_probe: 7084 fwnode_handle_put(port_fwnode); 7085 7086 i = 0; 7087 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7088 if (priv->port_list[i]) 7089 mvpp2_port_remove(priv->port_list[i]); 7090 i++; 7091 } 7092err_axi_clk: 7093 clk_disable_unprepare(priv->axi_clk); 7094 7095err_mg_core_clk: 7096 if (priv->hw_version == MVPP22) 7097 clk_disable_unprepare(priv->mg_core_clk); 7098err_mg_clk: 7099 if (priv->hw_version == MVPP22) 7100 clk_disable_unprepare(priv->mg_clk); 7101err_gop_clk: 7102 clk_disable_unprepare(priv->gop_clk); 7103err_pp_clk: 7104 clk_disable_unprepare(priv->pp_clk); 7105 return err; 7106} 7107 7108static int mvpp2_remove(struct platform_device *pdev) 7109{ 7110 struct mvpp2 *priv = platform_get_drvdata(pdev); 7111 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7112 int i = 0, poolnum = MVPP2_BM_POOLS_NUM; 7113 struct fwnode_handle *port_fwnode; 7114 7115 mvpp2_dbgfs_cleanup(priv); 7116 7117 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7118 if (priv->port_list[i]) { 7119 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 7120 mvpp2_port_remove(priv->port_list[i]); 7121 } 7122 i++; 7123 } 7124 7125 destroy_workqueue(priv->stats_queue); 7126 7127 if (priv->percpu_pools) 7128 poolnum = mvpp2_get_nrxqs(priv) * 2; 7129 7130 for (i = 0; i < poolnum; i++) { 7131 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 7132 7133 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); 7134 } 7135 7136 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7137 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 7138 7139 dma_free_coherent(&pdev->dev, 7140 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 7141 aggr_txq->descs, 7142 aggr_txq->descs_dma); 7143 } 7144 7145 if (is_acpi_node(port_fwnode)) 7146 return 0; 7147 7148 clk_disable_unprepare(priv->axi_clk); 7149 clk_disable_unprepare(priv->mg_core_clk); 7150 clk_disable_unprepare(priv->mg_clk); 7151 clk_disable_unprepare(priv->pp_clk); 7152 clk_disable_unprepare(priv->gop_clk); 7153 7154 return 0; 7155} 7156 7157static const struct of_device_id mvpp2_match[] = { 7158 { 7159 .compatible = "marvell,armada-375-pp2", 7160 .data = (void *)MVPP21, 7161 }, 7162 { 7163 .compatible = "marvell,armada-7k-pp22", 7164 .data = (void *)MVPP22, 7165 }, 7166 { } 7167}; 7168MODULE_DEVICE_TABLE(of, mvpp2_match); 7169 7170#ifdef CONFIG_ACPI 7171static const struct acpi_device_id mvpp2_acpi_match[] = { 7172 { "MRVL0110", MVPP22 }, 7173 { }, 7174}; 7175MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 7176#endif 7177 7178static struct platform_driver mvpp2_driver = { 7179 .probe = mvpp2_probe, 7180 .remove = mvpp2_remove, 7181 .driver = { 7182 .name = MVPP2_DRIVER_NAME, 7183 .of_match_table = mvpp2_match, 7184 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 7185 }, 7186}; 7187 7188static int __init mvpp2_driver_init(void) 7189{ 7190 return platform_driver_register(&mvpp2_driver); 7191} 7192module_init(mvpp2_driver_init); 7193 7194static void __exit mvpp2_driver_exit(void) 7195{ 7196 platform_driver_unregister(&mvpp2_driver); 7197 mvpp2_dbgfs_exit(); 7198} 7199module_exit(mvpp2_driver_exit); 7200 7201MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 7202MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 7203MODULE_LICENSE("GPL v2"); 7204