1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#include <linux/types.h> 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/netdevice.h> 8#include <linux/vmalloc.h> 9#include <linux/string.h> 10#include <linux/in.h> 11#include <linux/interrupt.h> 12#include <linux/ip.h> 13#include <linux/tcp.h> 14#include <linux/sctp.h> 15#include <linux/pkt_sched.h> 16#include <linux/ipv6.h> 17#include <linux/slab.h> 18#include <net/checksum.h> 19#include <net/ip6_checksum.h> 20#include <linux/etherdevice.h> 21#include <linux/ethtool.h> 22#include <linux/if.h> 23#include <linux/if_vlan.h> 24#include <linux/if_macvlan.h> 25#include <linux/if_bridge.h> 26#include <linux/prefetch.h> 27#include <linux/bpf.h> 28#include <linux/bpf_trace.h> 29#include <linux/atomic.h> 30#include <linux/numa.h> 31#include <generated/utsrelease.h> 32#include <scsi/fc/fc_fcoe.h> 33#include <net/udp_tunnel.h> 34#include <net/pkt_cls.h> 35#include <net/tc_act/tc_gact.h> 36#include <net/tc_act/tc_mirred.h> 37#include <net/vxlan.h> 38#include <net/mpls.h> 39#include <net/xdp_sock_drv.h> 40#include <net/xfrm.h> 41 42#include "ixgbe.h" 43#include "ixgbe_common.h" 44#include "ixgbe_dcb_82599.h" 45#include "ixgbe_phy.h" 46#include "ixgbe_sriov.h" 47#include "ixgbe_model.h" 48#include "ixgbe_txrx_common.h" 49 50char ixgbe_driver_name[] = "ixgbe"; 51static const char ixgbe_driver_string[] = 52 "Intel(R) 10 Gigabit PCI Express Network Driver"; 53#ifdef IXGBE_FCOE 54char ixgbe_default_device_descr[] = 55 "Intel(R) 10 Gigabit Network Connection"; 56#else 57static char ixgbe_default_device_descr[] = 58 "Intel(R) 10 Gigabit Network Connection"; 59#endif 60static const char ixgbe_copyright[] = 61 "Copyright (c) 1999-2016 Intel Corporation."; 62 63static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 64 65static const struct ixgbe_info *ixgbe_info_tbl[] = { 66 [board_82598] = &ixgbe_82598_info, 67 [board_82599] = &ixgbe_82599_info, 68 [board_X540] = &ixgbe_X540_info, 69 [board_X550] = &ixgbe_X550_info, 70 [board_X550EM_x] = &ixgbe_X550EM_x_info, 71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 72 [board_x550em_a] = &ixgbe_x550em_a_info, 73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 74}; 75 76/* ixgbe_pci_tbl - PCI Device ID Table 77 * 78 * Wildcard entries (PCI_ANY_ID) should come last 79 * Last entry must be all 0s 80 * 81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 82 * Class, Class Mask, private data (not used) } 83 */ 84static const struct pci_device_id ixgbe_pci_tbl[] = { 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 132 /* required last entry */ 133 {0, } 134}; 135MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 136 137#ifdef CONFIG_IXGBE_DCA 138static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 139 void *p); 140static struct notifier_block dca_notifier = { 141 .notifier_call = ixgbe_notify_dca, 142 .next = NULL, 143 .priority = 0 144}; 145#endif 146 147#ifdef CONFIG_PCI_IOV 148static unsigned int max_vfs; 149module_param(max_vfs, uint, 0); 150MODULE_PARM_DESC(max_vfs, 151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 152#endif /* CONFIG_PCI_IOV */ 153 154static unsigned int allow_unsupported_sfp; 155module_param(allow_unsupported_sfp, uint, 0); 156MODULE_PARM_DESC(allow_unsupported_sfp, 157 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 158 159#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 160static int debug = -1; 161module_param(debug, int, 0); 162MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 163 164MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 165MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 166MODULE_LICENSE("GPL v2"); 167 168static struct workqueue_struct *ixgbe_wq; 169 170static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 172 173static const struct net_device_ops ixgbe_netdev_ops; 174 175static bool netif_is_ixgbe(struct net_device *dev) 176{ 177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 178} 179 180static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 181 u32 reg, u16 *value) 182{ 183 struct pci_dev *parent_dev; 184 struct pci_bus *parent_bus; 185 186 parent_bus = adapter->pdev->bus->parent; 187 if (!parent_bus) 188 return -1; 189 190 parent_dev = parent_bus->self; 191 if (!parent_dev) 192 return -1; 193 194 if (!pci_is_pcie(parent_dev)) 195 return -1; 196 197 pcie_capability_read_word(parent_dev, reg, value); 198 if (*value == IXGBE_FAILED_READ_CFG_WORD && 199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 200 return -1; 201 return 0; 202} 203 204static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 205{ 206 struct ixgbe_hw *hw = &adapter->hw; 207 u16 link_status = 0; 208 int err; 209 210 hw->bus.type = ixgbe_bus_type_pci_express; 211 212 /* Get the negotiated link width and speed from PCI config space of the 213 * parent, as this device is behind a switch 214 */ 215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 216 217 /* assume caller will handle error case */ 218 if (err) 219 return err; 220 221 hw->bus.width = ixgbe_convert_bus_width(link_status); 222 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 223 224 return 0; 225} 226 227/** 228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 229 * @hw: hw specific details 230 * 231 * This function is used by probe to determine whether a device's PCI-Express 232 * bandwidth details should be gathered from the parent bus instead of from the 233 * device. Used to ensure that various locations all have the correct device ID 234 * checks. 235 */ 236static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 237{ 238 switch (hw->device_id) { 239 case IXGBE_DEV_ID_82599_SFP_SF_QP: 240 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 241 return true; 242 default: 243 return false; 244 } 245} 246 247static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 248 int expected_gts) 249{ 250 struct ixgbe_hw *hw = &adapter->hw; 251 struct pci_dev *pdev; 252 253 /* Some devices are not connected over PCIe and thus do not negotiate 254 * speed. These devices do not have valid bus info, and thus any report 255 * we generate may not be correct. 256 */ 257 if (hw->bus.type == ixgbe_bus_type_internal) 258 return; 259 260 /* determine whether to use the parent device */ 261 if (ixgbe_pcie_from_parent(&adapter->hw)) 262 pdev = adapter->pdev->bus->parent->self; 263 else 264 pdev = adapter->pdev; 265 266 pcie_print_link_status(pdev); 267} 268 269static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 270{ 271 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 272 !test_bit(__IXGBE_REMOVING, &adapter->state) && 273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 274 queue_work(ixgbe_wq, &adapter->service_task); 275} 276 277static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 278{ 279 struct ixgbe_adapter *adapter = hw->back; 280 281 if (!hw->hw_addr) 282 return; 283 hw->hw_addr = NULL; 284 e_dev_err("Adapter removed\n"); 285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 286 ixgbe_service_event_schedule(adapter); 287} 288 289static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 290{ 291 u8 __iomem *reg_addr; 292 u32 value; 293 int i; 294 295 reg_addr = READ_ONCE(hw->hw_addr); 296 if (ixgbe_removed(reg_addr)) 297 return IXGBE_FAILED_READ_REG; 298 299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 300 * so perform several status register reads to determine if the adapter 301 * has been removed. 302 */ 303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 304 value = readl(reg_addr + IXGBE_STATUS); 305 if (value != IXGBE_FAILED_READ_REG) 306 break; 307 mdelay(3); 308 } 309 310 if (value == IXGBE_FAILED_READ_REG) 311 ixgbe_remove_adapter(hw); 312 else 313 value = readl(reg_addr + reg); 314 return value; 315} 316 317/** 318 * ixgbe_read_reg - Read from device register 319 * @hw: hw specific details 320 * @reg: offset of register to read 321 * 322 * Returns : value read or IXGBE_FAILED_READ_REG if removed 323 * 324 * This function is used to read device registers. It checks for device 325 * removal by confirming any read that returns all ones by checking the 326 * status register value for all ones. This function avoids reading from 327 * the hardware if a removal was previously detected in which case it 328 * returns IXGBE_FAILED_READ_REG (all ones). 329 */ 330u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 331{ 332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 333 u32 value; 334 335 if (ixgbe_removed(reg_addr)) 336 return IXGBE_FAILED_READ_REG; 337 if (unlikely(hw->phy.nw_mng_if_sel & 338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 339 struct ixgbe_adapter *adapter; 340 int i; 341 342 for (i = 0; i < 200; ++i) { 343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 344 if (likely(!value)) 345 goto writes_completed; 346 if (value == IXGBE_FAILED_READ_REG) { 347 ixgbe_remove_adapter(hw); 348 return IXGBE_FAILED_READ_REG; 349 } 350 udelay(5); 351 } 352 353 adapter = hw->back; 354 e_warn(hw, "register writes incomplete %08x\n", value); 355 } 356 357writes_completed: 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 value = ixgbe_check_remove(hw, reg); 361 return value; 362} 363 364static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365{ 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374} 375 376u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377{ 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388} 389 390#ifdef CONFIG_PCI_IOV 391static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392{ 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403} 404#endif /* CONFIG_PCI_IOV */ 405 406void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407{ 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413} 414 415static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416{ 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422} 423 424struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427}; 428 429static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459}; 460 461 462/* 463 * ixgbe_regdump - register printout routine 464 */ 465static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466{ 467 int i; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", 530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 i = 0; 535 while (i < 64) { 536 int j; 537 char buf[9 * 8 + 1]; 538 char *p = buf; 539 540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 541 for (j = 0; j < 8; j++) 542 p += sprintf(p, " %08x", regs[i++]); 543 pr_err("%-15s%s\n", rname, buf); 544 } 545 546} 547 548static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 549{ 550 struct ixgbe_tx_buffer *tx_buffer; 551 552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 554 n, ring->next_to_use, ring->next_to_clean, 555 (u64)dma_unmap_addr(tx_buffer, dma), 556 dma_unmap_len(tx_buffer, len), 557 tx_buffer->next_to_watch, 558 (u64)tx_buffer->time_stamp); 559} 560 561/* 562 * ixgbe_dump - Print registers, tx-rings and rx-rings 563 */ 564static void ixgbe_dump(struct ixgbe_adapter *adapter) 565{ 566 struct net_device *netdev = adapter->netdev; 567 struct ixgbe_hw *hw = &adapter->hw; 568 struct ixgbe_reg_info *reginfo; 569 int n = 0; 570 struct ixgbe_ring *ring; 571 struct ixgbe_tx_buffer *tx_buffer; 572 union ixgbe_adv_tx_desc *tx_desc; 573 struct my_u0 { u64 a; u64 b; } *u0; 574 struct ixgbe_ring *rx_ring; 575 union ixgbe_adv_rx_desc *rx_desc; 576 struct ixgbe_rx_buffer *rx_buffer_info; 577 int i = 0; 578 579 if (!netif_msg_hw(adapter)) 580 return; 581 582 /* Print netdevice Info */ 583 if (netdev) { 584 dev_info(&adapter->pdev->dev, "Net device Info\n"); 585 pr_info("Device Name state " 586 "trans_start\n"); 587 pr_info("%-15s %016lX %016lX\n", 588 netdev->name, 589 netdev->state, 590 dev_trans_start(netdev)); 591 } 592 593 /* Print Registers */ 594 dev_info(&adapter->pdev->dev, "Register Dump\n"); 595 pr_info(" Register Name Value\n"); 596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 597 reginfo->name; reginfo++) { 598 ixgbe_regdump(hw, reginfo); 599 } 600 601 /* Print TX Ring Summary */ 602 if (!netdev || !netif_running(netdev)) 603 return; 604 605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 606 pr_info(" %s %s %s %s\n", 607 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 608 "leng", "ntw", "timestamp"); 609 for (n = 0; n < adapter->num_tx_queues; n++) { 610 ring = adapter->tx_ring[n]; 611 ixgbe_print_buffer(ring, n); 612 } 613 614 for (n = 0; n < adapter->num_xdp_queues; n++) { 615 ring = adapter->xdp_ring[n]; 616 ixgbe_print_buffer(ring, n); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; ring->desc && (i < ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(ring, i); 672 tx_buffer = &ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 const char *ring_desc; 676 677 if (i == ring->next_to_use && 678 i == ring->next_to_clean) 679 ring_desc = " NTC/U"; 680 else if (i == ring->next_to_use) 681 ring_desc = " NTU"; 682 else if (i == ring->next_to_clean) 683 ring_desc = " NTC"; 684 else 685 ring_desc = ""; 686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 687 i, 688 le64_to_cpu((__force __le64)u0->a), 689 le64_to_cpu((__force __le64)u0->b), 690 (u64)dma_unmap_addr(tx_buffer, dma), 691 dma_unmap_len(tx_buffer, len), 692 tx_buffer->next_to_watch, 693 (u64)tx_buffer->time_stamp, 694 tx_buffer->skb, 695 ring_desc); 696 697 if (netif_msg_pktdata(adapter) && 698 tx_buffer->skb) 699 print_hex_dump(KERN_INFO, "", 700 DUMP_PREFIX_ADDRESS, 16, 1, 701 tx_buffer->skb->data, 702 dma_unmap_len(tx_buffer, len), 703 true); 704 } 705 } 706 } 707 708 /* Print RX Rings Summary */ 709rx_ring_summary: 710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 711 pr_info("Queue [NTU] [NTC]\n"); 712 for (n = 0; n < adapter->num_rx_queues; n++) { 713 rx_ring = adapter->rx_ring[n]; 714 pr_info("%5d %5X %5X\n", 715 n, rx_ring->next_to_use, rx_ring->next_to_clean); 716 } 717 718 /* Print RX Rings */ 719 if (!netif_msg_rx_status(adapter)) 720 return; 721 722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 723 724 /* Receive Descriptor Formats 725 * 726 * 82598 Advanced Receive Descriptor (Read) Format 727 * 63 1 0 728 * +-----------------------------------------------------+ 729 * 0 | Packet Buffer Address [63:1] |A0/NSE| 730 * +----------------------------------------------+------+ 731 * 8 | Header Buffer Address [63:1] | DD | 732 * +-----------------------------------------------------+ 733 * 734 * 735 * 82598 Advanced Receive Descriptor (Write-Back) Format 736 * 737 * 63 48 47 32 31 30 21 20 16 15 4 3 0 738 * +------------------------------------------------------+ 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 740 * | Packet | IP | | | | Type | Type | 741 * | Checksum | Ident | | | | | | 742 * +------------------------------------------------------+ 743 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 744 * +------------------------------------------------------+ 745 * 63 48 47 32 31 20 19 0 746 * 747 * 82599+ Advanced Receive Descriptor (Read) Format 748 * 63 1 0 749 * +-----------------------------------------------------+ 750 * 0 | Packet Buffer Address [63:1] |A0/NSE| 751 * +----------------------------------------------+------+ 752 * 8 | Header Buffer Address [63:1] | DD | 753 * +-----------------------------------------------------+ 754 * 755 * 756 * 82599+ Advanced Receive Descriptor (Write-Back) Format 757 * 758 * 63 48 47 32 31 30 21 20 17 16 4 3 0 759 * +------------------------------------------------------+ 760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 762 * |/ Flow Dir Flt ID | | | | | | 763 * +------------------------------------------------------+ 764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 765 * +------------------------------------------------------+ 766 * 63 48 47 32 31 20 19 0 767 */ 768 769 for (n = 0; n < adapter->num_rx_queues; n++) { 770 rx_ring = adapter->rx_ring[n]; 771 pr_info("------------------------------------\n"); 772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 773 pr_info("------------------------------------\n"); 774 pr_info("%s%s%s\n", 775 "R [desc] [ PktBuf A0] ", 776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 777 "<-- Adv Rx Read format"); 778 pr_info("%s%s%s\n", 779 "RWB[desc] [PcsmIpSHl PtRs] ", 780 "[vl er S cks ln] ---------------- [bi->skb ] ", 781 "<-- Adv Rx Write-Back format"); 782 783 for (i = 0; i < rx_ring->count; i++) { 784 const char *ring_desc; 785 786 if (i == rx_ring->next_to_use) 787 ring_desc = " NTU"; 788 else if (i == rx_ring->next_to_clean) 789 ring_desc = " NTC"; 790 else 791 ring_desc = ""; 792 793 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 794 rx_desc = IXGBE_RX_DESC(rx_ring, i); 795 u0 = (struct my_u0 *)rx_desc; 796 if (rx_desc->wb.upper.length) { 797 /* Descriptor Done */ 798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 799 i, 800 le64_to_cpu((__force __le64)u0->a), 801 le64_to_cpu((__force __le64)u0->b), 802 rx_buffer_info->skb, 803 ring_desc); 804 } else { 805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 806 i, 807 le64_to_cpu((__force __le64)u0->a), 808 le64_to_cpu((__force __le64)u0->b), 809 (u64)rx_buffer_info->dma, 810 rx_buffer_info->skb, 811 ring_desc); 812 813 if (netif_msg_pktdata(adapter) && 814 rx_buffer_info->dma) { 815 print_hex_dump(KERN_INFO, "", 816 DUMP_PREFIX_ADDRESS, 16, 1, 817 page_address(rx_buffer_info->page) + 818 rx_buffer_info->page_offset, 819 ixgbe_rx_bufsz(rx_ring), true); 820 } 821 } 822 } 823 } 824} 825 826static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 827{ 828 u32 ctrl_ext; 829 830 /* Let firmware take over control of h/w */ 831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 834} 835 836static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 837{ 838 u32 ctrl_ext; 839 840 /* Let firmware know the driver has taken over */ 841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 844} 845 846/** 847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 848 * @adapter: pointer to adapter struct 849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 850 * @queue: queue to map the corresponding interrupt to 851 * @msix_vector: the vector to map to the corresponding queue 852 * 853 */ 854static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 855 u8 queue, u8 msix_vector) 856{ 857 u32 ivar, index; 858 struct ixgbe_hw *hw = &adapter->hw; 859 switch (hw->mac.type) { 860 case ixgbe_mac_82598EB: 861 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 862 if (direction == -1) 863 direction = 0; 864 index = (((direction * 64) + queue) >> 2) & 0x1F; 865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 866 ivar &= ~(0xFF << (8 * (queue & 0x3))); 867 ivar |= (msix_vector << (8 * (queue & 0x3))); 868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 869 break; 870 case ixgbe_mac_82599EB: 871 case ixgbe_mac_X540: 872 case ixgbe_mac_X550: 873 case ixgbe_mac_X550EM_x: 874 case ixgbe_mac_x550em_a: 875 if (direction == -1) { 876 /* other causes */ 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 index = ((queue & 1) * 8); 879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 880 ivar &= ~(0xFF << index); 881 ivar |= (msix_vector << index); 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 883 break; 884 } else { 885 /* tx or rx causes */ 886 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 887 index = ((16 * (queue & 1)) + (8 * direction)); 888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 889 ivar &= ~(0xFF << index); 890 ivar |= (msix_vector << index); 891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 892 break; 893 } 894 default: 895 break; 896 } 897} 898 899void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 900 u64 qmask) 901{ 902 u32 mask; 903 904 switch (adapter->hw.mac.type) { 905 case ixgbe_mac_82598EB: 906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 908 break; 909 case ixgbe_mac_82599EB: 910 case ixgbe_mac_X540: 911 case ixgbe_mac_X550: 912 case ixgbe_mac_X550EM_x: 913 case ixgbe_mac_x550em_a: 914 mask = (qmask & 0xFFFFFFFF); 915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 916 mask = (qmask >> 32); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 918 break; 919 default: 920 break; 921 } 922} 923 924static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 925{ 926 struct ixgbe_hw *hw = &adapter->hw; 927 struct ixgbe_hw_stats *hwstats = &adapter->stats; 928 int i; 929 u32 data; 930 931 if ((hw->fc.current_mode != ixgbe_fc_full) && 932 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 933 return; 934 935 switch (hw->mac.type) { 936 case ixgbe_mac_82598EB: 937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 938 break; 939 default: 940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 941 } 942 hwstats->lxoffrxc += data; 943 944 /* refill credits (no tx hang) if we received xoff */ 945 if (!data) 946 return; 947 948 for (i = 0; i < adapter->num_tx_queues; i++) 949 clear_bit(__IXGBE_HANG_CHECK_ARMED, 950 &adapter->tx_ring[i]->state); 951 952 for (i = 0; i < adapter->num_xdp_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->xdp_ring[i]->state); 955} 956 957static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 958{ 959 struct ixgbe_hw *hw = &adapter->hw; 960 struct ixgbe_hw_stats *hwstats = &adapter->stats; 961 u32 xoff[8] = {0}; 962 u8 tc; 963 int i; 964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 965 966 if (adapter->ixgbe_ieee_pfc) 967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 968 969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 970 ixgbe_update_xoff_rx_lfc(adapter); 971 return; 972 } 973 974 /* update stats for each tc, only valid with PFC enabled */ 975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 976 u32 pxoffrxc; 977 978 switch (hw->mac.type) { 979 case ixgbe_mac_82598EB: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 981 break; 982 default: 983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 984 } 985 hwstats->pxoffrxc[i] += pxoffrxc; 986 /* Get the TC for given UP */ 987 tc = netdev_get_prio_tc_map(adapter->netdev, i); 988 xoff[tc] += pxoffrxc; 989 } 990 991 /* disarm tx queues that have received xoff frames */ 992 for (i = 0; i < adapter->num_tx_queues; i++) { 993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 994 995 tc = tx_ring->dcb_tc; 996 if (xoff[tc]) 997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 998 } 999 1000 for (i = 0; i < adapter->num_xdp_queues; i++) { 1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1002 1003 tc = xdp_ring->dcb_tc; 1004 if (xoff[tc]) 1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1006 } 1007} 1008 1009static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1010{ 1011 return ring->stats.packets; 1012} 1013 1014static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1015{ 1016 unsigned int head, tail; 1017 1018 head = ring->next_to_clean; 1019 tail = ring->next_to_use; 1020 1021 return ((head <= tail) ? tail : tail + ring->count) - head; 1022} 1023 1024static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1025{ 1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1029 1030 clear_check_for_tx_hang(tx_ring); 1031 1032 /* 1033 * Check for a hung queue, but be thorough. This verifies 1034 * that a transmit has been completed since the previous 1035 * check AND there is at least one packet pending. The 1036 * ARMED bit is set to indicate a potential hang. The 1037 * bit is cleared if a pause frame is received to remove 1038 * false hang detection due to PFC or 802.3x frames. By 1039 * requiring this to fail twice we avoid races with 1040 * pfc clearing the ARMED bit and conditions where we 1041 * run the check_tx_hang logic with a transmit completion 1042 * pending but without time to complete it yet. 1043 */ 1044 if (tx_done_old == tx_done && tx_pending) 1045 /* make sure it is true for two checks in a row */ 1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1047 &tx_ring->state); 1048 /* update completed stats and continue */ 1049 tx_ring->tx_stats.tx_done_old = tx_done; 1050 /* reset the countdown */ 1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1052 1053 return false; 1054} 1055 1056/** 1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1058 * @adapter: driver private struct 1059 **/ 1060static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1061{ 1062 1063 /* Do the reset outside of interrupt context */ 1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1066 e_warn(drv, "initiating reset due to tx timeout\n"); 1067 ixgbe_service_event_schedule(adapter); 1068 } 1069} 1070 1071/** 1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1073 * @netdev: network interface device structure 1074 * @queue_index: Tx queue to set 1075 * @maxrate: desired maximum transmit bitrate 1076 **/ 1077static int ixgbe_tx_maxrate(struct net_device *netdev, 1078 int queue_index, u32 maxrate) 1079{ 1080 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1081 struct ixgbe_hw *hw = &adapter->hw; 1082 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1083 1084 if (!maxrate) 1085 return 0; 1086 1087 /* Calculate the rate factor values to set */ 1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1089 bcnrc_val /= maxrate; 1090 1091 /* clear everything but the rate factor */ 1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1093 IXGBE_RTTBCNRC_RF_DEC_MASK; 1094 1095 /* enable the rate scheduler */ 1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1097 1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1100 1101 return 0; 1102} 1103 1104/** 1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1106 * @q_vector: structure containing interrupt and ring information 1107 * @tx_ring: tx ring to clean 1108 * @napi_budget: Used to determine if we are in netpoll 1109 **/ 1110static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1111 struct ixgbe_ring *tx_ring, int napi_budget) 1112{ 1113 struct ixgbe_adapter *adapter = q_vector->adapter; 1114 struct ixgbe_tx_buffer *tx_buffer; 1115 union ixgbe_adv_tx_desc *tx_desc; 1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1117 unsigned int budget = q_vector->tx.work_limit; 1118 unsigned int i = tx_ring->next_to_clean; 1119 1120 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1121 return true; 1122 1123 tx_buffer = &tx_ring->tx_buffer_info[i]; 1124 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1125 i -= tx_ring->count; 1126 1127 do { 1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1129 1130 /* if next_to_watch is not set then there is no work pending */ 1131 if (!eop_desc) 1132 break; 1133 1134 /* prevent any other reads prior to eop_desc */ 1135 smp_rmb(); 1136 1137 /* if DD is not set pending work has not been completed */ 1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1139 break; 1140 1141 /* clear next_to_watch to prevent false hangs */ 1142 tx_buffer->next_to_watch = NULL; 1143 1144 /* update the statistics for this packet */ 1145 total_bytes += tx_buffer->bytecount; 1146 total_packets += tx_buffer->gso_segs; 1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1148 total_ipsec++; 1149 1150 /* free the skb */ 1151 if (ring_is_xdp(tx_ring)) 1152 xdp_return_frame(tx_buffer->xdpf); 1153 else 1154 napi_consume_skb(tx_buffer->skb, napi_budget); 1155 1156 /* unmap skb header data */ 1157 dma_unmap_single(tx_ring->dev, 1158 dma_unmap_addr(tx_buffer, dma), 1159 dma_unmap_len(tx_buffer, len), 1160 DMA_TO_DEVICE); 1161 1162 /* clear tx_buffer data */ 1163 dma_unmap_len_set(tx_buffer, len, 0); 1164 1165 /* unmap remaining buffers */ 1166 while (tx_desc != eop_desc) { 1167 tx_buffer++; 1168 tx_desc++; 1169 i++; 1170 if (unlikely(!i)) { 1171 i -= tx_ring->count; 1172 tx_buffer = tx_ring->tx_buffer_info; 1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1174 } 1175 1176 /* unmap any remaining paged data */ 1177 if (dma_unmap_len(tx_buffer, len)) { 1178 dma_unmap_page(tx_ring->dev, 1179 dma_unmap_addr(tx_buffer, dma), 1180 dma_unmap_len(tx_buffer, len), 1181 DMA_TO_DEVICE); 1182 dma_unmap_len_set(tx_buffer, len, 0); 1183 } 1184 } 1185 1186 /* move us one more past the eop_desc for start of next pkt */ 1187 tx_buffer++; 1188 tx_desc++; 1189 i++; 1190 if (unlikely(!i)) { 1191 i -= tx_ring->count; 1192 tx_buffer = tx_ring->tx_buffer_info; 1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1194 } 1195 1196 /* issue prefetch for next Tx descriptor */ 1197 prefetch(tx_desc); 1198 1199 /* update budget accounting */ 1200 budget--; 1201 } while (likely(budget)); 1202 1203 i += tx_ring->count; 1204 tx_ring->next_to_clean = i; 1205 u64_stats_update_begin(&tx_ring->syncp); 1206 tx_ring->stats.bytes += total_bytes; 1207 tx_ring->stats.packets += total_packets; 1208 u64_stats_update_end(&tx_ring->syncp); 1209 q_vector->tx.total_bytes += total_bytes; 1210 q_vector->tx.total_packets += total_packets; 1211 adapter->tx_ipsec += total_ipsec; 1212 1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1214 /* schedule immediate reset if we believe we hung */ 1215 struct ixgbe_hw *hw = &adapter->hw; 1216 e_err(drv, "Detected Tx Unit Hang %s\n" 1217 " Tx Queue <%d>\n" 1218 " TDH, TDT <%x>, <%x>\n" 1219 " next_to_use <%x>\n" 1220 " next_to_clean <%x>\n" 1221 "tx_buffer_info[next_to_clean]\n" 1222 " time_stamp <%lx>\n" 1223 " jiffies <%lx>\n", 1224 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1225 tx_ring->queue_index, 1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1228 tx_ring->next_to_use, i, 1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1230 1231 if (!ring_is_xdp(tx_ring)) 1232 netif_stop_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 1235 e_info(probe, 1236 "tx hang %d detected on queue %d, resetting adapter\n", 1237 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1238 1239 /* schedule immediate reset if we believe we hung */ 1240 ixgbe_tx_timeout_reset(adapter); 1241 1242 /* the adapter is about to reset, no point in enabling stuff */ 1243 return true; 1244 } 1245 1246 if (ring_is_xdp(tx_ring)) 1247 return !!budget; 1248 1249 netdev_tx_completed_queue(txring_txq(tx_ring), 1250 total_packets, total_bytes); 1251 1252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1255 /* Make sure that anybody stopping the queue after this 1256 * sees the new next_to_clean. 1257 */ 1258 smp_mb(); 1259 if (__netif_subqueue_stopped(tx_ring->netdev, 1260 tx_ring->queue_index) 1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1262 netif_wake_subqueue(tx_ring->netdev, 1263 tx_ring->queue_index); 1264 ++tx_ring->tx_stats.restart_queue; 1265 } 1266 } 1267 1268 return !!budget; 1269} 1270 1271#ifdef CONFIG_IXGBE_DCA 1272static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1273 struct ixgbe_ring *tx_ring, 1274 int cpu) 1275{ 1276 struct ixgbe_hw *hw = &adapter->hw; 1277 u32 txctrl = 0; 1278 u16 reg_offset; 1279 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1281 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1282 1283 switch (hw->mac.type) { 1284 case ixgbe_mac_82598EB: 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1286 break; 1287 case ixgbe_mac_82599EB: 1288 case ixgbe_mac_X540: 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1291 break; 1292 default: 1293 /* for unknown hardware do not write register */ 1294 return; 1295 } 1296 1297 /* 1298 * We can enable relaxed ordering for reads, but not writes when 1299 * DCA is enabled. This is due to a known issue in some chipsets 1300 * which will cause the DCA tag to be cleared. 1301 */ 1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1305 1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1307} 1308 1309static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1310 struct ixgbe_ring *rx_ring, 1311 int cpu) 1312{ 1313 struct ixgbe_hw *hw = &adapter->hw; 1314 u32 rxctrl = 0; 1315 u8 reg_idx = rx_ring->reg_idx; 1316 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1319 1320 switch (hw->mac.type) { 1321 case ixgbe_mac_82599EB: 1322 case ixgbe_mac_X540: 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 /* 1330 * We can enable relaxed ordering for reads, but not writes when 1331 * DCA is enabled. This is due to a known issue in some chipsets 1332 * which will cause the DCA tag to be cleared. 1333 */ 1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1337 1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1339} 1340 1341static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1342{ 1343 struct ixgbe_adapter *adapter = q_vector->adapter; 1344 struct ixgbe_ring *ring; 1345 int cpu = get_cpu(); 1346 1347 if (q_vector->cpu == cpu) 1348 goto out_no_update; 1349 1350 ixgbe_for_each_ring(ring, q_vector->tx) 1351 ixgbe_update_tx_dca(adapter, ring, cpu); 1352 1353 ixgbe_for_each_ring(ring, q_vector->rx) 1354 ixgbe_update_rx_dca(adapter, ring, cpu); 1355 1356 q_vector->cpu = cpu; 1357out_no_update: 1358 put_cpu(); 1359} 1360 1361static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1362{ 1363 int i; 1364 1365 /* always use CB2 mode, difference is masked in the CB driver */ 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1368 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1369 else 1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1371 IXGBE_DCA_CTRL_DCA_DISABLE); 1372 1373 for (i = 0; i < adapter->num_q_vectors; i++) { 1374 adapter->q_vector[i]->cpu = -1; 1375 ixgbe_update_dca(adapter->q_vector[i]); 1376 } 1377} 1378 1379static int __ixgbe_notify_dca(struct device *dev, void *data) 1380{ 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1382 unsigned long event = *(unsigned long *)data; 1383 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1385 return 0; 1386 1387 switch (event) { 1388 case DCA_PROVIDER_ADD: 1389 /* if we're already enabled, don't do it again */ 1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1391 break; 1392 if (dca_add_requester(dev) == 0) { 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1395 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1396 break; 1397 } 1398 fallthrough; /* DCA is disabled. */ 1399 case DCA_PROVIDER_REMOVE: 1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1401 dca_remove_requester(dev); 1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1404 IXGBE_DCA_CTRL_DCA_DISABLE); 1405 } 1406 break; 1407 } 1408 1409 return 0; 1410} 1411 1412#endif /* CONFIG_IXGBE_DCA */ 1413 1414#define IXGBE_RSS_L4_TYPES_MASK \ 1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1419 1420static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1421 union ixgbe_adv_rx_desc *rx_desc, 1422 struct sk_buff *skb) 1423{ 1424 u16 rss_type; 1425 1426 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1427 return; 1428 1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1430 IXGBE_RXDADV_RSSTYPE_MASK; 1431 1432 if (!rss_type) 1433 return; 1434 1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1438} 1439 1440#ifdef IXGBE_FCOE 1441/** 1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1443 * @ring: structure containing ring specific data 1444 * @rx_desc: advanced rx descriptor 1445 * 1446 * Returns : true if it is FCoE pkt 1447 */ 1448static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1449 union ixgbe_adv_rx_desc *rx_desc) 1450{ 1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1452 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1457} 1458 1459#endif /* IXGBE_FCOE */ 1460/** 1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1462 * @ring: structure containing ring specific data 1463 * @rx_desc: current Rx descriptor being processed 1464 * @skb: skb currently being received and modified 1465 **/ 1466static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1467 union ixgbe_adv_rx_desc *rx_desc, 1468 struct sk_buff *skb) 1469{ 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1471 bool encap_pkt = false; 1472 1473 skb_checksum_none_assert(skb); 1474 1475 /* Rx csum disabled */ 1476 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1477 return; 1478 1479 /* check for VXLAN and Geneve packets */ 1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1481 encap_pkt = true; 1482 skb->encapsulation = 1; 1483 } 1484 1485 /* if IP and error */ 1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1488 ring->rx_stats.csum_err++; 1489 return; 1490 } 1491 1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1493 return; 1494 1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1496 /* 1497 * 82599 errata, UDP frames with a 0 checksum can be marked as 1498 * checksum errors. 1499 */ 1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1502 return; 1503 1504 ring->rx_stats.csum_err++; 1505 return; 1506 } 1507 1508 /* It must be a TCP or UDP packet with a valid checksum */ 1509 skb->ip_summed = CHECKSUM_UNNECESSARY; 1510 if (encap_pkt) { 1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1512 return; 1513 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1515 skb->ip_summed = CHECKSUM_NONE; 1516 return; 1517 } 1518 /* If we checked the outer header let the stack know */ 1519 skb->csum_level = 1; 1520 } 1521} 1522 1523static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1524{ 1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1526} 1527 1528static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1529 struct ixgbe_rx_buffer *bi) 1530{ 1531 struct page *page = bi->page; 1532 dma_addr_t dma; 1533 1534 /* since we are recycling buffers we should seldom need to alloc */ 1535 if (likely(page)) 1536 return true; 1537 1538 /* alloc new page for storage */ 1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1540 if (unlikely(!page)) { 1541 rx_ring->rx_stats.alloc_rx_page_failed++; 1542 return false; 1543 } 1544 1545 /* map page for use */ 1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1547 ixgbe_rx_pg_size(rx_ring), 1548 DMA_FROM_DEVICE, 1549 IXGBE_RX_DMA_ATTR); 1550 1551 /* 1552 * if mapping failed free memory back to system since 1553 * there isn't much point in holding memory we can't use 1554 */ 1555 if (dma_mapping_error(rx_ring->dev, dma)) { 1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1557 1558 rx_ring->rx_stats.alloc_rx_page_failed++; 1559 return false; 1560 } 1561 1562 bi->dma = dma; 1563 bi->page = page; 1564 bi->page_offset = ixgbe_rx_offset(rx_ring); 1565 page_ref_add(page, USHRT_MAX - 1); 1566 bi->pagecnt_bias = USHRT_MAX; 1567 rx_ring->rx_stats.alloc_rx_page++; 1568 1569 return true; 1570} 1571 1572/** 1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1574 * @rx_ring: ring to place buffers on 1575 * @cleaned_count: number of buffers to replace 1576 **/ 1577void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1578{ 1579 union ixgbe_adv_rx_desc *rx_desc; 1580 struct ixgbe_rx_buffer *bi; 1581 u16 i = rx_ring->next_to_use; 1582 u16 bufsz; 1583 1584 /* nothing to do */ 1585 if (!cleaned_count) 1586 return; 1587 1588 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1589 bi = &rx_ring->rx_buffer_info[i]; 1590 i -= rx_ring->count; 1591 1592 bufsz = ixgbe_rx_bufsz(rx_ring); 1593 1594 do { 1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1596 break; 1597 1598 /* sync the buffer for use by the device */ 1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1600 bi->page_offset, bufsz, 1601 DMA_FROM_DEVICE); 1602 1603 /* 1604 * Refresh the desc even if buffer_addrs didn't change 1605 * because each write-back erases this info. 1606 */ 1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1608 1609 rx_desc++; 1610 bi++; 1611 i++; 1612 if (unlikely(!i)) { 1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1614 bi = rx_ring->rx_buffer_info; 1615 i -= rx_ring->count; 1616 } 1617 1618 /* clear the length for the next_to_use descriptor */ 1619 rx_desc->wb.upper.length = 0; 1620 1621 cleaned_count--; 1622 } while (cleaned_count); 1623 1624 i += rx_ring->count; 1625 1626 if (rx_ring->next_to_use != i) { 1627 rx_ring->next_to_use = i; 1628 1629 /* update next to alloc since we have filled the ring */ 1630 rx_ring->next_to_alloc = i; 1631 1632 /* Force memory writes to complete before letting h/w 1633 * know there are new descriptors to fetch. (Only 1634 * applicable for weak-ordered memory model archs, 1635 * such as IA-64). 1636 */ 1637 wmb(); 1638 writel(i, rx_ring->tail); 1639 } 1640} 1641 1642static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1643 struct sk_buff *skb) 1644{ 1645 u16 hdr_len = skb_headlen(skb); 1646 1647 /* set gso_size to avoid messing up TCP MSS */ 1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1649 IXGBE_CB(skb)->append_cnt); 1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1651} 1652 1653static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1654 struct sk_buff *skb) 1655{ 1656 /* if append_cnt is 0 then frame is not RSC */ 1657 if (!IXGBE_CB(skb)->append_cnt) 1658 return; 1659 1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1661 rx_ring->rx_stats.rsc_flush++; 1662 1663 ixgbe_set_rsc_gso_size(rx_ring, skb); 1664 1665 /* gso_size is computed using append_cnt so always clear it last */ 1666 IXGBE_CB(skb)->append_cnt = 0; 1667} 1668 1669/** 1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1671 * @rx_ring: rx descriptor ring packet is being transacted on 1672 * @rx_desc: pointer to the EOP Rx descriptor 1673 * @skb: pointer to current skb being populated 1674 * 1675 * This function checks the ring, descriptor, and packet information in 1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1677 * other fields within the skb. 1678 **/ 1679void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1680 union ixgbe_adv_rx_desc *rx_desc, 1681 struct sk_buff *skb) 1682{ 1683 struct net_device *dev = rx_ring->netdev; 1684 u32 flags = rx_ring->q_vector->adapter->flags; 1685 1686 ixgbe_update_rsc_stats(rx_ring, skb); 1687 1688 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1689 1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1691 1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1694 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1699 } 1700 1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1703 1704 /* record Rx queue, or update MACVLAN statistics */ 1705 if (netif_is_ixgbe(dev)) 1706 skb_record_rx_queue(skb, rx_ring->queue_index); 1707 else 1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1709 false); 1710 1711 skb->protocol = eth_type_trans(skb, dev); 1712} 1713 1714void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1715 struct sk_buff *skb) 1716{ 1717 napi_gro_receive(&q_vector->napi, skb); 1718} 1719 1720/** 1721 * ixgbe_is_non_eop - process handling of non-EOP buffers 1722 * @rx_ring: Rx ring being processed 1723 * @rx_desc: Rx descriptor for current buffer 1724 * @skb: Current socket buffer containing buffer in progress 1725 * 1726 * This function updates next to clean. If the buffer is an EOP buffer 1727 * this function exits returning false, otherwise it will place the 1728 * sk_buff in the next buffer to be chained and return true indicating 1729 * that this is in fact a non-EOP buffer. 1730 **/ 1731static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1732 union ixgbe_adv_rx_desc *rx_desc, 1733 struct sk_buff *skb) 1734{ 1735 u32 ntc = rx_ring->next_to_clean + 1; 1736 1737 /* fetch, update, and store next to clean */ 1738 ntc = (ntc < rx_ring->count) ? ntc : 0; 1739 rx_ring->next_to_clean = ntc; 1740 1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1742 1743 /* update RSC append count if present */ 1744 if (ring_is_rsc_enabled(rx_ring)) { 1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1747 1748 if (unlikely(rsc_enabled)) { 1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1750 1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1753 1754 /* update ntc based on RSC value */ 1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1756 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1758 } 1759 } 1760 1761 /* if we are the last buffer then there is nothing else to do */ 1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1763 return false; 1764 1765 /* place skb in next buffer to be received */ 1766 rx_ring->rx_buffer_info[ntc].skb = skb; 1767 rx_ring->rx_stats.non_eop_descs++; 1768 1769 return true; 1770} 1771 1772/** 1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1774 * @rx_ring: rx descriptor ring packet is being transacted on 1775 * @skb: pointer to current skb being adjusted 1776 * 1777 * This function is an ixgbe specific version of __pskb_pull_tail. The 1778 * main difference between this version and the original function is that 1779 * this function can make several assumptions about the state of things 1780 * that allow for significant optimizations versus the standard function. 1781 * As a result we can do things like drop a frag and maintain an accurate 1782 * truesize for the skb. 1783 */ 1784static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1785 struct sk_buff *skb) 1786{ 1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1788 unsigned char *va; 1789 unsigned int pull_len; 1790 1791 /* 1792 * it is valid to use page_address instead of kmap since we are 1793 * working with pages allocated out of the lomem pool per 1794 * alloc_page(GFP_ATOMIC) 1795 */ 1796 va = skb_frag_address(frag); 1797 1798 /* 1799 * we need the header to contain the greater of either ETH_HLEN or 1800 * 60 bytes if the skb->len is less than 60 for skb_pad. 1801 */ 1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1803 1804 /* align pull length to size of long to optimize memcpy performance */ 1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1806 1807 /* update all of the pointers */ 1808 skb_frag_size_sub(frag, pull_len); 1809 skb_frag_off_add(frag, pull_len); 1810 skb->data_len -= pull_len; 1811 skb->tail += pull_len; 1812} 1813 1814/** 1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1816 * @rx_ring: rx descriptor ring packet is being transacted on 1817 * @skb: pointer to current skb being updated 1818 * 1819 * This function provides a basic DMA sync up for the first fragment of an 1820 * skb. The reason for doing this is that the first fragment cannot be 1821 * unmapped until we have reached the end of packet descriptor for a buffer 1822 * chain. 1823 */ 1824static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1825 struct sk_buff *skb) 1826{ 1827 if (ring_uses_build_skb(rx_ring)) { 1828 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 1829 unsigned long offset = (unsigned long)(skb->data) & mask; 1830 1831 dma_sync_single_range_for_cpu(rx_ring->dev, 1832 IXGBE_CB(skb)->dma, 1833 offset, 1834 skb_headlen(skb), 1835 DMA_FROM_DEVICE); 1836 } else { 1837 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1838 1839 dma_sync_single_range_for_cpu(rx_ring->dev, 1840 IXGBE_CB(skb)->dma, 1841 skb_frag_off(frag), 1842 skb_frag_size(frag), 1843 DMA_FROM_DEVICE); 1844 } 1845 1846 /* If the page was released, just unmap it. */ 1847 if (unlikely(IXGBE_CB(skb)->page_released)) { 1848 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1849 ixgbe_rx_pg_size(rx_ring), 1850 DMA_FROM_DEVICE, 1851 IXGBE_RX_DMA_ATTR); 1852 } 1853} 1854 1855/** 1856 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1857 * @rx_ring: rx descriptor ring packet is being transacted on 1858 * @rx_desc: pointer to the EOP Rx descriptor 1859 * @skb: pointer to current skb being fixed 1860 * 1861 * Check if the skb is valid in the XDP case it will be an error pointer. 1862 * Return true in this case to abort processing and advance to next 1863 * descriptor. 1864 * 1865 * Check for corrupted packet headers caused by senders on the local L2 1866 * embedded NIC switch not setting up their Tx Descriptors right. These 1867 * should be very rare. 1868 * 1869 * Also address the case where we are pulling data in on pages only 1870 * and as such no data is present in the skb header. 1871 * 1872 * In addition if skb is not at least 60 bytes we need to pad it so that 1873 * it is large enough to qualify as a valid Ethernet frame. 1874 * 1875 * Returns true if an error was encountered and skb was freed. 1876 **/ 1877bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1878 union ixgbe_adv_rx_desc *rx_desc, 1879 struct sk_buff *skb) 1880{ 1881 struct net_device *netdev = rx_ring->netdev; 1882 1883 /* XDP packets use error pointer so abort at this point */ 1884 if (IS_ERR(skb)) 1885 return true; 1886 1887 /* Verify netdev is present, and that packet does not have any 1888 * errors that would be unacceptable to the netdev. 1889 */ 1890 if (!netdev || 1891 (unlikely(ixgbe_test_staterr(rx_desc, 1892 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1893 !(netdev->features & NETIF_F_RXALL)))) { 1894 dev_kfree_skb_any(skb); 1895 return true; 1896 } 1897 1898 /* place header in linear portion of buffer */ 1899 if (!skb_headlen(skb)) 1900 ixgbe_pull_tail(rx_ring, skb); 1901 1902#ifdef IXGBE_FCOE 1903 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1905 return false; 1906 1907#endif 1908 /* if eth_skb_pad returns an error the skb was freed */ 1909 if (eth_skb_pad(skb)) 1910 return true; 1911 1912 return false; 1913} 1914 1915/** 1916 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1917 * @rx_ring: rx descriptor ring to store buffers on 1918 * @old_buff: donor buffer to have page reused 1919 * 1920 * Synchronizes page for reuse by the adapter 1921 **/ 1922static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1923 struct ixgbe_rx_buffer *old_buff) 1924{ 1925 struct ixgbe_rx_buffer *new_buff; 1926 u16 nta = rx_ring->next_to_alloc; 1927 1928 new_buff = &rx_ring->rx_buffer_info[nta]; 1929 1930 /* update, and store next to alloc */ 1931 nta++; 1932 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1933 1934 /* Transfer page from old buffer to new buffer. 1935 * Move each member individually to avoid possible store 1936 * forwarding stalls and unnecessary copy of skb. 1937 */ 1938 new_buff->dma = old_buff->dma; 1939 new_buff->page = old_buff->page; 1940 new_buff->page_offset = old_buff->page_offset; 1941 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1942} 1943 1944static inline bool ixgbe_page_is_reserved(struct page *page) 1945{ 1946 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1947} 1948 1949static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1950 int rx_buffer_pgcnt) 1951{ 1952 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1953 struct page *page = rx_buffer->page; 1954 1955 /* avoid re-using remote pages */ 1956 if (unlikely(ixgbe_page_is_reserved(page))) 1957 return false; 1958 1959#if (PAGE_SIZE < 8192) 1960 /* if we are only owner of page we can reuse it */ 1961 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1962 return false; 1963#else 1964 /* The last offset is a bit aggressive in that we assume the 1965 * worst case of FCoE being enabled and using a 3K buffer. 1966 * However this should have minimal impact as the 1K extra is 1967 * still less than one buffer in size. 1968 */ 1969#define IXGBE_LAST_OFFSET \ 1970 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1971 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1972 return false; 1973#endif 1974 1975 /* If we have drained the page fragment pool we need to update 1976 * the pagecnt_bias and page count so that we fully restock the 1977 * number of references the driver holds. 1978 */ 1979 if (unlikely(pagecnt_bias == 1)) { 1980 page_ref_add(page, USHRT_MAX - 1); 1981 rx_buffer->pagecnt_bias = USHRT_MAX; 1982 } 1983 1984 return true; 1985} 1986 1987/** 1988 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1989 * @rx_ring: rx descriptor ring to transact packets on 1990 * @rx_buffer: buffer containing page to add 1991 * @skb: sk_buff to place the data into 1992 * @size: size of data in rx_buffer 1993 * 1994 * This function will add the data contained in rx_buffer->page to the skb. 1995 * This is done either through a direct copy if the data in the buffer is 1996 * less than the skb header size, otherwise it will just attach the page as 1997 * a frag to the skb. 1998 * 1999 * The function will then update the page offset if necessary and return 2000 * true if the buffer can be reused by the adapter. 2001 **/ 2002static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2003 struct ixgbe_rx_buffer *rx_buffer, 2004 struct sk_buff *skb, 2005 unsigned int size) 2006{ 2007#if (PAGE_SIZE < 8192) 2008 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2009#else 2010 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2011 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2012 SKB_DATA_ALIGN(size); 2013#endif 2014 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2015 rx_buffer->page_offset, size, truesize); 2016#if (PAGE_SIZE < 8192) 2017 rx_buffer->page_offset ^= truesize; 2018#else 2019 rx_buffer->page_offset += truesize; 2020#endif 2021} 2022 2023static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2024 union ixgbe_adv_rx_desc *rx_desc, 2025 struct sk_buff **skb, 2026 const unsigned int size, 2027 int *rx_buffer_pgcnt) 2028{ 2029 struct ixgbe_rx_buffer *rx_buffer; 2030 2031 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2032 *rx_buffer_pgcnt = 2033#if (PAGE_SIZE < 8192) 2034 page_count(rx_buffer->page); 2035#else 2036 0; 2037#endif 2038 prefetchw(rx_buffer->page); 2039 *skb = rx_buffer->skb; 2040 2041 /* Delay unmapping of the first packet. It carries the header 2042 * information, HW may still access the header after the writeback. 2043 * Only unmap it when EOP is reached 2044 */ 2045 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2046 if (!*skb) 2047 goto skip_sync; 2048 } else { 2049 if (*skb) 2050 ixgbe_dma_sync_frag(rx_ring, *skb); 2051 } 2052 2053 /* we are reusing so sync this buffer for CPU use */ 2054 dma_sync_single_range_for_cpu(rx_ring->dev, 2055 rx_buffer->dma, 2056 rx_buffer->page_offset, 2057 size, 2058 DMA_FROM_DEVICE); 2059skip_sync: 2060 rx_buffer->pagecnt_bias--; 2061 2062 return rx_buffer; 2063} 2064 2065static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2066 struct ixgbe_rx_buffer *rx_buffer, 2067 struct sk_buff *skb, 2068 int rx_buffer_pgcnt) 2069{ 2070 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2071 /* hand second half of page back to the ring */ 2072 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2073 } else { 2074 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2075 /* the page has been released from the ring */ 2076 IXGBE_CB(skb)->page_released = true; 2077 } else { 2078 /* we are not reusing the buffer so unmap it */ 2079 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2080 ixgbe_rx_pg_size(rx_ring), 2081 DMA_FROM_DEVICE, 2082 IXGBE_RX_DMA_ATTR); 2083 } 2084 __page_frag_cache_drain(rx_buffer->page, 2085 rx_buffer->pagecnt_bias); 2086 } 2087 2088 /* clear contents of rx_buffer */ 2089 rx_buffer->page = NULL; 2090 rx_buffer->skb = NULL; 2091} 2092 2093static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2094 struct ixgbe_rx_buffer *rx_buffer, 2095 struct xdp_buff *xdp, 2096 union ixgbe_adv_rx_desc *rx_desc) 2097{ 2098 unsigned int size = xdp->data_end - xdp->data; 2099#if (PAGE_SIZE < 8192) 2100 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2101#else 2102 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2103 xdp->data_hard_start); 2104#endif 2105 struct sk_buff *skb; 2106 2107 /* prefetch first cache line of first page */ 2108 net_prefetch(xdp->data); 2109 2110 /* Note, we get here by enabling legacy-rx via: 2111 * 2112 * ethtool --set-priv-flags <dev> legacy-rx on 2113 * 2114 * In this mode, we currently get 0 extra XDP headroom as 2115 * opposed to having legacy-rx off, where we process XDP 2116 * packets going to stack via ixgbe_build_skb(). The latter 2117 * provides us currently with 192 bytes of headroom. 2118 * 2119 * For ixgbe_construct_skb() mode it means that the 2120 * xdp->data_meta will always point to xdp->data, since 2121 * the helper cannot expand the head. Should this ever 2122 * change in future for legacy-rx mode on, then lets also 2123 * add xdp->data_meta handling here. 2124 */ 2125 2126 /* allocate a skb to store the frags */ 2127 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2128 if (unlikely(!skb)) 2129 return NULL; 2130 2131 if (size > IXGBE_RX_HDR_SIZE) { 2132 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2133 IXGBE_CB(skb)->dma = rx_buffer->dma; 2134 2135 skb_add_rx_frag(skb, 0, rx_buffer->page, 2136 xdp->data - page_address(rx_buffer->page), 2137 size, truesize); 2138#if (PAGE_SIZE < 8192) 2139 rx_buffer->page_offset ^= truesize; 2140#else 2141 rx_buffer->page_offset += truesize; 2142#endif 2143 } else { 2144 memcpy(__skb_put(skb, size), 2145 xdp->data, ALIGN(size, sizeof(long))); 2146 rx_buffer->pagecnt_bias++; 2147 } 2148 2149 return skb; 2150} 2151 2152static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2153 struct ixgbe_rx_buffer *rx_buffer, 2154 struct xdp_buff *xdp, 2155 union ixgbe_adv_rx_desc *rx_desc) 2156{ 2157 unsigned int metasize = xdp->data - xdp->data_meta; 2158#if (PAGE_SIZE < 8192) 2159 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2160#else 2161 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2162 SKB_DATA_ALIGN(xdp->data_end - 2163 xdp->data_hard_start); 2164#endif 2165 struct sk_buff *skb; 2166 2167 /* Prefetch first cache line of first page. If xdp->data_meta 2168 * is unused, this points extactly as xdp->data, otherwise we 2169 * likely have a consumer accessing first few bytes of meta 2170 * data, and then actual data. 2171 */ 2172 net_prefetch(xdp->data_meta); 2173 2174 /* build an skb to around the page buffer */ 2175 skb = build_skb(xdp->data_hard_start, truesize); 2176 if (unlikely(!skb)) 2177 return NULL; 2178 2179 /* update pointers within the skb to store the data */ 2180 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2181 __skb_put(skb, xdp->data_end - xdp->data); 2182 if (metasize) 2183 skb_metadata_set(skb, metasize); 2184 2185 /* record DMA address if this is the start of a chain of buffers */ 2186 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2187 IXGBE_CB(skb)->dma = rx_buffer->dma; 2188 2189 /* update buffer offset */ 2190#if (PAGE_SIZE < 8192) 2191 rx_buffer->page_offset ^= truesize; 2192#else 2193 rx_buffer->page_offset += truesize; 2194#endif 2195 2196 return skb; 2197} 2198 2199static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2200 struct ixgbe_ring *rx_ring, 2201 struct xdp_buff *xdp) 2202{ 2203 int err, result = IXGBE_XDP_PASS; 2204 struct bpf_prog *xdp_prog; 2205 struct xdp_frame *xdpf; 2206 u32 act; 2207 2208 rcu_read_lock(); 2209 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2210 2211 if (!xdp_prog) 2212 goto xdp_out; 2213 2214 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2215 2216 act = bpf_prog_run_xdp(xdp_prog, xdp); 2217 switch (act) { 2218 case XDP_PASS: 2219 break; 2220 case XDP_TX: 2221 xdpf = xdp_convert_buff_to_frame(xdp); 2222 if (unlikely(!xdpf)) 2223 goto out_failure; 2224 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2225 if (result == IXGBE_XDP_CONSUMED) 2226 goto out_failure; 2227 break; 2228 case XDP_REDIRECT: 2229 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2230 if (err) 2231 goto out_failure; 2232 result = IXGBE_XDP_REDIR; 2233 break; 2234 default: 2235 bpf_warn_invalid_xdp_action(act); 2236 fallthrough; 2237 case XDP_ABORTED: 2238out_failure: 2239 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2240 fallthrough; /* handle aborts by dropping packet */ 2241 case XDP_DROP: 2242 result = IXGBE_XDP_CONSUMED; 2243 break; 2244 } 2245xdp_out: 2246 rcu_read_unlock(); 2247 return ERR_PTR(-result); 2248} 2249 2250static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2251 unsigned int size) 2252{ 2253 unsigned int truesize; 2254 2255#if (PAGE_SIZE < 8192) 2256 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2257#else 2258 truesize = ring_uses_build_skb(rx_ring) ? 2259 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) + 2260 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2261 SKB_DATA_ALIGN(size); 2262#endif 2263 return truesize; 2264} 2265 2266static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2267 struct ixgbe_rx_buffer *rx_buffer, 2268 unsigned int size) 2269{ 2270 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2271#if (PAGE_SIZE < 8192) 2272 rx_buffer->page_offset ^= truesize; 2273#else 2274 rx_buffer->page_offset += truesize; 2275#endif 2276} 2277 2278/** 2279 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2280 * @q_vector: structure containing interrupt and ring information 2281 * @rx_ring: rx descriptor ring to transact packets on 2282 * @budget: Total limit on number of packets to process 2283 * 2284 * This function provides a "bounce buffer" approach to Rx interrupt 2285 * processing. The advantage to this is that on systems that have 2286 * expensive overhead for IOMMU access this provides a means of avoiding 2287 * it by maintaining the mapping of the page to the syste. 2288 * 2289 * Returns amount of work completed 2290 **/ 2291static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2292 struct ixgbe_ring *rx_ring, 2293 const int budget) 2294{ 2295 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2296 struct ixgbe_adapter *adapter = q_vector->adapter; 2297#ifdef IXGBE_FCOE 2298 int ddp_bytes; 2299 unsigned int mss = 0; 2300#endif /* IXGBE_FCOE */ 2301 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2302 unsigned int xdp_xmit = 0; 2303 struct xdp_buff xdp; 2304 2305 xdp.rxq = &rx_ring->xdp_rxq; 2306 2307 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2308#if (PAGE_SIZE < 8192) 2309 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2310#endif 2311 2312 while (likely(total_rx_packets < budget)) { 2313 union ixgbe_adv_rx_desc *rx_desc; 2314 struct ixgbe_rx_buffer *rx_buffer; 2315 struct sk_buff *skb; 2316 int rx_buffer_pgcnt; 2317 unsigned int size; 2318 2319 /* return some buffers to hardware, one at a time is too slow */ 2320 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2321 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2322 cleaned_count = 0; 2323 } 2324 2325 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2326 size = le16_to_cpu(rx_desc->wb.upper.length); 2327 if (!size) 2328 break; 2329 2330 /* This memory barrier is needed to keep us from reading 2331 * any other fields out of the rx_desc until we know the 2332 * descriptor has been written back 2333 */ 2334 dma_rmb(); 2335 2336 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2337 2338 /* retrieve a buffer from the ring */ 2339 if (!skb) { 2340 xdp.data = page_address(rx_buffer->page) + 2341 rx_buffer->page_offset; 2342 xdp.data_meta = xdp.data; 2343 xdp.data_hard_start = xdp.data - 2344 ixgbe_rx_offset(rx_ring); 2345 xdp.data_end = xdp.data + size; 2346#if (PAGE_SIZE > 4096) 2347 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2348 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2349#endif 2350 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2351 } 2352 2353 if (IS_ERR(skb)) { 2354 unsigned int xdp_res = -PTR_ERR(skb); 2355 2356 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2357 xdp_xmit |= xdp_res; 2358 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2359 } else { 2360 rx_buffer->pagecnt_bias++; 2361 } 2362 total_rx_packets++; 2363 total_rx_bytes += size; 2364 } else if (skb) { 2365 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2366 } else if (ring_uses_build_skb(rx_ring)) { 2367 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2368 &xdp, rx_desc); 2369 } else { 2370 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2371 &xdp, rx_desc); 2372 } 2373 2374 /* exit if we failed to retrieve a buffer */ 2375 if (!skb) { 2376 rx_ring->rx_stats.alloc_rx_buff_failed++; 2377 rx_buffer->pagecnt_bias++; 2378 break; 2379 } 2380 2381 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2382 cleaned_count++; 2383 2384 /* place incomplete frames back on ring for completion */ 2385 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2386 continue; 2387 2388 /* verify the packet layout is correct */ 2389 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2390 continue; 2391 2392 /* probably a little skewed due to removing CRC */ 2393 total_rx_bytes += skb->len; 2394 2395 /* populate checksum, timestamp, VLAN, and protocol */ 2396 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2397 2398#ifdef IXGBE_FCOE 2399 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2400 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2401 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2402 /* include DDPed FCoE data */ 2403 if (ddp_bytes > 0) { 2404 if (!mss) { 2405 mss = rx_ring->netdev->mtu - 2406 sizeof(struct fcoe_hdr) - 2407 sizeof(struct fc_frame_header) - 2408 sizeof(struct fcoe_crc_eof); 2409 if (mss > 512) 2410 mss &= ~511; 2411 } 2412 total_rx_bytes += ddp_bytes; 2413 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2414 mss); 2415 } 2416 if (!ddp_bytes) { 2417 dev_kfree_skb_any(skb); 2418 continue; 2419 } 2420 } 2421 2422#endif /* IXGBE_FCOE */ 2423 ixgbe_rx_skb(q_vector, skb); 2424 2425 /* update budget accounting */ 2426 total_rx_packets++; 2427 } 2428 2429 if (xdp_xmit & IXGBE_XDP_REDIR) 2430 xdp_do_flush_map(); 2431 2432 if (xdp_xmit & IXGBE_XDP_TX) { 2433 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2434 2435 /* Force memory writes to complete before letting h/w 2436 * know there are new descriptors to fetch. 2437 */ 2438 wmb(); 2439 writel(ring->next_to_use, ring->tail); 2440 } 2441 2442 u64_stats_update_begin(&rx_ring->syncp); 2443 rx_ring->stats.packets += total_rx_packets; 2444 rx_ring->stats.bytes += total_rx_bytes; 2445 u64_stats_update_end(&rx_ring->syncp); 2446 q_vector->rx.total_packets += total_rx_packets; 2447 q_vector->rx.total_bytes += total_rx_bytes; 2448 2449 return total_rx_packets; 2450} 2451 2452/** 2453 * ixgbe_configure_msix - Configure MSI-X hardware 2454 * @adapter: board private structure 2455 * 2456 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2457 * interrupts. 2458 **/ 2459static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2460{ 2461 struct ixgbe_q_vector *q_vector; 2462 int v_idx; 2463 u32 mask; 2464 2465 /* Populate MSIX to EITR Select */ 2466 if (adapter->num_vfs > 32) { 2467 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2469 } 2470 2471 /* 2472 * Populate the IVAR table and set the ITR values to the 2473 * corresponding register. 2474 */ 2475 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2476 struct ixgbe_ring *ring; 2477 q_vector = adapter->q_vector[v_idx]; 2478 2479 ixgbe_for_each_ring(ring, q_vector->rx) 2480 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2481 2482 ixgbe_for_each_ring(ring, q_vector->tx) 2483 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2484 2485 ixgbe_write_eitr(q_vector); 2486 } 2487 2488 switch (adapter->hw.mac.type) { 2489 case ixgbe_mac_82598EB: 2490 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2491 v_idx); 2492 break; 2493 case ixgbe_mac_82599EB: 2494 case ixgbe_mac_X540: 2495 case ixgbe_mac_X550: 2496 case ixgbe_mac_X550EM_x: 2497 case ixgbe_mac_x550em_a: 2498 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2499 break; 2500 default: 2501 break; 2502 } 2503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2504 2505 /* set up to autoclear timer, and the vectors */ 2506 mask = IXGBE_EIMS_ENABLE_MASK; 2507 mask &= ~(IXGBE_EIMS_OTHER | 2508 IXGBE_EIMS_MAILBOX | 2509 IXGBE_EIMS_LSC); 2510 2511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2512} 2513 2514/** 2515 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2516 * @q_vector: structure containing interrupt and ring information 2517 * @ring_container: structure containing ring performance data 2518 * 2519 * Stores a new ITR value based on packets and byte 2520 * counts during the last interrupt. The advantage of per interrupt 2521 * computation is faster updates and more accurate ITR for the current 2522 * traffic pattern. Constants in this function were computed 2523 * based on theoretical maximum wire speed and thresholds were set based 2524 * on testing data as well as attempting to minimize response time 2525 * while increasing bulk throughput. 2526 **/ 2527static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2528 struct ixgbe_ring_container *ring_container) 2529{ 2530 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2531 IXGBE_ITR_ADAPTIVE_LATENCY; 2532 unsigned int avg_wire_size, packets, bytes; 2533 unsigned long next_update = jiffies; 2534 2535 /* If we don't have any rings just leave ourselves set for maximum 2536 * possible latency so we take ourselves out of the equation. 2537 */ 2538 if (!ring_container->ring) 2539 return; 2540 2541 /* If we didn't update within up to 1 - 2 jiffies we can assume 2542 * that either packets are coming in so slow there hasn't been 2543 * any work, or that there is so much work that NAPI is dealing 2544 * with interrupt moderation and we don't need to do anything. 2545 */ 2546 if (time_after(next_update, ring_container->next_update)) 2547 goto clear_counts; 2548 2549 packets = ring_container->total_packets; 2550 2551 /* We have no packets to actually measure against. This means 2552 * either one of the other queues on this vector is active or 2553 * we are a Tx queue doing TSO with too high of an interrupt rate. 2554 * 2555 * When this occurs just tick up our delay by the minimum value 2556 * and hope that this extra delay will prevent us from being called 2557 * without any work on our queue. 2558 */ 2559 if (!packets) { 2560 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2561 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2562 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2563 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2564 goto clear_counts; 2565 } 2566 2567 bytes = ring_container->total_bytes; 2568 2569 /* If packets are less than 4 or bytes are less than 9000 assume 2570 * insufficient data to use bulk rate limiting approach. We are 2571 * likely latency driven. 2572 */ 2573 if (packets < 4 && bytes < 9000) { 2574 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2575 goto adjust_by_size; 2576 } 2577 2578 /* Between 4 and 48 we can assume that our current interrupt delay 2579 * is only slightly too low. As such we should increase it by a small 2580 * fixed amount. 2581 */ 2582 if (packets < 48) { 2583 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2584 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2585 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2586 goto clear_counts; 2587 } 2588 2589 /* Between 48 and 96 is our "goldilocks" zone where we are working 2590 * out "just right". Just report that our current ITR is good for us. 2591 */ 2592 if (packets < 96) { 2593 itr = q_vector->itr >> 2; 2594 goto clear_counts; 2595 } 2596 2597 /* If packet count is 96 or greater we are likely looking at a slight 2598 * overrun of the delay we want. Try halving our delay to see if that 2599 * will cut the number of packets in half per interrupt. 2600 */ 2601 if (packets < 256) { 2602 itr = q_vector->itr >> 3; 2603 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2604 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2605 goto clear_counts; 2606 } 2607 2608 /* The paths below assume we are dealing with a bulk ITR since number 2609 * of packets is 256 or greater. We are just going to have to compute 2610 * a value and try to bring the count under control, though for smaller 2611 * packet sizes there isn't much we can do as NAPI polling will likely 2612 * be kicking in sooner rather than later. 2613 */ 2614 itr = IXGBE_ITR_ADAPTIVE_BULK; 2615 2616adjust_by_size: 2617 /* If packet counts are 256 or greater we can assume we have a gross 2618 * overestimation of what the rate should be. Instead of trying to fine 2619 * tune it just use the formula below to try and dial in an exact value 2620 * give the current packet size of the frame. 2621 */ 2622 avg_wire_size = bytes / packets; 2623 2624 /* The following is a crude approximation of: 2625 * wmem_default / (size + overhead) = desired_pkts_per_int 2626 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2627 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2628 * 2629 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2630 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2631 * formula down to 2632 * 2633 * (170 * (size + 24)) / (size + 640) = ITR 2634 * 2635 * We first do some math on the packet size and then finally bitshift 2636 * by 8 after rounding up. We also have to account for PCIe link speed 2637 * difference as ITR scales based on this. 2638 */ 2639 if (avg_wire_size <= 60) { 2640 /* Start at 50k ints/sec */ 2641 avg_wire_size = 5120; 2642 } else if (avg_wire_size <= 316) { 2643 /* 50K ints/sec to 16K ints/sec */ 2644 avg_wire_size *= 40; 2645 avg_wire_size += 2720; 2646 } else if (avg_wire_size <= 1084) { 2647 /* 16K ints/sec to 9.2K ints/sec */ 2648 avg_wire_size *= 15; 2649 avg_wire_size += 11452; 2650 } else if (avg_wire_size < 1968) { 2651 /* 9.2K ints/sec to 8K ints/sec */ 2652 avg_wire_size *= 5; 2653 avg_wire_size += 22420; 2654 } else { 2655 /* plateau at a limit of 8K ints/sec */ 2656 avg_wire_size = 32256; 2657 } 2658 2659 /* If we are in low latency mode half our delay which doubles the rate 2660 * to somewhere between 100K to 16K ints/sec 2661 */ 2662 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2663 avg_wire_size >>= 1; 2664 2665 /* Resultant value is 256 times larger than it needs to be. This 2666 * gives us room to adjust the value as needed to either increase 2667 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2668 * 2669 * Use addition as we have already recorded the new latency flag 2670 * for the ITR value. 2671 */ 2672 switch (q_vector->adapter->link_speed) { 2673 case IXGBE_LINK_SPEED_10GB_FULL: 2674 case IXGBE_LINK_SPEED_100_FULL: 2675 default: 2676 itr += DIV_ROUND_UP(avg_wire_size, 2677 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2678 IXGBE_ITR_ADAPTIVE_MIN_INC; 2679 break; 2680 case IXGBE_LINK_SPEED_2_5GB_FULL: 2681 case IXGBE_LINK_SPEED_1GB_FULL: 2682 case IXGBE_LINK_SPEED_10_FULL: 2683 if (avg_wire_size > 8064) 2684 avg_wire_size = 8064; 2685 itr += DIV_ROUND_UP(avg_wire_size, 2686 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2687 IXGBE_ITR_ADAPTIVE_MIN_INC; 2688 break; 2689 } 2690 2691clear_counts: 2692 /* write back value */ 2693 ring_container->itr = itr; 2694 2695 /* next update should occur within next jiffy */ 2696 ring_container->next_update = next_update + 1; 2697 2698 ring_container->total_bytes = 0; 2699 ring_container->total_packets = 0; 2700} 2701 2702/** 2703 * ixgbe_write_eitr - write EITR register in hardware specific way 2704 * @q_vector: structure containing interrupt and ring information 2705 * 2706 * This function is made to be called by ethtool and by the driver 2707 * when it needs to update EITR registers at runtime. Hardware 2708 * specific quirks/differences are taken care of here. 2709 */ 2710void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2711{ 2712 struct ixgbe_adapter *adapter = q_vector->adapter; 2713 struct ixgbe_hw *hw = &adapter->hw; 2714 int v_idx = q_vector->v_idx; 2715 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2716 2717 switch (adapter->hw.mac.type) { 2718 case ixgbe_mac_82598EB: 2719 /* must write high and low 16 bits to reset counter */ 2720 itr_reg |= (itr_reg << 16); 2721 break; 2722 case ixgbe_mac_82599EB: 2723 case ixgbe_mac_X540: 2724 case ixgbe_mac_X550: 2725 case ixgbe_mac_X550EM_x: 2726 case ixgbe_mac_x550em_a: 2727 /* 2728 * set the WDIS bit to not clear the timer bits and cause an 2729 * immediate assertion of the interrupt 2730 */ 2731 itr_reg |= IXGBE_EITR_CNT_WDIS; 2732 break; 2733 default: 2734 break; 2735 } 2736 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2737} 2738 2739static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2740{ 2741 u32 new_itr; 2742 2743 ixgbe_update_itr(q_vector, &q_vector->tx); 2744 ixgbe_update_itr(q_vector, &q_vector->rx); 2745 2746 /* use the smallest value of new ITR delay calculations */ 2747 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2748 2749 /* Clear latency flag if set, shift into correct position */ 2750 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2751 new_itr <<= 2; 2752 2753 if (new_itr != q_vector->itr) { 2754 /* save the algorithm value here */ 2755 q_vector->itr = new_itr; 2756 2757 ixgbe_write_eitr(q_vector); 2758 } 2759} 2760 2761/** 2762 * ixgbe_check_overtemp_subtask - check for over temperature 2763 * @adapter: pointer to adapter 2764 **/ 2765static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2766{ 2767 struct ixgbe_hw *hw = &adapter->hw; 2768 u32 eicr = adapter->interrupt_event; 2769 2770 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2771 return; 2772 2773 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2774 return; 2775 2776 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2777 2778 switch (hw->device_id) { 2779 case IXGBE_DEV_ID_82599_T3_LOM: 2780 /* 2781 * Since the warning interrupt is for both ports 2782 * we don't have to check if: 2783 * - This interrupt wasn't for our port. 2784 * - We may have missed the interrupt so always have to 2785 * check if we got a LSC 2786 */ 2787 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2788 !(eicr & IXGBE_EICR_LSC)) 2789 return; 2790 2791 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2792 u32 speed; 2793 bool link_up = false; 2794 2795 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2796 2797 if (link_up) 2798 return; 2799 } 2800 2801 /* Check if this is not due to overtemp */ 2802 if (!hw->phy.ops.check_overtemp(hw)) 2803 return; 2804 2805 break; 2806 case IXGBE_DEV_ID_X550EM_A_1G_T: 2807 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2808 if (!hw->phy.ops.check_overtemp(hw)) 2809 return; 2810 break; 2811 default: 2812 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2813 return; 2814 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2815 return; 2816 break; 2817 } 2818 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2819 2820 adapter->interrupt_event = 0; 2821} 2822 2823static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2824{ 2825 struct ixgbe_hw *hw = &adapter->hw; 2826 2827 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2828 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2829 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2830 /* write to clear the interrupt */ 2831 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2832 } 2833} 2834 2835static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2836{ 2837 struct ixgbe_hw *hw = &adapter->hw; 2838 2839 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2840 return; 2841 2842 switch (adapter->hw.mac.type) { 2843 case ixgbe_mac_82599EB: 2844 /* 2845 * Need to check link state so complete overtemp check 2846 * on service task 2847 */ 2848 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2849 (eicr & IXGBE_EICR_LSC)) && 2850 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2851 adapter->interrupt_event = eicr; 2852 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2853 ixgbe_service_event_schedule(adapter); 2854 return; 2855 } 2856 return; 2857 case ixgbe_mac_x550em_a: 2858 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2859 adapter->interrupt_event = eicr; 2860 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2861 ixgbe_service_event_schedule(adapter); 2862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2863 IXGBE_EICR_GPI_SDP0_X550EM_a); 2864 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2865 IXGBE_EICR_GPI_SDP0_X550EM_a); 2866 } 2867 return; 2868 case ixgbe_mac_X550: 2869 case ixgbe_mac_X540: 2870 if (!(eicr & IXGBE_EICR_TS)) 2871 return; 2872 break; 2873 default: 2874 return; 2875 } 2876 2877 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2878} 2879 2880static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2881{ 2882 switch (hw->mac.type) { 2883 case ixgbe_mac_82598EB: 2884 if (hw->phy.type == ixgbe_phy_nl) 2885 return true; 2886 return false; 2887 case ixgbe_mac_82599EB: 2888 case ixgbe_mac_X550EM_x: 2889 case ixgbe_mac_x550em_a: 2890 switch (hw->mac.ops.get_media_type(hw)) { 2891 case ixgbe_media_type_fiber: 2892 case ixgbe_media_type_fiber_qsfp: 2893 return true; 2894 default: 2895 return false; 2896 } 2897 default: 2898 return false; 2899 } 2900} 2901 2902static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2903{ 2904 struct ixgbe_hw *hw = &adapter->hw; 2905 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2906 2907 if (!ixgbe_is_sfp(hw)) 2908 return; 2909 2910 /* Later MAC's use different SDP */ 2911 if (hw->mac.type >= ixgbe_mac_X540) 2912 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2913 2914 if (eicr & eicr_mask) { 2915 /* Clear the interrupt */ 2916 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2917 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2918 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2919 adapter->sfp_poll_time = 0; 2920 ixgbe_service_event_schedule(adapter); 2921 } 2922 } 2923 2924 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2925 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2926 /* Clear the interrupt */ 2927 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2928 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2929 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2930 ixgbe_service_event_schedule(adapter); 2931 } 2932 } 2933} 2934 2935static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2936{ 2937 struct ixgbe_hw *hw = &adapter->hw; 2938 2939 adapter->lsc_int++; 2940 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2941 adapter->link_check_timeout = jiffies; 2942 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2943 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2944 IXGBE_WRITE_FLUSH(hw); 2945 ixgbe_service_event_schedule(adapter); 2946 } 2947} 2948 2949static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2950 u64 qmask) 2951{ 2952 u32 mask; 2953 struct ixgbe_hw *hw = &adapter->hw; 2954 2955 switch (hw->mac.type) { 2956 case ixgbe_mac_82598EB: 2957 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2958 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2959 break; 2960 case ixgbe_mac_82599EB: 2961 case ixgbe_mac_X540: 2962 case ixgbe_mac_X550: 2963 case ixgbe_mac_X550EM_x: 2964 case ixgbe_mac_x550em_a: 2965 mask = (qmask & 0xFFFFFFFF); 2966 if (mask) 2967 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2968 mask = (qmask >> 32); 2969 if (mask) 2970 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2971 break; 2972 default: 2973 break; 2974 } 2975 /* skip the flush */ 2976} 2977 2978/** 2979 * ixgbe_irq_enable - Enable default interrupt generation settings 2980 * @adapter: board private structure 2981 * @queues: enable irqs for queues 2982 * @flush: flush register write 2983 **/ 2984static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2985 bool flush) 2986{ 2987 struct ixgbe_hw *hw = &adapter->hw; 2988 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2989 2990 /* don't reenable LSC while waiting for link */ 2991 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2992 mask &= ~IXGBE_EIMS_LSC; 2993 2994 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2995 switch (adapter->hw.mac.type) { 2996 case ixgbe_mac_82599EB: 2997 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2998 break; 2999 case ixgbe_mac_X540: 3000 case ixgbe_mac_X550: 3001 case ixgbe_mac_X550EM_x: 3002 case ixgbe_mac_x550em_a: 3003 mask |= IXGBE_EIMS_TS; 3004 break; 3005 default: 3006 break; 3007 } 3008 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3009 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3010 switch (adapter->hw.mac.type) { 3011 case ixgbe_mac_82599EB: 3012 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3013 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3014 fallthrough; 3015 case ixgbe_mac_X540: 3016 case ixgbe_mac_X550: 3017 case ixgbe_mac_X550EM_x: 3018 case ixgbe_mac_x550em_a: 3019 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3020 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3021 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3022 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3023 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3024 mask |= IXGBE_EICR_GPI_SDP0_X540; 3025 mask |= IXGBE_EIMS_ECC; 3026 mask |= IXGBE_EIMS_MAILBOX; 3027 break; 3028 default: 3029 break; 3030 } 3031 3032 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3033 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3034 mask |= IXGBE_EIMS_FLOW_DIR; 3035 3036 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3037 if (queues) 3038 ixgbe_irq_enable_queues(adapter, ~0); 3039 if (flush) 3040 IXGBE_WRITE_FLUSH(&adapter->hw); 3041} 3042 3043static irqreturn_t ixgbe_msix_other(int irq, void *data) 3044{ 3045 struct ixgbe_adapter *adapter = data; 3046 struct ixgbe_hw *hw = &adapter->hw; 3047 u32 eicr; 3048 3049 /* 3050 * Workaround for Silicon errata. Use clear-by-write instead 3051 * of clear-by-read. Reading with EICS will return the 3052 * interrupt causes without clearing, which later be done 3053 * with the write to EICR. 3054 */ 3055 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3056 3057 /* The lower 16bits of the EICR register are for the queue interrupts 3058 * which should be masked here in order to not accidentally clear them if 3059 * the bits are high when ixgbe_msix_other is called. There is a race 3060 * condition otherwise which results in possible performance loss 3061 * especially if the ixgbe_msix_other interrupt is triggering 3062 * consistently (as it would when PPS is turned on for the X540 device) 3063 */ 3064 eicr &= 0xFFFF0000; 3065 3066 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3067 3068 if (eicr & IXGBE_EICR_LSC) 3069 ixgbe_check_lsc(adapter); 3070 3071 if (eicr & IXGBE_EICR_MAILBOX) 3072 ixgbe_msg_task(adapter); 3073 3074 switch (hw->mac.type) { 3075 case ixgbe_mac_82599EB: 3076 case ixgbe_mac_X540: 3077 case ixgbe_mac_X550: 3078 case ixgbe_mac_X550EM_x: 3079 case ixgbe_mac_x550em_a: 3080 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3081 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3082 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3083 ixgbe_service_event_schedule(adapter); 3084 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3085 IXGBE_EICR_GPI_SDP0_X540); 3086 } 3087 if (eicr & IXGBE_EICR_ECC) { 3088 e_info(link, "Received ECC Err, initiating reset\n"); 3089 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3090 ixgbe_service_event_schedule(adapter); 3091 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3092 } 3093 /* Handle Flow Director Full threshold interrupt */ 3094 if (eicr & IXGBE_EICR_FLOW_DIR) { 3095 int reinit_count = 0; 3096 int i; 3097 for (i = 0; i < adapter->num_tx_queues; i++) { 3098 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3099 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3100 &ring->state)) 3101 reinit_count++; 3102 } 3103 if (reinit_count) { 3104 /* no more flow director interrupts until after init */ 3105 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3106 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3107 ixgbe_service_event_schedule(adapter); 3108 } 3109 } 3110 ixgbe_check_sfp_event(adapter, eicr); 3111 ixgbe_check_overtemp_event(adapter, eicr); 3112 break; 3113 default: 3114 break; 3115 } 3116 3117 ixgbe_check_fan_failure(adapter, eicr); 3118 3119 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3120 ixgbe_ptp_check_pps_event(adapter); 3121 3122 /* re-enable the original interrupt state, no lsc, no queues */ 3123 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3124 ixgbe_irq_enable(adapter, false, false); 3125 3126 return IRQ_HANDLED; 3127} 3128 3129static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3130{ 3131 struct ixgbe_q_vector *q_vector = data; 3132 3133 /* EIAM disabled interrupts (on this vector) for us */ 3134 3135 if (q_vector->rx.ring || q_vector->tx.ring) 3136 napi_schedule_irqoff(&q_vector->napi); 3137 3138 return IRQ_HANDLED; 3139} 3140 3141/** 3142 * ixgbe_poll - NAPI Rx polling callback 3143 * @napi: structure for representing this polling device 3144 * @budget: how many packets driver is allowed to clean 3145 * 3146 * This function is used for legacy and MSI, NAPI mode 3147 **/ 3148int ixgbe_poll(struct napi_struct *napi, int budget) 3149{ 3150 struct ixgbe_q_vector *q_vector = 3151 container_of(napi, struct ixgbe_q_vector, napi); 3152 struct ixgbe_adapter *adapter = q_vector->adapter; 3153 struct ixgbe_ring *ring; 3154 int per_ring_budget, work_done = 0; 3155 bool clean_complete = true; 3156 3157#ifdef CONFIG_IXGBE_DCA 3158 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3159 ixgbe_update_dca(q_vector); 3160#endif 3161 3162 ixgbe_for_each_ring(ring, q_vector->tx) { 3163 bool wd = ring->xsk_pool ? 3164 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3165 ixgbe_clean_tx_irq(q_vector, ring, budget); 3166 3167 if (!wd) 3168 clean_complete = false; 3169 } 3170 3171 /* Exit if we are called by netpoll */ 3172 if (budget <= 0) 3173 return budget; 3174 3175 /* attempt to distribute budget to each queue fairly, but don't allow 3176 * the budget to go below 1 because we'll exit polling */ 3177 if (q_vector->rx.count > 1) 3178 per_ring_budget = max(budget/q_vector->rx.count, 1); 3179 else 3180 per_ring_budget = budget; 3181 3182 ixgbe_for_each_ring(ring, q_vector->rx) { 3183 int cleaned = ring->xsk_pool ? 3184 ixgbe_clean_rx_irq_zc(q_vector, ring, 3185 per_ring_budget) : 3186 ixgbe_clean_rx_irq(q_vector, ring, 3187 per_ring_budget); 3188 3189 work_done += cleaned; 3190 if (cleaned >= per_ring_budget) 3191 clean_complete = false; 3192 } 3193 3194 /* If all work not completed, return budget and keep polling */ 3195 if (!clean_complete) 3196 return budget; 3197 3198 /* all work done, exit the polling mode */ 3199 if (likely(napi_complete_done(napi, work_done))) { 3200 if (adapter->rx_itr_setting & 1) 3201 ixgbe_set_itr(q_vector); 3202 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3203 ixgbe_irq_enable_queues(adapter, 3204 BIT_ULL(q_vector->v_idx)); 3205 } 3206 3207 return min(work_done, budget - 1); 3208} 3209 3210/** 3211 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3212 * @adapter: board private structure 3213 * 3214 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3215 * interrupts from the kernel. 3216 **/ 3217static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3218{ 3219 struct net_device *netdev = adapter->netdev; 3220 unsigned int ri = 0, ti = 0; 3221 int vector, err; 3222 3223 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3224 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3225 struct msix_entry *entry = &adapter->msix_entries[vector]; 3226 3227 if (q_vector->tx.ring && q_vector->rx.ring) { 3228 snprintf(q_vector->name, sizeof(q_vector->name), 3229 "%s-TxRx-%u", netdev->name, ri++); 3230 ti++; 3231 } else if (q_vector->rx.ring) { 3232 snprintf(q_vector->name, sizeof(q_vector->name), 3233 "%s-rx-%u", netdev->name, ri++); 3234 } else if (q_vector->tx.ring) { 3235 snprintf(q_vector->name, sizeof(q_vector->name), 3236 "%s-tx-%u", netdev->name, ti++); 3237 } else { 3238 /* skip this unused q_vector */ 3239 continue; 3240 } 3241 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3242 q_vector->name, q_vector); 3243 if (err) { 3244 e_err(probe, "request_irq failed for MSIX interrupt " 3245 "Error: %d\n", err); 3246 goto free_queue_irqs; 3247 } 3248 /* If Flow Director is enabled, set interrupt affinity */ 3249 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3250 /* assign the mask for this irq */ 3251 irq_set_affinity_hint(entry->vector, 3252 &q_vector->affinity_mask); 3253 } 3254 } 3255 3256 err = request_irq(adapter->msix_entries[vector].vector, 3257 ixgbe_msix_other, 0, netdev->name, adapter); 3258 if (err) { 3259 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3260 goto free_queue_irqs; 3261 } 3262 3263 return 0; 3264 3265free_queue_irqs: 3266 while (vector) { 3267 vector--; 3268 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3269 NULL); 3270 free_irq(adapter->msix_entries[vector].vector, 3271 adapter->q_vector[vector]); 3272 } 3273 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3274 pci_disable_msix(adapter->pdev); 3275 kfree(adapter->msix_entries); 3276 adapter->msix_entries = NULL; 3277 return err; 3278} 3279 3280/** 3281 * ixgbe_intr - legacy mode Interrupt Handler 3282 * @irq: interrupt number 3283 * @data: pointer to a network interface device structure 3284 **/ 3285static irqreturn_t ixgbe_intr(int irq, void *data) 3286{ 3287 struct ixgbe_adapter *adapter = data; 3288 struct ixgbe_hw *hw = &adapter->hw; 3289 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3290 u32 eicr; 3291 3292 /* 3293 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3294 * before the read of EICR. 3295 */ 3296 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3297 3298 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3299 * therefore no explicit interrupt disable is necessary */ 3300 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3301 if (!eicr) { 3302 /* 3303 * shared interrupt alert! 3304 * make sure interrupts are enabled because the read will 3305 * have disabled interrupts due to EIAM 3306 * finish the workaround of silicon errata on 82598. Unmask 3307 * the interrupt that we masked before the EICR read. 3308 */ 3309 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3310 ixgbe_irq_enable(adapter, true, true); 3311 return IRQ_NONE; /* Not our interrupt */ 3312 } 3313 3314 if (eicr & IXGBE_EICR_LSC) 3315 ixgbe_check_lsc(adapter); 3316 3317 switch (hw->mac.type) { 3318 case ixgbe_mac_82599EB: 3319 ixgbe_check_sfp_event(adapter, eicr); 3320 fallthrough; 3321 case ixgbe_mac_X540: 3322 case ixgbe_mac_X550: 3323 case ixgbe_mac_X550EM_x: 3324 case ixgbe_mac_x550em_a: 3325 if (eicr & IXGBE_EICR_ECC) { 3326 e_info(link, "Received ECC Err, initiating reset\n"); 3327 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3328 ixgbe_service_event_schedule(adapter); 3329 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3330 } 3331 ixgbe_check_overtemp_event(adapter, eicr); 3332 break; 3333 default: 3334 break; 3335 } 3336 3337 ixgbe_check_fan_failure(adapter, eicr); 3338 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3339 ixgbe_ptp_check_pps_event(adapter); 3340 3341 /* would disable interrupts here but EIAM disabled it */ 3342 napi_schedule_irqoff(&q_vector->napi); 3343 3344 /* 3345 * re-enable link(maybe) and non-queue interrupts, no flush. 3346 * ixgbe_poll will re-enable the queue interrupts 3347 */ 3348 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3349 ixgbe_irq_enable(adapter, false, false); 3350 3351 return IRQ_HANDLED; 3352} 3353 3354/** 3355 * ixgbe_request_irq - initialize interrupts 3356 * @adapter: board private structure 3357 * 3358 * Attempts to configure interrupts using the best available 3359 * capabilities of the hardware and kernel. 3360 **/ 3361static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3362{ 3363 struct net_device *netdev = adapter->netdev; 3364 int err; 3365 3366 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3367 err = ixgbe_request_msix_irqs(adapter); 3368 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3369 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3370 netdev->name, adapter); 3371 else 3372 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3373 netdev->name, adapter); 3374 3375 if (err) 3376 e_err(probe, "request_irq failed, Error %d\n", err); 3377 3378 return err; 3379} 3380 3381static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3382{ 3383 int vector; 3384 3385 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3386 free_irq(adapter->pdev->irq, adapter); 3387 return; 3388 } 3389 3390 if (!adapter->msix_entries) 3391 return; 3392 3393 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3394 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3395 struct msix_entry *entry = &adapter->msix_entries[vector]; 3396 3397 /* free only the irqs that were actually requested */ 3398 if (!q_vector->rx.ring && !q_vector->tx.ring) 3399 continue; 3400 3401 /* clear the affinity_mask in the IRQ descriptor */ 3402 irq_set_affinity_hint(entry->vector, NULL); 3403 3404 free_irq(entry->vector, q_vector); 3405 } 3406 3407 free_irq(adapter->msix_entries[vector].vector, adapter); 3408} 3409 3410/** 3411 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3412 * @adapter: board private structure 3413 **/ 3414static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3415{ 3416 switch (adapter->hw.mac.type) { 3417 case ixgbe_mac_82598EB: 3418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3419 break; 3420 case ixgbe_mac_82599EB: 3421 case ixgbe_mac_X540: 3422 case ixgbe_mac_X550: 3423 case ixgbe_mac_X550EM_x: 3424 case ixgbe_mac_x550em_a: 3425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3428 break; 3429 default: 3430 break; 3431 } 3432 IXGBE_WRITE_FLUSH(&adapter->hw); 3433 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3434 int vector; 3435 3436 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3437 synchronize_irq(adapter->msix_entries[vector].vector); 3438 3439 synchronize_irq(adapter->msix_entries[vector++].vector); 3440 } else { 3441 synchronize_irq(adapter->pdev->irq); 3442 } 3443} 3444 3445/** 3446 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3447 * @adapter: board private structure 3448 * 3449 **/ 3450static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3451{ 3452 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3453 3454 ixgbe_write_eitr(q_vector); 3455 3456 ixgbe_set_ivar(adapter, 0, 0, 0); 3457 ixgbe_set_ivar(adapter, 1, 0, 0); 3458 3459 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3460} 3461 3462/** 3463 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3464 * @adapter: board private structure 3465 * @ring: structure containing ring specific data 3466 * 3467 * Configure the Tx descriptor ring after a reset. 3468 **/ 3469void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3470 struct ixgbe_ring *ring) 3471{ 3472 struct ixgbe_hw *hw = &adapter->hw; 3473 u64 tdba = ring->dma; 3474 int wait_loop = 10; 3475 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3476 u8 reg_idx = ring->reg_idx; 3477 3478 ring->xsk_pool = NULL; 3479 if (ring_is_xdp(ring)) 3480 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3481 3482 /* disable queue to avoid issues while updating state */ 3483 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3484 IXGBE_WRITE_FLUSH(hw); 3485 3486 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3487 (tdba & DMA_BIT_MASK(32))); 3488 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3489 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3490 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3491 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3492 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3493 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3494 3495 /* 3496 * set WTHRESH to encourage burst writeback, it should not be set 3497 * higher than 1 when: 3498 * - ITR is 0 as it could cause false TX hangs 3499 * - ITR is set to > 100k int/sec and BQL is enabled 3500 * 3501 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3502 * to or less than the number of on chip descriptors, which is 3503 * currently 40. 3504 */ 3505 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3506 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3507 else 3508 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3509 3510 /* 3511 * Setting PTHRESH to 32 both improves performance 3512 * and avoids a TX hang with DFP enabled 3513 */ 3514 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3515 32; /* PTHRESH = 32 */ 3516 3517 /* reinitialize flowdirector state */ 3518 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3519 ring->atr_sample_rate = adapter->atr_sample_rate; 3520 ring->atr_count = 0; 3521 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3522 } else { 3523 ring->atr_sample_rate = 0; 3524 } 3525 3526 /* initialize XPS */ 3527 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3528 struct ixgbe_q_vector *q_vector = ring->q_vector; 3529 3530 if (q_vector) 3531 netif_set_xps_queue(ring->netdev, 3532 &q_vector->affinity_mask, 3533 ring->queue_index); 3534 } 3535 3536 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3537 3538 /* reinitialize tx_buffer_info */ 3539 memset(ring->tx_buffer_info, 0, 3540 sizeof(struct ixgbe_tx_buffer) * ring->count); 3541 3542 /* enable queue */ 3543 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3544 3545 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3546 if (hw->mac.type == ixgbe_mac_82598EB && 3547 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3548 return; 3549 3550 /* poll to verify queue is enabled */ 3551 do { 3552 usleep_range(1000, 2000); 3553 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3554 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3555 if (!wait_loop) 3556 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3557} 3558 3559static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3560{ 3561 struct ixgbe_hw *hw = &adapter->hw; 3562 u32 rttdcs, mtqc; 3563 u8 tcs = adapter->hw_tcs; 3564 3565 if (hw->mac.type == ixgbe_mac_82598EB) 3566 return; 3567 3568 /* disable the arbiter while setting MTQC */ 3569 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3570 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3571 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3572 3573 /* set transmit pool layout */ 3574 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3575 mtqc = IXGBE_MTQC_VT_ENA; 3576 if (tcs > 4) 3577 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3578 else if (tcs > 1) 3579 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3580 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3581 IXGBE_82599_VMDQ_4Q_MASK) 3582 mtqc |= IXGBE_MTQC_32VF; 3583 else 3584 mtqc |= IXGBE_MTQC_64VF; 3585 } else { 3586 if (tcs > 4) { 3587 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3588 } else if (tcs > 1) { 3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3590 } else { 3591 u8 max_txq = adapter->num_tx_queues + 3592 adapter->num_xdp_queues; 3593 if (max_txq > 63) 3594 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3595 else 3596 mtqc = IXGBE_MTQC_64Q_1PB; 3597 } 3598 } 3599 3600 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3601 3602 /* Enable Security TX Buffer IFG for multiple pb */ 3603 if (tcs) { 3604 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3605 sectx |= IXGBE_SECTX_DCB; 3606 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3607 } 3608 3609 /* re-enable the arbiter */ 3610 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3611 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3612} 3613 3614/** 3615 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3616 * @adapter: board private structure 3617 * 3618 * Configure the Tx unit of the MAC after a reset. 3619 **/ 3620static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3621{ 3622 struct ixgbe_hw *hw = &adapter->hw; 3623 u32 dmatxctl; 3624 u32 i; 3625 3626 ixgbe_setup_mtqc(adapter); 3627 3628 if (hw->mac.type != ixgbe_mac_82598EB) { 3629 /* DMATXCTL.EN must be before Tx queues are enabled */ 3630 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3631 dmatxctl |= IXGBE_DMATXCTL_TE; 3632 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3633 } 3634 3635 /* Setup the HW Tx Head and Tail descriptor pointers */ 3636 for (i = 0; i < adapter->num_tx_queues; i++) 3637 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3638 for (i = 0; i < adapter->num_xdp_queues; i++) 3639 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3640} 3641 3642static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3643 struct ixgbe_ring *ring) 3644{ 3645 struct ixgbe_hw *hw = &adapter->hw; 3646 u8 reg_idx = ring->reg_idx; 3647 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3648 3649 srrctl |= IXGBE_SRRCTL_DROP_EN; 3650 3651 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3652} 3653 3654static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3655 struct ixgbe_ring *ring) 3656{ 3657 struct ixgbe_hw *hw = &adapter->hw; 3658 u8 reg_idx = ring->reg_idx; 3659 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3660 3661 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3662 3663 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3664} 3665 3666#ifdef CONFIG_IXGBE_DCB 3667void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3668#else 3669static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3670#endif 3671{ 3672 int i; 3673 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3674 3675 if (adapter->ixgbe_ieee_pfc) 3676 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3677 3678 /* 3679 * We should set the drop enable bit if: 3680 * SR-IOV is enabled 3681 * or 3682 * Number of Rx queues > 1 and flow control is disabled 3683 * 3684 * This allows us to avoid head of line blocking for security 3685 * and performance reasons. 3686 */ 3687 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3688 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3689 for (i = 0; i < adapter->num_rx_queues; i++) 3690 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3691 } else { 3692 for (i = 0; i < adapter->num_rx_queues; i++) 3693 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3694 } 3695} 3696 3697#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3698 3699static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3700 struct ixgbe_ring *rx_ring) 3701{ 3702 struct ixgbe_hw *hw = &adapter->hw; 3703 u32 srrctl; 3704 u8 reg_idx = rx_ring->reg_idx; 3705 3706 if (hw->mac.type == ixgbe_mac_82598EB) { 3707 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3708 3709 /* 3710 * if VMDq is not active we must program one srrctl register 3711 * per RSS queue since we have enabled RDRXCTL.MVMEN 3712 */ 3713 reg_idx &= mask; 3714 } 3715 3716 /* configure header buffer length, needed for RSC */ 3717 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3718 3719 /* configure the packet buffer length */ 3720 if (rx_ring->xsk_pool) { 3721 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3722 3723 /* If the MAC support setting RXDCTL.RLPML, the 3724 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3725 * RXDCTL.RLPML is set to the actual UMEM buffer 3726 * size. If not, then we are stuck with a 1k buffer 3727 * size resolution. In this case frames larger than 3728 * the UMEM buffer size viewed in a 1k resolution will 3729 * be dropped. 3730 */ 3731 if (hw->mac.type != ixgbe_mac_82599EB) 3732 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3733 else 3734 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3735 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3736 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3737 } else { 3738 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3739 } 3740 3741 /* configure descriptor type */ 3742 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3743 3744 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3745} 3746 3747/** 3748 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3749 * @adapter: device handle 3750 * 3751 * - 82598/82599/X540: 128 3752 * - X550(non-SRIOV mode): 512 3753 * - X550(SRIOV mode): 64 3754 */ 3755u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3756{ 3757 if (adapter->hw.mac.type < ixgbe_mac_X550) 3758 return 128; 3759 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3760 return 64; 3761 else 3762 return 512; 3763} 3764 3765/** 3766 * ixgbe_store_key - Write the RSS key to HW 3767 * @adapter: device handle 3768 * 3769 * Write the RSS key stored in adapter.rss_key to HW. 3770 */ 3771void ixgbe_store_key(struct ixgbe_adapter *adapter) 3772{ 3773 struct ixgbe_hw *hw = &adapter->hw; 3774 int i; 3775 3776 for (i = 0; i < 10; i++) 3777 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3778} 3779 3780/** 3781 * ixgbe_init_rss_key - Initialize adapter RSS key 3782 * @adapter: device handle 3783 * 3784 * Allocates and initializes the RSS key if it is not allocated. 3785 **/ 3786static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3787{ 3788 u32 *rss_key; 3789 3790 if (!adapter->rss_key) { 3791 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3792 if (unlikely(!rss_key)) 3793 return -ENOMEM; 3794 3795 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3796 adapter->rss_key = rss_key; 3797 } 3798 3799 return 0; 3800} 3801 3802/** 3803 * ixgbe_store_reta - Write the RETA table to HW 3804 * @adapter: device handle 3805 * 3806 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3807 */ 3808void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3809{ 3810 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3811 struct ixgbe_hw *hw = &adapter->hw; 3812 u32 reta = 0; 3813 u32 indices_multi; 3814 u8 *indir_tbl = adapter->rss_indir_tbl; 3815 3816 /* Fill out the redirection table as follows: 3817 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3818 * indices. 3819 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3820 * - X550: 8 bit wide entries containing 6 bit RSS index 3821 */ 3822 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3823 indices_multi = 0x11; 3824 else 3825 indices_multi = 0x1; 3826 3827 /* Write redirection table to HW */ 3828 for (i = 0; i < reta_entries; i++) { 3829 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3830 if ((i & 3) == 3) { 3831 if (i < 128) 3832 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3833 else 3834 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3835 reta); 3836 reta = 0; 3837 } 3838 } 3839} 3840 3841/** 3842 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3843 * @adapter: device handle 3844 * 3845 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3846 */ 3847static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3848{ 3849 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3850 struct ixgbe_hw *hw = &adapter->hw; 3851 u32 vfreta = 0; 3852 3853 /* Write redirection table to HW */ 3854 for (i = 0; i < reta_entries; i++) { 3855 u16 pool = adapter->num_rx_pools; 3856 3857 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3858 if ((i & 3) != 3) 3859 continue; 3860 3861 while (pool--) 3862 IXGBE_WRITE_REG(hw, 3863 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3864 vfreta); 3865 vfreta = 0; 3866 } 3867} 3868 3869static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3870{ 3871 u32 i, j; 3872 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3873 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3874 3875 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3876 * make full use of any rings they may have. We will use the 3877 * PSRTYPE register to control how many rings we use within the PF. 3878 */ 3879 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3880 rss_i = 4; 3881 3882 /* Fill out hash function seeds */ 3883 ixgbe_store_key(adapter); 3884 3885 /* Fill out redirection table */ 3886 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3887 3888 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3889 if (j == rss_i) 3890 j = 0; 3891 3892 adapter->rss_indir_tbl[i] = j; 3893 } 3894 3895 ixgbe_store_reta(adapter); 3896} 3897 3898static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3899{ 3900 struct ixgbe_hw *hw = &adapter->hw; 3901 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3902 int i, j; 3903 3904 /* Fill out hash function seeds */ 3905 for (i = 0; i < 10; i++) { 3906 u16 pool = adapter->num_rx_pools; 3907 3908 while (pool--) 3909 IXGBE_WRITE_REG(hw, 3910 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3911 *(adapter->rss_key + i)); 3912 } 3913 3914 /* Fill out the redirection table */ 3915 for (i = 0, j = 0; i < 64; i++, j++) { 3916 if (j == rss_i) 3917 j = 0; 3918 3919 adapter->rss_indir_tbl[i] = j; 3920 } 3921 3922 ixgbe_store_vfreta(adapter); 3923} 3924 3925static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3926{ 3927 struct ixgbe_hw *hw = &adapter->hw; 3928 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3929 u32 rxcsum; 3930 3931 /* Disable indicating checksum in descriptor, enables RSS hash */ 3932 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3933 rxcsum |= IXGBE_RXCSUM_PCSD; 3934 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3935 3936 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3937 if (adapter->ring_feature[RING_F_RSS].mask) 3938 mrqc = IXGBE_MRQC_RSSEN; 3939 } else { 3940 u8 tcs = adapter->hw_tcs; 3941 3942 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3943 if (tcs > 4) 3944 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3945 else if (tcs > 1) 3946 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3947 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3948 IXGBE_82599_VMDQ_4Q_MASK) 3949 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3950 else 3951 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3952 3953 /* Enable L3/L4 for Tx Switched packets only for X550, 3954 * older devices do not support this feature 3955 */ 3956 if (hw->mac.type >= ixgbe_mac_X550) 3957 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3958 } else { 3959 if (tcs > 4) 3960 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3961 else if (tcs > 1) 3962 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3963 else 3964 mrqc = IXGBE_MRQC_RSSEN; 3965 } 3966 } 3967 3968 /* Perform hash on these packet types */ 3969 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3970 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3971 IXGBE_MRQC_RSS_FIELD_IPV6 | 3972 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3973 3974 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3975 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3976 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3977 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3978 3979 if ((hw->mac.type >= ixgbe_mac_X550) && 3980 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3981 u16 pool = adapter->num_rx_pools; 3982 3983 /* Enable VF RSS mode */ 3984 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3985 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3986 3987 /* Setup RSS through the VF registers */ 3988 ixgbe_setup_vfreta(adapter); 3989 vfmrqc = IXGBE_MRQC_RSSEN; 3990 vfmrqc |= rss_field; 3991 3992 while (pool--) 3993 IXGBE_WRITE_REG(hw, 3994 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3995 vfmrqc); 3996 } else { 3997 ixgbe_setup_reta(adapter); 3998 mrqc |= rss_field; 3999 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4000 } 4001} 4002 4003/** 4004 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4005 * @adapter: address of board private structure 4006 * @ring: structure containing ring specific data 4007 **/ 4008static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4009 struct ixgbe_ring *ring) 4010{ 4011 struct ixgbe_hw *hw = &adapter->hw; 4012 u32 rscctrl; 4013 u8 reg_idx = ring->reg_idx; 4014 4015 if (!ring_is_rsc_enabled(ring)) 4016 return; 4017 4018 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4019 rscctrl |= IXGBE_RSCCTL_RSCEN; 4020 /* 4021 * we must limit the number of descriptors so that the 4022 * total size of max desc * buf_len is not greater 4023 * than 65536 4024 */ 4025 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4026 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4027} 4028 4029#define IXGBE_MAX_RX_DESC_POLL 10 4030static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4031 struct ixgbe_ring *ring) 4032{ 4033 struct ixgbe_hw *hw = &adapter->hw; 4034 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4035 u32 rxdctl; 4036 u8 reg_idx = ring->reg_idx; 4037 4038 if (ixgbe_removed(hw->hw_addr)) 4039 return; 4040 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4041 if (hw->mac.type == ixgbe_mac_82598EB && 4042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4043 return; 4044 4045 do { 4046 usleep_range(1000, 2000); 4047 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4048 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4049 4050 if (!wait_loop) { 4051 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4052 "the polling period\n", reg_idx); 4053 } 4054} 4055 4056void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4057 struct ixgbe_ring *ring) 4058{ 4059 struct ixgbe_hw *hw = &adapter->hw; 4060 union ixgbe_adv_rx_desc *rx_desc; 4061 u64 rdba = ring->dma; 4062 u32 rxdctl; 4063 u8 reg_idx = ring->reg_idx; 4064 4065 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4066 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4067 if (ring->xsk_pool) { 4068 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4069 MEM_TYPE_XSK_BUFF_POOL, 4070 NULL)); 4071 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4072 } else { 4073 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4074 MEM_TYPE_PAGE_SHARED, NULL)); 4075 } 4076 4077 /* disable queue to avoid use of these values while updating state */ 4078 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4079 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4080 4081 /* write value back with RXDCTL.ENABLE bit cleared */ 4082 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4083 IXGBE_WRITE_FLUSH(hw); 4084 4085 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4086 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4087 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4088 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4089 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4090 IXGBE_WRITE_FLUSH(hw); 4091 4092 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4093 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4094 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4095 4096 ixgbe_configure_srrctl(adapter, ring); 4097 ixgbe_configure_rscctl(adapter, ring); 4098 4099 if (hw->mac.type == ixgbe_mac_82598EB) { 4100 /* 4101 * enable cache line friendly hardware writes: 4102 * PTHRESH=32 descriptors (half the internal cache), 4103 * this also removes ugly rx_no_buffer_count increment 4104 * HTHRESH=4 descriptors (to minimize latency on fetch) 4105 * WTHRESH=8 burst writeback up to two cache lines 4106 */ 4107 rxdctl &= ~0x3FFFFF; 4108 rxdctl |= 0x080420; 4109#if (PAGE_SIZE < 8192) 4110 /* RXDCTL.RLPML does not work on 82599 */ 4111 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4112 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4113 IXGBE_RXDCTL_RLPML_EN); 4114 4115 /* Limit the maximum frame size so we don't overrun the skb. 4116 * This can happen in SRIOV mode when the MTU of the VF is 4117 * higher than the MTU of the PF. 4118 */ 4119 if (ring_uses_build_skb(ring) && 4120 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4121 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4122 IXGBE_RXDCTL_RLPML_EN; 4123#endif 4124 } 4125 4126 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4127 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4128 4129 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4130 IXGBE_RXDCTL_RLPML_EN); 4131 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4132 4133 ring->rx_buf_len = xsk_buf_len; 4134 } 4135 4136 /* initialize rx_buffer_info */ 4137 memset(ring->rx_buffer_info, 0, 4138 sizeof(struct ixgbe_rx_buffer) * ring->count); 4139 4140 /* initialize Rx descriptor 0 */ 4141 rx_desc = IXGBE_RX_DESC(ring, 0); 4142 rx_desc->wb.upper.length = 0; 4143 4144 /* enable receive descriptor ring */ 4145 rxdctl |= IXGBE_RXDCTL_ENABLE; 4146 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4147 4148 ixgbe_rx_desc_queue_enable(adapter, ring); 4149 if (ring->xsk_pool) 4150 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4151 else 4152 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4153} 4154 4155static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4156{ 4157 struct ixgbe_hw *hw = &adapter->hw; 4158 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4159 u16 pool = adapter->num_rx_pools; 4160 4161 /* PSRTYPE must be initialized in non 82598 adapters */ 4162 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4163 IXGBE_PSRTYPE_UDPHDR | 4164 IXGBE_PSRTYPE_IPV4HDR | 4165 IXGBE_PSRTYPE_L2HDR | 4166 IXGBE_PSRTYPE_IPV6HDR; 4167 4168 if (hw->mac.type == ixgbe_mac_82598EB) 4169 return; 4170 4171 if (rss_i > 3) 4172 psrtype |= 2u << 29; 4173 else if (rss_i > 1) 4174 psrtype |= 1u << 29; 4175 4176 while (pool--) 4177 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4178} 4179 4180static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4181{ 4182 struct ixgbe_hw *hw = &adapter->hw; 4183 u16 pool = adapter->num_rx_pools; 4184 u32 reg_offset, vf_shift, vmolr; 4185 u32 gcr_ext, vmdctl; 4186 int i; 4187 4188 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4189 return; 4190 4191 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4192 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4193 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4194 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4195 vmdctl |= IXGBE_VT_CTL_REPLEN; 4196 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4197 4198 /* accept untagged packets until a vlan tag is 4199 * specifically set for the VMDQ queue/pool 4200 */ 4201 vmolr = IXGBE_VMOLR_AUPE; 4202 while (pool--) 4203 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4204 4205 vf_shift = VMDQ_P(0) % 32; 4206 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4207 4208 /* Enable only the PF's pool for Tx/Rx */ 4209 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4210 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4211 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4212 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4213 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4214 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4215 4216 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4217 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4218 4219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4220 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4221 4222 /* 4223 * Set up VF register offsets for selected VT Mode, 4224 * i.e. 32 or 64 VFs for SR-IOV 4225 */ 4226 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4227 case IXGBE_82599_VMDQ_8Q_MASK: 4228 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4229 break; 4230 case IXGBE_82599_VMDQ_4Q_MASK: 4231 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4232 break; 4233 default: 4234 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4235 break; 4236 } 4237 4238 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4239 4240 for (i = 0; i < adapter->num_vfs; i++) { 4241 /* configure spoof checking */ 4242 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4243 adapter->vfinfo[i].spoofchk_enabled); 4244 4245 /* Enable/Disable RSS query feature */ 4246 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4247 adapter->vfinfo[i].rss_query_enabled); 4248 } 4249} 4250 4251static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4252{ 4253 struct ixgbe_hw *hw = &adapter->hw; 4254 struct net_device *netdev = adapter->netdev; 4255 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4256 struct ixgbe_ring *rx_ring; 4257 int i; 4258 u32 mhadd, hlreg0; 4259 4260#ifdef IXGBE_FCOE 4261 /* adjust max frame to be able to do baby jumbo for FCoE */ 4262 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4263 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4264 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4265 4266#endif /* IXGBE_FCOE */ 4267 4268 /* adjust max frame to be at least the size of a standard frame */ 4269 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4270 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4271 4272 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4273 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4274 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4275 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4276 4277 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4278 } 4279 4280 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4281 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4282 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4283 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4284 4285 /* 4286 * Setup the HW Rx Head and Tail Descriptor Pointers and 4287 * the Base and Length of the Rx Descriptor Ring 4288 */ 4289 for (i = 0; i < adapter->num_rx_queues; i++) { 4290 rx_ring = adapter->rx_ring[i]; 4291 4292 clear_ring_rsc_enabled(rx_ring); 4293 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4294 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4295 4296 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4297 set_ring_rsc_enabled(rx_ring); 4298 4299 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4300 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4301 4302 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4303 continue; 4304 4305 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4306 4307#if (PAGE_SIZE < 8192) 4308 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4309 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4310 4311 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4312 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4313 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4314#endif 4315 } 4316} 4317 4318static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4319{ 4320 struct ixgbe_hw *hw = &adapter->hw; 4321 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4322 4323 switch (hw->mac.type) { 4324 case ixgbe_mac_82598EB: 4325 /* 4326 * For VMDq support of different descriptor types or 4327 * buffer sizes through the use of multiple SRRCTL 4328 * registers, RDRXCTL.MVMEN must be set to 1 4329 * 4330 * also, the manual doesn't mention it clearly but DCA hints 4331 * will only use queue 0's tags unless this bit is set. Side 4332 * effects of setting this bit are only that SRRCTL must be 4333 * fully programmed [0..15] 4334 */ 4335 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4336 break; 4337 case ixgbe_mac_X550: 4338 case ixgbe_mac_X550EM_x: 4339 case ixgbe_mac_x550em_a: 4340 if (adapter->num_vfs) 4341 rdrxctl |= IXGBE_RDRXCTL_PSP; 4342 fallthrough; 4343 case ixgbe_mac_82599EB: 4344 case ixgbe_mac_X540: 4345 /* Disable RSC for ACK packets */ 4346 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4347 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4348 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4349 /* hardware requires some bits to be set by default */ 4350 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4351 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4352 break; 4353 default: 4354 /* We should do nothing since we don't know this hardware */ 4355 return; 4356 } 4357 4358 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4359} 4360 4361/** 4362 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4363 * @adapter: board private structure 4364 * 4365 * Configure the Rx unit of the MAC after a reset. 4366 **/ 4367static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4368{ 4369 struct ixgbe_hw *hw = &adapter->hw; 4370 int i; 4371 u32 rxctrl, rfctl; 4372 4373 /* disable receives while setting up the descriptors */ 4374 hw->mac.ops.disable_rx(hw); 4375 4376 ixgbe_setup_psrtype(adapter); 4377 ixgbe_setup_rdrxctl(adapter); 4378 4379 /* RSC Setup */ 4380 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4381 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4382 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4383 rfctl |= IXGBE_RFCTL_RSC_DIS; 4384 4385 /* disable NFS filtering */ 4386 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4387 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4388 4389 /* Program registers for the distribution of queues */ 4390 ixgbe_setup_mrqc(adapter); 4391 4392 /* set_rx_buffer_len must be called before ring initialization */ 4393 ixgbe_set_rx_buffer_len(adapter); 4394 4395 /* 4396 * Setup the HW Rx Head and Tail Descriptor Pointers and 4397 * the Base and Length of the Rx Descriptor Ring 4398 */ 4399 for (i = 0; i < adapter->num_rx_queues; i++) 4400 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4401 4402 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4403 /* disable drop enable for 82598 parts */ 4404 if (hw->mac.type == ixgbe_mac_82598EB) 4405 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4406 4407 /* enable all receives */ 4408 rxctrl |= IXGBE_RXCTRL_RXEN; 4409 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4410} 4411 4412static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4413 __be16 proto, u16 vid) 4414{ 4415 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4416 struct ixgbe_hw *hw = &adapter->hw; 4417 4418 /* add VID to filter table */ 4419 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4420 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4421 4422 set_bit(vid, adapter->active_vlans); 4423 4424 return 0; 4425} 4426 4427static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4428{ 4429 u32 vlvf; 4430 int idx; 4431 4432 /* short cut the special case */ 4433 if (vlan == 0) 4434 return 0; 4435 4436 /* Search for the vlan id in the VLVF entries */ 4437 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4438 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4439 if ((vlvf & VLAN_VID_MASK) == vlan) 4440 break; 4441 } 4442 4443 return idx; 4444} 4445 4446void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4447{ 4448 struct ixgbe_hw *hw = &adapter->hw; 4449 u32 bits, word; 4450 int idx; 4451 4452 idx = ixgbe_find_vlvf_entry(hw, vid); 4453 if (!idx) 4454 return; 4455 4456 /* See if any other pools are set for this VLAN filter 4457 * entry other than the PF. 4458 */ 4459 word = idx * 2 + (VMDQ_P(0) / 32); 4460 bits = ~BIT(VMDQ_P(0) % 32); 4461 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4462 4463 /* Disable the filter so this falls into the default pool. */ 4464 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4465 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4466 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4467 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4468 } 4469} 4470 4471static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4472 __be16 proto, u16 vid) 4473{ 4474 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4475 struct ixgbe_hw *hw = &adapter->hw; 4476 4477 /* remove VID from filter table */ 4478 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4479 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4480 4481 clear_bit(vid, adapter->active_vlans); 4482 4483 return 0; 4484} 4485 4486/** 4487 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4488 * @adapter: driver data 4489 */ 4490static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4491{ 4492 struct ixgbe_hw *hw = &adapter->hw; 4493 u32 vlnctrl; 4494 int i, j; 4495 4496 switch (hw->mac.type) { 4497 case ixgbe_mac_82598EB: 4498 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4499 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4500 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4501 break; 4502 case ixgbe_mac_82599EB: 4503 case ixgbe_mac_X540: 4504 case ixgbe_mac_X550: 4505 case ixgbe_mac_X550EM_x: 4506 case ixgbe_mac_x550em_a: 4507 for (i = 0; i < adapter->num_rx_queues; i++) { 4508 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4509 4510 if (!netif_is_ixgbe(ring->netdev)) 4511 continue; 4512 4513 j = ring->reg_idx; 4514 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4515 vlnctrl &= ~IXGBE_RXDCTL_VME; 4516 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4517 } 4518 break; 4519 default: 4520 break; 4521 } 4522} 4523 4524/** 4525 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4526 * @adapter: driver data 4527 */ 4528static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4529{ 4530 struct ixgbe_hw *hw = &adapter->hw; 4531 u32 vlnctrl; 4532 int i, j; 4533 4534 switch (hw->mac.type) { 4535 case ixgbe_mac_82598EB: 4536 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4537 vlnctrl |= IXGBE_VLNCTRL_VME; 4538 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4539 break; 4540 case ixgbe_mac_82599EB: 4541 case ixgbe_mac_X540: 4542 case ixgbe_mac_X550: 4543 case ixgbe_mac_X550EM_x: 4544 case ixgbe_mac_x550em_a: 4545 for (i = 0; i < adapter->num_rx_queues; i++) { 4546 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4547 4548 if (!netif_is_ixgbe(ring->netdev)) 4549 continue; 4550 4551 j = ring->reg_idx; 4552 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4553 vlnctrl |= IXGBE_RXDCTL_VME; 4554 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4555 } 4556 break; 4557 default: 4558 break; 4559 } 4560} 4561 4562static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4563{ 4564 struct ixgbe_hw *hw = &adapter->hw; 4565 u32 vlnctrl, i; 4566 4567 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4568 4569 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4570 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4571 vlnctrl |= IXGBE_VLNCTRL_VFE; 4572 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4573 } else { 4574 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4575 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4576 return; 4577 } 4578 4579 /* Nothing to do for 82598 */ 4580 if (hw->mac.type == ixgbe_mac_82598EB) 4581 return; 4582 4583 /* We are already in VLAN promisc, nothing to do */ 4584 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4585 return; 4586 4587 /* Set flag so we don't redo unnecessary work */ 4588 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4589 4590 /* Add PF to all active pools */ 4591 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4592 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4593 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4594 4595 vlvfb |= BIT(VMDQ_P(0) % 32); 4596 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4597 } 4598 4599 /* Set all bits in the VLAN filter table array */ 4600 for (i = hw->mac.vft_size; i--;) 4601 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4602} 4603 4604#define VFTA_BLOCK_SIZE 8 4605static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4606{ 4607 struct ixgbe_hw *hw = &adapter->hw; 4608 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4609 u32 vid_start = vfta_offset * 32; 4610 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4611 u32 i, vid, word, bits; 4612 4613 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4614 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4615 4616 /* pull VLAN ID from VLVF */ 4617 vid = vlvf & VLAN_VID_MASK; 4618 4619 /* only concern outselves with a certain range */ 4620 if (vid < vid_start || vid >= vid_end) 4621 continue; 4622 4623 if (vlvf) { 4624 /* record VLAN ID in VFTA */ 4625 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4626 4627 /* if PF is part of this then continue */ 4628 if (test_bit(vid, adapter->active_vlans)) 4629 continue; 4630 } 4631 4632 /* remove PF from the pool */ 4633 word = i * 2 + VMDQ_P(0) / 32; 4634 bits = ~BIT(VMDQ_P(0) % 32); 4635 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4636 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4637 } 4638 4639 /* extract values from active_vlans and write back to VFTA */ 4640 for (i = VFTA_BLOCK_SIZE; i--;) { 4641 vid = (vfta_offset + i) * 32; 4642 word = vid / BITS_PER_LONG; 4643 bits = vid % BITS_PER_LONG; 4644 4645 vfta[i] |= adapter->active_vlans[word] >> bits; 4646 4647 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4648 } 4649} 4650 4651static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4652{ 4653 struct ixgbe_hw *hw = &adapter->hw; 4654 u32 vlnctrl, i; 4655 4656 /* Set VLAN filtering to enabled */ 4657 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4658 vlnctrl |= IXGBE_VLNCTRL_VFE; 4659 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4660 4661 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4662 hw->mac.type == ixgbe_mac_82598EB) 4663 return; 4664 4665 /* We are not in VLAN promisc, nothing to do */ 4666 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4667 return; 4668 4669 /* Set flag so we don't redo unnecessary work */ 4670 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4671 4672 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4673 ixgbe_scrub_vfta(adapter, i); 4674} 4675 4676static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4677{ 4678 u16 vid = 1; 4679 4680 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4681 4682 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4683 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4684} 4685 4686/** 4687 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4688 * @netdev: network interface device structure 4689 * 4690 * Writes multicast address list to the MTA hash table. 4691 * Returns: -ENOMEM on failure 4692 * 0 on no addresses written 4693 * X on writing X addresses to MTA 4694 **/ 4695static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4696{ 4697 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4698 struct ixgbe_hw *hw = &adapter->hw; 4699 4700 if (!netif_running(netdev)) 4701 return 0; 4702 4703 if (hw->mac.ops.update_mc_addr_list) 4704 hw->mac.ops.update_mc_addr_list(hw, netdev); 4705 else 4706 return -ENOMEM; 4707 4708#ifdef CONFIG_PCI_IOV 4709 ixgbe_restore_vf_multicasts(adapter); 4710#endif 4711 4712 return netdev_mc_count(netdev); 4713} 4714 4715#ifdef CONFIG_PCI_IOV 4716void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4717{ 4718 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4719 struct ixgbe_hw *hw = &adapter->hw; 4720 int i; 4721 4722 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4723 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4724 4725 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4726 hw->mac.ops.set_rar(hw, i, 4727 mac_table->addr, 4728 mac_table->pool, 4729 IXGBE_RAH_AV); 4730 else 4731 hw->mac.ops.clear_rar(hw, i); 4732 } 4733} 4734 4735#endif 4736static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4737{ 4738 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4739 struct ixgbe_hw *hw = &adapter->hw; 4740 int i; 4741 4742 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4743 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4744 continue; 4745 4746 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4747 4748 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4749 hw->mac.ops.set_rar(hw, i, 4750 mac_table->addr, 4751 mac_table->pool, 4752 IXGBE_RAH_AV); 4753 else 4754 hw->mac.ops.clear_rar(hw, i); 4755 } 4756} 4757 4758static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4759{ 4760 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4761 struct ixgbe_hw *hw = &adapter->hw; 4762 int i; 4763 4764 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4765 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4766 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4767 } 4768 4769 ixgbe_sync_mac_table(adapter); 4770} 4771 4772static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4773{ 4774 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4775 struct ixgbe_hw *hw = &adapter->hw; 4776 int i, count = 0; 4777 4778 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4779 /* do not count default RAR as available */ 4780 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4781 continue; 4782 4783 /* only count unused and addresses that belong to us */ 4784 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4785 if (mac_table->pool != pool) 4786 continue; 4787 } 4788 4789 count++; 4790 } 4791 4792 return count; 4793} 4794 4795/* this function destroys the first RAR entry */ 4796static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4797{ 4798 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4799 struct ixgbe_hw *hw = &adapter->hw; 4800 4801 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4802 mac_table->pool = VMDQ_P(0); 4803 4804 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4805 4806 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4807 IXGBE_RAH_AV); 4808} 4809 4810int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4811 const u8 *addr, u16 pool) 4812{ 4813 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4814 struct ixgbe_hw *hw = &adapter->hw; 4815 int i; 4816 4817 if (is_zero_ether_addr(addr)) 4818 return -EINVAL; 4819 4820 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4821 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4822 continue; 4823 4824 ether_addr_copy(mac_table->addr, addr); 4825 mac_table->pool = pool; 4826 4827 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4828 IXGBE_MAC_STATE_IN_USE; 4829 4830 ixgbe_sync_mac_table(adapter); 4831 4832 return i; 4833 } 4834 4835 return -ENOMEM; 4836} 4837 4838int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4839 const u8 *addr, u16 pool) 4840{ 4841 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4842 struct ixgbe_hw *hw = &adapter->hw; 4843 int i; 4844 4845 if (is_zero_ether_addr(addr)) 4846 return -EINVAL; 4847 4848 /* search table for addr, if found clear IN_USE flag and sync */ 4849 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4850 /* we can only delete an entry if it is in use */ 4851 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4852 continue; 4853 /* we only care about entries that belong to the given pool */ 4854 if (mac_table->pool != pool) 4855 continue; 4856 /* we only care about a specific MAC address */ 4857 if (!ether_addr_equal(addr, mac_table->addr)) 4858 continue; 4859 4860 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4861 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4862 4863 ixgbe_sync_mac_table(adapter); 4864 4865 return 0; 4866 } 4867 4868 return -ENOMEM; 4869} 4870 4871static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4872{ 4873 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4874 int ret; 4875 4876 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4877 4878 return min_t(int, ret, 0); 4879} 4880 4881static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4882{ 4883 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4884 4885 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4886 4887 return 0; 4888} 4889 4890/** 4891 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4892 * @netdev: network interface device structure 4893 * 4894 * The set_rx_method entry point is called whenever the unicast/multicast 4895 * address list or the network interface flags are updated. This routine is 4896 * responsible for configuring the hardware for proper unicast, multicast and 4897 * promiscuous mode. 4898 **/ 4899void ixgbe_set_rx_mode(struct net_device *netdev) 4900{ 4901 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4902 struct ixgbe_hw *hw = &adapter->hw; 4903 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4904 netdev_features_t features = netdev->features; 4905 int count; 4906 4907 /* Check for Promiscuous and All Multicast modes */ 4908 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4909 4910 /* set all bits that we expect to always be set */ 4911 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4912 fctrl |= IXGBE_FCTRL_BAM; 4913 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4914 fctrl |= IXGBE_FCTRL_PMCF; 4915 4916 /* clear the bits we are changing the status of */ 4917 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4918 if (netdev->flags & IFF_PROMISC) { 4919 hw->addr_ctrl.user_set_promisc = true; 4920 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4921 vmolr |= IXGBE_VMOLR_MPE; 4922 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4923 } else { 4924 if (netdev->flags & IFF_ALLMULTI) { 4925 fctrl |= IXGBE_FCTRL_MPE; 4926 vmolr |= IXGBE_VMOLR_MPE; 4927 } 4928 hw->addr_ctrl.user_set_promisc = false; 4929 } 4930 4931 /* 4932 * Write addresses to available RAR registers, if there is not 4933 * sufficient space to store all the addresses then enable 4934 * unicast promiscuous mode 4935 */ 4936 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4937 fctrl |= IXGBE_FCTRL_UPE; 4938 vmolr |= IXGBE_VMOLR_ROPE; 4939 } 4940 4941 /* Write addresses to the MTA, if the attempt fails 4942 * then we should just turn on promiscuous mode so 4943 * that we can at least receive multicast traffic 4944 */ 4945 count = ixgbe_write_mc_addr_list(netdev); 4946 if (count < 0) { 4947 fctrl |= IXGBE_FCTRL_MPE; 4948 vmolr |= IXGBE_VMOLR_MPE; 4949 } else if (count) { 4950 vmolr |= IXGBE_VMOLR_ROMPE; 4951 } 4952 4953 if (hw->mac.type != ixgbe_mac_82598EB) { 4954 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4955 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4956 IXGBE_VMOLR_ROPE); 4957 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4958 } 4959 4960 /* This is useful for sniffing bad packets. */ 4961 if (features & NETIF_F_RXALL) { 4962 /* UPE and MPE will be handled by normal PROMISC logic 4963 * in e1000e_set_rx_mode */ 4964 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4965 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4966 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4967 4968 fctrl &= ~(IXGBE_FCTRL_DPF); 4969 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4970 } 4971 4972 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4973 4974 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4975 ixgbe_vlan_strip_enable(adapter); 4976 else 4977 ixgbe_vlan_strip_disable(adapter); 4978 4979 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4980 ixgbe_vlan_promisc_disable(adapter); 4981 else 4982 ixgbe_vlan_promisc_enable(adapter); 4983} 4984 4985static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4986{ 4987 int q_idx; 4988 4989 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4990 napi_enable(&adapter->q_vector[q_idx]->napi); 4991} 4992 4993static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4994{ 4995 int q_idx; 4996 4997 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4998 napi_disable(&adapter->q_vector[q_idx]->napi); 4999} 5000 5001static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 5002{ 5003 struct ixgbe_adapter *adapter = netdev_priv(dev); 5004 struct ixgbe_hw *hw = &adapter->hw; 5005 struct udp_tunnel_info ti; 5006 5007 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5008 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5009 adapter->vxlan_port = ti.port; 5010 else 5011 adapter->geneve_port = ti.port; 5012 5013 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5014 ntohs(adapter->vxlan_port) | 5015 ntohs(adapter->geneve_port) << 5016 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5017 return 0; 5018} 5019 5020static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5021 .sync_table = ixgbe_udp_tunnel_sync, 5022 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5023 .tables = { 5024 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5025 }, 5026}; 5027 5028static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5029 .sync_table = ixgbe_udp_tunnel_sync, 5030 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5031 .tables = { 5032 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5033 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5034 }, 5035}; 5036 5037#ifdef CONFIG_IXGBE_DCB 5038/** 5039 * ixgbe_configure_dcb - Configure DCB hardware 5040 * @adapter: ixgbe adapter struct 5041 * 5042 * This is called by the driver on open to configure the DCB hardware. 5043 * This is also called by the gennetlink interface when reconfiguring 5044 * the DCB state. 5045 */ 5046static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5047{ 5048 struct ixgbe_hw *hw = &adapter->hw; 5049 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5050 5051 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5052 if (hw->mac.type == ixgbe_mac_82598EB) 5053 netif_set_gso_max_size(adapter->netdev, 65536); 5054 return; 5055 } 5056 5057 if (hw->mac.type == ixgbe_mac_82598EB) 5058 netif_set_gso_max_size(adapter->netdev, 32768); 5059 5060#ifdef IXGBE_FCOE 5061 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5062 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5063#endif 5064 5065 /* reconfigure the hardware */ 5066 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5067 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5068 DCB_TX_CONFIG); 5069 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5070 DCB_RX_CONFIG); 5071 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5072 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5073 ixgbe_dcb_hw_ets(&adapter->hw, 5074 adapter->ixgbe_ieee_ets, 5075 max_frame); 5076 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5077 adapter->ixgbe_ieee_pfc->pfc_en, 5078 adapter->ixgbe_ieee_ets->prio_tc); 5079 } 5080 5081 /* Enable RSS Hash per TC */ 5082 if (hw->mac.type != ixgbe_mac_82598EB) { 5083 u32 msb = 0; 5084 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5085 5086 while (rss_i) { 5087 msb++; 5088 rss_i >>= 1; 5089 } 5090 5091 /* write msb to all 8 TCs in one write */ 5092 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5093 } 5094} 5095#endif 5096 5097/* Additional bittime to account for IXGBE framing */ 5098#define IXGBE_ETH_FRAMING 20 5099 5100/** 5101 * ixgbe_hpbthresh - calculate high water mark for flow control 5102 * 5103 * @adapter: board private structure to calculate for 5104 * @pb: packet buffer to calculate 5105 */ 5106static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5107{ 5108 struct ixgbe_hw *hw = &adapter->hw; 5109 struct net_device *dev = adapter->netdev; 5110 int link, tc, kb, marker; 5111 u32 dv_id, rx_pba; 5112 5113 /* Calculate max LAN frame size */ 5114 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5115 5116#ifdef IXGBE_FCOE 5117 /* FCoE traffic class uses FCOE jumbo frames */ 5118 if ((dev->features & NETIF_F_FCOE_MTU) && 5119 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5120 (pb == ixgbe_fcoe_get_tc(adapter))) 5121 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5122#endif 5123 5124 /* Calculate delay value for device */ 5125 switch (hw->mac.type) { 5126 case ixgbe_mac_X540: 5127 case ixgbe_mac_X550: 5128 case ixgbe_mac_X550EM_x: 5129 case ixgbe_mac_x550em_a: 5130 dv_id = IXGBE_DV_X540(link, tc); 5131 break; 5132 default: 5133 dv_id = IXGBE_DV(link, tc); 5134 break; 5135 } 5136 5137 /* Loopback switch introduces additional latency */ 5138 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5139 dv_id += IXGBE_B2BT(tc); 5140 5141 /* Delay value is calculated in bit times convert to KB */ 5142 kb = IXGBE_BT2KB(dv_id); 5143 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5144 5145 marker = rx_pba - kb; 5146 5147 /* It is possible that the packet buffer is not large enough 5148 * to provide required headroom. In this case throw an error 5149 * to user and a do the best we can. 5150 */ 5151 if (marker < 0) { 5152 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5153 "headroom to support flow control." 5154 "Decrease MTU or number of traffic classes\n", pb); 5155 marker = tc + 1; 5156 } 5157 5158 return marker; 5159} 5160 5161/** 5162 * ixgbe_lpbthresh - calculate low water mark for for flow control 5163 * 5164 * @adapter: board private structure to calculate for 5165 * @pb: packet buffer to calculate 5166 */ 5167static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5168{ 5169 struct ixgbe_hw *hw = &adapter->hw; 5170 struct net_device *dev = adapter->netdev; 5171 int tc; 5172 u32 dv_id; 5173 5174 /* Calculate max LAN frame size */ 5175 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5176 5177#ifdef IXGBE_FCOE 5178 /* FCoE traffic class uses FCOE jumbo frames */ 5179 if ((dev->features & NETIF_F_FCOE_MTU) && 5180 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5181 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5182 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5183#endif 5184 5185 /* Calculate delay value for device */ 5186 switch (hw->mac.type) { 5187 case ixgbe_mac_X540: 5188 case ixgbe_mac_X550: 5189 case ixgbe_mac_X550EM_x: 5190 case ixgbe_mac_x550em_a: 5191 dv_id = IXGBE_LOW_DV_X540(tc); 5192 break; 5193 default: 5194 dv_id = IXGBE_LOW_DV(tc); 5195 break; 5196 } 5197 5198 /* Delay value is calculated in bit times convert to KB */ 5199 return IXGBE_BT2KB(dv_id); 5200} 5201 5202/* 5203 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5204 */ 5205static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5206{ 5207 struct ixgbe_hw *hw = &adapter->hw; 5208 int num_tc = adapter->hw_tcs; 5209 int i; 5210 5211 if (!num_tc) 5212 num_tc = 1; 5213 5214 for (i = 0; i < num_tc; i++) { 5215 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5216 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5217 5218 /* Low water marks must not be larger than high water marks */ 5219 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5220 hw->fc.low_water[i] = 0; 5221 } 5222 5223 for (; i < MAX_TRAFFIC_CLASS; i++) 5224 hw->fc.high_water[i] = 0; 5225} 5226 5227static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5228{ 5229 struct ixgbe_hw *hw = &adapter->hw; 5230 int hdrm; 5231 u8 tc = adapter->hw_tcs; 5232 5233 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5234 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5235 hdrm = 32 << adapter->fdir_pballoc; 5236 else 5237 hdrm = 0; 5238 5239 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5240 ixgbe_pbthresh_setup(adapter); 5241} 5242 5243static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5244{ 5245 struct ixgbe_hw *hw = &adapter->hw; 5246 struct hlist_node *node2; 5247 struct ixgbe_fdir_filter *filter; 5248 u8 queue; 5249 5250 spin_lock(&adapter->fdir_perfect_lock); 5251 5252 if (!hlist_empty(&adapter->fdir_filter_list)) 5253 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5254 5255 hlist_for_each_entry_safe(filter, node2, 5256 &adapter->fdir_filter_list, fdir_node) { 5257 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5258 queue = IXGBE_FDIR_DROP_QUEUE; 5259 } else { 5260 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5261 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5262 5263 if (!vf && (ring >= adapter->num_rx_queues)) { 5264 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5265 ring); 5266 continue; 5267 } else if (vf && 5268 ((vf > adapter->num_vfs) || 5269 ring >= adapter->num_rx_queues_per_pool)) { 5270 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5271 vf, ring); 5272 continue; 5273 } 5274 5275 /* Map the ring onto the absolute queue index */ 5276 if (!vf) 5277 queue = adapter->rx_ring[ring]->reg_idx; 5278 else 5279 queue = ((vf - 1) * 5280 adapter->num_rx_queues_per_pool) + ring; 5281 } 5282 5283 ixgbe_fdir_write_perfect_filter_82599(hw, 5284 &filter->filter, filter->sw_idx, queue); 5285 } 5286 5287 spin_unlock(&adapter->fdir_perfect_lock); 5288} 5289 5290/** 5291 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5292 * @rx_ring: ring to free buffers from 5293 **/ 5294static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5295{ 5296 u16 i = rx_ring->next_to_clean; 5297 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5298 5299 if (rx_ring->xsk_pool) { 5300 ixgbe_xsk_clean_rx_ring(rx_ring); 5301 goto skip_free; 5302 } 5303 5304 /* Free all the Rx ring sk_buffs */ 5305 while (i != rx_ring->next_to_alloc) { 5306 if (rx_buffer->skb) { 5307 struct sk_buff *skb = rx_buffer->skb; 5308 if (IXGBE_CB(skb)->page_released) 5309 dma_unmap_page_attrs(rx_ring->dev, 5310 IXGBE_CB(skb)->dma, 5311 ixgbe_rx_pg_size(rx_ring), 5312 DMA_FROM_DEVICE, 5313 IXGBE_RX_DMA_ATTR); 5314 dev_kfree_skb(skb); 5315 } 5316 5317 /* Invalidate cache lines that may have been written to by 5318 * device so that we avoid corrupting memory. 5319 */ 5320 dma_sync_single_range_for_cpu(rx_ring->dev, 5321 rx_buffer->dma, 5322 rx_buffer->page_offset, 5323 ixgbe_rx_bufsz(rx_ring), 5324 DMA_FROM_DEVICE); 5325 5326 /* free resources associated with mapping */ 5327 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5328 ixgbe_rx_pg_size(rx_ring), 5329 DMA_FROM_DEVICE, 5330 IXGBE_RX_DMA_ATTR); 5331 __page_frag_cache_drain(rx_buffer->page, 5332 rx_buffer->pagecnt_bias); 5333 5334 i++; 5335 rx_buffer++; 5336 if (i == rx_ring->count) { 5337 i = 0; 5338 rx_buffer = rx_ring->rx_buffer_info; 5339 } 5340 } 5341 5342skip_free: 5343 rx_ring->next_to_alloc = 0; 5344 rx_ring->next_to_clean = 0; 5345 rx_ring->next_to_use = 0; 5346} 5347 5348static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5349 struct ixgbe_fwd_adapter *accel) 5350{ 5351 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5352 int num_tc = netdev_get_num_tc(adapter->netdev); 5353 struct net_device *vdev = accel->netdev; 5354 int i, baseq, err; 5355 5356 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5357 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5358 accel->pool, adapter->num_rx_pools, 5359 baseq, baseq + adapter->num_rx_queues_per_pool); 5360 5361 accel->rx_base_queue = baseq; 5362 accel->tx_base_queue = baseq; 5363 5364 /* record configuration for macvlan interface in vdev */ 5365 for (i = 0; i < num_tc; i++) 5366 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5367 i, rss_i, baseq + (rss_i * i)); 5368 5369 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5370 adapter->rx_ring[baseq + i]->netdev = vdev; 5371 5372 /* Guarantee all rings are updated before we update the 5373 * MAC address filter. 5374 */ 5375 wmb(); 5376 5377 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5378 * need to only treat it as an error value if it is negative. 5379 */ 5380 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5381 VMDQ_P(accel->pool)); 5382 if (err >= 0) 5383 return 0; 5384 5385 /* if we cannot add the MAC rule then disable the offload */ 5386 macvlan_release_l2fw_offload(vdev); 5387 5388 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5389 adapter->rx_ring[baseq + i]->netdev = NULL; 5390 5391 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5392 5393 /* unbind the queues and drop the subordinate channel config */ 5394 netdev_unbind_sb_channel(adapter->netdev, vdev); 5395 netdev_set_sb_channel(vdev, 0); 5396 5397 clear_bit(accel->pool, adapter->fwd_bitmask); 5398 kfree(accel); 5399 5400 return err; 5401} 5402 5403static int ixgbe_macvlan_up(struct net_device *vdev, 5404 struct netdev_nested_priv *priv) 5405{ 5406 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5407 struct ixgbe_fwd_adapter *accel; 5408 5409 if (!netif_is_macvlan(vdev)) 5410 return 0; 5411 5412 accel = macvlan_accel_priv(vdev); 5413 if (!accel) 5414 return 0; 5415 5416 ixgbe_fwd_ring_up(adapter, accel); 5417 5418 return 0; 5419} 5420 5421static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5422{ 5423 struct netdev_nested_priv priv = { 5424 .data = (void *)adapter, 5425 }; 5426 5427 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5428 ixgbe_macvlan_up, &priv); 5429} 5430 5431static void ixgbe_configure(struct ixgbe_adapter *adapter) 5432{ 5433 struct ixgbe_hw *hw = &adapter->hw; 5434 5435 ixgbe_configure_pb(adapter); 5436#ifdef CONFIG_IXGBE_DCB 5437 ixgbe_configure_dcb(adapter); 5438#endif 5439 /* 5440 * We must restore virtualization before VLANs or else 5441 * the VLVF registers will not be populated 5442 */ 5443 ixgbe_configure_virtualization(adapter); 5444 5445 ixgbe_set_rx_mode(adapter->netdev); 5446 ixgbe_restore_vlan(adapter); 5447 ixgbe_ipsec_restore(adapter); 5448 5449 switch (hw->mac.type) { 5450 case ixgbe_mac_82599EB: 5451 case ixgbe_mac_X540: 5452 hw->mac.ops.disable_rx_buff(hw); 5453 break; 5454 default: 5455 break; 5456 } 5457 5458 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5459 ixgbe_init_fdir_signature_82599(&adapter->hw, 5460 adapter->fdir_pballoc); 5461 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5462 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5463 adapter->fdir_pballoc); 5464 ixgbe_fdir_filter_restore(adapter); 5465 } 5466 5467 switch (hw->mac.type) { 5468 case ixgbe_mac_82599EB: 5469 case ixgbe_mac_X540: 5470 hw->mac.ops.enable_rx_buff(hw); 5471 break; 5472 default: 5473 break; 5474 } 5475 5476#ifdef CONFIG_IXGBE_DCA 5477 /* configure DCA */ 5478 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5479 ixgbe_setup_dca(adapter); 5480#endif /* CONFIG_IXGBE_DCA */ 5481 5482#ifdef IXGBE_FCOE 5483 /* configure FCoE L2 filters, redirection table, and Rx control */ 5484 ixgbe_configure_fcoe(adapter); 5485 5486#endif /* IXGBE_FCOE */ 5487 ixgbe_configure_tx(adapter); 5488 ixgbe_configure_rx(adapter); 5489 ixgbe_configure_dfwd(adapter); 5490} 5491 5492/** 5493 * ixgbe_sfp_link_config - set up SFP+ link 5494 * @adapter: pointer to private adapter struct 5495 **/ 5496static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5497{ 5498 /* 5499 * We are assuming the worst case scenario here, and that 5500 * is that an SFP was inserted/removed after the reset 5501 * but before SFP detection was enabled. As such the best 5502 * solution is to just start searching as soon as we start 5503 */ 5504 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5505 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5506 5507 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5508 adapter->sfp_poll_time = 0; 5509} 5510 5511/** 5512 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5513 * @hw: pointer to private hardware struct 5514 * 5515 * Returns 0 on success, negative on failure 5516 **/ 5517static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5518{ 5519 u32 speed; 5520 bool autoneg, link_up = false; 5521 int ret = -EIO; 5522 5523 if (hw->mac.ops.check_link) 5524 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5525 5526 if (ret) 5527 return ret; 5528 5529 speed = hw->phy.autoneg_advertised; 5530 if (!speed && hw->mac.ops.get_link_capabilities) { 5531 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5532 &autoneg); 5533 /* remove NBASE-T speeds from default autonegotiation 5534 * to accommodate broken network switches in the field 5535 * which cannot cope with advertised NBASE-T speeds 5536 */ 5537 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5538 IXGBE_LINK_SPEED_2_5GB_FULL); 5539 } 5540 5541 if (ret) 5542 return ret; 5543 5544 if (hw->mac.ops.setup_link) 5545 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5546 5547 return ret; 5548} 5549 5550static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5551{ 5552 struct ixgbe_hw *hw = &adapter->hw; 5553 u32 gpie = 0; 5554 5555 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5556 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5557 IXGBE_GPIE_OCD; 5558 gpie |= IXGBE_GPIE_EIAME; 5559 /* 5560 * use EIAM to auto-mask when MSI-X interrupt is asserted 5561 * this saves a register write for every interrupt 5562 */ 5563 switch (hw->mac.type) { 5564 case ixgbe_mac_82598EB: 5565 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5566 break; 5567 case ixgbe_mac_82599EB: 5568 case ixgbe_mac_X540: 5569 case ixgbe_mac_X550: 5570 case ixgbe_mac_X550EM_x: 5571 case ixgbe_mac_x550em_a: 5572 default: 5573 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5574 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5575 break; 5576 } 5577 } else { 5578 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5579 * specifically only auto mask tx and rx interrupts */ 5580 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5581 } 5582 5583 /* XXX: to interrupt immediately for EICS writes, enable this */ 5584 /* gpie |= IXGBE_GPIE_EIMEN; */ 5585 5586 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5587 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5588 5589 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5590 case IXGBE_82599_VMDQ_8Q_MASK: 5591 gpie |= IXGBE_GPIE_VTMODE_16; 5592 break; 5593 case IXGBE_82599_VMDQ_4Q_MASK: 5594 gpie |= IXGBE_GPIE_VTMODE_32; 5595 break; 5596 default: 5597 gpie |= IXGBE_GPIE_VTMODE_64; 5598 break; 5599 } 5600 } 5601 5602 /* Enable Thermal over heat sensor interrupt */ 5603 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5604 switch (adapter->hw.mac.type) { 5605 case ixgbe_mac_82599EB: 5606 gpie |= IXGBE_SDP0_GPIEN_8259X; 5607 break; 5608 default: 5609 break; 5610 } 5611 } 5612 5613 /* Enable fan failure interrupt */ 5614 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5615 gpie |= IXGBE_SDP1_GPIEN(hw); 5616 5617 switch (hw->mac.type) { 5618 case ixgbe_mac_82599EB: 5619 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5620 break; 5621 case ixgbe_mac_X550EM_x: 5622 case ixgbe_mac_x550em_a: 5623 gpie |= IXGBE_SDP0_GPIEN_X540; 5624 break; 5625 default: 5626 break; 5627 } 5628 5629 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5630} 5631 5632static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5633{ 5634 struct ixgbe_hw *hw = &adapter->hw; 5635 int err; 5636 u32 ctrl_ext; 5637 5638 ixgbe_get_hw_control(adapter); 5639 ixgbe_setup_gpie(adapter); 5640 5641 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5642 ixgbe_configure_msix(adapter); 5643 else 5644 ixgbe_configure_msi_and_legacy(adapter); 5645 5646 /* enable the optics for 82599 SFP+ fiber */ 5647 if (hw->mac.ops.enable_tx_laser) 5648 hw->mac.ops.enable_tx_laser(hw); 5649 5650 if (hw->phy.ops.set_phy_power) 5651 hw->phy.ops.set_phy_power(hw, true); 5652 5653 smp_mb__before_atomic(); 5654 clear_bit(__IXGBE_DOWN, &adapter->state); 5655 ixgbe_napi_enable_all(adapter); 5656 5657 if (ixgbe_is_sfp(hw)) { 5658 ixgbe_sfp_link_config(adapter); 5659 } else { 5660 err = ixgbe_non_sfp_link_config(hw); 5661 if (err) 5662 e_err(probe, "link_config FAILED %d\n", err); 5663 } 5664 5665 /* clear any pending interrupts, may auto mask */ 5666 IXGBE_READ_REG(hw, IXGBE_EICR); 5667 ixgbe_irq_enable(adapter, true, true); 5668 5669 /* 5670 * If this adapter has a fan, check to see if we had a failure 5671 * before we enabled the interrupt. 5672 */ 5673 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5674 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5675 if (esdp & IXGBE_ESDP_SDP1) 5676 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5677 } 5678 5679 /* bring the link up in the watchdog, this could race with our first 5680 * link up interrupt but shouldn't be a problem */ 5681 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5682 adapter->link_check_timeout = jiffies; 5683 mod_timer(&adapter->service_timer, jiffies); 5684 5685 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5686 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5687 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5688 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5689 5690 /* update setting rx tx for all active vfs */ 5691 ixgbe_set_all_vfs(adapter); 5692} 5693 5694void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5695{ 5696 /* put off any impending NetWatchDogTimeout */ 5697 netif_trans_update(adapter->netdev); 5698 5699 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5700 usleep_range(1000, 2000); 5701 if (adapter->hw.phy.type == ixgbe_phy_fw) 5702 ixgbe_watchdog_link_is_down(adapter); 5703 ixgbe_down(adapter); 5704 /* 5705 * If SR-IOV enabled then wait a bit before bringing the adapter 5706 * back up to give the VFs time to respond to the reset. The 5707 * two second wait is based upon the watchdog timer cycle in 5708 * the VF driver. 5709 */ 5710 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5711 msleep(2000); 5712 ixgbe_up(adapter); 5713 clear_bit(__IXGBE_RESETTING, &adapter->state); 5714} 5715 5716void ixgbe_up(struct ixgbe_adapter *adapter) 5717{ 5718 /* hardware has been reset, we need to reload some things */ 5719 ixgbe_configure(adapter); 5720 5721 ixgbe_up_complete(adapter); 5722} 5723 5724static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5725{ 5726 u16 devctl2; 5727 5728 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5729 5730 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5731 case IXGBE_PCIDEVCTRL2_17_34s: 5732 case IXGBE_PCIDEVCTRL2_4_8s: 5733 /* For now we cap the upper limit on delay to 2 seconds 5734 * as we end up going up to 34 seconds of delay in worst 5735 * case timeout value. 5736 */ 5737 case IXGBE_PCIDEVCTRL2_1_2s: 5738 return 2000000ul; /* 2.0 s */ 5739 case IXGBE_PCIDEVCTRL2_260_520ms: 5740 return 520000ul; /* 520 ms */ 5741 case IXGBE_PCIDEVCTRL2_65_130ms: 5742 return 130000ul; /* 130 ms */ 5743 case IXGBE_PCIDEVCTRL2_16_32ms: 5744 return 32000ul; /* 32 ms */ 5745 case IXGBE_PCIDEVCTRL2_1_2ms: 5746 return 2000ul; /* 2 ms */ 5747 case IXGBE_PCIDEVCTRL2_50_100us: 5748 return 100ul; /* 100 us */ 5749 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5750 return 32000ul; /* 32 ms */ 5751 default: 5752 break; 5753 } 5754 5755 /* We shouldn't need to hit this path, but just in case default as 5756 * though completion timeout is not supported and support 32ms. 5757 */ 5758 return 32000ul; 5759} 5760 5761void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5762{ 5763 unsigned long wait_delay, delay_interval; 5764 struct ixgbe_hw *hw = &adapter->hw; 5765 int i, wait_loop; 5766 u32 rxdctl; 5767 5768 /* disable receives */ 5769 hw->mac.ops.disable_rx(hw); 5770 5771 if (ixgbe_removed(hw->hw_addr)) 5772 return; 5773 5774 /* disable all enabled Rx queues */ 5775 for (i = 0; i < adapter->num_rx_queues; i++) { 5776 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5777 u8 reg_idx = ring->reg_idx; 5778 5779 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5780 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5781 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5782 5783 /* write value back with RXDCTL.ENABLE bit cleared */ 5784 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5785 } 5786 5787 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5788 if (hw->mac.type == ixgbe_mac_82598EB && 5789 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5790 return; 5791 5792 /* Determine our minimum delay interval. We will increase this value 5793 * with each subsequent test. This way if the device returns quickly 5794 * we should spend as little time as possible waiting, however as 5795 * the time increases we will wait for larger periods of time. 5796 * 5797 * The trick here is that we increase the interval using the 5798 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5799 * of that wait is that it totals up to 100x whatever interval we 5800 * choose. Since our minimum wait is 100us we can just divide the 5801 * total timeout by 100 to get our minimum delay interval. 5802 */ 5803 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5804 5805 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5806 wait_delay = delay_interval; 5807 5808 while (wait_loop--) { 5809 usleep_range(wait_delay, wait_delay + 10); 5810 wait_delay += delay_interval * 2; 5811 rxdctl = 0; 5812 5813 /* OR together the reading of all the active RXDCTL registers, 5814 * and then test the result. We need the disable to complete 5815 * before we start freeing the memory and invalidating the 5816 * DMA mappings. 5817 */ 5818 for (i = 0; i < adapter->num_rx_queues; i++) { 5819 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5820 u8 reg_idx = ring->reg_idx; 5821 5822 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5823 } 5824 5825 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5826 return; 5827 } 5828 5829 e_err(drv, 5830 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5831} 5832 5833void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5834{ 5835 unsigned long wait_delay, delay_interval; 5836 struct ixgbe_hw *hw = &adapter->hw; 5837 int i, wait_loop; 5838 u32 txdctl; 5839 5840 if (ixgbe_removed(hw->hw_addr)) 5841 return; 5842 5843 /* disable all enabled Tx queues */ 5844 for (i = 0; i < adapter->num_tx_queues; i++) { 5845 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5846 u8 reg_idx = ring->reg_idx; 5847 5848 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5849 } 5850 5851 /* disable all enabled XDP Tx queues */ 5852 for (i = 0; i < adapter->num_xdp_queues; i++) { 5853 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5854 u8 reg_idx = ring->reg_idx; 5855 5856 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5857 } 5858 5859 /* If the link is not up there shouldn't be much in the way of 5860 * pending transactions. Those that are left will be flushed out 5861 * when the reset logic goes through the flush sequence to clean out 5862 * the pending Tx transactions. 5863 */ 5864 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5865 goto dma_engine_disable; 5866 5867 /* Determine our minimum delay interval. We will increase this value 5868 * with each subsequent test. This way if the device returns quickly 5869 * we should spend as little time as possible waiting, however as 5870 * the time increases we will wait for larger periods of time. 5871 * 5872 * The trick here is that we increase the interval using the 5873 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5874 * of that wait is that it totals up to 100x whatever interval we 5875 * choose. Since our minimum wait is 100us we can just divide the 5876 * total timeout by 100 to get our minimum delay interval. 5877 */ 5878 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5879 5880 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5881 wait_delay = delay_interval; 5882 5883 while (wait_loop--) { 5884 usleep_range(wait_delay, wait_delay + 10); 5885 wait_delay += delay_interval * 2; 5886 txdctl = 0; 5887 5888 /* OR together the reading of all the active TXDCTL registers, 5889 * and then test the result. We need the disable to complete 5890 * before we start freeing the memory and invalidating the 5891 * DMA mappings. 5892 */ 5893 for (i = 0; i < adapter->num_tx_queues; i++) { 5894 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5895 u8 reg_idx = ring->reg_idx; 5896 5897 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5898 } 5899 for (i = 0; i < adapter->num_xdp_queues; i++) { 5900 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5901 u8 reg_idx = ring->reg_idx; 5902 5903 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5904 } 5905 5906 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5907 goto dma_engine_disable; 5908 } 5909 5910 e_err(drv, 5911 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5912 5913dma_engine_disable: 5914 /* Disable the Tx DMA engine on 82599 and later MAC */ 5915 switch (hw->mac.type) { 5916 case ixgbe_mac_82599EB: 5917 case ixgbe_mac_X540: 5918 case ixgbe_mac_X550: 5919 case ixgbe_mac_X550EM_x: 5920 case ixgbe_mac_x550em_a: 5921 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5922 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5923 ~IXGBE_DMATXCTL_TE)); 5924 fallthrough; 5925 default: 5926 break; 5927 } 5928} 5929 5930void ixgbe_reset(struct ixgbe_adapter *adapter) 5931{ 5932 struct ixgbe_hw *hw = &adapter->hw; 5933 struct net_device *netdev = adapter->netdev; 5934 int err; 5935 5936 if (ixgbe_removed(hw->hw_addr)) 5937 return; 5938 /* lock SFP init bit to prevent race conditions with the watchdog */ 5939 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5940 usleep_range(1000, 2000); 5941 5942 /* clear all SFP and link config related flags while holding SFP_INIT */ 5943 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5944 IXGBE_FLAG2_SFP_NEEDS_RESET); 5945 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5946 5947 err = hw->mac.ops.init_hw(hw); 5948 switch (err) { 5949 case 0: 5950 case -ENOENT: 5951 case -EOPNOTSUPP: 5952 break; 5953 case -EALREADY: 5954 e_dev_err("primary disable timed out\n"); 5955 break; 5956 case -EACCES: 5957 /* We are running on a pre-production device, log a warning */ 5958 e_dev_warn("This device is a pre-production adapter/LOM. " 5959 "Please be aware there may be issues associated with " 5960 "your hardware. If you are experiencing problems " 5961 "please contact your Intel or hardware " 5962 "representative who provided you with this " 5963 "hardware.\n"); 5964 break; 5965 default: 5966 e_dev_err("Hardware Error: %d\n", err); 5967 } 5968 5969 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5970 5971 /* flush entries out of MAC table */ 5972 ixgbe_flush_sw_mac_table(adapter); 5973 __dev_uc_unsync(netdev, NULL); 5974 5975 /* do not flush user set addresses */ 5976 ixgbe_mac_set_default_filter(adapter); 5977 5978 /* update SAN MAC vmdq pool selection */ 5979 if (hw->mac.san_mac_rar_index) 5980 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5981 5982 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5983 ixgbe_ptp_reset(adapter); 5984 5985 if (hw->phy.ops.set_phy_power) { 5986 if (!netif_running(adapter->netdev) && !adapter->wol) 5987 hw->phy.ops.set_phy_power(hw, false); 5988 else 5989 hw->phy.ops.set_phy_power(hw, true); 5990 } 5991} 5992 5993/** 5994 * ixgbe_clean_tx_ring - Free Tx Buffers 5995 * @tx_ring: ring to be cleaned 5996 **/ 5997static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5998{ 5999 u16 i = tx_ring->next_to_clean; 6000 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6001 6002 if (tx_ring->xsk_pool) { 6003 ixgbe_xsk_clean_tx_ring(tx_ring); 6004 goto out; 6005 } 6006 6007 while (i != tx_ring->next_to_use) { 6008 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6009 6010 /* Free all the Tx ring sk_buffs */ 6011 if (ring_is_xdp(tx_ring)) 6012 xdp_return_frame(tx_buffer->xdpf); 6013 else 6014 dev_kfree_skb_any(tx_buffer->skb); 6015 6016 /* unmap skb header data */ 6017 dma_unmap_single(tx_ring->dev, 6018 dma_unmap_addr(tx_buffer, dma), 6019 dma_unmap_len(tx_buffer, len), 6020 DMA_TO_DEVICE); 6021 6022 /* check for eop_desc to determine the end of the packet */ 6023 eop_desc = tx_buffer->next_to_watch; 6024 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6025 6026 /* unmap remaining buffers */ 6027 while (tx_desc != eop_desc) { 6028 tx_buffer++; 6029 tx_desc++; 6030 i++; 6031 if (unlikely(i == tx_ring->count)) { 6032 i = 0; 6033 tx_buffer = tx_ring->tx_buffer_info; 6034 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6035 } 6036 6037 /* unmap any remaining paged data */ 6038 if (dma_unmap_len(tx_buffer, len)) 6039 dma_unmap_page(tx_ring->dev, 6040 dma_unmap_addr(tx_buffer, dma), 6041 dma_unmap_len(tx_buffer, len), 6042 DMA_TO_DEVICE); 6043 } 6044 6045 /* move us one more past the eop_desc for start of next pkt */ 6046 tx_buffer++; 6047 i++; 6048 if (unlikely(i == tx_ring->count)) { 6049 i = 0; 6050 tx_buffer = tx_ring->tx_buffer_info; 6051 } 6052 } 6053 6054 /* reset BQL for queue */ 6055 if (!ring_is_xdp(tx_ring)) 6056 netdev_tx_reset_queue(txring_txq(tx_ring)); 6057 6058out: 6059 /* reset next_to_use and next_to_clean */ 6060 tx_ring->next_to_use = 0; 6061 tx_ring->next_to_clean = 0; 6062} 6063 6064/** 6065 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6066 * @adapter: board private structure 6067 **/ 6068static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6069{ 6070 int i; 6071 6072 for (i = 0; i < adapter->num_rx_queues; i++) 6073 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6074} 6075 6076/** 6077 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6078 * @adapter: board private structure 6079 **/ 6080static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6081{ 6082 int i; 6083 6084 for (i = 0; i < adapter->num_tx_queues; i++) 6085 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6086 for (i = 0; i < adapter->num_xdp_queues; i++) 6087 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6088} 6089 6090static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6091{ 6092 struct hlist_node *node2; 6093 struct ixgbe_fdir_filter *filter; 6094 6095 spin_lock(&adapter->fdir_perfect_lock); 6096 6097 hlist_for_each_entry_safe(filter, node2, 6098 &adapter->fdir_filter_list, fdir_node) { 6099 hlist_del(&filter->fdir_node); 6100 kfree(filter); 6101 } 6102 adapter->fdir_filter_count = 0; 6103 6104 spin_unlock(&adapter->fdir_perfect_lock); 6105} 6106 6107void ixgbe_down(struct ixgbe_adapter *adapter) 6108{ 6109 struct net_device *netdev = adapter->netdev; 6110 struct ixgbe_hw *hw = &adapter->hw; 6111 int i; 6112 6113 /* signal that we are down to the interrupt handler */ 6114 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6115 return; /* do nothing if already down */ 6116 6117 /* Shut off incoming Tx traffic */ 6118 netif_tx_stop_all_queues(netdev); 6119 6120 /* call carrier off first to avoid false dev_watchdog timeouts */ 6121 netif_carrier_off(netdev); 6122 netif_tx_disable(netdev); 6123 6124 /* Disable Rx */ 6125 ixgbe_disable_rx(adapter); 6126 6127 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6128 if (adapter->xdp_ring[0]) 6129 synchronize_rcu(); 6130 6131 ixgbe_irq_disable(adapter); 6132 6133 ixgbe_napi_disable_all(adapter); 6134 6135 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6136 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6137 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6138 6139 del_timer_sync(&adapter->service_timer); 6140 6141 if (adapter->num_vfs) { 6142 /* Clear EITR Select mapping */ 6143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6144 6145 /* Mark all the VFs as inactive */ 6146 for (i = 0 ; i < adapter->num_vfs; i++) 6147 adapter->vfinfo[i].clear_to_send = false; 6148 6149 /* update setting rx tx for all active vfs */ 6150 ixgbe_set_all_vfs(adapter); 6151 } 6152 6153 /* disable transmits in the hardware now that interrupts are off */ 6154 ixgbe_disable_tx(adapter); 6155 6156 if (!pci_channel_offline(adapter->pdev)) 6157 ixgbe_reset(adapter); 6158 6159 /* power down the optics for 82599 SFP+ fiber */ 6160 if (hw->mac.ops.disable_tx_laser) 6161 hw->mac.ops.disable_tx_laser(hw); 6162 6163 ixgbe_clean_all_tx_rings(adapter); 6164 ixgbe_clean_all_rx_rings(adapter); 6165} 6166 6167/** 6168 * ixgbe_eee_capable - helper function to determine EEE support on X550 6169 * @adapter: board private structure 6170 */ 6171static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6172{ 6173 struct ixgbe_hw *hw = &adapter->hw; 6174 6175 switch (hw->device_id) { 6176 case IXGBE_DEV_ID_X550EM_A_1G_T: 6177 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6178 if (!hw->phy.eee_speeds_supported) 6179 break; 6180 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6181 if (!hw->phy.eee_speeds_advertised) 6182 break; 6183 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6184 break; 6185 default: 6186 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6187 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6188 break; 6189 } 6190} 6191 6192/** 6193 * ixgbe_tx_timeout - Respond to a Tx Hang 6194 * @netdev: network interface device structure 6195 * @txqueue: queue number that timed out 6196 **/ 6197static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6198{ 6199 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6200 6201 /* Do the reset outside of interrupt context */ 6202 ixgbe_tx_timeout_reset(adapter); 6203} 6204 6205#ifdef CONFIG_IXGBE_DCB 6206static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6207{ 6208 struct ixgbe_hw *hw = &adapter->hw; 6209 struct tc_configuration *tc; 6210 int j; 6211 6212 switch (hw->mac.type) { 6213 case ixgbe_mac_82598EB: 6214 case ixgbe_mac_82599EB: 6215 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6216 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6217 break; 6218 case ixgbe_mac_X540: 6219 case ixgbe_mac_X550: 6220 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6221 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6222 break; 6223 case ixgbe_mac_X550EM_x: 6224 case ixgbe_mac_x550em_a: 6225 default: 6226 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6227 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6228 break; 6229 } 6230 6231 /* Configure DCB traffic classes */ 6232 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6233 tc = &adapter->dcb_cfg.tc_config[j]; 6234 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6235 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6236 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6237 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6238 tc->dcb_pfc = pfc_disabled; 6239 } 6240 6241 /* Initialize default user to priority mapping, UPx->TC0 */ 6242 tc = &adapter->dcb_cfg.tc_config[0]; 6243 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6244 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6245 6246 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6247 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6248 adapter->dcb_cfg.pfc_mode_enable = false; 6249 adapter->dcb_set_bitmap = 0x00; 6250 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6251 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6252 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6253 sizeof(adapter->temp_dcb_cfg)); 6254} 6255#endif 6256 6257/** 6258 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6259 * @adapter: board private structure to initialize 6260 * @ii: pointer to ixgbe_info for device 6261 * 6262 * ixgbe_sw_init initializes the Adapter private data structure. 6263 * Fields are initialized based on PCI device information and 6264 * OS network device settings (MTU size). 6265 **/ 6266static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6267 const struct ixgbe_info *ii) 6268{ 6269 struct ixgbe_hw *hw = &adapter->hw; 6270 struct pci_dev *pdev = adapter->pdev; 6271 unsigned int rss, fdir; 6272 u32 fwsm; 6273 int i; 6274 6275 /* PCI config space info */ 6276 6277 hw->vendor_id = pdev->vendor; 6278 hw->device_id = pdev->device; 6279 hw->revision_id = pdev->revision; 6280 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6281 hw->subsystem_device_id = pdev->subsystem_device; 6282 6283 /* get_invariants needs the device IDs */ 6284 ii->get_invariants(hw); 6285 6286 /* Set common capability flags and settings */ 6287 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6288 adapter->ring_feature[RING_F_RSS].limit = rss; 6289 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6290 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6291 adapter->atr_sample_rate = 20; 6292 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6293 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6294 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6295 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6296#ifdef CONFIG_IXGBE_DCA 6297 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6298#endif 6299#ifdef CONFIG_IXGBE_DCB 6300 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6301 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6302#endif 6303#ifdef IXGBE_FCOE 6304 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6305 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6306#ifdef CONFIG_IXGBE_DCB 6307 /* Default traffic class to use for FCoE */ 6308 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6309#endif /* CONFIG_IXGBE_DCB */ 6310#endif /* IXGBE_FCOE */ 6311 6312 /* initialize static ixgbe jump table entries */ 6313 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6314 GFP_KERNEL); 6315 if (!adapter->jump_tables[0]) 6316 return -ENOMEM; 6317 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6318 6319 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6320 adapter->jump_tables[i] = NULL; 6321 6322 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6323 sizeof(struct ixgbe_mac_addr), 6324 GFP_KERNEL); 6325 if (!adapter->mac_table) 6326 return -ENOMEM; 6327 6328 if (ixgbe_init_rss_key(adapter)) 6329 return -ENOMEM; 6330 6331 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL); 6332 if (!adapter->af_xdp_zc_qps) 6333 return -ENOMEM; 6334 6335 /* Set MAC specific capability flags and exceptions */ 6336 switch (hw->mac.type) { 6337 case ixgbe_mac_82598EB: 6338 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6339 6340 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6341 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6342 6343 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6344 adapter->ring_feature[RING_F_FDIR].limit = 0; 6345 adapter->atr_sample_rate = 0; 6346 adapter->fdir_pballoc = 0; 6347#ifdef IXGBE_FCOE 6348 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6349 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6350#ifdef CONFIG_IXGBE_DCB 6351 adapter->fcoe.up = 0; 6352#endif /* IXGBE_DCB */ 6353#endif /* IXGBE_FCOE */ 6354 break; 6355 case ixgbe_mac_82599EB: 6356 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6357 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6358 break; 6359 case ixgbe_mac_X540: 6360 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6361 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6362 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6363 break; 6364 case ixgbe_mac_x550em_a: 6365 switch (hw->device_id) { 6366 case IXGBE_DEV_ID_X550EM_A_1G_T: 6367 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6368 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6369 break; 6370 default: 6371 break; 6372 } 6373 fallthrough; 6374 case ixgbe_mac_X550EM_x: 6375#ifdef CONFIG_IXGBE_DCB 6376 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6377#endif 6378#ifdef IXGBE_FCOE 6379 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6380#ifdef CONFIG_IXGBE_DCB 6381 adapter->fcoe.up = 0; 6382#endif /* IXGBE_DCB */ 6383#endif /* IXGBE_FCOE */ 6384 fallthrough; 6385 case ixgbe_mac_X550: 6386 if (hw->mac.type == ixgbe_mac_X550) 6387 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6388#ifdef CONFIG_IXGBE_DCA 6389 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6390#endif 6391 break; 6392 default: 6393 break; 6394 } 6395 6396#ifdef IXGBE_FCOE 6397 /* FCoE support exists, always init the FCoE lock */ 6398 spin_lock_init(&adapter->fcoe.lock); 6399 6400#endif 6401 /* n-tuple support exists, always init our spinlock */ 6402 spin_lock_init(&adapter->fdir_perfect_lock); 6403 6404 /* init spinlock to avoid concurrency of VF resources */ 6405 spin_lock_init(&adapter->vfs_lock); 6406 6407#ifdef CONFIG_IXGBE_DCB 6408 ixgbe_init_dcb(adapter); 6409#endif 6410 ixgbe_init_ipsec_offload(adapter); 6411 6412 /* default flow control settings */ 6413 hw->fc.requested_mode = ixgbe_fc_full; 6414 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6415 ixgbe_pbthresh_setup(adapter); 6416 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6417 hw->fc.send_xon = true; 6418 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6419 6420#ifdef CONFIG_PCI_IOV 6421 if (max_vfs > 0) 6422 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6423 6424 /* assign number of SR-IOV VFs */ 6425 if (hw->mac.type != ixgbe_mac_82598EB) { 6426 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6427 max_vfs = 0; 6428 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6429 } 6430 } 6431#endif /* CONFIG_PCI_IOV */ 6432 6433 /* enable itr by default in dynamic mode */ 6434 adapter->rx_itr_setting = 1; 6435 adapter->tx_itr_setting = 1; 6436 6437 /* set default ring sizes */ 6438 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6439 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6440 6441 /* set default work limits */ 6442 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6443 6444 /* initialize eeprom parameters */ 6445 if (ixgbe_init_eeprom_params_generic(hw)) { 6446 e_dev_err("EEPROM initialization failed\n"); 6447 return -EIO; 6448 } 6449 6450 /* PF holds first pool slot */ 6451 set_bit(0, adapter->fwd_bitmask); 6452 set_bit(__IXGBE_DOWN, &adapter->state); 6453 6454 return 0; 6455} 6456 6457/** 6458 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6459 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6460 * 6461 * Return 0 on success, negative on failure 6462 **/ 6463int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6464{ 6465 struct device *dev = tx_ring->dev; 6466 int orig_node = dev_to_node(dev); 6467 int ring_node = NUMA_NO_NODE; 6468 int size; 6469 6470 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6471 6472 if (tx_ring->q_vector) 6473 ring_node = tx_ring->q_vector->numa_node; 6474 6475 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6476 if (!tx_ring->tx_buffer_info) 6477 tx_ring->tx_buffer_info = vmalloc(size); 6478 if (!tx_ring->tx_buffer_info) 6479 goto err; 6480 6481 /* round up to nearest 4K */ 6482 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6483 tx_ring->size = ALIGN(tx_ring->size, 4096); 6484 6485 set_dev_node(dev, ring_node); 6486 tx_ring->desc = dma_alloc_coherent(dev, 6487 tx_ring->size, 6488 &tx_ring->dma, 6489 GFP_KERNEL); 6490 set_dev_node(dev, orig_node); 6491 if (!tx_ring->desc) 6492 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6493 &tx_ring->dma, GFP_KERNEL); 6494 if (!tx_ring->desc) 6495 goto err; 6496 6497 tx_ring->next_to_use = 0; 6498 tx_ring->next_to_clean = 0; 6499 return 0; 6500 6501err: 6502 vfree(tx_ring->tx_buffer_info); 6503 tx_ring->tx_buffer_info = NULL; 6504 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6505 return -ENOMEM; 6506} 6507 6508/** 6509 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6510 * @adapter: board private structure 6511 * 6512 * If this function returns with an error, then it's possible one or 6513 * more of the rings is populated (while the rest are not). It is the 6514 * callers duty to clean those orphaned rings. 6515 * 6516 * Return 0 on success, negative on failure 6517 **/ 6518static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6519{ 6520 int i, j = 0, err = 0; 6521 6522 for (i = 0; i < adapter->num_tx_queues; i++) { 6523 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6524 if (!err) 6525 continue; 6526 6527 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6528 goto err_setup_tx; 6529 } 6530 for (j = 0; j < adapter->num_xdp_queues; j++) { 6531 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6532 if (!err) 6533 continue; 6534 6535 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6536 goto err_setup_tx; 6537 } 6538 6539 return 0; 6540err_setup_tx: 6541 /* rewind the index freeing the rings as we go */ 6542 while (j--) 6543 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6544 while (i--) 6545 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6546 return err; 6547} 6548 6549/** 6550 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6551 * @adapter: pointer to ixgbe_adapter 6552 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6553 * 6554 * Returns 0 on success, negative on failure 6555 **/ 6556int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6557 struct ixgbe_ring *rx_ring) 6558{ 6559 struct device *dev = rx_ring->dev; 6560 int orig_node = dev_to_node(dev); 6561 int ring_node = NUMA_NO_NODE; 6562 int size; 6563 6564 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6565 6566 if (rx_ring->q_vector) 6567 ring_node = rx_ring->q_vector->numa_node; 6568 6569 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6570 if (!rx_ring->rx_buffer_info) 6571 rx_ring->rx_buffer_info = vmalloc(size); 6572 if (!rx_ring->rx_buffer_info) 6573 goto err; 6574 6575 /* Round up to nearest 4K */ 6576 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6577 rx_ring->size = ALIGN(rx_ring->size, 4096); 6578 6579 set_dev_node(dev, ring_node); 6580 rx_ring->desc = dma_alloc_coherent(dev, 6581 rx_ring->size, 6582 &rx_ring->dma, 6583 GFP_KERNEL); 6584 set_dev_node(dev, orig_node); 6585 if (!rx_ring->desc) 6586 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6587 &rx_ring->dma, GFP_KERNEL); 6588 if (!rx_ring->desc) 6589 goto err; 6590 6591 rx_ring->next_to_clean = 0; 6592 rx_ring->next_to_use = 0; 6593 6594 /* XDP RX-queue info */ 6595 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6596 rx_ring->queue_index) < 0) 6597 goto err; 6598 6599 rx_ring->xdp_prog = adapter->xdp_prog; 6600 6601 return 0; 6602err: 6603 vfree(rx_ring->rx_buffer_info); 6604 rx_ring->rx_buffer_info = NULL; 6605 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6606 return -ENOMEM; 6607} 6608 6609/** 6610 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6611 * @adapter: board private structure 6612 * 6613 * If this function returns with an error, then it's possible one or 6614 * more of the rings is populated (while the rest are not). It is the 6615 * callers duty to clean those orphaned rings. 6616 * 6617 * Return 0 on success, negative on failure 6618 **/ 6619static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6620{ 6621 int i, err = 0; 6622 6623 for (i = 0; i < adapter->num_rx_queues; i++) { 6624 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6625 if (!err) 6626 continue; 6627 6628 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6629 goto err_setup_rx; 6630 } 6631 6632#ifdef IXGBE_FCOE 6633 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6634 if (!err) 6635#endif 6636 return 0; 6637err_setup_rx: 6638 /* rewind the index freeing the rings as we go */ 6639 while (i--) 6640 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6641 return err; 6642} 6643 6644/** 6645 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6646 * @tx_ring: Tx descriptor ring for a specific queue 6647 * 6648 * Free all transmit software resources 6649 **/ 6650void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6651{ 6652 ixgbe_clean_tx_ring(tx_ring); 6653 6654 vfree(tx_ring->tx_buffer_info); 6655 tx_ring->tx_buffer_info = NULL; 6656 6657 /* if not set, then don't free */ 6658 if (!tx_ring->desc) 6659 return; 6660 6661 dma_free_coherent(tx_ring->dev, tx_ring->size, 6662 tx_ring->desc, tx_ring->dma); 6663 6664 tx_ring->desc = NULL; 6665} 6666 6667/** 6668 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6669 * @adapter: board private structure 6670 * 6671 * Free all transmit software resources 6672 **/ 6673static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6674{ 6675 int i; 6676 6677 for (i = 0; i < adapter->num_tx_queues; i++) 6678 if (adapter->tx_ring[i]->desc) 6679 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6680 for (i = 0; i < adapter->num_xdp_queues; i++) 6681 if (adapter->xdp_ring[i]->desc) 6682 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6683} 6684 6685/** 6686 * ixgbe_free_rx_resources - Free Rx Resources 6687 * @rx_ring: ring to clean the resources from 6688 * 6689 * Free all receive software resources 6690 **/ 6691void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6692{ 6693 ixgbe_clean_rx_ring(rx_ring); 6694 6695 rx_ring->xdp_prog = NULL; 6696 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6697 vfree(rx_ring->rx_buffer_info); 6698 rx_ring->rx_buffer_info = NULL; 6699 6700 /* if not set, then don't free */ 6701 if (!rx_ring->desc) 6702 return; 6703 6704 dma_free_coherent(rx_ring->dev, rx_ring->size, 6705 rx_ring->desc, rx_ring->dma); 6706 6707 rx_ring->desc = NULL; 6708} 6709 6710/** 6711 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6712 * @adapter: board private structure 6713 * 6714 * Free all receive software resources 6715 **/ 6716static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6717{ 6718 int i; 6719 6720#ifdef IXGBE_FCOE 6721 ixgbe_free_fcoe_ddp_resources(adapter); 6722 6723#endif 6724 for (i = 0; i < adapter->num_rx_queues; i++) 6725 if (adapter->rx_ring[i]->desc) 6726 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6727} 6728 6729/** 6730 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 6731 * @adapter: device handle, pointer to adapter 6732 */ 6733static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 6734{ 6735 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 6736 return IXGBE_RXBUFFER_2K; 6737 else 6738 return IXGBE_RXBUFFER_3K; 6739} 6740 6741/** 6742 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6743 * @netdev: network interface device structure 6744 * @new_mtu: new value for maximum frame size 6745 * 6746 * Returns 0 on success, negative on failure 6747 **/ 6748static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6749{ 6750 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6751 6752 if (ixgbe_enabled_xdp_adapter(adapter)) { 6753 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 6754 6755 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 6756 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6757 return -EINVAL; 6758 } 6759 } 6760 6761 /* 6762 * For 82599EB we cannot allow legacy VFs to enable their receive 6763 * paths when MTU greater than 1500 is configured. So display a 6764 * warning that legacy VFs will be disabled. 6765 */ 6766 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6767 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6768 (new_mtu > ETH_DATA_LEN)) 6769 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6770 6771 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6772 netdev->mtu, new_mtu); 6773 6774 /* must set new MTU before calling down or up */ 6775 netdev->mtu = new_mtu; 6776 6777 if (netif_running(netdev)) 6778 ixgbe_reinit_locked(adapter); 6779 6780 return 0; 6781} 6782 6783/** 6784 * ixgbe_open - Called when a network interface is made active 6785 * @netdev: network interface device structure 6786 * 6787 * Returns 0 on success, negative value on failure 6788 * 6789 * The open entry point is called when a network interface is made 6790 * active by the system (IFF_UP). At this point all resources needed 6791 * for transmit and receive operations are allocated, the interrupt 6792 * handler is registered with the OS, the watchdog timer is started, 6793 * and the stack is notified that the interface is ready. 6794 **/ 6795int ixgbe_open(struct net_device *netdev) 6796{ 6797 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6798 struct ixgbe_hw *hw = &adapter->hw; 6799 int err, queues; 6800 6801 /* disallow open during test */ 6802 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6803 return -EBUSY; 6804 6805 netif_carrier_off(netdev); 6806 6807 /* allocate transmit descriptors */ 6808 err = ixgbe_setup_all_tx_resources(adapter); 6809 if (err) 6810 goto err_setup_tx; 6811 6812 /* allocate receive descriptors */ 6813 err = ixgbe_setup_all_rx_resources(adapter); 6814 if (err) 6815 goto err_setup_rx; 6816 6817 ixgbe_configure(adapter); 6818 6819 err = ixgbe_request_irq(adapter); 6820 if (err) 6821 goto err_req_irq; 6822 6823 /* Notify the stack of the actual queue counts. */ 6824 queues = adapter->num_tx_queues; 6825 err = netif_set_real_num_tx_queues(netdev, queues); 6826 if (err) 6827 goto err_set_queues; 6828 6829 queues = adapter->num_rx_queues; 6830 err = netif_set_real_num_rx_queues(netdev, queues); 6831 if (err) 6832 goto err_set_queues; 6833 6834 ixgbe_ptp_init(adapter); 6835 6836 ixgbe_up_complete(adapter); 6837 6838 udp_tunnel_nic_reset_ntf(netdev); 6839 6840 return 0; 6841 6842err_set_queues: 6843 ixgbe_free_irq(adapter); 6844err_req_irq: 6845 ixgbe_free_all_rx_resources(adapter); 6846 if (hw->phy.ops.set_phy_power && !adapter->wol) 6847 hw->phy.ops.set_phy_power(&adapter->hw, false); 6848err_setup_rx: 6849 ixgbe_free_all_tx_resources(adapter); 6850err_setup_tx: 6851 ixgbe_reset(adapter); 6852 6853 return err; 6854} 6855 6856static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6857{ 6858 ixgbe_ptp_suspend(adapter); 6859 6860 if (adapter->hw.phy.ops.enter_lplu) { 6861 adapter->hw.phy.reset_disable = true; 6862 ixgbe_down(adapter); 6863 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6864 adapter->hw.phy.reset_disable = false; 6865 } else { 6866 ixgbe_down(adapter); 6867 } 6868 6869 ixgbe_free_irq(adapter); 6870 6871 ixgbe_free_all_tx_resources(adapter); 6872 ixgbe_free_all_rx_resources(adapter); 6873} 6874 6875/** 6876 * ixgbe_close - Disables a network interface 6877 * @netdev: network interface device structure 6878 * 6879 * Returns 0, this is not allowed to fail 6880 * 6881 * The close entry point is called when an interface is de-activated 6882 * by the OS. The hardware is still under the drivers control, but 6883 * needs to be disabled. A global MAC reset is issued to stop the 6884 * hardware, and all transmit and receive resources are freed. 6885 **/ 6886int ixgbe_close(struct net_device *netdev) 6887{ 6888 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6889 6890 ixgbe_ptp_stop(adapter); 6891 6892 if (netif_device_present(netdev)) 6893 ixgbe_close_suspend(adapter); 6894 6895 ixgbe_fdir_filter_exit(adapter); 6896 6897 ixgbe_release_hw_control(adapter); 6898 6899 return 0; 6900} 6901 6902static int __maybe_unused ixgbe_resume(struct device *dev_d) 6903{ 6904 struct pci_dev *pdev = to_pci_dev(dev_d); 6905 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6906 struct net_device *netdev = adapter->netdev; 6907 u32 err; 6908 6909 adapter->hw.hw_addr = adapter->io_addr; 6910 6911 err = pci_enable_device_mem(pdev); 6912 if (err) { 6913 e_dev_err("Cannot enable PCI device from suspend\n"); 6914 return err; 6915 } 6916 smp_mb__before_atomic(); 6917 clear_bit(__IXGBE_DISABLED, &adapter->state); 6918 pci_set_master(pdev); 6919 6920 device_wakeup_disable(dev_d); 6921 6922 ixgbe_reset(adapter); 6923 6924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6925 6926 rtnl_lock(); 6927 err = ixgbe_init_interrupt_scheme(adapter); 6928 if (!err && netif_running(netdev)) 6929 err = ixgbe_open(netdev); 6930 6931 6932 if (!err) 6933 netif_device_attach(netdev); 6934 rtnl_unlock(); 6935 6936 return err; 6937} 6938 6939static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6940{ 6941 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6942 struct net_device *netdev = adapter->netdev; 6943 struct ixgbe_hw *hw = &adapter->hw; 6944 u32 ctrl; 6945 u32 wufc = adapter->wol; 6946 6947 rtnl_lock(); 6948 netif_device_detach(netdev); 6949 6950 if (netif_running(netdev)) 6951 ixgbe_close_suspend(adapter); 6952 6953 ixgbe_clear_interrupt_scheme(adapter); 6954 rtnl_unlock(); 6955 6956 if (hw->mac.ops.stop_link_on_d3) 6957 hw->mac.ops.stop_link_on_d3(hw); 6958 6959 if (wufc) { 6960 u32 fctrl; 6961 6962 ixgbe_set_rx_mode(netdev); 6963 6964 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6965 if (hw->mac.ops.enable_tx_laser) 6966 hw->mac.ops.enable_tx_laser(hw); 6967 6968 /* enable the reception of multicast packets */ 6969 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6970 fctrl |= IXGBE_FCTRL_MPE; 6971 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6972 6973 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6974 ctrl |= IXGBE_CTRL_GIO_DIS; 6975 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6976 6977 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6978 } else { 6979 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6980 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6981 } 6982 6983 switch (hw->mac.type) { 6984 case ixgbe_mac_82598EB: 6985 pci_wake_from_d3(pdev, false); 6986 break; 6987 case ixgbe_mac_82599EB: 6988 case ixgbe_mac_X540: 6989 case ixgbe_mac_X550: 6990 case ixgbe_mac_X550EM_x: 6991 case ixgbe_mac_x550em_a: 6992 pci_wake_from_d3(pdev, !!wufc); 6993 break; 6994 default: 6995 break; 6996 } 6997 6998 *enable_wake = !!wufc; 6999 if (hw->phy.ops.set_phy_power && !*enable_wake) 7000 hw->phy.ops.set_phy_power(hw, false); 7001 7002 ixgbe_release_hw_control(adapter); 7003 7004 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7005 pci_disable_device(pdev); 7006 7007 return 0; 7008} 7009 7010static int __maybe_unused ixgbe_suspend(struct device *dev_d) 7011{ 7012 struct pci_dev *pdev = to_pci_dev(dev_d); 7013 int retval; 7014 bool wake; 7015 7016 retval = __ixgbe_shutdown(pdev, &wake); 7017 7018 device_set_wakeup_enable(dev_d, wake); 7019 7020 return retval; 7021} 7022 7023static void ixgbe_shutdown(struct pci_dev *pdev) 7024{ 7025 bool wake; 7026 7027 __ixgbe_shutdown(pdev, &wake); 7028 7029 if (system_state == SYSTEM_POWER_OFF) { 7030 pci_wake_from_d3(pdev, wake); 7031 pci_set_power_state(pdev, PCI_D3hot); 7032 } 7033} 7034 7035/** 7036 * ixgbe_update_stats - Update the board statistics counters. 7037 * @adapter: board private structure 7038 **/ 7039void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7040{ 7041 struct net_device *netdev = adapter->netdev; 7042 struct ixgbe_hw *hw = &adapter->hw; 7043 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7044 u64 total_mpc = 0; 7045 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7046 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7047 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7048 u64 alloc_rx_page = 0; 7049 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7050 7051 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7052 test_bit(__IXGBE_RESETTING, &adapter->state)) 7053 return; 7054 7055 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7056 u64 rsc_count = 0; 7057 u64 rsc_flush = 0; 7058 for (i = 0; i < adapter->num_rx_queues; i++) { 7059 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7060 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7061 } 7062 adapter->rsc_total_count = rsc_count; 7063 adapter->rsc_total_flush = rsc_flush; 7064 } 7065 7066 for (i = 0; i < adapter->num_rx_queues; i++) { 7067 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7068 7069 if (!rx_ring) 7070 continue; 7071 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7072 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7073 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7074 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7075 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7076 bytes += rx_ring->stats.bytes; 7077 packets += rx_ring->stats.packets; 7078 } 7079 adapter->non_eop_descs = non_eop_descs; 7080 adapter->alloc_rx_page = alloc_rx_page; 7081 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7082 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7083 adapter->hw_csum_rx_error = hw_csum_rx_error; 7084 netdev->stats.rx_bytes = bytes; 7085 netdev->stats.rx_packets = packets; 7086 7087 bytes = 0; 7088 packets = 0; 7089 /* gather some stats to the adapter struct that are per queue */ 7090 for (i = 0; i < adapter->num_tx_queues; i++) { 7091 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7092 7093 if (!tx_ring) 7094 continue; 7095 restart_queue += tx_ring->tx_stats.restart_queue; 7096 tx_busy += tx_ring->tx_stats.tx_busy; 7097 bytes += tx_ring->stats.bytes; 7098 packets += tx_ring->stats.packets; 7099 } 7100 for (i = 0; i < adapter->num_xdp_queues; i++) { 7101 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7102 7103 if (!xdp_ring) 7104 continue; 7105 restart_queue += xdp_ring->tx_stats.restart_queue; 7106 tx_busy += xdp_ring->tx_stats.tx_busy; 7107 bytes += xdp_ring->stats.bytes; 7108 packets += xdp_ring->stats.packets; 7109 } 7110 adapter->restart_queue = restart_queue; 7111 adapter->tx_busy = tx_busy; 7112 netdev->stats.tx_bytes = bytes; 7113 netdev->stats.tx_packets = packets; 7114 7115 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7116 7117 /* 8 register reads */ 7118 for (i = 0; i < 8; i++) { 7119 /* for packet buffers not used, the register should read 0 */ 7120 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7121 missed_rx += mpc; 7122 hwstats->mpc[i] += mpc; 7123 total_mpc += hwstats->mpc[i]; 7124 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7125 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7126 switch (hw->mac.type) { 7127 case ixgbe_mac_82598EB: 7128 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7129 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7130 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7131 hwstats->pxonrxc[i] += 7132 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7133 break; 7134 case ixgbe_mac_82599EB: 7135 case ixgbe_mac_X540: 7136 case ixgbe_mac_X550: 7137 case ixgbe_mac_X550EM_x: 7138 case ixgbe_mac_x550em_a: 7139 hwstats->pxonrxc[i] += 7140 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7141 break; 7142 default: 7143 break; 7144 } 7145 } 7146 7147 /*16 register reads */ 7148 for (i = 0; i < 16; i++) { 7149 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7150 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7151 if ((hw->mac.type == ixgbe_mac_82599EB) || 7152 (hw->mac.type == ixgbe_mac_X540) || 7153 (hw->mac.type == ixgbe_mac_X550) || 7154 (hw->mac.type == ixgbe_mac_X550EM_x) || 7155 (hw->mac.type == ixgbe_mac_x550em_a)) { 7156 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7157 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7158 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7159 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7160 } 7161 } 7162 7163 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7164 /* work around hardware counting issue */ 7165 hwstats->gprc -= missed_rx; 7166 7167 ixgbe_update_xoff_received(adapter); 7168 7169 /* 82598 hardware only has a 32 bit counter in the high register */ 7170 switch (hw->mac.type) { 7171 case ixgbe_mac_82598EB: 7172 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7173 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7174 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7175 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7176 break; 7177 case ixgbe_mac_X540: 7178 case ixgbe_mac_X550: 7179 case ixgbe_mac_X550EM_x: 7180 case ixgbe_mac_x550em_a: 7181 /* OS2BMC stats are X540 and later */ 7182 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7183 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7184 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7185 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7186 fallthrough; 7187 case ixgbe_mac_82599EB: 7188 for (i = 0; i < 16; i++) 7189 adapter->hw_rx_no_dma_resources += 7190 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7191 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7192 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7193 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7194 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7195 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7196 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7197 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7198 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7199 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7200#ifdef IXGBE_FCOE 7201 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7202 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7203 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7204 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7205 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7206 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7207 /* Add up per cpu counters for total ddp aloc fail */ 7208 if (adapter->fcoe.ddp_pool) { 7209 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7210 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7211 unsigned int cpu; 7212 u64 noddp = 0, noddp_ext_buff = 0; 7213 for_each_possible_cpu(cpu) { 7214 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7215 noddp += ddp_pool->noddp; 7216 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7217 } 7218 hwstats->fcoe_noddp = noddp; 7219 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7220 } 7221#endif /* IXGBE_FCOE */ 7222 break; 7223 default: 7224 break; 7225 } 7226 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7227 hwstats->bprc += bprc; 7228 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7229 if (hw->mac.type == ixgbe_mac_82598EB) 7230 hwstats->mprc -= bprc; 7231 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7232 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7233 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7234 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7235 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7236 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7237 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7238 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7239 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7240 hwstats->lxontxc += lxon; 7241 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7242 hwstats->lxofftxc += lxoff; 7243 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7244 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7245 /* 7246 * 82598 errata - tx of flow control packets is included in tx counters 7247 */ 7248 xon_off_tot = lxon + lxoff; 7249 hwstats->gptc -= xon_off_tot; 7250 hwstats->mptc -= xon_off_tot; 7251 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7252 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7253 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7254 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7255 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7256 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7257 hwstats->ptc64 -= xon_off_tot; 7258 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7259 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7260 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7261 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7262 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7263 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7264 7265 /* Fill out the OS statistics structure */ 7266 netdev->stats.multicast = hwstats->mprc; 7267 7268 /* Rx Errors */ 7269 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7270 netdev->stats.rx_dropped = 0; 7271 netdev->stats.rx_length_errors = hwstats->rlec; 7272 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7273 netdev->stats.rx_missed_errors = total_mpc; 7274} 7275 7276/** 7277 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7278 * @adapter: pointer to the device adapter structure 7279 **/ 7280static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7281{ 7282 struct ixgbe_hw *hw = &adapter->hw; 7283 int i; 7284 7285 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7286 return; 7287 7288 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7289 7290 /* if interface is down do nothing */ 7291 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7292 return; 7293 7294 /* do nothing if we are not using signature filters */ 7295 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7296 return; 7297 7298 adapter->fdir_overflow++; 7299 7300 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7301 for (i = 0; i < adapter->num_tx_queues; i++) 7302 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7303 &(adapter->tx_ring[i]->state)); 7304 for (i = 0; i < adapter->num_xdp_queues; i++) 7305 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7306 &adapter->xdp_ring[i]->state); 7307 /* re-enable flow director interrupts */ 7308 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7309 } else { 7310 e_err(probe, "failed to finish FDIR re-initialization, " 7311 "ignored adding FDIR ATR filters\n"); 7312 } 7313} 7314 7315/** 7316 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7317 * @adapter: pointer to the device adapter structure 7318 * 7319 * This function serves two purposes. First it strobes the interrupt lines 7320 * in order to make certain interrupts are occurring. Secondly it sets the 7321 * bits needed to check for TX hangs. As a result we should immediately 7322 * determine if a hang has occurred. 7323 */ 7324static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7325{ 7326 struct ixgbe_hw *hw = &adapter->hw; 7327 u64 eics = 0; 7328 int i; 7329 7330 /* If we're down, removing or resetting, just bail */ 7331 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7332 test_bit(__IXGBE_REMOVING, &adapter->state) || 7333 test_bit(__IXGBE_RESETTING, &adapter->state)) 7334 return; 7335 7336 /* Force detection of hung controller */ 7337 if (netif_carrier_ok(adapter->netdev)) { 7338 for (i = 0; i < adapter->num_tx_queues; i++) 7339 set_check_for_tx_hang(adapter->tx_ring[i]); 7340 for (i = 0; i < adapter->num_xdp_queues; i++) 7341 set_check_for_tx_hang(adapter->xdp_ring[i]); 7342 } 7343 7344 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7345 /* 7346 * for legacy and MSI interrupts don't set any bits 7347 * that are enabled for EIAM, because this operation 7348 * would set *both* EIMS and EICS for any bit in EIAM 7349 */ 7350 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7351 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7352 } else { 7353 /* get one bit for every active tx/rx interrupt vector */ 7354 for (i = 0; i < adapter->num_q_vectors; i++) { 7355 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7356 if (qv->rx.ring || qv->tx.ring) 7357 eics |= BIT_ULL(i); 7358 } 7359 } 7360 7361 /* Cause software interrupt to ensure rings are cleaned */ 7362 ixgbe_irq_rearm_queues(adapter, eics); 7363} 7364 7365/** 7366 * ixgbe_watchdog_update_link - update the link status 7367 * @adapter: pointer to the device adapter structure 7368 **/ 7369static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7370{ 7371 struct ixgbe_hw *hw = &adapter->hw; 7372 u32 link_speed = adapter->link_speed; 7373 bool link_up = adapter->link_up; 7374 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7375 7376 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7377 return; 7378 7379 if (hw->mac.ops.check_link) { 7380 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7381 } else { 7382 /* always assume link is up, if no check link function */ 7383 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7384 link_up = true; 7385 } 7386 7387 if (adapter->ixgbe_ieee_pfc) 7388 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7389 7390 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7391 hw->mac.ops.fc_enable(hw); 7392 ixgbe_set_rx_drop_en(adapter); 7393 } 7394 7395 if (link_up || 7396 time_after(jiffies, (adapter->link_check_timeout + 7397 IXGBE_TRY_LINK_TIMEOUT))) { 7398 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7399 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7400 IXGBE_WRITE_FLUSH(hw); 7401 } 7402 7403 adapter->link_up = link_up; 7404 adapter->link_speed = link_speed; 7405} 7406 7407static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7408{ 7409#ifdef CONFIG_IXGBE_DCB 7410 struct net_device *netdev = adapter->netdev; 7411 struct dcb_app app = { 7412 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7413 .protocol = 0, 7414 }; 7415 u8 up = 0; 7416 7417 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7418 up = dcb_ieee_getapp_mask(netdev, &app); 7419 7420 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7421#endif 7422} 7423 7424/** 7425 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7426 * print link up message 7427 * @adapter: pointer to the device adapter structure 7428 **/ 7429static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7430{ 7431 struct net_device *netdev = adapter->netdev; 7432 struct ixgbe_hw *hw = &adapter->hw; 7433 u32 link_speed = adapter->link_speed; 7434 const char *speed_str; 7435 bool flow_rx, flow_tx; 7436 7437 /* only continue if link was previously down */ 7438 if (netif_carrier_ok(netdev)) 7439 return; 7440 7441 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7442 7443 switch (hw->mac.type) { 7444 case ixgbe_mac_82598EB: { 7445 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7446 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7447 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7448 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7449 } 7450 break; 7451 case ixgbe_mac_X540: 7452 case ixgbe_mac_X550: 7453 case ixgbe_mac_X550EM_x: 7454 case ixgbe_mac_x550em_a: 7455 case ixgbe_mac_82599EB: { 7456 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7457 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7458 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7459 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7460 } 7461 break; 7462 default: 7463 flow_tx = false; 7464 flow_rx = false; 7465 break; 7466 } 7467 7468 adapter->last_rx_ptp_check = jiffies; 7469 7470 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7471 ixgbe_ptp_start_cyclecounter(adapter); 7472 7473 switch (link_speed) { 7474 case IXGBE_LINK_SPEED_10GB_FULL: 7475 speed_str = "10 Gbps"; 7476 break; 7477 case IXGBE_LINK_SPEED_5GB_FULL: 7478 speed_str = "5 Gbps"; 7479 break; 7480 case IXGBE_LINK_SPEED_2_5GB_FULL: 7481 speed_str = "2.5 Gbps"; 7482 break; 7483 case IXGBE_LINK_SPEED_1GB_FULL: 7484 speed_str = "1 Gbps"; 7485 break; 7486 case IXGBE_LINK_SPEED_100_FULL: 7487 speed_str = "100 Mbps"; 7488 break; 7489 case IXGBE_LINK_SPEED_10_FULL: 7490 speed_str = "10 Mbps"; 7491 break; 7492 default: 7493 speed_str = "unknown speed"; 7494 break; 7495 } 7496 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7497 ((flow_rx && flow_tx) ? "RX/TX" : 7498 (flow_rx ? "RX" : 7499 (flow_tx ? "TX" : "None")))); 7500 7501 netif_carrier_on(netdev); 7502 ixgbe_check_vf_rate_limit(adapter); 7503 7504 /* enable transmits */ 7505 netif_tx_wake_all_queues(adapter->netdev); 7506 7507 /* update the default user priority for VFs */ 7508 ixgbe_update_default_up(adapter); 7509 7510 /* ping all the active vfs to let them know link has changed */ 7511 ixgbe_ping_all_vfs(adapter); 7512} 7513 7514/** 7515 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7516 * print link down message 7517 * @adapter: pointer to the adapter structure 7518 **/ 7519static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7520{ 7521 struct net_device *netdev = adapter->netdev; 7522 struct ixgbe_hw *hw = &adapter->hw; 7523 7524 adapter->link_up = false; 7525 adapter->link_speed = 0; 7526 7527 /* only continue if link was up previously */ 7528 if (!netif_carrier_ok(netdev)) 7529 return; 7530 7531 /* poll for SFP+ cable when link is down */ 7532 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7533 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7534 7535 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7536 ixgbe_ptp_start_cyclecounter(adapter); 7537 7538 e_info(drv, "NIC Link is Down\n"); 7539 netif_carrier_off(netdev); 7540 7541 /* ping all the active vfs to let them know link has changed */ 7542 ixgbe_ping_all_vfs(adapter); 7543} 7544 7545static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7546{ 7547 int i; 7548 7549 for (i = 0; i < adapter->num_tx_queues; i++) { 7550 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7551 7552 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7553 return true; 7554 } 7555 7556 for (i = 0; i < adapter->num_xdp_queues; i++) { 7557 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7558 7559 if (ring->next_to_use != ring->next_to_clean) 7560 return true; 7561 } 7562 7563 return false; 7564} 7565 7566static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7567{ 7568 struct ixgbe_hw *hw = &adapter->hw; 7569 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7570 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7571 7572 int i, j; 7573 7574 if (!adapter->num_vfs) 7575 return false; 7576 7577 /* resetting the PF is only needed for MAC before X550 */ 7578 if (hw->mac.type >= ixgbe_mac_X550) 7579 return false; 7580 7581 for (i = 0; i < adapter->num_vfs; i++) { 7582 for (j = 0; j < q_per_pool; j++) { 7583 u32 h, t; 7584 7585 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7586 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7587 7588 if (h != t) 7589 return true; 7590 } 7591 } 7592 7593 return false; 7594} 7595 7596/** 7597 * ixgbe_watchdog_flush_tx - flush queues on link down 7598 * @adapter: pointer to the device adapter structure 7599 **/ 7600static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7601{ 7602 if (!netif_carrier_ok(adapter->netdev)) { 7603 if (ixgbe_ring_tx_pending(adapter) || 7604 ixgbe_vf_tx_pending(adapter)) { 7605 /* We've lost link, so the controller stops DMA, 7606 * but we've got queued Tx work that's never going 7607 * to get done, so reset controller to flush Tx. 7608 * (Do the reset outside of interrupt context). 7609 */ 7610 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7611 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7612 } 7613 } 7614} 7615 7616#ifdef CONFIG_PCI_IOV 7617static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 7618{ 7619 struct ixgbe_hw *hw = &adapter->hw; 7620 7621 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 7622 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 7623 adapter->vfinfo[vf].primary_abort_count++; 7624 if (adapter->vfinfo[vf].primary_abort_count == 7625 IXGBE_PRIMARY_ABORT_LIMIT) { 7626 ixgbe_set_vf_link_state(adapter, vf, 7627 IFLA_VF_LINK_STATE_DISABLE); 7628 adapter->vfinfo[vf].primary_abort_count = 0; 7629 7630 e_info(drv, 7631 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 7632 hw->bus.func, vf, 7633 adapter->vfinfo[vf].vf_mac_addresses); 7634 } 7635 } 7636} 7637 7638static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7639{ 7640 struct ixgbe_hw *hw = &adapter->hw; 7641 struct pci_dev *pdev = adapter->pdev; 7642 unsigned int vf; 7643 u32 gpc; 7644 7645 if (!(netif_carrier_ok(adapter->netdev))) 7646 return; 7647 7648 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7649 if (gpc) /* If incrementing then no need for the check below */ 7650 return; 7651 /* Check to see if a bad DMA write target from an errant or 7652 * malicious VF has caused a PCIe error. If so then we can 7653 * issue a VFLR to the offending VF(s) and then resume without 7654 * requesting a full slot reset. 7655 */ 7656 7657 if (!pdev) 7658 return; 7659 7660 /* check status reg for all VFs owned by this PF */ 7661 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7662 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7663 u16 status_reg; 7664 7665 if (!vfdev) 7666 continue; 7667 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7668 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7669 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 7670 ixgbe_bad_vf_abort(adapter, vf); 7671 pcie_flr(vfdev); 7672 } 7673 } 7674} 7675 7676static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7677{ 7678 u32 ssvpc; 7679 7680 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7681 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7682 adapter->num_vfs == 0) 7683 return; 7684 7685 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7686 7687 /* 7688 * ssvpc register is cleared on read, if zero then no 7689 * spoofed packets in the last interval. 7690 */ 7691 if (!ssvpc) 7692 return; 7693 7694 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7695} 7696#else 7697static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7698{ 7699} 7700 7701static void 7702ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7703{ 7704} 7705#endif /* CONFIG_PCI_IOV */ 7706 7707 7708/** 7709 * ixgbe_watchdog_subtask - check and bring link up 7710 * @adapter: pointer to the device adapter structure 7711 **/ 7712static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7713{ 7714 /* if interface is down, removing or resetting, do nothing */ 7715 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7716 test_bit(__IXGBE_REMOVING, &adapter->state) || 7717 test_bit(__IXGBE_RESETTING, &adapter->state)) 7718 return; 7719 7720 ixgbe_watchdog_update_link(adapter); 7721 7722 if (adapter->link_up) 7723 ixgbe_watchdog_link_is_up(adapter); 7724 else 7725 ixgbe_watchdog_link_is_down(adapter); 7726 7727 ixgbe_check_for_bad_vf(adapter); 7728 ixgbe_spoof_check(adapter); 7729 ixgbe_update_stats(adapter); 7730 7731 ixgbe_watchdog_flush_tx(adapter); 7732} 7733 7734/** 7735 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7736 * @adapter: the ixgbe adapter structure 7737 **/ 7738static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7739{ 7740 struct ixgbe_hw *hw = &adapter->hw; 7741 s32 err; 7742 7743 /* not searching for SFP so there is nothing to do here */ 7744 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7745 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7746 return; 7747 7748 if (adapter->sfp_poll_time && 7749 time_after(adapter->sfp_poll_time, jiffies)) 7750 return; /* If not yet time to poll for SFP */ 7751 7752 /* someone else is in init, wait until next service event */ 7753 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7754 return; 7755 7756 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7757 7758 err = hw->phy.ops.identify_sfp(hw); 7759 if (err == -EOPNOTSUPP) 7760 goto sfp_out; 7761 7762 if (err == -ENOENT) { 7763 /* If no cable is present, then we need to reset 7764 * the next time we find a good cable. */ 7765 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7766 } 7767 7768 /* exit on error */ 7769 if (err) 7770 goto sfp_out; 7771 7772 /* exit if reset not needed */ 7773 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7774 goto sfp_out; 7775 7776 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7777 7778 /* 7779 * A module may be identified correctly, but the EEPROM may not have 7780 * support for that module. setup_sfp() will fail in that case, so 7781 * we should not allow that module to load. 7782 */ 7783 if (hw->mac.type == ixgbe_mac_82598EB) 7784 err = hw->phy.ops.reset(hw); 7785 else 7786 err = hw->mac.ops.setup_sfp(hw); 7787 7788 if (err == -EOPNOTSUPP) 7789 goto sfp_out; 7790 7791 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7792 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7793 7794sfp_out: 7795 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7796 7797 if (err == -EOPNOTSUPP && 7798 adapter->netdev->reg_state == NETREG_REGISTERED) { 7799 e_dev_err("failed to initialize because an unsupported " 7800 "SFP+ module type was detected.\n"); 7801 e_dev_err("Reload the driver after installing a " 7802 "supported module.\n"); 7803 unregister_netdev(adapter->netdev); 7804 } 7805} 7806 7807/** 7808 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7809 * @adapter: the ixgbe adapter structure 7810 **/ 7811static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7812{ 7813 struct ixgbe_hw *hw = &adapter->hw; 7814 u32 cap_speed; 7815 u32 speed; 7816 bool autoneg = false; 7817 7818 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7819 return; 7820 7821 /* someone else is in init, wait until next service event */ 7822 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7823 return; 7824 7825 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7826 7827 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7828 7829 /* advertise highest capable link speed */ 7830 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7831 speed = IXGBE_LINK_SPEED_10GB_FULL; 7832 else 7833 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7834 IXGBE_LINK_SPEED_1GB_FULL); 7835 7836 if (hw->mac.ops.setup_link) 7837 hw->mac.ops.setup_link(hw, speed, true); 7838 7839 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7840 adapter->link_check_timeout = jiffies; 7841 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7842} 7843 7844/** 7845 * ixgbe_service_timer - Timer Call-back 7846 * @t: pointer to timer_list structure 7847 **/ 7848static void ixgbe_service_timer(struct timer_list *t) 7849{ 7850 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7851 unsigned long next_event_offset; 7852 7853 /* poll faster when waiting for link */ 7854 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7855 next_event_offset = HZ / 10; 7856 else 7857 next_event_offset = HZ * 2; 7858 7859 /* Reset the timer */ 7860 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7861 7862 ixgbe_service_event_schedule(adapter); 7863} 7864 7865static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7866{ 7867 struct ixgbe_hw *hw = &adapter->hw; 7868 bool overtemp; 7869 7870 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7871 return; 7872 7873 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7874 7875 if (!hw->phy.ops.handle_lasi) 7876 return; 7877 7878 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 7879 if (overtemp) 7880 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7881} 7882 7883static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7884{ 7885 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7886 return; 7887 7888 rtnl_lock(); 7889 /* If we're already down, removing or resetting, just bail */ 7890 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7891 test_bit(__IXGBE_REMOVING, &adapter->state) || 7892 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7893 rtnl_unlock(); 7894 return; 7895 } 7896 7897 ixgbe_dump(adapter); 7898 netdev_err(adapter->netdev, "Reset adapter\n"); 7899 adapter->tx_timeout_count++; 7900 7901 ixgbe_reinit_locked(adapter); 7902 rtnl_unlock(); 7903} 7904 7905/** 7906 * ixgbe_check_fw_error - Check firmware for errors 7907 * @adapter: the adapter private structure 7908 * 7909 * Check firmware errors in register FWSM 7910 */ 7911static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7912{ 7913 struct ixgbe_hw *hw = &adapter->hw; 7914 u32 fwsm; 7915 7916 /* read fwsm.ext_err_ind register and log errors */ 7917 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7918 7919 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7920 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7921 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7922 fwsm); 7923 7924 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7925 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7926 return true; 7927 } 7928 7929 return false; 7930} 7931 7932/** 7933 * ixgbe_service_task - manages and runs subtasks 7934 * @work: pointer to work_struct containing our data 7935 **/ 7936static void ixgbe_service_task(struct work_struct *work) 7937{ 7938 struct ixgbe_adapter *adapter = container_of(work, 7939 struct ixgbe_adapter, 7940 service_task); 7941 if (ixgbe_removed(adapter->hw.hw_addr)) { 7942 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7943 rtnl_lock(); 7944 ixgbe_down(adapter); 7945 rtnl_unlock(); 7946 } 7947 ixgbe_service_event_complete(adapter); 7948 return; 7949 } 7950 if (ixgbe_check_fw_error(adapter)) { 7951 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 7952 unregister_netdev(adapter->netdev); 7953 ixgbe_service_event_complete(adapter); 7954 return; 7955 } 7956 ixgbe_reset_subtask(adapter); 7957 ixgbe_phy_interrupt_subtask(adapter); 7958 ixgbe_sfp_detection_subtask(adapter); 7959 ixgbe_sfp_link_config_subtask(adapter); 7960 ixgbe_check_overtemp_subtask(adapter); 7961 ixgbe_watchdog_subtask(adapter); 7962 ixgbe_fdir_reinit_subtask(adapter); 7963 ixgbe_check_hang_subtask(adapter); 7964 7965 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7966 ixgbe_ptp_overflow_check(adapter); 7967 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7968 ixgbe_ptp_rx_hang(adapter); 7969 ixgbe_ptp_tx_hang(adapter); 7970 } 7971 7972 ixgbe_service_event_complete(adapter); 7973} 7974 7975static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7976 struct ixgbe_tx_buffer *first, 7977 u8 *hdr_len, 7978 struct ixgbe_ipsec_tx_data *itd) 7979{ 7980 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7981 struct sk_buff *skb = first->skb; 7982 union { 7983 struct iphdr *v4; 7984 struct ipv6hdr *v6; 7985 unsigned char *hdr; 7986 } ip; 7987 union { 7988 struct tcphdr *tcp; 7989 struct udphdr *udp; 7990 unsigned char *hdr; 7991 } l4; 7992 u32 paylen, l4_offset; 7993 u32 fceof_saidx = 0; 7994 int err; 7995 7996 if (skb->ip_summed != CHECKSUM_PARTIAL) 7997 return 0; 7998 7999 if (!skb_is_gso(skb)) 8000 return 0; 8001 8002 err = skb_cow_head(skb, 0); 8003 if (err < 0) 8004 return err; 8005 8006 if (eth_p_mpls(first->protocol)) 8007 ip.hdr = skb_inner_network_header(skb); 8008 else 8009 ip.hdr = skb_network_header(skb); 8010 l4.hdr = skb_checksum_start(skb); 8011 8012 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8013 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8014 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8015 8016 /* initialize outer IP header fields */ 8017 if (ip.v4->version == 4) { 8018 unsigned char *csum_start = skb_checksum_start(skb); 8019 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8020 int len = csum_start - trans_start; 8021 8022 /* IP header will have to cancel out any data that 8023 * is not a part of the outer IP header, so set to 8024 * a reverse csum if needed, else init check to 0. 8025 */ 8026 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8027 csum_fold(csum_partial(trans_start, 8028 len, 0)) : 0; 8029 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8030 8031 ip.v4->tot_len = 0; 8032 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8033 IXGBE_TX_FLAGS_CSUM | 8034 IXGBE_TX_FLAGS_IPV4; 8035 } else { 8036 ip.v6->payload_len = 0; 8037 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8038 IXGBE_TX_FLAGS_CSUM; 8039 } 8040 8041 /* determine offset of inner transport header */ 8042 l4_offset = l4.hdr - skb->data; 8043 8044 /* remove payload length from inner checksum */ 8045 paylen = skb->len - l4_offset; 8046 8047 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8048 /* compute length of segmentation header */ 8049 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8050 csum_replace_by_diff(&l4.tcp->check, 8051 (__force __wsum)htonl(paylen)); 8052 } else { 8053 /* compute length of segmentation header */ 8054 *hdr_len = sizeof(*l4.udp) + l4_offset; 8055 csum_replace_by_diff(&l4.udp->check, 8056 (__force __wsum)htonl(paylen)); 8057 } 8058 8059 /* update gso size and bytecount with header size */ 8060 first->gso_segs = skb_shinfo(skb)->gso_segs; 8061 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8062 8063 /* mss_l4len_id: use 0 as index for TSO */ 8064 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8065 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8066 8067 fceof_saidx |= itd->sa_idx; 8068 type_tucmd |= itd->flags | itd->trailer_len; 8069 8070 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8071 vlan_macip_lens = l4.hdr - ip.hdr; 8072 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8073 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8074 8075 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8076 mss_l4len_idx); 8077 8078 return 1; 8079} 8080 8081static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 8082{ 8083 unsigned int offset = 0; 8084 8085 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 8086 8087 return offset == skb_checksum_start_offset(skb); 8088} 8089 8090static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8091 struct ixgbe_tx_buffer *first, 8092 struct ixgbe_ipsec_tx_data *itd) 8093{ 8094 struct sk_buff *skb = first->skb; 8095 u32 vlan_macip_lens = 0; 8096 u32 fceof_saidx = 0; 8097 u32 type_tucmd = 0; 8098 8099 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8100csum_failed: 8101 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8102 IXGBE_TX_FLAGS_CC))) 8103 return; 8104 goto no_csum; 8105 } 8106 8107 switch (skb->csum_offset) { 8108 case offsetof(struct tcphdr, check): 8109 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8110 fallthrough; 8111 case offsetof(struct udphdr, check): 8112 break; 8113 case offsetof(struct sctphdr, checksum): 8114 /* validate that this is actually an SCTP request */ 8115 if (((first->protocol == htons(ETH_P_IP)) && 8116 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 8117 ((first->protocol == htons(ETH_P_IPV6)) && 8118 ixgbe_ipv6_csum_is_sctp(skb))) { 8119 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8120 break; 8121 } 8122 fallthrough; 8123 default: 8124 skb_checksum_help(skb); 8125 goto csum_failed; 8126 } 8127 8128 /* update TX checksum flag */ 8129 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8130 vlan_macip_lens = skb_checksum_start_offset(skb) - 8131 skb_network_offset(skb); 8132no_csum: 8133 /* vlan_macip_lens: MACLEN, VLAN tag */ 8134 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8135 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8136 8137 fceof_saidx |= itd->sa_idx; 8138 type_tucmd |= itd->flags | itd->trailer_len; 8139 8140 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8141} 8142 8143#define IXGBE_SET_FLAG(_input, _flag, _result) \ 8144 ((_flag <= _result) ? \ 8145 ((u32)(_input & _flag) * (_result / _flag)) : \ 8146 ((u32)(_input & _flag) / (_flag / _result))) 8147 8148static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8149{ 8150 /* set type for advanced descriptor with frame checksum insertion */ 8151 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8152 IXGBE_ADVTXD_DCMD_DEXT | 8153 IXGBE_ADVTXD_DCMD_IFCS; 8154 8155 /* set HW vlan bit if vlan is present */ 8156 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8157 IXGBE_ADVTXD_DCMD_VLE); 8158 8159 /* set segmentation enable bits for TSO/FSO */ 8160 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8161 IXGBE_ADVTXD_DCMD_TSE); 8162 8163 /* set timestamp bit if present */ 8164 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8165 IXGBE_ADVTXD_MAC_TSTAMP); 8166 8167 /* insert frame checksum */ 8168 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8169 8170 return cmd_type; 8171} 8172 8173static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8174 u32 tx_flags, unsigned int paylen) 8175{ 8176 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8177 8178 /* enable L4 checksum for TSO and TX checksum offload */ 8179 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8180 IXGBE_TX_FLAGS_CSUM, 8181 IXGBE_ADVTXD_POPTS_TXSM); 8182 8183 /* enable IPv4 checksum for TSO */ 8184 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8185 IXGBE_TX_FLAGS_IPV4, 8186 IXGBE_ADVTXD_POPTS_IXSM); 8187 8188 /* enable IPsec */ 8189 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8190 IXGBE_TX_FLAGS_IPSEC, 8191 IXGBE_ADVTXD_POPTS_IPSEC); 8192 8193 /* 8194 * Check Context must be set if Tx switch is enabled, which it 8195 * always is for case where virtual functions are running 8196 */ 8197 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8198 IXGBE_TX_FLAGS_CC, 8199 IXGBE_ADVTXD_CC); 8200 8201 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8202} 8203 8204static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8205{ 8206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8207 8208 /* Herbert's original patch had: 8209 * smp_mb__after_netif_stop_queue(); 8210 * but since that doesn't exist yet, just open code it. 8211 */ 8212 smp_mb(); 8213 8214 /* We need to check again in a case another CPU has just 8215 * made room available. 8216 */ 8217 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8218 return -EBUSY; 8219 8220 /* A reprieve! - use start_queue because it doesn't call schedule */ 8221 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8222 ++tx_ring->tx_stats.restart_queue; 8223 return 0; 8224} 8225 8226static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8227{ 8228 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8229 return 0; 8230 8231 return __ixgbe_maybe_stop_tx(tx_ring, size); 8232} 8233 8234static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8235 struct ixgbe_tx_buffer *first, 8236 const u8 hdr_len) 8237{ 8238 struct sk_buff *skb = first->skb; 8239 struct ixgbe_tx_buffer *tx_buffer; 8240 union ixgbe_adv_tx_desc *tx_desc; 8241 skb_frag_t *frag; 8242 dma_addr_t dma; 8243 unsigned int data_len, size; 8244 u32 tx_flags = first->tx_flags; 8245 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8246 u16 i = tx_ring->next_to_use; 8247 8248 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8249 8250 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8251 8252 size = skb_headlen(skb); 8253 data_len = skb->data_len; 8254 8255#ifdef IXGBE_FCOE 8256 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8257 if (data_len < sizeof(struct fcoe_crc_eof)) { 8258 size -= sizeof(struct fcoe_crc_eof) - data_len; 8259 data_len = 0; 8260 } else { 8261 data_len -= sizeof(struct fcoe_crc_eof); 8262 } 8263 } 8264 8265#endif 8266 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8267 8268 tx_buffer = first; 8269 8270 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8271 if (dma_mapping_error(tx_ring->dev, dma)) 8272 goto dma_error; 8273 8274 /* record length, and DMA address */ 8275 dma_unmap_len_set(tx_buffer, len, size); 8276 dma_unmap_addr_set(tx_buffer, dma, dma); 8277 8278 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8279 8280 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8281 tx_desc->read.cmd_type_len = 8282 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8283 8284 i++; 8285 tx_desc++; 8286 if (i == tx_ring->count) { 8287 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8288 i = 0; 8289 } 8290 tx_desc->read.olinfo_status = 0; 8291 8292 dma += IXGBE_MAX_DATA_PER_TXD; 8293 size -= IXGBE_MAX_DATA_PER_TXD; 8294 8295 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8296 } 8297 8298 if (likely(!data_len)) 8299 break; 8300 8301 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8302 8303 i++; 8304 tx_desc++; 8305 if (i == tx_ring->count) { 8306 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8307 i = 0; 8308 } 8309 tx_desc->read.olinfo_status = 0; 8310 8311#ifdef IXGBE_FCOE 8312 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8313#else 8314 size = skb_frag_size(frag); 8315#endif 8316 data_len -= size; 8317 8318 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8319 DMA_TO_DEVICE); 8320 8321 tx_buffer = &tx_ring->tx_buffer_info[i]; 8322 } 8323 8324 /* write last descriptor with RS and EOP bits */ 8325 cmd_type |= size | IXGBE_TXD_CMD; 8326 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8327 8328 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8329 8330 /* set the timestamp */ 8331 first->time_stamp = jiffies; 8332 8333 skb_tx_timestamp(skb); 8334 8335 /* 8336 * Force memory writes to complete before letting h/w know there 8337 * are new descriptors to fetch. (Only applicable for weak-ordered 8338 * memory model archs, such as IA-64). 8339 * 8340 * We also need this memory barrier to make certain all of the 8341 * status bits have been updated before next_to_watch is written. 8342 */ 8343 wmb(); 8344 8345 /* set next_to_watch value indicating a packet is present */ 8346 first->next_to_watch = tx_desc; 8347 8348 i++; 8349 if (i == tx_ring->count) 8350 i = 0; 8351 8352 tx_ring->next_to_use = i; 8353 8354 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8355 8356 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8357 writel(i, tx_ring->tail); 8358 } 8359 8360 return 0; 8361dma_error: 8362 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8363 8364 /* clear dma mappings for failed tx_buffer_info map */ 8365 for (;;) { 8366 tx_buffer = &tx_ring->tx_buffer_info[i]; 8367 if (dma_unmap_len(tx_buffer, len)) 8368 dma_unmap_page(tx_ring->dev, 8369 dma_unmap_addr(tx_buffer, dma), 8370 dma_unmap_len(tx_buffer, len), 8371 DMA_TO_DEVICE); 8372 dma_unmap_len_set(tx_buffer, len, 0); 8373 if (tx_buffer == first) 8374 break; 8375 if (i == 0) 8376 i += tx_ring->count; 8377 i--; 8378 } 8379 8380 dev_kfree_skb_any(first->skb); 8381 first->skb = NULL; 8382 8383 tx_ring->next_to_use = i; 8384 8385 return -1; 8386} 8387 8388static void ixgbe_atr(struct ixgbe_ring *ring, 8389 struct ixgbe_tx_buffer *first) 8390{ 8391 struct ixgbe_q_vector *q_vector = ring->q_vector; 8392 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8393 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8394 union { 8395 unsigned char *network; 8396 struct iphdr *ipv4; 8397 struct ipv6hdr *ipv6; 8398 } hdr; 8399 struct tcphdr *th; 8400 unsigned int hlen; 8401 struct sk_buff *skb; 8402 __be16 vlan_id; 8403 int l4_proto; 8404 8405 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8406 if (!q_vector) 8407 return; 8408 8409 /* do nothing if sampling is disabled */ 8410 if (!ring->atr_sample_rate) 8411 return; 8412 8413 ring->atr_count++; 8414 8415 /* currently only IPv4/IPv6 with TCP is supported */ 8416 if ((first->protocol != htons(ETH_P_IP)) && 8417 (first->protocol != htons(ETH_P_IPV6))) 8418 return; 8419 8420 /* snag network header to get L4 type and address */ 8421 skb = first->skb; 8422 hdr.network = skb_network_header(skb); 8423 if (unlikely(hdr.network <= skb->data)) 8424 return; 8425 if (skb->encapsulation && 8426 first->protocol == htons(ETH_P_IP) && 8427 hdr.ipv4->protocol == IPPROTO_UDP) { 8428 struct ixgbe_adapter *adapter = q_vector->adapter; 8429 8430 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8431 vxlan_headroom(0))) 8432 return; 8433 8434 /* verify the port is recognized as VXLAN */ 8435 if (adapter->vxlan_port && 8436 udp_hdr(skb)->dest == adapter->vxlan_port) 8437 hdr.network = skb_inner_network_header(skb); 8438 8439 if (adapter->geneve_port && 8440 udp_hdr(skb)->dest == adapter->geneve_port) 8441 hdr.network = skb_inner_network_header(skb); 8442 } 8443 8444 /* Make sure we have at least [minimum IPv4 header + TCP] 8445 * or [IPv6 header] bytes 8446 */ 8447 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8448 return; 8449 8450 /* Currently only IPv4/IPv6 with TCP is supported */ 8451 switch (hdr.ipv4->version) { 8452 case IPVERSION: 8453 /* access ihl as u8 to avoid unaligned access on ia64 */ 8454 hlen = (hdr.network[0] & 0x0F) << 2; 8455 l4_proto = hdr.ipv4->protocol; 8456 break; 8457 case 6: 8458 hlen = hdr.network - skb->data; 8459 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8460 hlen -= hdr.network - skb->data; 8461 break; 8462 default: 8463 return; 8464 } 8465 8466 if (l4_proto != IPPROTO_TCP) 8467 return; 8468 8469 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8470 hlen + sizeof(struct tcphdr))) 8471 return; 8472 8473 th = (struct tcphdr *)(hdr.network + hlen); 8474 8475 /* skip this packet since the socket is closing */ 8476 if (th->fin) 8477 return; 8478 8479 /* sample on all syn packets or once every atr sample count */ 8480 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8481 return; 8482 8483 /* reset sample count */ 8484 ring->atr_count = 0; 8485 8486 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8487 8488 /* 8489 * src and dst are inverted, think how the receiver sees them 8490 * 8491 * The input is broken into two sections, a non-compressed section 8492 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8493 * is XORed together and stored in the compressed dword. 8494 */ 8495 input.formatted.vlan_id = vlan_id; 8496 8497 /* 8498 * since src port and flex bytes occupy the same word XOR them together 8499 * and write the value to source port portion of compressed dword 8500 */ 8501 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8502 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8503 else 8504 common.port.src ^= th->dest ^ first->protocol; 8505 common.port.dst ^= th->source; 8506 8507 switch (hdr.ipv4->version) { 8508 case IPVERSION: 8509 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8510 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8511 break; 8512 case 6: 8513 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8514 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8515 hdr.ipv6->saddr.s6_addr32[1] ^ 8516 hdr.ipv6->saddr.s6_addr32[2] ^ 8517 hdr.ipv6->saddr.s6_addr32[3] ^ 8518 hdr.ipv6->daddr.s6_addr32[0] ^ 8519 hdr.ipv6->daddr.s6_addr32[1] ^ 8520 hdr.ipv6->daddr.s6_addr32[2] ^ 8521 hdr.ipv6->daddr.s6_addr32[3]; 8522 break; 8523 default: 8524 break; 8525 } 8526 8527 if (hdr.network != skb_network_header(skb)) 8528 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8529 8530 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8531 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8532 input, common, ring->queue_index); 8533} 8534 8535#ifdef IXGBE_FCOE 8536static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8537 struct net_device *sb_dev) 8538{ 8539 struct ixgbe_adapter *adapter; 8540 struct ixgbe_ring_feature *f; 8541 int txq; 8542 8543 if (sb_dev) { 8544 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8545 struct net_device *vdev = sb_dev; 8546 8547 txq = vdev->tc_to_txq[tc].offset; 8548 txq += reciprocal_scale(skb_get_hash(skb), 8549 vdev->tc_to_txq[tc].count); 8550 8551 return txq; 8552 } 8553 8554 /* 8555 * only execute the code below if protocol is FCoE 8556 * or FIP and we have FCoE enabled on the adapter 8557 */ 8558 switch (vlan_get_protocol(skb)) { 8559 case htons(ETH_P_FCOE): 8560 case htons(ETH_P_FIP): 8561 adapter = netdev_priv(dev); 8562 8563 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8564 break; 8565 fallthrough; 8566 default: 8567 return netdev_pick_tx(dev, skb, sb_dev); 8568 } 8569 8570 f = &adapter->ring_feature[RING_F_FCOE]; 8571 8572 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8573 smp_processor_id(); 8574 8575 while (txq >= f->indices) 8576 txq -= f->indices; 8577 8578 return txq + f->offset; 8579} 8580 8581#endif 8582int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8583 struct xdp_frame *xdpf) 8584{ 8585 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8586 struct ixgbe_tx_buffer *tx_buffer; 8587 union ixgbe_adv_tx_desc *tx_desc; 8588 u32 len, cmd_type; 8589 dma_addr_t dma; 8590 u16 i; 8591 8592 len = xdpf->len; 8593 8594 if (unlikely(!ixgbe_desc_unused(ring))) 8595 return IXGBE_XDP_CONSUMED; 8596 8597 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8598 if (dma_mapping_error(ring->dev, dma)) 8599 return IXGBE_XDP_CONSUMED; 8600 8601 /* record the location of the first descriptor for this packet */ 8602 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8603 tx_buffer->bytecount = len; 8604 tx_buffer->gso_segs = 1; 8605 tx_buffer->protocol = 0; 8606 8607 i = ring->next_to_use; 8608 tx_desc = IXGBE_TX_DESC(ring, i); 8609 8610 dma_unmap_len_set(tx_buffer, len, len); 8611 dma_unmap_addr_set(tx_buffer, dma, dma); 8612 tx_buffer->xdpf = xdpf; 8613 8614 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8615 8616 /* put descriptor type bits */ 8617 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8618 IXGBE_ADVTXD_DCMD_DEXT | 8619 IXGBE_ADVTXD_DCMD_IFCS; 8620 cmd_type |= len | IXGBE_TXD_CMD; 8621 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8622 tx_desc->read.olinfo_status = 8623 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8624 8625 /* Avoid any potential race with xdp_xmit and cleanup */ 8626 smp_wmb(); 8627 8628 /* set next_to_watch value indicating a packet is present */ 8629 i++; 8630 if (i == ring->count) 8631 i = 0; 8632 8633 tx_buffer->next_to_watch = tx_desc; 8634 ring->next_to_use = i; 8635 8636 return IXGBE_XDP_TX; 8637} 8638 8639netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8640 struct ixgbe_adapter *adapter, 8641 struct ixgbe_ring *tx_ring) 8642{ 8643 struct ixgbe_tx_buffer *first; 8644 int tso; 8645 u32 tx_flags = 0; 8646 unsigned short f; 8647 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8648 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8649 __be16 protocol = skb->protocol; 8650 u8 hdr_len = 0; 8651 8652 /* 8653 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8654 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8655 * + 2 desc gap to keep tail from touching head, 8656 * + 1 desc for context descriptor, 8657 * otherwise try next time 8658 */ 8659 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8660 count += TXD_USE_COUNT(skb_frag_size( 8661 &skb_shinfo(skb)->frags[f])); 8662 8663 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8664 tx_ring->tx_stats.tx_busy++; 8665 return NETDEV_TX_BUSY; 8666 } 8667 8668 /* record the location of the first descriptor for this packet */ 8669 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8670 first->skb = skb; 8671 first->bytecount = skb->len; 8672 first->gso_segs = 1; 8673 8674 /* if we have a HW VLAN tag being added default to the HW one */ 8675 if (skb_vlan_tag_present(skb)) { 8676 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8677 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8678 /* else if it is a SW VLAN check the next protocol and store the tag */ 8679 } else if (protocol == htons(ETH_P_8021Q)) { 8680 struct vlan_hdr *vhdr, _vhdr; 8681 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8682 if (!vhdr) 8683 goto out_drop; 8684 8685 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8686 IXGBE_TX_FLAGS_VLAN_SHIFT; 8687 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8688 } 8689 protocol = vlan_get_protocol(skb); 8690 8691 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8692 adapter->ptp_clock) { 8693 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8694 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8695 &adapter->state)) { 8696 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8697 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8698 8699 /* schedule check for Tx timestamp */ 8700 adapter->ptp_tx_skb = skb_get(skb); 8701 adapter->ptp_tx_start = jiffies; 8702 schedule_work(&adapter->ptp_tx_work); 8703 } else { 8704 adapter->tx_hwtstamp_skipped++; 8705 } 8706 } 8707 8708#ifdef CONFIG_PCI_IOV 8709 /* 8710 * Use the l2switch_enable flag - would be false if the DMA 8711 * Tx switch had been disabled. 8712 */ 8713 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8714 tx_flags |= IXGBE_TX_FLAGS_CC; 8715 8716#endif 8717 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8718 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8719 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8720 (skb->priority != TC_PRIO_CONTROL))) { 8721 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8722 tx_flags |= (skb->priority & 0x7) << 8723 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8724 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8725 struct vlan_ethhdr *vhdr; 8726 8727 if (skb_cow_head(skb, 0)) 8728 goto out_drop; 8729 vhdr = skb_vlan_eth_hdr(skb); 8730 vhdr->h_vlan_TCI = htons(tx_flags >> 8731 IXGBE_TX_FLAGS_VLAN_SHIFT); 8732 } else { 8733 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8734 } 8735 } 8736 8737 /* record initial flags and protocol */ 8738 first->tx_flags = tx_flags; 8739 first->protocol = protocol; 8740 8741#ifdef IXGBE_FCOE 8742 /* setup tx offload for FCoE */ 8743 if ((protocol == htons(ETH_P_FCOE)) && 8744 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8745 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8746 if (tso < 0) 8747 goto out_drop; 8748 8749 goto xmit_fcoe; 8750 } 8751 8752#endif /* IXGBE_FCOE */ 8753 8754#ifdef CONFIG_IXGBE_IPSEC 8755 if (xfrm_offload(skb) && 8756 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8757 goto out_drop; 8758#endif 8759 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8760 if (tso < 0) 8761 goto out_drop; 8762 else if (!tso) 8763 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8764 8765 /* add the ATR filter if ATR is on */ 8766 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8767 ixgbe_atr(tx_ring, first); 8768 8769#ifdef IXGBE_FCOE 8770xmit_fcoe: 8771#endif /* IXGBE_FCOE */ 8772 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8773 goto cleanup_tx_timestamp; 8774 8775 return NETDEV_TX_OK; 8776 8777out_drop: 8778 dev_kfree_skb_any(first->skb); 8779 first->skb = NULL; 8780cleanup_tx_timestamp: 8781 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8782 dev_kfree_skb_any(adapter->ptp_tx_skb); 8783 adapter->ptp_tx_skb = NULL; 8784 cancel_work_sync(&adapter->ptp_tx_work); 8785 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8786 } 8787 8788 return NETDEV_TX_OK; 8789} 8790 8791static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8792 struct net_device *netdev, 8793 struct ixgbe_ring *ring) 8794{ 8795 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8796 struct ixgbe_ring *tx_ring; 8797 8798 /* 8799 * The minimum packet size for olinfo paylen is 17 so pad the skb 8800 * in order to meet this minimum size requirement. 8801 */ 8802 if (skb_put_padto(skb, 17)) 8803 return NETDEV_TX_OK; 8804 8805 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8806 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8807 return NETDEV_TX_BUSY; 8808 8809 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8810} 8811 8812static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8813 struct net_device *netdev) 8814{ 8815 return __ixgbe_xmit_frame(skb, netdev, NULL); 8816} 8817 8818/** 8819 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8820 * @netdev: network interface device structure 8821 * @p: pointer to an address structure 8822 * 8823 * Returns 0 on success, negative on failure 8824 **/ 8825static int ixgbe_set_mac(struct net_device *netdev, void *p) 8826{ 8827 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8828 struct ixgbe_hw *hw = &adapter->hw; 8829 struct sockaddr *addr = p; 8830 8831 if (!is_valid_ether_addr(addr->sa_data)) 8832 return -EADDRNOTAVAIL; 8833 8834 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8835 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8836 8837 ixgbe_mac_set_default_filter(adapter); 8838 8839 return 0; 8840} 8841 8842static int 8843ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8844{ 8845 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8846 struct ixgbe_hw *hw = &adapter->hw; 8847 u16 value; 8848 int rc; 8849 8850 if (adapter->mii_bus) { 8851 int regnum = addr; 8852 8853 if (devad != MDIO_DEVAD_NONE) 8854 regnum |= (devad << 16) | MII_ADDR_C45; 8855 8856 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8857 } 8858 8859 if (prtad != hw->phy.mdio.prtad) 8860 return -EINVAL; 8861 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8862 if (!rc) 8863 rc = value; 8864 return rc; 8865} 8866 8867static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8868 u16 addr, u16 value) 8869{ 8870 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8871 struct ixgbe_hw *hw = &adapter->hw; 8872 8873 if (adapter->mii_bus) { 8874 int regnum = addr; 8875 8876 if (devad != MDIO_DEVAD_NONE) 8877 regnum |= (devad << 16) | MII_ADDR_C45; 8878 8879 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8880 } 8881 8882 if (prtad != hw->phy.mdio.prtad) 8883 return -EINVAL; 8884 return hw->phy.ops.write_reg(hw, addr, devad, value); 8885} 8886 8887static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8888{ 8889 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8890 8891 switch (cmd) { 8892 case SIOCSHWTSTAMP: 8893 return ixgbe_ptp_set_ts_config(adapter, req); 8894 case SIOCGHWTSTAMP: 8895 return ixgbe_ptp_get_ts_config(adapter, req); 8896 case SIOCGMIIPHY: 8897 if (!adapter->hw.phy.ops.read_reg) 8898 return -EOPNOTSUPP; 8899 fallthrough; 8900 default: 8901 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8902 } 8903} 8904 8905/** 8906 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8907 * netdev->dev_addrs 8908 * @dev: network interface device structure 8909 * 8910 * Returns non-zero on failure 8911 **/ 8912static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8913{ 8914 int err = 0; 8915 struct ixgbe_adapter *adapter = netdev_priv(dev); 8916 struct ixgbe_hw *hw = &adapter->hw; 8917 8918 if (is_valid_ether_addr(hw->mac.san_addr)) { 8919 rtnl_lock(); 8920 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8921 rtnl_unlock(); 8922 8923 /* update SAN MAC vmdq pool selection */ 8924 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8925 } 8926 return err; 8927} 8928 8929/** 8930 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8931 * netdev->dev_addrs 8932 * @dev: network interface device structure 8933 * 8934 * Returns non-zero on failure 8935 **/ 8936static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8937{ 8938 int err = 0; 8939 struct ixgbe_adapter *adapter = netdev_priv(dev); 8940 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8941 8942 if (is_valid_ether_addr(mac->san_addr)) { 8943 rtnl_lock(); 8944 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8945 rtnl_unlock(); 8946 } 8947 return err; 8948} 8949 8950static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8951 struct ixgbe_ring *ring) 8952{ 8953 u64 bytes, packets; 8954 unsigned int start; 8955 8956 if (ring) { 8957 do { 8958 start = u64_stats_fetch_begin_irq(&ring->syncp); 8959 packets = ring->stats.packets; 8960 bytes = ring->stats.bytes; 8961 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8962 stats->tx_packets += packets; 8963 stats->tx_bytes += bytes; 8964 } 8965} 8966 8967static void ixgbe_get_stats64(struct net_device *netdev, 8968 struct rtnl_link_stats64 *stats) 8969{ 8970 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8971 int i; 8972 8973 rcu_read_lock(); 8974 for (i = 0; i < adapter->num_rx_queues; i++) { 8975 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8976 u64 bytes, packets; 8977 unsigned int start; 8978 8979 if (ring) { 8980 do { 8981 start = u64_stats_fetch_begin_irq(&ring->syncp); 8982 packets = ring->stats.packets; 8983 bytes = ring->stats.bytes; 8984 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8985 stats->rx_packets += packets; 8986 stats->rx_bytes += bytes; 8987 } 8988 } 8989 8990 for (i = 0; i < adapter->num_tx_queues; i++) { 8991 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8992 8993 ixgbe_get_ring_stats64(stats, ring); 8994 } 8995 for (i = 0; i < adapter->num_xdp_queues; i++) { 8996 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8997 8998 ixgbe_get_ring_stats64(stats, ring); 8999 } 9000 rcu_read_unlock(); 9001 9002 /* following stats updated by ixgbe_watchdog_task() */ 9003 stats->multicast = netdev->stats.multicast; 9004 stats->rx_errors = netdev->stats.rx_errors; 9005 stats->rx_length_errors = netdev->stats.rx_length_errors; 9006 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9007 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9008} 9009 9010#ifdef CONFIG_IXGBE_DCB 9011/** 9012 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9013 * @adapter: pointer to ixgbe_adapter 9014 * @tc: number of traffic classes currently enabled 9015 * 9016 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9017 * 802.1Q priority maps to a packet buffer that exists. 9018 */ 9019static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9020{ 9021 struct ixgbe_hw *hw = &adapter->hw; 9022 u32 reg, rsave; 9023 int i; 9024 9025 /* 82598 have a static priority to TC mapping that can not 9026 * be changed so no validation is needed. 9027 */ 9028 if (hw->mac.type == ixgbe_mac_82598EB) 9029 return; 9030 9031 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9032 rsave = reg; 9033 9034 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9035 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9036 9037 /* If up2tc is out of bounds default to zero */ 9038 if (up2tc > tc) 9039 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9040 } 9041 9042 if (reg != rsave) 9043 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9044 9045 return; 9046} 9047 9048/** 9049 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9050 * @adapter: Pointer to adapter struct 9051 * 9052 * Populate the netdev user priority to tc map 9053 */ 9054static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9055{ 9056 struct net_device *dev = adapter->netdev; 9057 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9058 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9059 u8 prio; 9060 9061 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9062 u8 tc = 0; 9063 9064 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9065 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9066 else if (ets) 9067 tc = ets->prio_tc[prio]; 9068 9069 netdev_set_prio_tc_map(dev, prio, tc); 9070 } 9071} 9072 9073#endif /* CONFIG_IXGBE_DCB */ 9074static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9075 struct netdev_nested_priv *priv) 9076{ 9077 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9078 struct ixgbe_fwd_adapter *accel; 9079 int pool; 9080 9081 /* we only care about macvlans... */ 9082 if (!netif_is_macvlan(vdev)) 9083 return 0; 9084 9085 /* that have hardware offload enabled... */ 9086 accel = macvlan_accel_priv(vdev); 9087 if (!accel) 9088 return 0; 9089 9090 /* If we can relocate to a different bit do so */ 9091 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9092 if (pool < adapter->num_rx_pools) { 9093 set_bit(pool, adapter->fwd_bitmask); 9094 accel->pool = pool; 9095 return 0; 9096 } 9097 9098 /* if we cannot find a free pool then disable the offload */ 9099 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9100 macvlan_release_l2fw_offload(vdev); 9101 9102 /* unbind the queues and drop the subordinate channel config */ 9103 netdev_unbind_sb_channel(adapter->netdev, vdev); 9104 netdev_set_sb_channel(vdev, 0); 9105 9106 kfree(accel); 9107 9108 return 0; 9109} 9110 9111static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9112{ 9113 struct ixgbe_adapter *adapter = netdev_priv(dev); 9114 struct netdev_nested_priv priv = { 9115 .data = (void *)adapter, 9116 }; 9117 9118 /* flush any stale bits out of the fwd bitmask */ 9119 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9120 9121 /* walk through upper devices reassigning pools */ 9122 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9123 &priv); 9124} 9125 9126/** 9127 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9128 * 9129 * @dev: net device to configure 9130 * @tc: number of traffic classes to enable 9131 */ 9132int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9133{ 9134 struct ixgbe_adapter *adapter = netdev_priv(dev); 9135 struct ixgbe_hw *hw = &adapter->hw; 9136 9137 /* Hardware supports up to 8 traffic classes */ 9138 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9139 return -EINVAL; 9140 9141 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9142 return -EINVAL; 9143 9144 /* Hardware has to reinitialize queues and interrupts to 9145 * match packet buffer alignment. Unfortunately, the 9146 * hardware is not flexible enough to do this dynamically. 9147 */ 9148 if (netif_running(dev)) 9149 ixgbe_close(dev); 9150 else 9151 ixgbe_reset(adapter); 9152 9153 ixgbe_clear_interrupt_scheme(adapter); 9154 9155#ifdef CONFIG_IXGBE_DCB 9156 if (tc) { 9157 if (adapter->xdp_prog) { 9158 e_warn(probe, "DCB is not supported with XDP\n"); 9159 9160 ixgbe_init_interrupt_scheme(adapter); 9161 if (netif_running(dev)) 9162 ixgbe_open(dev); 9163 return -EINVAL; 9164 } 9165 9166 netdev_set_num_tc(dev, tc); 9167 ixgbe_set_prio_tc_map(adapter); 9168 9169 adapter->hw_tcs = tc; 9170 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9171 9172 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9173 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9174 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9175 } 9176 } else { 9177 netdev_reset_tc(dev); 9178 9179 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9180 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9181 9182 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9183 adapter->hw_tcs = tc; 9184 9185 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9186 adapter->dcb_cfg.pfc_mode_enable = false; 9187 } 9188 9189 ixgbe_validate_rtr(adapter, tc); 9190 9191#endif /* CONFIG_IXGBE_DCB */ 9192 ixgbe_init_interrupt_scheme(adapter); 9193 9194 ixgbe_defrag_macvlan_pools(dev); 9195 9196 if (netif_running(dev)) 9197 return ixgbe_open(dev); 9198 9199 return 0; 9200} 9201 9202static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9203 struct tc_cls_u32_offload *cls) 9204{ 9205 u32 hdl = cls->knode.handle; 9206 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9207 u32 loc = cls->knode.handle & 0xfffff; 9208 int err = 0, i, j; 9209 struct ixgbe_jump_table *jump = NULL; 9210 9211 if (loc > IXGBE_MAX_HW_ENTRIES) 9212 return -EINVAL; 9213 9214 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9215 return -EINVAL; 9216 9217 /* Clear this filter in the link data it is associated with */ 9218 if (uhtid != 0x800) { 9219 jump = adapter->jump_tables[uhtid]; 9220 if (!jump) 9221 return -EINVAL; 9222 if (!test_bit(loc - 1, jump->child_loc_map)) 9223 return -EINVAL; 9224 clear_bit(loc - 1, jump->child_loc_map); 9225 } 9226 9227 /* Check if the filter being deleted is a link */ 9228 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9229 jump = adapter->jump_tables[i]; 9230 if (jump && jump->link_hdl == hdl) { 9231 /* Delete filters in the hardware in the child hash 9232 * table associated with this link 9233 */ 9234 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9235 if (!test_bit(j, jump->child_loc_map)) 9236 continue; 9237 spin_lock(&adapter->fdir_perfect_lock); 9238 err = ixgbe_update_ethtool_fdir_entry(adapter, 9239 NULL, 9240 j + 1); 9241 spin_unlock(&adapter->fdir_perfect_lock); 9242 clear_bit(j, jump->child_loc_map); 9243 } 9244 /* Remove resources for this link */ 9245 kfree(jump->input); 9246 kfree(jump->mask); 9247 kfree(jump); 9248 adapter->jump_tables[i] = NULL; 9249 return err; 9250 } 9251 } 9252 9253 spin_lock(&adapter->fdir_perfect_lock); 9254 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9255 spin_unlock(&adapter->fdir_perfect_lock); 9256 return err; 9257} 9258 9259static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9260 struct tc_cls_u32_offload *cls) 9261{ 9262 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9263 9264 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9265 return -EINVAL; 9266 9267 /* This ixgbe devices do not support hash tables at the moment 9268 * so abort when given hash tables. 9269 */ 9270 if (cls->hnode.divisor > 0) 9271 return -EINVAL; 9272 9273 set_bit(uhtid - 1, &adapter->tables); 9274 return 0; 9275} 9276 9277static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9278 struct tc_cls_u32_offload *cls) 9279{ 9280 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9281 9282 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9283 return -EINVAL; 9284 9285 clear_bit(uhtid - 1, &adapter->tables); 9286 return 0; 9287} 9288 9289#ifdef CONFIG_NET_CLS_ACT 9290struct upper_walk_data { 9291 struct ixgbe_adapter *adapter; 9292 u64 action; 9293 int ifindex; 9294 u8 queue; 9295}; 9296 9297static int get_macvlan_queue(struct net_device *upper, 9298 struct netdev_nested_priv *priv) 9299{ 9300 if (netif_is_macvlan(upper)) { 9301 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9302 struct ixgbe_adapter *adapter; 9303 struct upper_walk_data *data; 9304 int ifindex; 9305 9306 data = (struct upper_walk_data *)priv->data; 9307 ifindex = data->ifindex; 9308 adapter = data->adapter; 9309 if (vadapter && upper->ifindex == ifindex) { 9310 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9311 data->action = data->queue; 9312 return 1; 9313 } 9314 } 9315 9316 return 0; 9317} 9318 9319static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9320 u8 *queue, u64 *action) 9321{ 9322 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9323 unsigned int num_vfs = adapter->num_vfs, vf; 9324 struct netdev_nested_priv priv; 9325 struct upper_walk_data data; 9326 struct net_device *upper; 9327 9328 /* redirect to a SRIOV VF */ 9329 for (vf = 0; vf < num_vfs; ++vf) { 9330 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9331 if (upper->ifindex == ifindex) { 9332 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9333 *action = vf + 1; 9334 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9335 return 0; 9336 } 9337 } 9338 9339 /* redirect to a offloaded macvlan netdev */ 9340 data.adapter = adapter; 9341 data.ifindex = ifindex; 9342 data.action = 0; 9343 data.queue = 0; 9344 priv.data = (void *)&data; 9345 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9346 get_macvlan_queue, &priv)) { 9347 *action = data.action; 9348 *queue = data.queue; 9349 9350 return 0; 9351 } 9352 9353 return -EINVAL; 9354} 9355 9356static int parse_tc_actions(struct ixgbe_adapter *adapter, 9357 struct tcf_exts *exts, u64 *action, u8 *queue) 9358{ 9359 const struct tc_action *a; 9360 int i; 9361 9362 if (!tcf_exts_has_actions(exts)) 9363 return -EINVAL; 9364 9365 tcf_exts_for_each_action(i, a, exts) { 9366 /* Drop action */ 9367 if (is_tcf_gact_shot(a)) { 9368 *action = IXGBE_FDIR_DROP_QUEUE; 9369 *queue = IXGBE_FDIR_DROP_QUEUE; 9370 return 0; 9371 } 9372 9373 /* Redirect to a VF or a offloaded macvlan */ 9374 if (is_tcf_mirred_egress_redirect(a)) { 9375 struct net_device *dev = tcf_mirred_dev(a); 9376 9377 if (!dev) 9378 return -EINVAL; 9379 return handle_redirect_action(adapter, dev->ifindex, 9380 queue, action); 9381 } 9382 9383 return -EINVAL; 9384 } 9385 9386 return -EINVAL; 9387} 9388#else 9389static int parse_tc_actions(struct ixgbe_adapter *adapter, 9390 struct tcf_exts *exts, u64 *action, u8 *queue) 9391{ 9392 return -EINVAL; 9393} 9394#endif /* CONFIG_NET_CLS_ACT */ 9395 9396static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9397 union ixgbe_atr_input *mask, 9398 struct tc_cls_u32_offload *cls, 9399 struct ixgbe_mat_field *field_ptr, 9400 struct ixgbe_nexthdr *nexthdr) 9401{ 9402 int i, j, off; 9403 __be32 val, m; 9404 bool found_entry = false, found_jump_field = false; 9405 9406 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9407 off = cls->knode.sel->keys[i].off; 9408 val = cls->knode.sel->keys[i].val; 9409 m = cls->knode.sel->keys[i].mask; 9410 9411 for (j = 0; field_ptr[j].val; j++) { 9412 if (field_ptr[j].off == off) { 9413 field_ptr[j].val(input, mask, (__force u32)val, 9414 (__force u32)m); 9415 input->filter.formatted.flow_type |= 9416 field_ptr[j].type; 9417 found_entry = true; 9418 break; 9419 } 9420 } 9421 if (nexthdr) { 9422 if (nexthdr->off == cls->knode.sel->keys[i].off && 9423 nexthdr->val == 9424 (__force u32)cls->knode.sel->keys[i].val && 9425 nexthdr->mask == 9426 (__force u32)cls->knode.sel->keys[i].mask) 9427 found_jump_field = true; 9428 else 9429 continue; 9430 } 9431 } 9432 9433 if (nexthdr && !found_jump_field) 9434 return -EINVAL; 9435 9436 if (!found_entry) 9437 return 0; 9438 9439 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9440 IXGBE_ATR_L4TYPE_MASK; 9441 9442 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9443 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9444 9445 return 0; 9446} 9447 9448static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9449 struct tc_cls_u32_offload *cls) 9450{ 9451 __be16 protocol = cls->common.protocol; 9452 u32 loc = cls->knode.handle & 0xfffff; 9453 struct ixgbe_hw *hw = &adapter->hw; 9454 struct ixgbe_mat_field *field_ptr; 9455 struct ixgbe_fdir_filter *input = NULL; 9456 union ixgbe_atr_input *mask = NULL; 9457 struct ixgbe_jump_table *jump = NULL; 9458 int i, err = -EINVAL; 9459 u8 queue; 9460 u32 uhtid, link_uhtid; 9461 9462 uhtid = TC_U32_USERHTID(cls->knode.handle); 9463 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9464 9465 /* At the moment cls_u32 jumps to network layer and skips past 9466 * L2 headers. The canonical method to match L2 frames is to use 9467 * negative values. However this is error prone at best but really 9468 * just broken because there is no way to "know" what sort of hdr 9469 * is in front of the network layer. Fix cls_u32 to support L2 9470 * headers when needed. 9471 */ 9472 if (protocol != htons(ETH_P_IP)) 9473 return err; 9474 9475 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9476 e_err(drv, "Location out of range\n"); 9477 return err; 9478 } 9479 9480 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9481 * links and also the fields used to advance the parser across each 9482 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9483 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9484 * To add support for new nodes update ixgbe_model.h parse structures 9485 * this function _should_ be generic try not to hardcode values here. 9486 */ 9487 if (uhtid == 0x800) { 9488 field_ptr = (adapter->jump_tables[0])->mat; 9489 } else { 9490 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9491 return err; 9492 if (!adapter->jump_tables[uhtid]) 9493 return err; 9494 field_ptr = (adapter->jump_tables[uhtid])->mat; 9495 } 9496 9497 if (!field_ptr) 9498 return err; 9499 9500 /* At this point we know the field_ptr is valid and need to either 9501 * build cls_u32 link or attach filter. Because adding a link to 9502 * a handle that does not exist is invalid and the same for adding 9503 * rules to handles that don't exist. 9504 */ 9505 9506 if (link_uhtid) { 9507 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9508 9509 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9510 return err; 9511 9512 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9513 return err; 9514 9515 /* Multiple filters as links to the same hash table are not 9516 * supported. To add a new filter with the same next header 9517 * but different match/jump conditions, create a new hash table 9518 * and link to it. 9519 */ 9520 if (adapter->jump_tables[link_uhtid] && 9521 (adapter->jump_tables[link_uhtid])->link_hdl) { 9522 e_err(drv, "Link filter exists for link: %x\n", 9523 link_uhtid); 9524 return err; 9525 } 9526 9527 for (i = 0; nexthdr[i].jump; i++) { 9528 if (nexthdr[i].o != cls->knode.sel->offoff || 9529 nexthdr[i].s != cls->knode.sel->offshift || 9530 nexthdr[i].m != 9531 (__force u32)cls->knode.sel->offmask) 9532 return err; 9533 9534 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9535 if (!jump) 9536 return -ENOMEM; 9537 input = kzalloc(sizeof(*input), GFP_KERNEL); 9538 if (!input) { 9539 err = -ENOMEM; 9540 goto free_jump; 9541 } 9542 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9543 if (!mask) { 9544 err = -ENOMEM; 9545 goto free_input; 9546 } 9547 jump->input = input; 9548 jump->mask = mask; 9549 jump->link_hdl = cls->knode.handle; 9550 9551 err = ixgbe_clsu32_build_input(input, mask, cls, 9552 field_ptr, &nexthdr[i]); 9553 if (!err) { 9554 jump->mat = nexthdr[i].jump; 9555 adapter->jump_tables[link_uhtid] = jump; 9556 break; 9557 } else { 9558 kfree(mask); 9559 kfree(input); 9560 kfree(jump); 9561 } 9562 } 9563 return 0; 9564 } 9565 9566 input = kzalloc(sizeof(*input), GFP_KERNEL); 9567 if (!input) 9568 return -ENOMEM; 9569 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9570 if (!mask) { 9571 err = -ENOMEM; 9572 goto free_input; 9573 } 9574 9575 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9576 if ((adapter->jump_tables[uhtid])->input) 9577 memcpy(input, (adapter->jump_tables[uhtid])->input, 9578 sizeof(*input)); 9579 if ((adapter->jump_tables[uhtid])->mask) 9580 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9581 sizeof(*mask)); 9582 9583 /* Lookup in all child hash tables if this location is already 9584 * filled with a filter 9585 */ 9586 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9587 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9588 9589 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9590 e_err(drv, "Filter exists in location: %x\n", 9591 loc); 9592 err = -EINVAL; 9593 goto err_out; 9594 } 9595 } 9596 } 9597 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9598 if (err) 9599 goto err_out; 9600 9601 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9602 &queue); 9603 if (err < 0) 9604 goto err_out; 9605 9606 input->sw_idx = loc; 9607 9608 spin_lock(&adapter->fdir_perfect_lock); 9609 9610 if (hlist_empty(&adapter->fdir_filter_list)) { 9611 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9612 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9613 if (err) 9614 goto err_out_w_lock; 9615 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9616 err = -EINVAL; 9617 goto err_out_w_lock; 9618 } 9619 9620 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9621 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9622 input->sw_idx, queue); 9623 if (err) 9624 goto err_out_w_lock; 9625 9626 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9627 spin_unlock(&adapter->fdir_perfect_lock); 9628 9629 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9630 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9631 9632 kfree(mask); 9633 return err; 9634err_out_w_lock: 9635 spin_unlock(&adapter->fdir_perfect_lock); 9636err_out: 9637 kfree(mask); 9638free_input: 9639 kfree(input); 9640free_jump: 9641 kfree(jump); 9642 return err; 9643} 9644 9645static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9646 struct tc_cls_u32_offload *cls_u32) 9647{ 9648 switch (cls_u32->command) { 9649 case TC_CLSU32_NEW_KNODE: 9650 case TC_CLSU32_REPLACE_KNODE: 9651 return ixgbe_configure_clsu32(adapter, cls_u32); 9652 case TC_CLSU32_DELETE_KNODE: 9653 return ixgbe_delete_clsu32(adapter, cls_u32); 9654 case TC_CLSU32_NEW_HNODE: 9655 case TC_CLSU32_REPLACE_HNODE: 9656 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9657 case TC_CLSU32_DELETE_HNODE: 9658 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9659 default: 9660 return -EOPNOTSUPP; 9661 } 9662} 9663 9664static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9665 void *cb_priv) 9666{ 9667 struct ixgbe_adapter *adapter = cb_priv; 9668 9669 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9670 return -EOPNOTSUPP; 9671 9672 switch (type) { 9673 case TC_SETUP_CLSU32: 9674 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9675 default: 9676 return -EOPNOTSUPP; 9677 } 9678} 9679 9680static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9681 struct tc_mqprio_qopt *mqprio) 9682{ 9683 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9684 return ixgbe_setup_tc(dev, mqprio->num_tc); 9685} 9686 9687static LIST_HEAD(ixgbe_block_cb_list); 9688 9689static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9690 void *type_data) 9691{ 9692 struct ixgbe_adapter *adapter = netdev_priv(dev); 9693 9694 switch (type) { 9695 case TC_SETUP_BLOCK: 9696 return flow_block_cb_setup_simple(type_data, 9697 &ixgbe_block_cb_list, 9698 ixgbe_setup_tc_block_cb, 9699 adapter, adapter, true); 9700 case TC_SETUP_QDISC_MQPRIO: 9701 return ixgbe_setup_tc_mqprio(dev, type_data); 9702 default: 9703 return -EOPNOTSUPP; 9704 } 9705} 9706 9707#ifdef CONFIG_PCI_IOV 9708void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9709{ 9710 struct net_device *netdev = adapter->netdev; 9711 9712 rtnl_lock(); 9713 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9714 rtnl_unlock(); 9715} 9716 9717#endif 9718void ixgbe_do_reset(struct net_device *netdev) 9719{ 9720 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9721 9722 if (netif_running(netdev)) 9723 ixgbe_reinit_locked(adapter); 9724 else 9725 ixgbe_reset(adapter); 9726} 9727 9728static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9729 netdev_features_t features) 9730{ 9731 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9732 9733 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9734 if (!(features & NETIF_F_RXCSUM)) 9735 features &= ~NETIF_F_LRO; 9736 9737 /* Turn off LRO if not RSC capable */ 9738 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9739 features &= ~NETIF_F_LRO; 9740 9741 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9742 e_dev_err("LRO is not supported with XDP\n"); 9743 features &= ~NETIF_F_LRO; 9744 } 9745 9746 return features; 9747} 9748 9749static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9750{ 9751 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9752 num_online_cpus()); 9753 9754 /* go back to full RSS if we're not running SR-IOV */ 9755 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9756 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9757 IXGBE_FLAG_SRIOV_ENABLED); 9758 9759 adapter->ring_feature[RING_F_RSS].limit = rss; 9760 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9761 9762 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9763} 9764 9765static int ixgbe_set_features(struct net_device *netdev, 9766 netdev_features_t features) 9767{ 9768 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9769 netdev_features_t changed = netdev->features ^ features; 9770 bool need_reset = false; 9771 9772 /* Make sure RSC matches LRO, reset if change */ 9773 if (!(features & NETIF_F_LRO)) { 9774 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9775 need_reset = true; 9776 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9777 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9778 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9779 if (adapter->rx_itr_setting == 1 || 9780 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9781 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9782 need_reset = true; 9783 } else if ((changed ^ features) & NETIF_F_LRO) { 9784 e_info(probe, "rx-usecs set too low, " 9785 "disabling RSC\n"); 9786 } 9787 } 9788 9789 /* 9790 * Check if Flow Director n-tuple support or hw_tc support was 9791 * enabled or disabled. If the state changed, we need to reset. 9792 */ 9793 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9794 /* turn off ATR, enable perfect filters and reset */ 9795 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9796 need_reset = true; 9797 9798 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9799 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9800 } else { 9801 /* turn off perfect filters, enable ATR and reset */ 9802 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9803 need_reset = true; 9804 9805 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9806 9807 /* We cannot enable ATR if SR-IOV is enabled */ 9808 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9809 /* We cannot enable ATR if we have 2 or more tcs */ 9810 (adapter->hw_tcs > 1) || 9811 /* We cannot enable ATR if RSS is disabled */ 9812 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9813 /* A sample rate of 0 indicates ATR disabled */ 9814 (!adapter->atr_sample_rate)) 9815 ; /* do nothing not supported */ 9816 else /* otherwise supported and set the flag */ 9817 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9818 } 9819 9820 if (changed & NETIF_F_RXALL) 9821 need_reset = true; 9822 9823 netdev->features = features; 9824 9825 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9826 ixgbe_reset_l2fw_offload(adapter); 9827 else if (need_reset) 9828 ixgbe_do_reset(netdev); 9829 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9830 NETIF_F_HW_VLAN_CTAG_FILTER)) 9831 ixgbe_set_rx_mode(netdev); 9832 9833 return 1; 9834} 9835 9836static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9837 struct net_device *dev, 9838 const unsigned char *addr, u16 vid, 9839 u16 flags, 9840 struct netlink_ext_ack *extack) 9841{ 9842 /* guarantee we can provide a unique filter for the unicast address */ 9843 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9844 struct ixgbe_adapter *adapter = netdev_priv(dev); 9845 u16 pool = VMDQ_P(0); 9846 9847 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9848 return -ENOMEM; 9849 } 9850 9851 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9852} 9853 9854/** 9855 * ixgbe_configure_bridge_mode - set various bridge modes 9856 * @adapter: the private structure 9857 * @mode: requested bridge mode 9858 * 9859 * Configure some settings require for various bridge modes. 9860 **/ 9861static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9862 __u16 mode) 9863{ 9864 struct ixgbe_hw *hw = &adapter->hw; 9865 unsigned int p, num_pools; 9866 u32 vmdctl; 9867 9868 switch (mode) { 9869 case BRIDGE_MODE_VEPA: 9870 /* disable Tx loopback, rely on switch hairpin mode */ 9871 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9872 9873 /* must enable Rx switching replication to allow multicast 9874 * packet reception on all VFs, and to enable source address 9875 * pruning. 9876 */ 9877 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9878 vmdctl |= IXGBE_VT_CTL_REPLEN; 9879 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9880 9881 /* enable Rx source address pruning. Note, this requires 9882 * replication to be enabled or else it does nothing. 9883 */ 9884 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9885 for (p = 0; p < num_pools; p++) { 9886 if (hw->mac.ops.set_source_address_pruning) 9887 hw->mac.ops.set_source_address_pruning(hw, 9888 true, 9889 p); 9890 } 9891 break; 9892 case BRIDGE_MODE_VEB: 9893 /* enable Tx loopback for internal VF/PF communication */ 9894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9895 IXGBE_PFDTXGSWC_VT_LBEN); 9896 9897 /* disable Rx switching replication unless we have SR-IOV 9898 * virtual functions 9899 */ 9900 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9901 if (!adapter->num_vfs) 9902 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9903 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9904 9905 /* disable Rx source address pruning, since we don't expect to 9906 * be receiving external loopback of our transmitted frames. 9907 */ 9908 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9909 for (p = 0; p < num_pools; p++) { 9910 if (hw->mac.ops.set_source_address_pruning) 9911 hw->mac.ops.set_source_address_pruning(hw, 9912 false, 9913 p); 9914 } 9915 break; 9916 default: 9917 return -EINVAL; 9918 } 9919 9920 adapter->bridge_mode = mode; 9921 9922 e_info(drv, "enabling bridge mode: %s\n", 9923 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9924 9925 return 0; 9926} 9927 9928static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9929 struct nlmsghdr *nlh, u16 flags, 9930 struct netlink_ext_ack *extack) 9931{ 9932 struct ixgbe_adapter *adapter = netdev_priv(dev); 9933 struct nlattr *attr, *br_spec; 9934 int rem; 9935 9936 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9937 return -EOPNOTSUPP; 9938 9939 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9940 if (!br_spec) 9941 return -EINVAL; 9942 9943 nla_for_each_nested(attr, br_spec, rem) { 9944 int status; 9945 __u16 mode; 9946 9947 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9948 continue; 9949 9950 if (nla_len(attr) < sizeof(mode)) 9951 return -EINVAL; 9952 9953 mode = nla_get_u16(attr); 9954 status = ixgbe_configure_bridge_mode(adapter, mode); 9955 if (status) 9956 return status; 9957 9958 break; 9959 } 9960 9961 return 0; 9962} 9963 9964static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9965 struct net_device *dev, 9966 u32 filter_mask, int nlflags) 9967{ 9968 struct ixgbe_adapter *adapter = netdev_priv(dev); 9969 9970 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9971 return 0; 9972 9973 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9974 adapter->bridge_mode, 0, 0, nlflags, 9975 filter_mask, NULL); 9976} 9977 9978static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9979{ 9980 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9981 struct ixgbe_fwd_adapter *accel; 9982 int tcs = adapter->hw_tcs ? : 1; 9983 int pool, err; 9984 9985 if (adapter->xdp_prog) { 9986 e_warn(probe, "L2FW offload is not supported with XDP\n"); 9987 return ERR_PTR(-EINVAL); 9988 } 9989 9990 /* The hardware supported by ixgbe only filters on the destination MAC 9991 * address. In order to avoid issues we only support offloading modes 9992 * where the hardware can actually provide the functionality. 9993 */ 9994 if (!macvlan_supports_dest_filter(vdev)) 9995 return ERR_PTR(-EMEDIUMTYPE); 9996 9997 /* We need to lock down the macvlan to be a single queue device so that 9998 * we can reuse the tc_to_txq field in the macvlan netdev to represent 9999 * the queue mapping to our netdev. 10000 */ 10001 if (netif_is_multiqueue(vdev)) 10002 return ERR_PTR(-ERANGE); 10003 10004 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10005 if (pool == adapter->num_rx_pools) { 10006 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10007 u16 reserved_pools; 10008 10009 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10010 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10011 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10012 return ERR_PTR(-EBUSY); 10013 10014 /* Hardware has a limited number of available pools. Each VF, 10015 * and the PF require a pool. Check to ensure we don't 10016 * attempt to use more then the available number of pools. 10017 */ 10018 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10019 return ERR_PTR(-EBUSY); 10020 10021 /* Enable VMDq flag so device will be set in VM mode */ 10022 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10023 IXGBE_FLAG_SRIOV_ENABLED; 10024 10025 /* Try to reserve as many queues per pool as possible, 10026 * we start with the configurations that support 4 queues 10027 * per pools, followed by 2, and then by just 1 per pool. 10028 */ 10029 if (used_pools < 32 && adapter->num_rx_pools < 16) 10030 reserved_pools = min_t(u16, 10031 32 - used_pools, 10032 16 - adapter->num_rx_pools); 10033 else if (adapter->num_rx_pools < 32) 10034 reserved_pools = min_t(u16, 10035 64 - used_pools, 10036 32 - adapter->num_rx_pools); 10037 else 10038 reserved_pools = 64 - used_pools; 10039 10040 10041 if (!reserved_pools) 10042 return ERR_PTR(-EBUSY); 10043 10044 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10045 10046 /* Force reinit of ring allocation with VMDQ enabled */ 10047 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10048 if (err) 10049 return ERR_PTR(err); 10050 10051 if (pool >= adapter->num_rx_pools) 10052 return ERR_PTR(-ENOMEM); 10053 } 10054 10055 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10056 if (!accel) 10057 return ERR_PTR(-ENOMEM); 10058 10059 set_bit(pool, adapter->fwd_bitmask); 10060 netdev_set_sb_channel(vdev, pool); 10061 accel->pool = pool; 10062 accel->netdev = vdev; 10063 10064 if (!netif_running(pdev)) 10065 return accel; 10066 10067 err = ixgbe_fwd_ring_up(adapter, accel); 10068 if (err) 10069 return ERR_PTR(err); 10070 10071 return accel; 10072} 10073 10074static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10075{ 10076 struct ixgbe_fwd_adapter *accel = priv; 10077 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10078 unsigned int rxbase = accel->rx_base_queue; 10079 unsigned int i; 10080 10081 /* delete unicast filter associated with offloaded interface */ 10082 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10083 VMDQ_P(accel->pool)); 10084 10085 /* Allow remaining Rx packets to get flushed out of the 10086 * Rx FIFO before we drop the netdev for the ring. 10087 */ 10088 usleep_range(10000, 20000); 10089 10090 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10091 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10092 struct ixgbe_q_vector *qv = ring->q_vector; 10093 10094 /* Make sure we aren't processing any packets and clear 10095 * netdev to shut down the ring. 10096 */ 10097 if (netif_running(adapter->netdev)) 10098 napi_synchronize(&qv->napi); 10099 ring->netdev = NULL; 10100 } 10101 10102 /* unbind the queues and drop the subordinate channel config */ 10103 netdev_unbind_sb_channel(pdev, accel->netdev); 10104 netdev_set_sb_channel(accel->netdev, 0); 10105 10106 clear_bit(accel->pool, adapter->fwd_bitmask); 10107 kfree(accel); 10108} 10109 10110#define IXGBE_MAX_MAC_HDR_LEN 127 10111#define IXGBE_MAX_NETWORK_HDR_LEN 511 10112 10113static netdev_features_t 10114ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10115 netdev_features_t features) 10116{ 10117 unsigned int network_hdr_len, mac_hdr_len; 10118 10119 /* Make certain the headers can be described by a context descriptor */ 10120 mac_hdr_len = skb_network_header(skb) - skb->data; 10121 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10122 return features & ~(NETIF_F_HW_CSUM | 10123 NETIF_F_SCTP_CRC | 10124 NETIF_F_GSO_UDP_L4 | 10125 NETIF_F_HW_VLAN_CTAG_TX | 10126 NETIF_F_TSO | 10127 NETIF_F_TSO6); 10128 10129 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10130 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10131 return features & ~(NETIF_F_HW_CSUM | 10132 NETIF_F_SCTP_CRC | 10133 NETIF_F_GSO_UDP_L4 | 10134 NETIF_F_TSO | 10135 NETIF_F_TSO6); 10136 10137 /* We can only support IPV4 TSO in tunnels if we can mangle the 10138 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10139 * IPsec offoad sets skb->encapsulation but still can handle 10140 * the TSO, so it's the exception. 10141 */ 10142 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10143#ifdef CONFIG_IXGBE_IPSEC 10144 if (!secpath_exists(skb)) 10145#endif 10146 features &= ~NETIF_F_TSO; 10147 } 10148 10149 return features; 10150} 10151 10152static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10153{ 10154 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10155 struct ixgbe_adapter *adapter = netdev_priv(dev); 10156 struct bpf_prog *old_prog; 10157 bool need_reset; 10158 int num_queues; 10159 10160 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10161 return -EINVAL; 10162 10163 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10164 return -EINVAL; 10165 10166 /* verify ixgbe ring attributes are sufficient for XDP */ 10167 for (i = 0; i < adapter->num_rx_queues; i++) { 10168 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10169 10170 if (ring_is_rsc_enabled(ring)) 10171 return -EINVAL; 10172 10173 if (frame_size > ixgbe_rx_bufsz(ring)) 10174 return -EINVAL; 10175 } 10176 10177 if (nr_cpu_ids > MAX_XDP_QUEUES) 10178 return -ENOMEM; 10179 10180 old_prog = xchg(&adapter->xdp_prog, prog); 10181 need_reset = (!!prog != !!old_prog); 10182 10183 /* If transitioning XDP modes reconfigure rings */ 10184 if (need_reset) { 10185 int err; 10186 10187 if (!prog) 10188 /* Wait until ndo_xsk_wakeup completes. */ 10189 synchronize_rcu(); 10190 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10191 10192 if (err) { 10193 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10194 return -EINVAL; 10195 } 10196 } else { 10197 for (i = 0; i < adapter->num_rx_queues; i++) 10198 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10199 adapter->xdp_prog); 10200 } 10201 10202 if (old_prog) 10203 bpf_prog_put(old_prog); 10204 10205 /* Kick start the NAPI context if there is an AF_XDP socket open 10206 * on that queue id. This so that receiving will start. 10207 */ 10208 if (need_reset && prog) { 10209 num_queues = min_t(int, adapter->num_rx_queues, 10210 adapter->num_xdp_queues); 10211 for (i = 0; i < num_queues; i++) 10212 if (adapter->xdp_ring[i]->xsk_pool) 10213 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10214 XDP_WAKEUP_RX); 10215 } 10216 10217 return 0; 10218} 10219 10220static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10221{ 10222 struct ixgbe_adapter *adapter = netdev_priv(dev); 10223 10224 switch (xdp->command) { 10225 case XDP_SETUP_PROG: 10226 return ixgbe_xdp_setup(dev, xdp->prog); 10227 case XDP_SETUP_XSK_POOL: 10228 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10229 xdp->xsk.queue_id); 10230 10231 default: 10232 return -EINVAL; 10233 } 10234} 10235 10236void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10237{ 10238 /* Force memory writes to complete before letting h/w know there 10239 * are new descriptors to fetch. 10240 */ 10241 wmb(); 10242 writel(ring->next_to_use, ring->tail); 10243} 10244 10245static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10246 struct xdp_frame **frames, u32 flags) 10247{ 10248 struct ixgbe_adapter *adapter = netdev_priv(dev); 10249 struct ixgbe_ring *ring; 10250 int drops = 0; 10251 int i; 10252 10253 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10254 return -ENETDOWN; 10255 10256 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10257 return -EINVAL; 10258 10259 /* During program transitions its possible adapter->xdp_prog is assigned 10260 * but ring has not been configured yet. In this case simply abort xmit. 10261 */ 10262 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10263 if (unlikely(!ring)) 10264 return -ENXIO; 10265 10266 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10267 return -ENXIO; 10268 10269 for (i = 0; i < n; i++) { 10270 struct xdp_frame *xdpf = frames[i]; 10271 int err; 10272 10273 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10274 if (err != IXGBE_XDP_TX) { 10275 xdp_return_frame_rx_napi(xdpf); 10276 drops++; 10277 } 10278 } 10279 10280 if (unlikely(flags & XDP_XMIT_FLUSH)) 10281 ixgbe_xdp_ring_update_tail(ring); 10282 10283 return n - drops; 10284} 10285 10286static const struct net_device_ops ixgbe_netdev_ops = { 10287 .ndo_open = ixgbe_open, 10288 .ndo_stop = ixgbe_close, 10289 .ndo_start_xmit = ixgbe_xmit_frame, 10290 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10291 .ndo_validate_addr = eth_validate_addr, 10292 .ndo_set_mac_address = ixgbe_set_mac, 10293 .ndo_change_mtu = ixgbe_change_mtu, 10294 .ndo_tx_timeout = ixgbe_tx_timeout, 10295 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10296 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10297 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10298 .ndo_do_ioctl = ixgbe_ioctl, 10299 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10300 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10301 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10302 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10303 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 10304 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10305 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10306 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10307 .ndo_get_stats64 = ixgbe_get_stats64, 10308 .ndo_setup_tc = __ixgbe_setup_tc, 10309#ifdef IXGBE_FCOE 10310 .ndo_select_queue = ixgbe_select_queue, 10311 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10312 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10313 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10314 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10315 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10316 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10317 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10318#endif /* IXGBE_FCOE */ 10319 .ndo_set_features = ixgbe_set_features, 10320 .ndo_fix_features = ixgbe_fix_features, 10321 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10322 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10323 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10324 .ndo_dfwd_add_station = ixgbe_fwd_add, 10325 .ndo_dfwd_del_station = ixgbe_fwd_del, 10326 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, 10327 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, 10328 .ndo_features_check = ixgbe_features_check, 10329 .ndo_bpf = ixgbe_xdp, 10330 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10331 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10332}; 10333 10334static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10335 struct ixgbe_ring *tx_ring) 10336{ 10337 unsigned long wait_delay, delay_interval; 10338 struct ixgbe_hw *hw = &adapter->hw; 10339 u8 reg_idx = tx_ring->reg_idx; 10340 int wait_loop; 10341 u32 txdctl; 10342 10343 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10344 10345 /* delay mechanism from ixgbe_disable_tx */ 10346 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10347 10348 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10349 wait_delay = delay_interval; 10350 10351 while (wait_loop--) { 10352 usleep_range(wait_delay, wait_delay + 10); 10353 wait_delay += delay_interval * 2; 10354 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10355 10356 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10357 return; 10358 } 10359 10360 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10361} 10362 10363static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10364 struct ixgbe_ring *tx_ring) 10365{ 10366 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10367 ixgbe_disable_txr_hw(adapter, tx_ring); 10368} 10369 10370static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10371 struct ixgbe_ring *rx_ring) 10372{ 10373 unsigned long wait_delay, delay_interval; 10374 struct ixgbe_hw *hw = &adapter->hw; 10375 u8 reg_idx = rx_ring->reg_idx; 10376 int wait_loop; 10377 u32 rxdctl; 10378 10379 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10380 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10381 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10382 10383 /* write value back with RXDCTL.ENABLE bit cleared */ 10384 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10385 10386 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10387 if (hw->mac.type == ixgbe_mac_82598EB && 10388 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10389 return; 10390 10391 /* delay mechanism from ixgbe_disable_rx */ 10392 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10393 10394 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10395 wait_delay = delay_interval; 10396 10397 while (wait_loop--) { 10398 usleep_range(wait_delay, wait_delay + 10); 10399 wait_delay += delay_interval * 2; 10400 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10401 10402 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10403 return; 10404 } 10405 10406 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10407} 10408 10409static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10410{ 10411 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10412 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10413} 10414 10415static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10416{ 10417 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10418 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10419} 10420 10421/** 10422 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10423 * @adapter: adapter structure 10424 * @ring: ring index 10425 * 10426 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10427 * assumes that the netdev is running. 10428 **/ 10429void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10430{ 10431 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10432 10433 rx_ring = adapter->rx_ring[ring]; 10434 tx_ring = adapter->tx_ring[ring]; 10435 xdp_ring = adapter->xdp_ring[ring]; 10436 10437 ixgbe_disable_txr(adapter, tx_ring); 10438 if (xdp_ring) 10439 ixgbe_disable_txr(adapter, xdp_ring); 10440 ixgbe_disable_rxr_hw(adapter, rx_ring); 10441 10442 if (xdp_ring) 10443 synchronize_rcu(); 10444 10445 /* Rx/Tx/XDP Tx share the same napi context. */ 10446 napi_disable(&rx_ring->q_vector->napi); 10447 10448 ixgbe_clean_tx_ring(tx_ring); 10449 if (xdp_ring) 10450 ixgbe_clean_tx_ring(xdp_ring); 10451 ixgbe_clean_rx_ring(rx_ring); 10452 10453 ixgbe_reset_txr_stats(tx_ring); 10454 if (xdp_ring) 10455 ixgbe_reset_txr_stats(xdp_ring); 10456 ixgbe_reset_rxr_stats(rx_ring); 10457} 10458 10459/** 10460 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10461 * @adapter: adapter structure 10462 * @ring: ring index 10463 * 10464 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10465 * assumes that the netdev is running. 10466 **/ 10467void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10468{ 10469 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10470 10471 rx_ring = adapter->rx_ring[ring]; 10472 tx_ring = adapter->tx_ring[ring]; 10473 xdp_ring = adapter->xdp_ring[ring]; 10474 10475 /* Rx/Tx/XDP Tx share the same napi context. */ 10476 napi_enable(&rx_ring->q_vector->napi); 10477 10478 ixgbe_configure_tx_ring(adapter, tx_ring); 10479 if (xdp_ring) 10480 ixgbe_configure_tx_ring(adapter, xdp_ring); 10481 ixgbe_configure_rx_ring(adapter, rx_ring); 10482 10483 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10484 if (xdp_ring) 10485 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10486} 10487 10488/** 10489 * ixgbe_enumerate_functions - Get the number of ports this device has 10490 * @adapter: adapter structure 10491 * 10492 * This function enumerates the phsyical functions co-located on a single slot, 10493 * in order to determine how many ports a device has. This is most useful in 10494 * determining the required GT/s of PCIe bandwidth necessary for optimal 10495 * performance. 10496 **/ 10497static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10498{ 10499 struct pci_dev *entry, *pdev = adapter->pdev; 10500 int physfns = 0; 10501 10502 /* Some cards can not use the generic count PCIe functions method, 10503 * because they are behind a parent switch, so we hardcode these with 10504 * the correct number of functions. 10505 */ 10506 if (ixgbe_pcie_from_parent(&adapter->hw)) 10507 physfns = 4; 10508 10509 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10510 /* don't count virtual functions */ 10511 if (entry->is_virtfn) 10512 continue; 10513 10514 /* When the devices on the bus don't all match our device ID, 10515 * we can't reliably determine the correct number of 10516 * functions. This can occur if a function has been direct 10517 * attached to a virtual machine using VT-d, for example. In 10518 * this case, simply return -1 to indicate this. 10519 */ 10520 if ((entry->vendor != pdev->vendor) || 10521 (entry->device != pdev->device)) 10522 return -1; 10523 10524 physfns++; 10525 } 10526 10527 return physfns; 10528} 10529 10530/** 10531 * ixgbe_wol_supported - Check whether device supports WoL 10532 * @adapter: the adapter private structure 10533 * @device_id: the device ID 10534 * @subdevice_id: the subsystem device ID 10535 * 10536 * This function is used by probe and ethtool to determine 10537 * which devices have WoL support 10538 * 10539 **/ 10540bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10541 u16 subdevice_id) 10542{ 10543 struct ixgbe_hw *hw = &adapter->hw; 10544 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10545 10546 /* WOL not supported on 82598 */ 10547 if (hw->mac.type == ixgbe_mac_82598EB) 10548 return false; 10549 10550 /* check eeprom to see if WOL is enabled for X540 and newer */ 10551 if (hw->mac.type >= ixgbe_mac_X540) { 10552 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10553 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10554 (hw->bus.func == 0))) 10555 return true; 10556 } 10557 10558 /* WOL is determined based on device IDs for 82599 MACs */ 10559 switch (device_id) { 10560 case IXGBE_DEV_ID_82599_SFP: 10561 /* Only these subdevices could supports WOL */ 10562 switch (subdevice_id) { 10563 case IXGBE_SUBDEV_ID_82599_560FLR: 10564 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10565 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10566 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10567 /* only support first port */ 10568 if (hw->bus.func != 0) 10569 break; 10570 fallthrough; 10571 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10572 case IXGBE_SUBDEV_ID_82599_SFP: 10573 case IXGBE_SUBDEV_ID_82599_RNDC: 10574 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10575 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10576 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10577 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10578 return true; 10579 } 10580 break; 10581 case IXGBE_DEV_ID_82599EN_SFP: 10582 /* Only these subdevices support WOL */ 10583 switch (subdevice_id) { 10584 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10585 return true; 10586 } 10587 break; 10588 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10589 /* All except this subdevice support WOL */ 10590 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10591 return true; 10592 break; 10593 case IXGBE_DEV_ID_82599_KX4: 10594 return true; 10595 default: 10596 break; 10597 } 10598 10599 return false; 10600} 10601 10602/** 10603 * ixgbe_set_fw_version - Set FW version 10604 * @adapter: the adapter private structure 10605 * 10606 * This function is used by probe and ethtool to determine the FW version to 10607 * format to display. The FW version is taken from the EEPROM/NVM. 10608 */ 10609static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10610{ 10611 struct ixgbe_hw *hw = &adapter->hw; 10612 struct ixgbe_nvm_version nvm_ver; 10613 10614 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10615 if (nvm_ver.oem_valid) { 10616 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10617 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10618 nvm_ver.oem_release); 10619 return; 10620 } 10621 10622 ixgbe_get_etk_id(hw, &nvm_ver); 10623 ixgbe_get_orom_version(hw, &nvm_ver); 10624 10625 if (nvm_ver.or_valid) { 10626 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10627 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10628 nvm_ver.or_build, nvm_ver.or_patch); 10629 return; 10630 } 10631 10632 /* Set ETrack ID format */ 10633 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10634 "0x%08x", nvm_ver.etk_id); 10635} 10636 10637/** 10638 * ixgbe_probe - Device Initialization Routine 10639 * @pdev: PCI device information struct 10640 * @ent: entry in ixgbe_pci_tbl 10641 * 10642 * Returns 0 on success, negative on failure 10643 * 10644 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10645 * The OS initialization, configuring of the adapter private structure, 10646 * and a hardware reset occur. 10647 **/ 10648static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10649{ 10650 struct net_device *netdev; 10651 struct ixgbe_adapter *adapter = NULL; 10652 struct ixgbe_hw *hw; 10653 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10654 int i, err, pci_using_dac, expected_gts; 10655 unsigned int indices = MAX_TX_QUEUES; 10656 u8 part_str[IXGBE_PBANUM_LENGTH]; 10657 bool disable_dev = false; 10658#ifdef IXGBE_FCOE 10659 u16 device_caps; 10660#endif 10661 u32 eec; 10662 10663 /* Catch broken hardware that put the wrong VF device ID in 10664 * the PCIe SR-IOV capability. 10665 */ 10666 if (pdev->is_virtfn) { 10667 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10668 pci_name(pdev), pdev->vendor, pdev->device); 10669 return -EINVAL; 10670 } 10671 10672 err = pci_enable_device_mem(pdev); 10673 if (err) 10674 return err; 10675 10676 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10677 pci_using_dac = 1; 10678 } else { 10679 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10680 if (err) { 10681 dev_err(&pdev->dev, 10682 "No usable DMA configuration, aborting\n"); 10683 goto err_dma; 10684 } 10685 pci_using_dac = 0; 10686 } 10687 10688 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10689 if (err) { 10690 dev_err(&pdev->dev, 10691 "pci_request_selected_regions failed 0x%x\n", err); 10692 goto err_pci_reg; 10693 } 10694 10695 pci_enable_pcie_error_reporting(pdev); 10696 10697 pci_set_master(pdev); 10698 pci_save_state(pdev); 10699 10700 if (ii->mac == ixgbe_mac_82598EB) { 10701#ifdef CONFIG_IXGBE_DCB 10702 /* 8 TC w/ 4 queues per TC */ 10703 indices = 4 * MAX_TRAFFIC_CLASS; 10704#else 10705 indices = IXGBE_MAX_RSS_INDICES; 10706#endif 10707 } 10708 10709 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10710 if (!netdev) { 10711 err = -ENOMEM; 10712 goto err_alloc_etherdev; 10713 } 10714 10715 SET_NETDEV_DEV(netdev, &pdev->dev); 10716 10717 adapter = netdev_priv(netdev); 10718 10719 adapter->netdev = netdev; 10720 adapter->pdev = pdev; 10721 hw = &adapter->hw; 10722 hw->back = adapter; 10723 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10724 10725 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10726 pci_resource_len(pdev, 0)); 10727 adapter->io_addr = hw->hw_addr; 10728 if (!hw->hw_addr) { 10729 err = -EIO; 10730 goto err_ioremap; 10731 } 10732 10733 netdev->netdev_ops = &ixgbe_netdev_ops; 10734 ixgbe_set_ethtool_ops(netdev); 10735 netdev->watchdog_timeo = 5 * HZ; 10736 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10737 10738 /* Setup hw api */ 10739 hw->mac.ops = *ii->mac_ops; 10740 hw->mac.type = ii->mac; 10741 hw->mvals = ii->mvals; 10742 if (ii->link_ops) 10743 hw->link.ops = *ii->link_ops; 10744 10745 /* EEPROM */ 10746 hw->eeprom.ops = *ii->eeprom_ops; 10747 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10748 if (ixgbe_removed(hw->hw_addr)) { 10749 err = -EIO; 10750 goto err_ioremap; 10751 } 10752 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10753 if (!(eec & BIT(8))) 10754 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10755 10756 /* PHY */ 10757 hw->phy.ops = *ii->phy_ops; 10758 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10759 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10760 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10761 hw->phy.mdio.mmds = 0; 10762 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10763 hw->phy.mdio.dev = netdev; 10764 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10765 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10766 10767 /* setup the private structure */ 10768 err = ixgbe_sw_init(adapter, ii); 10769 if (err) 10770 goto err_sw_init; 10771 10772 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 10773 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 10774 10775 switch (adapter->hw.mac.type) { 10776 case ixgbe_mac_X550: 10777 case ixgbe_mac_X550EM_x: 10778 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 10779 break; 10780 case ixgbe_mac_x550em_a: 10781 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 10782 break; 10783 default: 10784 break; 10785 } 10786 10787 /* Make sure the SWFW semaphore is in a valid state */ 10788 if (hw->mac.ops.init_swfw_sync) 10789 hw->mac.ops.init_swfw_sync(hw); 10790 10791 /* Make it possible the adapter to be woken up via WOL */ 10792 switch (adapter->hw.mac.type) { 10793 case ixgbe_mac_82599EB: 10794 case ixgbe_mac_X540: 10795 case ixgbe_mac_X550: 10796 case ixgbe_mac_X550EM_x: 10797 case ixgbe_mac_x550em_a: 10798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10799 break; 10800 default: 10801 break; 10802 } 10803 10804 /* 10805 * If there is a fan on this device and it has failed log the 10806 * failure. 10807 */ 10808 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10809 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10810 if (esdp & IXGBE_ESDP_SDP1) 10811 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10812 } 10813 10814 if (allow_unsupported_sfp) 10815 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10816 10817 /* reset_hw fills in the perm_addr as well */ 10818 hw->phy.reset_if_overtemp = true; 10819 err = hw->mac.ops.reset_hw(hw); 10820 hw->phy.reset_if_overtemp = false; 10821 ixgbe_set_eee_capable(adapter); 10822 if (err == -ENOENT) { 10823 err = 0; 10824 } else if (err == -EOPNOTSUPP) { 10825 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10826 e_dev_err("Reload the driver after installing a supported module.\n"); 10827 goto err_sw_init; 10828 } else if (err) { 10829 e_dev_err("HW Init failed: %d\n", err); 10830 goto err_sw_init; 10831 } 10832 10833#ifdef CONFIG_PCI_IOV 10834 /* SR-IOV not supported on the 82598 */ 10835 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10836 goto skip_sriov; 10837 /* Mailbox */ 10838 ixgbe_init_mbx_params_pf(hw); 10839 hw->mbx.ops = ii->mbx_ops; 10840 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10841 ixgbe_enable_sriov(adapter, max_vfs); 10842skip_sriov: 10843 10844#endif 10845 netdev->features = NETIF_F_SG | 10846 NETIF_F_TSO | 10847 NETIF_F_TSO6 | 10848 NETIF_F_RXHASH | 10849 NETIF_F_RXCSUM | 10850 NETIF_F_HW_CSUM; 10851 10852#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10853 NETIF_F_GSO_GRE_CSUM | \ 10854 NETIF_F_GSO_IPXIP4 | \ 10855 NETIF_F_GSO_IPXIP6 | \ 10856 NETIF_F_GSO_UDP_TUNNEL | \ 10857 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10858 10859 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10860 netdev->features |= NETIF_F_GSO_PARTIAL | 10861 IXGBE_GSO_PARTIAL_FEATURES; 10862 10863 if (hw->mac.type >= ixgbe_mac_82599EB) 10864 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 10865 10866#ifdef CONFIG_IXGBE_IPSEC 10867#define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10868 NETIF_F_HW_ESP_TX_CSUM | \ 10869 NETIF_F_GSO_ESP) 10870 10871 if (adapter->ipsec) 10872 netdev->features |= IXGBE_ESP_FEATURES; 10873#endif 10874 /* copy netdev features into list of user selectable features */ 10875 netdev->hw_features |= netdev->features | 10876 NETIF_F_HW_VLAN_CTAG_FILTER | 10877 NETIF_F_HW_VLAN_CTAG_RX | 10878 NETIF_F_HW_VLAN_CTAG_TX | 10879 NETIF_F_RXALL | 10880 NETIF_F_HW_L2FW_DOFFLOAD; 10881 10882 if (hw->mac.type >= ixgbe_mac_82599EB) 10883 netdev->hw_features |= NETIF_F_NTUPLE | 10884 NETIF_F_HW_TC; 10885 10886 if (pci_using_dac) 10887 netdev->features |= NETIF_F_HIGHDMA; 10888 10889 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10890 netdev->hw_enc_features |= netdev->vlan_features; 10891 netdev->mpls_features |= NETIF_F_SG | 10892 NETIF_F_TSO | 10893 NETIF_F_TSO6 | 10894 NETIF_F_HW_CSUM; 10895 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10896 10897 /* set this bit last since it cannot be part of vlan_features */ 10898 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10899 NETIF_F_HW_VLAN_CTAG_RX | 10900 NETIF_F_HW_VLAN_CTAG_TX; 10901 10902 netdev->priv_flags |= IFF_UNICAST_FLT; 10903 netdev->priv_flags |= IFF_SUPP_NOFCS; 10904 10905 /* MTU range: 68 - 9710 */ 10906 netdev->min_mtu = ETH_MIN_MTU; 10907 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10908 10909#ifdef CONFIG_IXGBE_DCB 10910 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10911 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10912#endif 10913 10914#ifdef IXGBE_FCOE 10915 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10916 unsigned int fcoe_l; 10917 10918 if (hw->mac.ops.get_device_caps) { 10919 hw->mac.ops.get_device_caps(hw, &device_caps); 10920 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10921 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10922 } 10923 10924 10925 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10926 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10927 10928 netdev->features |= NETIF_F_FSO | 10929 NETIF_F_FCOE_CRC; 10930 10931 netdev->vlan_features |= NETIF_F_FSO | 10932 NETIF_F_FCOE_CRC | 10933 NETIF_F_FCOE_MTU; 10934 } 10935#endif /* IXGBE_FCOE */ 10936 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10937 netdev->hw_features |= NETIF_F_LRO; 10938 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10939 netdev->features |= NETIF_F_LRO; 10940 10941 if (ixgbe_check_fw_error(adapter)) { 10942 err = -EIO; 10943 goto err_sw_init; 10944 } 10945 10946 /* make sure the EEPROM is good */ 10947 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10948 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10949 err = -EIO; 10950 goto err_sw_init; 10951 } 10952 10953 eth_platform_get_mac_address(&adapter->pdev->dev, 10954 adapter->hw.mac.perm_addr); 10955 10956 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10957 10958 if (!is_valid_ether_addr(netdev->dev_addr)) { 10959 e_dev_err("invalid MAC address\n"); 10960 err = -EIO; 10961 goto err_sw_init; 10962 } 10963 10964 /* Set hw->mac.addr to permanent MAC address */ 10965 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10966 ixgbe_mac_set_default_filter(adapter); 10967 10968 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10969 10970 if (ixgbe_removed(hw->hw_addr)) { 10971 err = -EIO; 10972 goto err_sw_init; 10973 } 10974 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10975 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10976 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10977 10978 err = ixgbe_init_interrupt_scheme(adapter); 10979 if (err) 10980 goto err_sw_init; 10981 10982 for (i = 0; i < adapter->num_rx_queues; i++) 10983 u64_stats_init(&adapter->rx_ring[i]->syncp); 10984 for (i = 0; i < adapter->num_tx_queues; i++) 10985 u64_stats_init(&adapter->tx_ring[i]->syncp); 10986 for (i = 0; i < adapter->num_xdp_queues; i++) 10987 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10988 10989 /* WOL not supported for all devices */ 10990 adapter->wol = 0; 10991 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10992 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10993 pdev->subsystem_device); 10994 if (hw->wol_enabled) 10995 adapter->wol = IXGBE_WUFC_MAG; 10996 10997 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10998 10999 /* save off EEPROM version number */ 11000 ixgbe_set_fw_version(adapter); 11001 11002 /* pick up the PCI bus settings for reporting later */ 11003 if (ixgbe_pcie_from_parent(hw)) 11004 ixgbe_get_parent_bus_info(adapter); 11005 else 11006 hw->mac.ops.get_bus_info(hw); 11007 11008 /* calculate the expected PCIe bandwidth required for optimal 11009 * performance. Note that some older parts will never have enough 11010 * bandwidth due to being older generation PCIe parts. We clamp these 11011 * parts to ensure no warning is displayed if it can't be fixed. 11012 */ 11013 switch (hw->mac.type) { 11014 case ixgbe_mac_82598EB: 11015 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11016 break; 11017 default: 11018 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11019 break; 11020 } 11021 11022 /* don't check link if we failed to enumerate functions */ 11023 if (expected_gts > 0) 11024 ixgbe_check_minimum_link(adapter, expected_gts); 11025 11026 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11027 if (err) 11028 strlcpy(part_str, "Unknown", sizeof(part_str)); 11029 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11030 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11031 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11032 part_str); 11033 else 11034 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11035 hw->mac.type, hw->phy.type, part_str); 11036 11037 e_dev_info("%pM\n", netdev->dev_addr); 11038 11039 /* reset the hardware with the new settings */ 11040 err = hw->mac.ops.start_hw(hw); 11041 if (err == -EACCES) { 11042 /* We are running on a pre-production device, log a warning */ 11043 e_dev_warn("This device is a pre-production adapter/LOM. " 11044 "Please be aware there may be issues associated " 11045 "with your hardware. If you are experiencing " 11046 "problems please contact your Intel or hardware " 11047 "representative who provided you with this " 11048 "hardware.\n"); 11049 } 11050 strcpy(netdev->name, "eth%d"); 11051 pci_set_drvdata(pdev, adapter); 11052 err = register_netdev(netdev); 11053 if (err) 11054 goto err_register; 11055 11056 11057 /* power down the optics for 82599 SFP+ fiber */ 11058 if (hw->mac.ops.disable_tx_laser) 11059 hw->mac.ops.disable_tx_laser(hw); 11060 11061 /* carrier off reporting is important to ethtool even BEFORE open */ 11062 netif_carrier_off(netdev); 11063 11064#ifdef CONFIG_IXGBE_DCA 11065 if (dca_add_requester(&pdev->dev) == 0) { 11066 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11067 ixgbe_setup_dca(adapter); 11068 } 11069#endif 11070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11071 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11072 for (i = 0; i < adapter->num_vfs; i++) 11073 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11074 } 11075 11076 /* firmware requires driver version to be 0xFFFFFFFF 11077 * since os does not support feature 11078 */ 11079 if (hw->mac.ops.set_fw_drv_ver) 11080 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11081 sizeof(UTS_RELEASE) - 1, 11082 UTS_RELEASE); 11083 11084 /* add san mac addr to netdev */ 11085 ixgbe_add_sanmac_netdev(netdev); 11086 11087 e_dev_info("%s\n", ixgbe_default_device_descr); 11088 11089#ifdef CONFIG_IXGBE_HWMON 11090 if (ixgbe_sysfs_init(adapter)) 11091 e_err(probe, "failed to allocate sysfs resources\n"); 11092#endif /* CONFIG_IXGBE_HWMON */ 11093 11094 ixgbe_dbg_adapter_init(adapter); 11095 11096 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11097 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11098 hw->mac.ops.setup_link(hw, 11099 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11100 true); 11101 11102 err = ixgbe_mii_bus_init(hw); 11103 if (err) 11104 goto err_netdev; 11105 11106 return 0; 11107 11108err_netdev: 11109 unregister_netdev(netdev); 11110err_register: 11111 ixgbe_release_hw_control(adapter); 11112 ixgbe_clear_interrupt_scheme(adapter); 11113err_sw_init: 11114 ixgbe_disable_sriov(adapter); 11115 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11116 iounmap(adapter->io_addr); 11117 kfree(adapter->jump_tables[0]); 11118 kfree(adapter->mac_table); 11119 kfree(adapter->rss_key); 11120 bitmap_free(adapter->af_xdp_zc_qps); 11121err_ioremap: 11122 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11123 free_netdev(netdev); 11124err_alloc_etherdev: 11125 pci_disable_pcie_error_reporting(pdev); 11126 pci_release_mem_regions(pdev); 11127err_pci_reg: 11128err_dma: 11129 if (!adapter || disable_dev) 11130 pci_disable_device(pdev); 11131 return err; 11132} 11133 11134/** 11135 * ixgbe_remove - Device Removal Routine 11136 * @pdev: PCI device information struct 11137 * 11138 * ixgbe_remove is called by the PCI subsystem to alert the driver 11139 * that it should release a PCI device. The could be caused by a 11140 * Hot-Plug event, or because the driver is going to be removed from 11141 * memory. 11142 **/ 11143static void ixgbe_remove(struct pci_dev *pdev) 11144{ 11145 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11146 struct net_device *netdev; 11147 bool disable_dev; 11148 int i; 11149 11150 /* if !adapter then we already cleaned up in probe */ 11151 if (!adapter) 11152 return; 11153 11154 netdev = adapter->netdev; 11155 ixgbe_dbg_adapter_exit(adapter); 11156 11157 set_bit(__IXGBE_REMOVING, &adapter->state); 11158 cancel_work_sync(&adapter->service_task); 11159 11160 if (adapter->mii_bus) 11161 mdiobus_unregister(adapter->mii_bus); 11162 11163#ifdef CONFIG_IXGBE_DCA 11164 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11165 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11166 dca_remove_requester(&pdev->dev); 11167 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11168 IXGBE_DCA_CTRL_DCA_DISABLE); 11169 } 11170 11171#endif 11172#ifdef CONFIG_IXGBE_HWMON 11173 ixgbe_sysfs_exit(adapter); 11174#endif /* CONFIG_IXGBE_HWMON */ 11175 11176 /* remove the added san mac */ 11177 ixgbe_del_sanmac_netdev(netdev); 11178 11179#ifdef CONFIG_PCI_IOV 11180 ixgbe_disable_sriov(adapter); 11181#endif 11182 if (netdev->reg_state == NETREG_REGISTERED) 11183 unregister_netdev(netdev); 11184 11185 ixgbe_stop_ipsec_offload(adapter); 11186 ixgbe_clear_interrupt_scheme(adapter); 11187 11188 ixgbe_release_hw_control(adapter); 11189 11190#ifdef CONFIG_DCB 11191 kfree(adapter->ixgbe_ieee_pfc); 11192 kfree(adapter->ixgbe_ieee_ets); 11193 11194#endif 11195 iounmap(adapter->io_addr); 11196 pci_release_mem_regions(pdev); 11197 11198 e_dev_info("complete\n"); 11199 11200 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11201 if (adapter->jump_tables[i]) { 11202 kfree(adapter->jump_tables[i]->input); 11203 kfree(adapter->jump_tables[i]->mask); 11204 } 11205 kfree(adapter->jump_tables[i]); 11206 } 11207 11208 kfree(adapter->mac_table); 11209 kfree(adapter->rss_key); 11210 bitmap_free(adapter->af_xdp_zc_qps); 11211 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11212 free_netdev(netdev); 11213 11214 pci_disable_pcie_error_reporting(pdev); 11215 11216 if (disable_dev) 11217 pci_disable_device(pdev); 11218} 11219 11220/** 11221 * ixgbe_io_error_detected - called when PCI error is detected 11222 * @pdev: Pointer to PCI device 11223 * @state: The current pci connection state 11224 * 11225 * This function is called after a PCI bus error affecting 11226 * this device has been detected. 11227 */ 11228static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11229 pci_channel_state_t state) 11230{ 11231 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11232 struct net_device *netdev = adapter->netdev; 11233 11234#ifdef CONFIG_PCI_IOV 11235 struct ixgbe_hw *hw = &adapter->hw; 11236 struct pci_dev *bdev, *vfdev; 11237 u32 dw0, dw1, dw2, dw3; 11238 int vf, pos; 11239 u16 req_id, pf_func; 11240 11241 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11242 adapter->num_vfs == 0) 11243 goto skip_bad_vf_detection; 11244 11245 bdev = pdev->bus->self; 11246 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11247 bdev = bdev->bus->self; 11248 11249 if (!bdev) 11250 goto skip_bad_vf_detection; 11251 11252 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11253 if (!pos) 11254 goto skip_bad_vf_detection; 11255 11256 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11257 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11258 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11259 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11260 if (ixgbe_removed(hw->hw_addr)) 11261 goto skip_bad_vf_detection; 11262 11263 req_id = dw1 >> 16; 11264 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11265 if (!(req_id & 0x0080)) 11266 goto skip_bad_vf_detection; 11267 11268 pf_func = req_id & 0x01; 11269 if ((pf_func & 1) == (pdev->devfn & 1)) { 11270 unsigned int device_id; 11271 11272 vf = (req_id & 0x7F) >> 1; 11273 e_dev_err("VF %d has caused a PCIe error\n", vf); 11274 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11275 "%8.8x\tdw3: %8.8x\n", 11276 dw0, dw1, dw2, dw3); 11277 switch (adapter->hw.mac.type) { 11278 case ixgbe_mac_82599EB: 11279 device_id = IXGBE_82599_VF_DEVICE_ID; 11280 break; 11281 case ixgbe_mac_X540: 11282 device_id = IXGBE_X540_VF_DEVICE_ID; 11283 break; 11284 case ixgbe_mac_X550: 11285 device_id = IXGBE_DEV_ID_X550_VF; 11286 break; 11287 case ixgbe_mac_X550EM_x: 11288 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11289 break; 11290 case ixgbe_mac_x550em_a: 11291 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11292 break; 11293 default: 11294 device_id = 0; 11295 break; 11296 } 11297 11298 /* Find the pci device of the offending VF */ 11299 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11300 while (vfdev) { 11301 if (vfdev->devfn == (req_id & 0xFF)) 11302 break; 11303 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11304 device_id, vfdev); 11305 } 11306 /* 11307 * There's a slim chance the VF could have been hot plugged, 11308 * so if it is no longer present we don't need to issue the 11309 * VFLR. Just clean up the AER in that case. 11310 */ 11311 if (vfdev) { 11312 pcie_flr(vfdev); 11313 /* Free device reference count */ 11314 pci_dev_put(vfdev); 11315 } 11316 } 11317 11318 /* 11319 * Even though the error may have occurred on the other port 11320 * we still need to increment the vf error reference count for 11321 * both ports because the I/O resume function will be called 11322 * for both of them. 11323 */ 11324 adapter->vferr_refcount++; 11325 11326 return PCI_ERS_RESULT_RECOVERED; 11327 11328skip_bad_vf_detection: 11329#endif /* CONFIG_PCI_IOV */ 11330 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11331 return PCI_ERS_RESULT_DISCONNECT; 11332 11333 if (!netif_device_present(netdev)) 11334 return PCI_ERS_RESULT_DISCONNECT; 11335 11336 rtnl_lock(); 11337 netif_device_detach(netdev); 11338 11339 if (netif_running(netdev)) 11340 ixgbe_close_suspend(adapter); 11341 11342 if (state == pci_channel_io_perm_failure) { 11343 rtnl_unlock(); 11344 return PCI_ERS_RESULT_DISCONNECT; 11345 } 11346 11347 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11348 pci_disable_device(pdev); 11349 rtnl_unlock(); 11350 11351 /* Request a slot reset. */ 11352 return PCI_ERS_RESULT_NEED_RESET; 11353} 11354 11355/** 11356 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11357 * @pdev: Pointer to PCI device 11358 * 11359 * Restart the card from scratch, as if from a cold-boot. 11360 */ 11361static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11362{ 11363 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11364 pci_ers_result_t result; 11365 11366 if (pci_enable_device_mem(pdev)) { 11367 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11368 result = PCI_ERS_RESULT_DISCONNECT; 11369 } else { 11370 smp_mb__before_atomic(); 11371 clear_bit(__IXGBE_DISABLED, &adapter->state); 11372 adapter->hw.hw_addr = adapter->io_addr; 11373 pci_set_master(pdev); 11374 pci_restore_state(pdev); 11375 pci_save_state(pdev); 11376 11377 pci_wake_from_d3(pdev, false); 11378 11379 ixgbe_reset(adapter); 11380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11381 result = PCI_ERS_RESULT_RECOVERED; 11382 } 11383 11384 return result; 11385} 11386 11387/** 11388 * ixgbe_io_resume - called when traffic can start flowing again. 11389 * @pdev: Pointer to PCI device 11390 * 11391 * This callback is called when the error recovery driver tells us that 11392 * its OK to resume normal operation. 11393 */ 11394static void ixgbe_io_resume(struct pci_dev *pdev) 11395{ 11396 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11397 struct net_device *netdev = adapter->netdev; 11398 11399#ifdef CONFIG_PCI_IOV 11400 if (adapter->vferr_refcount) { 11401 e_info(drv, "Resuming after VF err\n"); 11402 adapter->vferr_refcount--; 11403 return; 11404 } 11405 11406#endif 11407 rtnl_lock(); 11408 if (netif_running(netdev)) 11409 ixgbe_open(netdev); 11410 11411 netif_device_attach(netdev); 11412 rtnl_unlock(); 11413} 11414 11415static const struct pci_error_handlers ixgbe_err_handler = { 11416 .error_detected = ixgbe_io_error_detected, 11417 .slot_reset = ixgbe_io_slot_reset, 11418 .resume = ixgbe_io_resume, 11419}; 11420 11421static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11422 11423static struct pci_driver ixgbe_driver = { 11424 .name = ixgbe_driver_name, 11425 .id_table = ixgbe_pci_tbl, 11426 .probe = ixgbe_probe, 11427 .remove = ixgbe_remove, 11428 .driver.pm = &ixgbe_pm_ops, 11429 .shutdown = ixgbe_shutdown, 11430 .sriov_configure = ixgbe_pci_sriov_configure, 11431 .err_handler = &ixgbe_err_handler 11432}; 11433 11434/** 11435 * ixgbe_init_module - Driver Registration Routine 11436 * 11437 * ixgbe_init_module is the first routine called when the driver is 11438 * loaded. All it does is register with the PCI subsystem. 11439 **/ 11440static int __init ixgbe_init_module(void) 11441{ 11442 int ret; 11443 pr_info("%s\n", ixgbe_driver_string); 11444 pr_info("%s\n", ixgbe_copyright); 11445 11446 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11447 if (!ixgbe_wq) { 11448 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11449 return -ENOMEM; 11450 } 11451 11452 ixgbe_dbg_init(); 11453 11454 ret = pci_register_driver(&ixgbe_driver); 11455 if (ret) { 11456 destroy_workqueue(ixgbe_wq); 11457 ixgbe_dbg_exit(); 11458 return ret; 11459 } 11460 11461#ifdef CONFIG_IXGBE_DCA 11462 dca_register_notify(&dca_notifier); 11463#endif 11464 11465 return 0; 11466} 11467 11468module_init(ixgbe_init_module); 11469 11470/** 11471 * ixgbe_exit_module - Driver Exit Cleanup Routine 11472 * 11473 * ixgbe_exit_module is called just before the driver is removed 11474 * from memory. 11475 **/ 11476static void __exit ixgbe_exit_module(void) 11477{ 11478#ifdef CONFIG_IXGBE_DCA 11479 dca_unregister_notify(&dca_notifier); 11480#endif 11481 pci_unregister_driver(&ixgbe_driver); 11482 11483 ixgbe_dbg_exit(); 11484 if (ixgbe_wq) { 11485 destroy_workqueue(ixgbe_wq); 11486 ixgbe_wq = NULL; 11487 } 11488} 11489 11490#ifdef CONFIG_IXGBE_DCA 11491static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11492 void *p) 11493{ 11494 int ret_val; 11495 11496 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11497 __ixgbe_notify_dca); 11498 11499 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11500} 11501 11502#endif /* CONFIG_IXGBE_DCA */ 11503 11504module_exit(ixgbe_exit_module); 11505 11506/* ixgbe_main.c */ 11507