1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#ifndef _IXGBE_H_ 5#define _IXGBE_H_ 6 7#include <linux/bitops.h> 8#include <linux/types.h> 9#include <linux/pci.h> 10#include <linux/netdevice.h> 11#include <linux/cpumask.h> 12#include <linux/aer.h> 13#include <linux/if_vlan.h> 14#include <linux/jiffies.h> 15#include <linux/phy.h> 16 17#include <linux/timecounter.h> 18#include <linux/net_tstamp.h> 19#include <linux/ptp_clock_kernel.h> 20 21#include "ixgbe_type.h" 22#include "ixgbe_common.h" 23#include "ixgbe_dcb.h" 24#if IS_ENABLED(CONFIG_FCOE) 25#define IXGBE_FCOE 26#include "ixgbe_fcoe.h" 27#endif /* IS_ENABLED(CONFIG_FCOE) */ 28#ifdef CONFIG_IXGBE_DCA 29#include <linux/dca.h> 30#endif 31#include "ixgbe_ipsec.h" 32 33#include <net/xdp.h> 34 35/* common prefix used by pr_<> macros */ 36#undef pr_fmt 37#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39/* TX/RX descriptor defines */ 40#define IXGBE_DEFAULT_TXD 512 41#define IXGBE_DEFAULT_TX_WORK 256 42#define IXGBE_MAX_TXD 4096 43#define IXGBE_MIN_TXD 64 44 45#if (PAGE_SIZE < 8192) 46#define IXGBE_DEFAULT_RXD 512 47#else 48#define IXGBE_DEFAULT_RXD 128 49#endif 50#define IXGBE_MAX_RXD 4096 51#define IXGBE_MIN_RXD 64 52 53/* flow control */ 54#define IXGBE_MIN_FCRTL 0x40 55#define IXGBE_MAX_FCRTL 0x7FF80 56#define IXGBE_MIN_FCRTH 0x600 57#define IXGBE_MAX_FCRTH 0x7FFF0 58#define IXGBE_DEFAULT_FCPAUSE 0xFFFF 59#define IXGBE_MIN_FCPAUSE 0 60#define IXGBE_MAX_FCPAUSE 0xFFFF 61 62/* Supported Rx Buffer Sizes */ 63#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 64#define IXGBE_RXBUFFER_1536 1536 65#define IXGBE_RXBUFFER_2K 2048 66#define IXGBE_RXBUFFER_3K 3072 67#define IXGBE_RXBUFFER_4K 4096 68#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 69 70#define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 71 72/* Attempt to maximize the headroom available for incoming frames. We 73 * use a 2K buffer for receives and need 1536/1534 to store the data for 74 * the frame. This leaves us with 512 bytes of room. From that we need 75 * to deduct the space needed for the shared info and the padding needed 76 * to IP align the frame. 77 * 78 * Note: For cache line sizes 256 or larger this value is going to end 79 * up negative. In these cases we should fall back to the 3K 80 * buffers. 81 */ 82#if (PAGE_SIZE < 8192) 83#define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 84#define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 85((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 86 87static inline int ixgbe_compute_pad(int rx_buf_len) 88{ 89 int page_size, pad_size; 90 91 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 92 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 93 94 return pad_size; 95} 96 97static inline int ixgbe_skb_pad(void) 98{ 99 int rx_buf_len; 100 101 /* If a 2K buffer cannot handle a standard Ethernet frame then 102 * optimize padding for a 3K buffer instead of a 1.5K buffer. 103 * 104 * For a 3K buffer we need to add enough padding to allow for 105 * tailroom due to NET_IP_ALIGN possibly shifting us out of 106 * cache-line alignment. 107 */ 108 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 109 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 110 else 111 rx_buf_len = IXGBE_RXBUFFER_1536; 112 113 /* if needed make room for NET_IP_ALIGN */ 114 rx_buf_len -= NET_IP_ALIGN; 115 116 return ixgbe_compute_pad(rx_buf_len); 117} 118 119#define IXGBE_SKB_PAD ixgbe_skb_pad() 120#else 121#define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 122#endif 123 124/* 125 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 126 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 127 * this adds up to 448 bytes of extra data. 128 * 129 * Since netdev_alloc_skb now allocates a page fragment we can use a value 130 * of 256 and the resultant skb will have a truesize of 960 or less. 131 */ 132#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 133 134/* How many Rx Buffers do we bundle into one write to the hardware ? */ 135#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 136 137#define IXGBE_RX_DMA_ATTR \ 138 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 139 140enum ixgbe_tx_flags { 141 /* cmd_type flags */ 142 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 143 IXGBE_TX_FLAGS_TSO = 0x02, 144 IXGBE_TX_FLAGS_TSTAMP = 0x04, 145 146 /* olinfo flags */ 147 IXGBE_TX_FLAGS_CC = 0x08, 148 IXGBE_TX_FLAGS_IPV4 = 0x10, 149 IXGBE_TX_FLAGS_CSUM = 0x20, 150 IXGBE_TX_FLAGS_IPSEC = 0x40, 151 152 /* software defined flags */ 153 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 154 IXGBE_TX_FLAGS_FCOE = 0x100, 155}; 156 157/* VLAN info */ 158#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 159#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 160#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 161#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 162 163#define IXGBE_MAX_VF_MC_ENTRIES 30 164#define IXGBE_MAX_VF_FUNCTIONS 64 165#define IXGBE_MAX_VFTA_ENTRIES 128 166#define MAX_EMULATION_MAC_ADDRS 16 167#define IXGBE_MAX_PF_MACVLANS 15 168#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 169#define IXGBE_82599_VF_DEVICE_ID 0x10ED 170#define IXGBE_X540_VF_DEVICE_ID 0x1515 171 172struct vf_data_storage { 173 struct pci_dev *vfdev; 174 unsigned char vf_mac_addresses[ETH_ALEN]; 175 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 176 u16 num_vf_mc_hashes; 177 bool clear_to_send; 178 bool pf_set_mac; 179 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 180 u16 pf_qos; 181 u16 tx_rate; 182 int link_enable; 183 int link_state; 184 u8 spoofchk_enabled; 185 bool rss_query_enabled; 186 u8 trusted; 187 int xcast_mode; 188 unsigned int vf_api; 189 u8 primary_abort_count; 190}; 191 192enum ixgbevf_xcast_modes { 193 IXGBEVF_XCAST_MODE_NONE = 0, 194 IXGBEVF_XCAST_MODE_MULTI, 195 IXGBEVF_XCAST_MODE_ALLMULTI, 196 IXGBEVF_XCAST_MODE_PROMISC, 197}; 198 199struct vf_macvlans { 200 struct list_head l; 201 int vf; 202 bool free; 203 bool is_macvlan; 204 u8 vf_macvlan[ETH_ALEN]; 205}; 206 207#define IXGBE_MAX_TXD_PWR 14 208#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 209 210/* Tx Descriptors needed, worst case */ 211#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 212#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 213 214/* wrapper around a pointer to a socket buffer, 215 * so a DMA handle can be stored along with the buffer */ 216struct ixgbe_tx_buffer { 217 union ixgbe_adv_tx_desc *next_to_watch; 218 unsigned long time_stamp; 219 union { 220 struct sk_buff *skb; 221 struct xdp_frame *xdpf; 222 }; 223 unsigned int bytecount; 224 unsigned short gso_segs; 225 __be16 protocol; 226 DEFINE_DMA_UNMAP_ADDR(dma); 227 DEFINE_DMA_UNMAP_LEN(len); 228 u32 tx_flags; 229}; 230 231struct ixgbe_rx_buffer { 232 union { 233 struct { 234 struct sk_buff *skb; 235 dma_addr_t dma; 236 struct page *page; 237 __u32 page_offset; 238 __u16 pagecnt_bias; 239 }; 240 struct { 241 bool discard; 242 struct xdp_buff *xdp; 243 }; 244 }; 245}; 246 247struct ixgbe_queue_stats { 248 u64 packets; 249 u64 bytes; 250}; 251 252struct ixgbe_tx_queue_stats { 253 u64 restart_queue; 254 u64 tx_busy; 255 u64 tx_done_old; 256}; 257 258struct ixgbe_rx_queue_stats { 259 u64 rsc_count; 260 u64 rsc_flush; 261 u64 non_eop_descs; 262 u64 alloc_rx_page; 263 u64 alloc_rx_page_failed; 264 u64 alloc_rx_buff_failed; 265 u64 csum_err; 266}; 267 268#define IXGBE_TS_HDR_LEN 8 269 270enum ixgbe_ring_state_t { 271 __IXGBE_RX_3K_BUFFER, 272 __IXGBE_RX_BUILD_SKB_ENABLED, 273 __IXGBE_RX_RSC_ENABLED, 274 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 275 __IXGBE_RX_FCOE, 276 __IXGBE_TX_FDIR_INIT_DONE, 277 __IXGBE_TX_XPS_INIT_DONE, 278 __IXGBE_TX_DETECT_HANG, 279 __IXGBE_HANG_CHECK_ARMED, 280 __IXGBE_TX_XDP_RING, 281 __IXGBE_TX_DISABLED, 282}; 283 284#define ring_uses_build_skb(ring) \ 285 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 286 287struct ixgbe_fwd_adapter { 288 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 289 struct net_device *netdev; 290 unsigned int tx_base_queue; 291 unsigned int rx_base_queue; 292 int pool; 293}; 294 295#define check_for_tx_hang(ring) \ 296 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 297#define set_check_for_tx_hang(ring) \ 298 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 299#define clear_check_for_tx_hang(ring) \ 300 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 301#define ring_is_rsc_enabled(ring) \ 302 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 303#define set_ring_rsc_enabled(ring) \ 304 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 305#define clear_ring_rsc_enabled(ring) \ 306 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 307#define ring_is_xdp(ring) \ 308 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 309#define set_ring_xdp(ring) \ 310 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 311#define clear_ring_xdp(ring) \ 312 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 313struct ixgbe_ring { 314 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 315 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 316 struct net_device *netdev; /* netdev ring belongs to */ 317 struct bpf_prog *xdp_prog; 318 struct device *dev; /* device for DMA mapping */ 319 void *desc; /* descriptor ring memory */ 320 union { 321 struct ixgbe_tx_buffer *tx_buffer_info; 322 struct ixgbe_rx_buffer *rx_buffer_info; 323 }; 324 unsigned long state; 325 u8 __iomem *tail; 326 dma_addr_t dma; /* phys. address of descriptor ring */ 327 unsigned int size; /* length in bytes */ 328 329 u16 count; /* amount of descriptors */ 330 331 u8 queue_index; /* needed for multiqueue queue management */ 332 u8 reg_idx; /* holds the special value that gets 333 * the hardware register offset 334 * associated with this ring, which is 335 * different for DCB and RSS modes 336 */ 337 u16 next_to_use; 338 u16 next_to_clean; 339 340 unsigned long last_rx_timestamp; 341 342 union { 343 u16 next_to_alloc; 344 struct { 345 u8 atr_sample_rate; 346 u8 atr_count; 347 }; 348 }; 349 350 u8 dcb_tc; 351 struct ixgbe_queue_stats stats; 352 struct u64_stats_sync syncp; 353 union { 354 struct ixgbe_tx_queue_stats tx_stats; 355 struct ixgbe_rx_queue_stats rx_stats; 356 }; 357 struct xdp_rxq_info xdp_rxq; 358 struct xsk_buff_pool *xsk_pool; 359 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 360 u16 rx_buf_len; 361} ____cacheline_internodealigned_in_smp; 362 363enum ixgbe_ring_f_enum { 364 RING_F_NONE = 0, 365 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 366 RING_F_RSS, 367 RING_F_FDIR, 368#ifdef IXGBE_FCOE 369 RING_F_FCOE, 370#endif /* IXGBE_FCOE */ 371 372 RING_F_ARRAY_SIZE /* must be last in enum set */ 373}; 374 375#define IXGBE_MAX_RSS_INDICES 16 376#define IXGBE_MAX_RSS_INDICES_X550 63 377#define IXGBE_MAX_VMDQ_INDICES 64 378#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 379#define IXGBE_MAX_FCOE_INDICES 8 380#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 381#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 382#define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 383#define IXGBE_MAX_L2A_QUEUES 4 384#define IXGBE_BAD_L2A_QUEUE 3 385#define IXGBE_MAX_MACVLANS 63 386 387struct ixgbe_ring_feature { 388 u16 limit; /* upper limit on feature indices */ 389 u16 indices; /* current value of indices */ 390 u16 mask; /* Mask used for feature to ring mapping */ 391 u16 offset; /* offset to start of feature */ 392} ____cacheline_internodealigned_in_smp; 393 394#define IXGBE_82599_VMDQ_8Q_MASK 0x78 395#define IXGBE_82599_VMDQ_4Q_MASK 0x7C 396#define IXGBE_82599_VMDQ_2Q_MASK 0x7E 397 398/* 399 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 400 * this is twice the size of a half page we need to double the page order 401 * for FCoE enabled Rx queues. 402 */ 403static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 404{ 405 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 406 return IXGBE_RXBUFFER_3K; 407#if (PAGE_SIZE < 8192) 408 if (ring_uses_build_skb(ring)) 409 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 410#endif 411 return IXGBE_RXBUFFER_2K; 412} 413 414static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 415{ 416#if (PAGE_SIZE < 8192) 417 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 418 return 1; 419#endif 420 return 0; 421} 422#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 423 424#define IXGBE_ITR_ADAPTIVE_MIN_INC 2 425#define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 426#define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 427#define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 428#define IXGBE_ITR_ADAPTIVE_BULK 0x00 429 430struct ixgbe_ring_container { 431 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 432 unsigned long next_update; /* jiffies value of last update */ 433 unsigned int total_bytes; /* total bytes processed this int */ 434 unsigned int total_packets; /* total packets processed this int */ 435 u16 work_limit; /* total work allowed per interrupt */ 436 u8 count; /* total number of rings in vector */ 437 u8 itr; /* current ITR setting for ring */ 438}; 439 440/* iterator for handling rings in ring container */ 441#define ixgbe_for_each_ring(pos, head) \ 442 for (pos = (head).ring; pos != NULL; pos = pos->next) 443 444#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 445 ? 8 : 1) 446#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 447 448/* MAX_Q_VECTORS of these are allocated, 449 * but we only use one per queue-specific vector. 450 */ 451struct ixgbe_q_vector { 452 struct ixgbe_adapter *adapter; 453#ifdef CONFIG_IXGBE_DCA 454 int cpu; /* CPU for DCA */ 455#endif 456 u16 v_idx; /* index of q_vector within array, also used for 457 * finding the bit in EICR and friends that 458 * represents the vector for this ring */ 459 u16 itr; /* Interrupt throttle rate written to EITR */ 460 struct ixgbe_ring_container rx, tx; 461 462 struct napi_struct napi; 463 cpumask_t affinity_mask; 464 int numa_node; 465 struct rcu_head rcu; /* to avoid race with update stats on free */ 466 char name[IFNAMSIZ + 9]; 467 468 /* for dynamic allocation of rings associated with this q_vector */ 469 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp; 470}; 471 472#ifdef CONFIG_IXGBE_HWMON 473 474#define IXGBE_HWMON_TYPE_LOC 0 475#define IXGBE_HWMON_TYPE_TEMP 1 476#define IXGBE_HWMON_TYPE_CAUTION 2 477#define IXGBE_HWMON_TYPE_MAX 3 478 479struct hwmon_attr { 480 struct device_attribute dev_attr; 481 struct ixgbe_hw *hw; 482 struct ixgbe_thermal_diode_data *sensor; 483 char name[12]; 484}; 485 486struct hwmon_buff { 487 struct attribute_group group; 488 const struct attribute_group *groups[2]; 489 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 490 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 491 unsigned int n_hwmon; 492}; 493#endif /* CONFIG_IXGBE_HWMON */ 494 495/* 496 * microsecond values for various ITR rates shifted by 2 to fit itr register 497 * with the first 3 bits reserved 0 498 */ 499#define IXGBE_MIN_RSC_ITR 24 500#define IXGBE_100K_ITR 40 501#define IXGBE_20K_ITR 200 502#define IXGBE_12K_ITR 336 503 504/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 505static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 506 const u32 stat_err_bits) 507{ 508 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 509} 510 511static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 512{ 513 u16 ntc = ring->next_to_clean; 514 u16 ntu = ring->next_to_use; 515 516 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 517} 518 519#define IXGBE_RX_DESC(R, i) \ 520 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 521#define IXGBE_TX_DESC(R, i) \ 522 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 523#define IXGBE_TX_CTXTDESC(R, i) \ 524 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 525 526#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 527#ifdef IXGBE_FCOE 528/* Use 3K as the baby jumbo frame size for FCoE */ 529#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 530#endif /* IXGBE_FCOE */ 531 532#define OTHER_VECTOR 1 533#define NON_Q_VECTORS (OTHER_VECTOR) 534 535#define MAX_MSIX_VECTORS_82599 64 536#define MAX_Q_VECTORS_82599 64 537#define MAX_MSIX_VECTORS_82598 18 538#define MAX_Q_VECTORS_82598 16 539 540struct ixgbe_mac_addr { 541 u8 addr[ETH_ALEN]; 542 u16 pool; 543 u16 state; /* bitmask */ 544}; 545 546#define IXGBE_MAC_STATE_DEFAULT 0x1 547#define IXGBE_MAC_STATE_MODIFIED 0x2 548#define IXGBE_MAC_STATE_IN_USE 0x4 549 550#define MAX_Q_VECTORS MAX_Q_VECTORS_82599 551#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 552 553#define MIN_MSIX_Q_VECTORS 1 554#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 555 556/* default to trying for four seconds */ 557#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 558#define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 559 560#define IXGBE_PRIMARY_ABORT_LIMIT 5 561 562/* board specific private data structure */ 563struct ixgbe_adapter { 564 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 565 /* OS defined structs */ 566 struct net_device *netdev; 567 struct bpf_prog *xdp_prog; 568 struct pci_dev *pdev; 569 struct mii_bus *mii_bus; 570 571 unsigned long state; 572 573 /* Some features need tri-state capability, 574 * thus the additional *_CAPABLE flags. 575 */ 576 u32 flags; 577#define IXGBE_FLAG_MSI_ENABLED BIT(1) 578#define IXGBE_FLAG_MSIX_ENABLED BIT(3) 579#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 580#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 581#define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 582#define IXGBE_FLAG_DCA_ENABLED BIT(8) 583#define IXGBE_FLAG_DCA_CAPABLE BIT(9) 584#define IXGBE_FLAG_IMIR_ENABLED BIT(10) 585#define IXGBE_FLAG_MQ_CAPABLE BIT(11) 586#define IXGBE_FLAG_DCB_ENABLED BIT(12) 587#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 588#define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 589#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 590#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 591#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 592#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 593#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 594#define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 595#define IXGBE_FLAG_FCOE_ENABLED BIT(21) 596#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 597#define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 598#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 599#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 600#define IXGBE_FLAG_DCB_CAPABLE BIT(27) 601 602 u32 flags2; 603#define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 604#define IXGBE_FLAG2_RSC_ENABLED BIT(1) 605#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 606#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 607#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 608#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 609#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 610#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 611#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 612#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 613#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 614#define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 615#define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 616#define IXGBE_FLAG2_EEE_ENABLED BIT(15) 617#define IXGBE_FLAG2_RX_LEGACY BIT(16) 618#define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 619#define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 620#define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19) 621 622 /* Tx fast path data */ 623 int num_tx_queues; 624 u16 tx_itr_setting; 625 u16 tx_work_limit; 626 u64 tx_ipsec; 627 628 /* Rx fast path data */ 629 int num_rx_queues; 630 u16 rx_itr_setting; 631 u64 rx_ipsec; 632 633 /* Port number used to identify VXLAN traffic */ 634 __be16 vxlan_port; 635 __be16 geneve_port; 636 637 /* XDP */ 638 int num_xdp_queues; 639 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES]; 640 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */ 641 642 /* TX */ 643 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 644 645 u64 restart_queue; 646 u64 lsc_int; 647 u32 tx_timeout_count; 648 649 /* RX */ 650 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 651 int num_rx_pools; /* == num_rx_queues in 82598 */ 652 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 653 u64 hw_csum_rx_error; 654 u64 hw_rx_no_dma_resources; 655 u64 rsc_total_count; 656 u64 rsc_total_flush; 657 u64 non_eop_descs; 658 u32 alloc_rx_page; 659 u32 alloc_rx_page_failed; 660 u32 alloc_rx_buff_failed; 661 662 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 663 664 /* DCB parameters */ 665 struct ieee_pfc *ixgbe_ieee_pfc; 666 struct ieee_ets *ixgbe_ieee_ets; 667 struct ixgbe_dcb_config dcb_cfg; 668 struct ixgbe_dcb_config temp_dcb_cfg; 669 u8 hw_tcs; 670 u8 dcb_set_bitmap; 671 u8 dcbx_cap; 672 enum ixgbe_fc_mode last_lfc_mode; 673 674 int num_q_vectors; /* current number of q_vectors for device */ 675 int max_q_vectors; /* true count of q_vectors for device */ 676 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 677 struct msix_entry *msix_entries; 678 679 u32 test_icr; 680 struct ixgbe_ring test_tx_ring; 681 struct ixgbe_ring test_rx_ring; 682 683 /* structs defined in ixgbe_hw.h */ 684 struct ixgbe_hw hw; 685 u16 msg_enable; 686 struct ixgbe_hw_stats stats; 687 688 u64 tx_busy; 689 unsigned int tx_ring_count; 690 unsigned int xdp_ring_count; 691 unsigned int rx_ring_count; 692 693 u32 link_speed; 694 bool link_up; 695 unsigned long sfp_poll_time; 696 unsigned long link_check_timeout; 697 698 struct timer_list service_timer; 699 struct work_struct service_task; 700 701 struct hlist_head fdir_filter_list; 702 unsigned long fdir_overflow; /* number of times ATR was backed off */ 703 union ixgbe_atr_input fdir_mask; 704 int fdir_filter_count; 705 u32 fdir_pballoc; 706 u32 atr_sample_rate; 707 spinlock_t fdir_perfect_lock; 708 709#ifdef IXGBE_FCOE 710 struct ixgbe_fcoe fcoe; 711#endif /* IXGBE_FCOE */ 712 u8 __iomem *io_addr; /* Mainly for iounmap use */ 713 u32 wol; 714 715 u16 bridge_mode; 716 717 char eeprom_id[NVM_VER_SIZE]; 718 u16 eeprom_cap; 719 720 u32 interrupt_event; 721 u32 led_reg; 722 723 struct ptp_clock *ptp_clock; 724 struct ptp_clock_info ptp_caps; 725 struct work_struct ptp_tx_work; 726 struct sk_buff *ptp_tx_skb; 727 struct hwtstamp_config tstamp_config; 728 unsigned long ptp_tx_start; 729 unsigned long last_overflow_check; 730 unsigned long last_rx_ptp_check; 731 unsigned long last_rx_timestamp; 732 spinlock_t tmreg_lock; 733 struct cyclecounter hw_cc; 734 struct timecounter hw_tc; 735 u32 base_incval; 736 u32 tx_hwtstamp_timeouts; 737 u32 tx_hwtstamp_skipped; 738 u32 rx_hwtstamp_cleared; 739 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 740 741 /* SR-IOV */ 742 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 743 unsigned int num_vfs; 744 struct vf_data_storage *vfinfo; 745 int vf_rate_link_speed; 746 struct vf_macvlans vf_mvs; 747 struct vf_macvlans *mv_list; 748 749 u32 timer_event_accumulator; 750 u32 vferr_refcount; 751 struct ixgbe_mac_addr *mac_table; 752 struct kobject *info_kobj; 753#ifdef CONFIG_IXGBE_HWMON 754 struct hwmon_buff *ixgbe_hwmon_buff; 755#endif /* CONFIG_IXGBE_HWMON */ 756#ifdef CONFIG_DEBUG_FS 757 struct dentry *ixgbe_dbg_adapter; 758#endif /*CONFIG_DEBUG_FS*/ 759 760 u8 default_up; 761 /* Bitmask indicating in use pools */ 762 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 763 764#define IXGBE_MAX_LINK_HANDLE 10 765 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 766 unsigned long tables; 767 768/* maximum number of RETA entries among all devices supported by ixgbe 769 * driver: currently it's x550 device in non-SRIOV mode 770 */ 771#define IXGBE_MAX_RETA_ENTRIES 512 772 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 773 774#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 775 u32 *rss_key; 776 777#ifdef CONFIG_IXGBE_IPSEC 778 struct ixgbe_ipsec *ipsec; 779#endif /* CONFIG_IXGBE_IPSEC */ 780 spinlock_t vfs_lock; 781}; 782 783static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 784{ 785 switch (adapter->hw.mac.type) { 786 case ixgbe_mac_82598EB: 787 case ixgbe_mac_82599EB: 788 case ixgbe_mac_X540: 789 return IXGBE_MAX_RSS_INDICES; 790 case ixgbe_mac_X550: 791 case ixgbe_mac_X550EM_x: 792 case ixgbe_mac_x550em_a: 793 return IXGBE_MAX_RSS_INDICES_X550; 794 default: 795 return 0; 796 } 797} 798 799struct ixgbe_fdir_filter { 800 struct hlist_node fdir_node; 801 union ixgbe_atr_input filter; 802 u16 sw_idx; 803 u64 action; 804}; 805 806enum ixgbe_state_t { 807 __IXGBE_TESTING, 808 __IXGBE_RESETTING, 809 __IXGBE_DOWN, 810 __IXGBE_DISABLED, 811 __IXGBE_REMOVING, 812 __IXGBE_SERVICE_SCHED, 813 __IXGBE_SERVICE_INITED, 814 __IXGBE_IN_SFP_INIT, 815 __IXGBE_PTP_RUNNING, 816 __IXGBE_PTP_TX_IN_PROGRESS, 817 __IXGBE_RESET_REQUESTED, 818}; 819 820struct ixgbe_cb { 821 union { /* Union defining head/tail partner */ 822 struct sk_buff *head; 823 struct sk_buff *tail; 824 }; 825 dma_addr_t dma; 826 u16 append_cnt; 827 bool page_released; 828}; 829#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 830 831enum ixgbe_boards { 832 board_82598, 833 board_82599, 834 board_X540, 835 board_X550, 836 board_X550EM_x, 837 board_x550em_x_fw, 838 board_x550em_a, 839 board_x550em_a_fw, 840}; 841 842extern const struct ixgbe_info ixgbe_82598_info; 843extern const struct ixgbe_info ixgbe_82599_info; 844extern const struct ixgbe_info ixgbe_X540_info; 845extern const struct ixgbe_info ixgbe_X550_info; 846extern const struct ixgbe_info ixgbe_X550EM_x_info; 847extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 848extern const struct ixgbe_info ixgbe_x550em_a_info; 849extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 850#ifdef CONFIG_IXGBE_DCB 851extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 852#endif 853 854extern char ixgbe_driver_name[]; 855#ifdef IXGBE_FCOE 856extern char ixgbe_default_device_descr[]; 857#endif /* IXGBE_FCOE */ 858 859int ixgbe_open(struct net_device *netdev); 860int ixgbe_close(struct net_device *netdev); 861void ixgbe_up(struct ixgbe_adapter *adapter); 862void ixgbe_down(struct ixgbe_adapter *adapter); 863void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 864void ixgbe_reset(struct ixgbe_adapter *adapter); 865void ixgbe_set_ethtool_ops(struct net_device *netdev); 866int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 867int ixgbe_setup_tx_resources(struct ixgbe_ring *); 868void ixgbe_free_rx_resources(struct ixgbe_ring *); 869void ixgbe_free_tx_resources(struct ixgbe_ring *); 870void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 871void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 872void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 873void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 874void ixgbe_update_stats(struct ixgbe_adapter *adapter); 875int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 876bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 877 u16 subdevice_id); 878#ifdef CONFIG_PCI_IOV 879void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 880#endif 881int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 882 const u8 *addr, u16 queue); 883int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 884 const u8 *addr, u16 queue); 885void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 886void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 887netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 888 struct ixgbe_ring *); 889void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 890 struct ixgbe_tx_buffer *); 891void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 892void ixgbe_write_eitr(struct ixgbe_q_vector *); 893int ixgbe_poll(struct napi_struct *napi, int budget); 894int ethtool_ioctl(struct ifreq *ifr); 895s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 896s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 897s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 898s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 899 union ixgbe_atr_hash_dword input, 900 union ixgbe_atr_hash_dword common, 901 u8 queue); 902s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 903 union ixgbe_atr_input *input_mask); 904s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 905 union ixgbe_atr_input *input, 906 u16 soft_id, u8 queue); 907s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 908 union ixgbe_atr_input *input, 909 u16 soft_id); 910void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 911 union ixgbe_atr_input *mask); 912int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 913 struct ixgbe_fdir_filter *input, 914 u16 sw_idx); 915void ixgbe_set_rx_mode(struct net_device *netdev); 916#ifdef CONFIG_IXGBE_DCB 917void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 918#endif 919int ixgbe_setup_tc(struct net_device *dev, u8 tc); 920void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 921void ixgbe_do_reset(struct net_device *netdev); 922#ifdef CONFIG_IXGBE_HWMON 923void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 924int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 925#endif /* CONFIG_IXGBE_HWMON */ 926#ifdef IXGBE_FCOE 927void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 928int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 929 u8 *hdr_len); 930int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 931 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 932int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 933 struct scatterlist *sgl, unsigned int sgc); 934int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 935 struct scatterlist *sgl, unsigned int sgc); 936int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 937int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 938void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 939int ixgbe_fcoe_enable(struct net_device *netdev); 940int ixgbe_fcoe_disable(struct net_device *netdev); 941#ifdef CONFIG_IXGBE_DCB 942u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 943u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 944#endif /* CONFIG_IXGBE_DCB */ 945int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 946int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 947 struct netdev_fcoe_hbainfo *info); 948u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 949#endif /* IXGBE_FCOE */ 950#ifdef CONFIG_DEBUG_FS 951void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 952void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 953void ixgbe_dbg_init(void); 954void ixgbe_dbg_exit(void); 955#else 956static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 957static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 958static inline void ixgbe_dbg_init(void) {} 959static inline void ixgbe_dbg_exit(void) {} 960#endif /* CONFIG_DEBUG_FS */ 961static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 962{ 963 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 964} 965 966void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 967void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 968void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 969void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 970void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 971void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 972void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 973void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 974static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 975 union ixgbe_adv_rx_desc *rx_desc, 976 struct sk_buff *skb) 977{ 978 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 979 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 980 return; 981 } 982 983 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 984 return; 985 986 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 987 988 /* Update the last_rx_timestamp timer in order to enable watchdog check 989 * for error case of latched timestamp on a dropped packet. 990 */ 991 rx_ring->last_rx_timestamp = jiffies; 992} 993 994int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 995int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 996void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 997void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 998void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 999#ifdef CONFIG_PCI_IOV 1000void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1001#endif 1002 1003netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1004 struct ixgbe_adapter *adapter, 1005 struct ixgbe_ring *tx_ring); 1006u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1007void ixgbe_store_key(struct ixgbe_adapter *adapter); 1008void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1009s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1010 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1011#ifdef CONFIG_IXGBE_IPSEC 1012void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1013void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1014void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1015void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1016 union ixgbe_adv_rx_desc *rx_desc, 1017 struct sk_buff *skb); 1018int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1019 struct ixgbe_ipsec_tx_data *itd); 1020void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1021int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1022int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1023#else 1024static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1025static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1026static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1027static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1028 union ixgbe_adv_rx_desc *rx_desc, 1029 struct sk_buff *skb) { } 1030static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1031 struct ixgbe_tx_buffer *first, 1032 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1033static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1034 u32 vf) { } 1035static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1036 u32 *mbuf, u32 vf) { return -EACCES; } 1037static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1038 u32 *mbuf, u32 vf) { return -EACCES; } 1039#endif /* CONFIG_IXGBE_IPSEC */ 1040 1041static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter) 1042{ 1043 return !!adapter->xdp_prog; 1044} 1045 1046#endif /* _IXGBE_H_ */ 1047