18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* Copyright (c) 2020 Intel Corporation */ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_cibool igc_reg_test(struct igc_adapter *adapter, u64 *data); 58c2ecf20Sopenharmony_cibool igc_eeprom_test(struct igc_adapter *adapter, u64 *data); 68c2ecf20Sopenharmony_cibool igc_link_test(struct igc_adapter *adapter, u64 *data); 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_cistruct igc_reg_test { 98c2ecf20Sopenharmony_ci u16 reg; 108c2ecf20Sopenharmony_ci u8 array_len; 118c2ecf20Sopenharmony_ci u8 test_type; 128c2ecf20Sopenharmony_ci u32 mask; 138c2ecf20Sopenharmony_ci u32 write; 148c2ecf20Sopenharmony_ci}; 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci/* In the hardware, registers are laid out either singly, in arrays 178c2ecf20Sopenharmony_ci * spaced 0x40 bytes apart, or in contiguous tables. We assume 188c2ecf20Sopenharmony_ci * most tests take place on arrays or single registers (handled 198c2ecf20Sopenharmony_ci * as a single-element array) and special-case the tables. 208c2ecf20Sopenharmony_ci * Table tests are always pattern tests. 218c2ecf20Sopenharmony_ci * 228c2ecf20Sopenharmony_ci * We also make provision for some required setup steps by specifying 238c2ecf20Sopenharmony_ci * registers to be written without any read-back testing. 248c2ecf20Sopenharmony_ci */ 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#define PATTERN_TEST 1 278c2ecf20Sopenharmony_ci#define SET_READ_TEST 2 288c2ecf20Sopenharmony_ci#define TABLE32_TEST 3 298c2ecf20Sopenharmony_ci#define TABLE64_TEST_LO 4 308c2ecf20Sopenharmony_ci#define TABLE64_TEST_HI 5 31