1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018 Intel Corporation */ 3 4#ifndef _IGC_H_ 5#define _IGC_H_ 6 7#include <linux/kobject.h> 8#include <linux/pci.h> 9#include <linux/netdevice.h> 10#include <linux/vmalloc.h> 11#include <linux/ethtool.h> 12#include <linux/sctp.h> 13#include <linux/ptp_clock_kernel.h> 14#include <linux/timecounter.h> 15#include <linux/net_tstamp.h> 16#include <linux/bitfield.h> 17 18#include "igc_hw.h" 19 20void igc_ethtool_set_ops(struct net_device *); 21 22/* Transmit and receive queues */ 23#define IGC_MAX_RX_QUEUES 4 24#define IGC_MAX_TX_QUEUES 4 25 26#define MAX_Q_VECTORS 8 27#define MAX_STD_JUMBO_FRAME_SIZE 9216 28 29#define MAX_ETYPE_FILTER 8 30#define IGC_RETA_SIZE 128 31 32enum igc_mac_filter_type { 33 IGC_MAC_FILTER_TYPE_DST = 0, 34 IGC_MAC_FILTER_TYPE_SRC 35}; 36 37struct igc_tx_queue_stats { 38 u64 packets; 39 u64 bytes; 40 u64 restart_queue; 41 u64 restart_queue2; 42}; 43 44struct igc_rx_queue_stats { 45 u64 packets; 46 u64 bytes; 47 u64 drops; 48 u64 csum_err; 49 u64 alloc_failed; 50}; 51 52struct igc_rx_packet_stats { 53 u64 ipv4_packets; /* IPv4 headers processed */ 54 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 55 u64 ipv6_packets; /* IPv6 headers processed */ 56 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 57 u64 tcp_packets; /* TCP headers processed */ 58 u64 udp_packets; /* UDP headers processed */ 59 u64 sctp_packets; /* SCTP headers processed */ 60 u64 nfs_packets; /* NFS headers processe */ 61 u64 other_packets; 62}; 63 64struct igc_ring_container { 65 struct igc_ring *ring; /* pointer to linked list of rings */ 66 unsigned int total_bytes; /* total bytes processed this int */ 67 unsigned int total_packets; /* total packets processed this int */ 68 u16 work_limit; /* total work allowed per interrupt */ 69 u8 count; /* total number of rings in vector */ 70 u8 itr; /* current ITR setting for ring */ 71}; 72 73struct igc_ring { 74 struct igc_q_vector *q_vector; /* backlink to q_vector */ 75 struct net_device *netdev; /* back pointer to net_device */ 76 struct device *dev; /* device for dma mapping */ 77 union { /* array of buffer info structs */ 78 struct igc_tx_buffer *tx_buffer_info; 79 struct igc_rx_buffer *rx_buffer_info; 80 }; 81 void *desc; /* descriptor ring memory */ 82 unsigned long flags; /* ring specific flags */ 83 void __iomem *tail; /* pointer to ring tail register */ 84 dma_addr_t dma; /* phys address of the ring */ 85 unsigned int size; /* length of desc. ring in bytes */ 86 87 u16 count; /* number of desc. in the ring */ 88 u8 queue_index; /* logical index of the ring*/ 89 u8 reg_idx; /* physical index of the ring */ 90 bool launchtime_enable; /* true if LaunchTime is enabled */ 91 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 92 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 93 94 u32 start_time; 95 u32 end_time; 96 97 /* everything past this point are written often */ 98 u16 next_to_clean; 99 u16 next_to_use; 100 u16 next_to_alloc; 101 102 union { 103 /* TX */ 104 struct { 105 struct igc_tx_queue_stats tx_stats; 106 struct u64_stats_sync tx_syncp; 107 struct u64_stats_sync tx_syncp2; 108 }; 109 /* RX */ 110 struct { 111 struct igc_rx_queue_stats rx_stats; 112 struct igc_rx_packet_stats pkt_stats; 113 struct u64_stats_sync rx_syncp; 114 struct sk_buff *skb; 115 }; 116 }; 117} ____cacheline_internodealigned_in_smp; 118 119/* Board specific private data structure */ 120struct igc_adapter { 121 struct net_device *netdev; 122 123 struct ethtool_eee eee; 124 u16 eee_advert; 125 126 unsigned long state; 127 unsigned int flags; 128 unsigned int num_q_vectors; 129 130 struct msix_entry *msix_entries; 131 132 /* TX */ 133 u16 tx_work_limit; 134 u32 tx_timeout_count; 135 int num_tx_queues; 136 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 137 138 /* RX */ 139 int num_rx_queues; 140 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 141 142 struct timer_list watchdog_timer; 143 struct timer_list dma_err_timer; 144 struct timer_list phy_info_timer; 145 146 u32 wol; 147 u32 en_mng_pt; 148 u16 link_speed; 149 u16 link_duplex; 150 151 u8 port_num; 152 153 u8 __iomem *io_addr; 154 /* Interrupt Throttle Rate */ 155 u32 rx_itr_setting; 156 u32 tx_itr_setting; 157 158 struct work_struct reset_task; 159 struct work_struct watchdog_task; 160 struct work_struct dma_err_task; 161 bool fc_autoneg; 162 163 u8 tx_timeout_factor; 164 165 int msg_enable; 166 u32 max_frame_size; 167 u32 min_frame_size; 168 169 ktime_t base_time; 170 ktime_t cycle_time; 171 172 /* OS defined structs */ 173 struct pci_dev *pdev; 174 /* lock for statistics */ 175 spinlock_t stats64_lock; 176 struct rtnl_link_stats64 stats64; 177 178 /* structs defined in igc_hw.h */ 179 struct igc_hw hw; 180 struct igc_hw_stats stats; 181 182 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 183 u32 eims_enable_mask; 184 u32 eims_other; 185 186 u16 tx_ring_count; 187 u16 rx_ring_count; 188 189 u32 tx_hwtstamp_timeouts; 190 u32 tx_hwtstamp_skipped; 191 u32 rx_hwtstamp_cleared; 192 193 u32 rss_queues; 194 u32 rss_indir_tbl_init; 195 196 /* Any access to elements in nfc_rule_list is protected by the 197 * nfc_rule_lock. 198 */ 199 struct mutex nfc_rule_lock; 200 struct list_head nfc_rule_list; 201 unsigned int nfc_rule_count; 202 203 u8 rss_indir_tbl[IGC_RETA_SIZE]; 204 205 unsigned long link_check_timeout; 206 struct igc_info ei; 207 208 u32 test_icr; 209 210 struct ptp_clock *ptp_clock; 211 struct ptp_clock_info ptp_caps; 212 struct work_struct ptp_tx_work; 213 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 214 * ptp_tx_lock. 215 */ 216 spinlock_t ptp_tx_lock; 217 struct sk_buff *ptp_tx_skb; 218 struct hwtstamp_config tstamp_config; 219 unsigned long ptp_tx_start; 220 unsigned int ptp_flags; 221 /* System time value lock */ 222 spinlock_t tmreg_lock; 223 struct cyclecounter cc; 224 struct timecounter tc; 225 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 226 ktime_t ptp_reset_start; /* Reset time in clock mono */ 227}; 228 229void igc_up(struct igc_adapter *adapter); 230void igc_down(struct igc_adapter *adapter); 231int igc_open(struct net_device *netdev); 232int igc_close(struct net_device *netdev); 233int igc_setup_tx_resources(struct igc_ring *ring); 234int igc_setup_rx_resources(struct igc_ring *ring); 235void igc_free_tx_resources(struct igc_ring *ring); 236void igc_free_rx_resources(struct igc_ring *ring); 237unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 238void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 239 const u32 max_rss_queues); 240int igc_reinit_queues(struct igc_adapter *adapter); 241void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 242bool igc_has_link(struct igc_adapter *adapter); 243void igc_reset(struct igc_adapter *adapter); 244int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 245void igc_update_stats(struct igc_adapter *adapter); 246 247/* igc_dump declarations */ 248void igc_rings_dump(struct igc_adapter *adapter); 249void igc_regs_dump(struct igc_adapter *adapter); 250 251extern char igc_driver_name[]; 252 253#define IGC_REGS_LEN 740 254 255/* flags controlling PTP/1588 function */ 256#define IGC_PTP_ENABLED BIT(0) 257 258/* Flags definitions */ 259#define IGC_FLAG_HAS_MSI BIT(0) 260#define IGC_FLAG_QUEUE_PAIRS BIT(3) 261#define IGC_FLAG_DMAC BIT(4) 262#define IGC_FLAG_PTP BIT(8) 263#define IGC_FLAG_WOL_SUPPORTED BIT(8) 264#define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 265#define IGC_FLAG_MEDIA_RESET BIT(10) 266#define IGC_FLAG_MAS_ENABLE BIT(12) 267#define IGC_FLAG_HAS_MSIX BIT(13) 268#define IGC_FLAG_EEE BIT(14) 269#define IGC_FLAG_VLAN_PROMISC BIT(15) 270#define IGC_FLAG_RX_LEGACY BIT(16) 271#define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 272 273#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 274#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 275 276#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 277#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 278#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 279 280/* RX-desc Write-Back format RSS Type's */ 281enum igc_rss_type_num { 282 IGC_RSS_TYPE_NO_HASH = 0, 283 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 284 IGC_RSS_TYPE_HASH_IPV4 = 2, 285 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 286 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 287 IGC_RSS_TYPE_HASH_IPV6 = 5, 288 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 289 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 290 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 291 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 292 IGC_RSS_TYPE_MAX = 10, 293}; 294#define IGC_RSS_TYPE_MAX_TABLE 16 295#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 296 297/* igc_rss_type - Rx descriptor RSS type field */ 298static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 299{ 300 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 301 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 302 * is slightly slower than via u32 (wb.lower.lo_dword.data) 303 */ 304 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 305} 306 307/* Interrupt defines */ 308#define IGC_START_ITR 648 /* ~6000 ints/sec */ 309#define IGC_4K_ITR 980 310#define IGC_20K_ITR 196 311#define IGC_70K_ITR 56 312 313#define IGC_DEFAULT_ITR 3 /* dynamic */ 314#define IGC_MAX_ITR_USECS 10000 315#define IGC_MIN_ITR_USECS 10 316#define NON_Q_VECTORS 1 317#define MAX_MSIX_ENTRIES 10 318 319/* TX/RX descriptor defines */ 320#define IGC_DEFAULT_TXD 256 321#define IGC_DEFAULT_TX_WORK 128 322#define IGC_MIN_TXD 64 323#define IGC_MAX_TXD 4096 324 325#define IGC_DEFAULT_RXD 256 326#define IGC_MIN_RXD 64 327#define IGC_MAX_RXD 4096 328 329/* Supported Rx Buffer Sizes */ 330#define IGC_RXBUFFER_256 256 331#define IGC_RXBUFFER_2048 2048 332#define IGC_RXBUFFER_3072 3072 333 334#define AUTO_ALL_MODES 0 335#define IGC_RX_HDR_LEN IGC_RXBUFFER_256 336 337/* Transmit and receive latency (for PTP timestamps) */ 338#define IGC_I225_TX_LATENCY_10 240 339#define IGC_I225_TX_LATENCY_100 58 340#define IGC_I225_TX_LATENCY_1000 80 341#define IGC_I225_TX_LATENCY_2500 1325 342#define IGC_I225_RX_LATENCY_10 6450 343#define IGC_I225_RX_LATENCY_100 185 344#define IGC_I225_RX_LATENCY_1000 300 345#define IGC_I225_RX_LATENCY_2500 1485 346 347/* RX and TX descriptor control thresholds. 348 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 349 * descriptors available in its onboard memory. 350 * Setting this to 0 disables RX descriptor prefetch. 351 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 352 * available in host memory. 353 * If PTHRESH is 0, this should also be 0. 354 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 355 * descriptors until either it has this many to write back, or the 356 * ITR timer expires. 357 */ 358#define IGC_RX_PTHRESH 8 359#define IGC_RX_HTHRESH 8 360#define IGC_TX_PTHRESH 8 361#define IGC_TX_HTHRESH 1 362#define IGC_RX_WTHRESH 4 363#define IGC_TX_WTHRESH 16 364 365#define IGC_RX_DMA_ATTR \ 366 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 367 368#define IGC_TS_HDR_LEN 16 369 370#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 371 372#if (PAGE_SIZE < 8192) 373#define IGC_MAX_FRAME_BUILD_SKB \ 374 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 375#else 376#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 377#endif 378 379/* How many Rx Buffers do we bundle into one write to the hardware ? */ 380#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 381 382/* VLAN info */ 383#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 384 385/* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 386static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 387 const u32 stat_err_bits) 388{ 389 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 390} 391 392enum igc_state_t { 393 __IGC_TESTING, 394 __IGC_RESETTING, 395 __IGC_DOWN, 396}; 397 398enum igc_tx_flags { 399 /* cmd_type flags */ 400 IGC_TX_FLAGS_VLAN = 0x01, 401 IGC_TX_FLAGS_TSO = 0x02, 402 IGC_TX_FLAGS_TSTAMP = 0x04, 403 404 /* olinfo flags */ 405 IGC_TX_FLAGS_IPV4 = 0x10, 406 IGC_TX_FLAGS_CSUM = 0x20, 407}; 408 409enum igc_boards { 410 board_base, 411}; 412 413/* The largest size we can write to the descriptor is 65535. In order to 414 * maintain a power of two alignment we have to limit ourselves to 32K. 415 */ 416#define IGC_MAX_TXD_PWR 15 417#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 418 419/* Tx Descriptors needed, worst case */ 420#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 421#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 422 423/* wrapper around a pointer to a socket buffer, 424 * so a DMA handle can be stored along with the buffer 425 */ 426struct igc_tx_buffer { 427 union igc_adv_tx_desc *next_to_watch; 428 unsigned long time_stamp; 429 struct sk_buff *skb; 430 unsigned int bytecount; 431 u16 gso_segs; 432 __be16 protocol; 433 434 DEFINE_DMA_UNMAP_ADDR(dma); 435 DEFINE_DMA_UNMAP_LEN(len); 436 u32 tx_flags; 437}; 438 439struct igc_rx_buffer { 440 dma_addr_t dma; 441 struct page *page; 442#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 443 __u32 page_offset; 444#else 445 __u16 page_offset; 446#endif 447 __u16 pagecnt_bias; 448}; 449 450struct igc_q_vector { 451 struct igc_adapter *adapter; /* backlink */ 452 void __iomem *itr_register; 453 u32 eims_value; /* EIMS mask value */ 454 455 u16 itr_val; 456 u8 set_itr; 457 458 struct igc_ring_container rx, tx; 459 460 struct napi_struct napi; 461 462 struct rcu_head rcu; /* to avoid race with update stats on free */ 463 char name[IFNAMSIZ + 9]; 464 struct net_device poll_dev; 465 466 /* for dynamic allocation of rings associated with this q_vector */ 467 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 468}; 469 470enum igc_filter_match_flags { 471 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 472 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 473 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 474 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 475}; 476 477struct igc_nfc_filter { 478 u8 match_flags; 479 u16 etype; 480 u16 vlan_tci; 481 u8 src_addr[ETH_ALEN]; 482 u8 dst_addr[ETH_ALEN]; 483}; 484 485struct igc_nfc_rule { 486 struct list_head list; 487 struct igc_nfc_filter filter; 488 u32 location; 489 u16 action; 490}; 491 492/* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority 493 * based, and 8 ethertype based. 494 */ 495#define IGC_MAX_RXNFC_RULES 32 496 497/* igc_desc_unused - calculate if we have unused descriptors */ 498static inline u16 igc_desc_unused(const struct igc_ring *ring) 499{ 500 u16 ntc = ring->next_to_clean; 501 u16 ntu = ring->next_to_use; 502 503 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 504} 505 506static inline s32 igc_get_phy_info(struct igc_hw *hw) 507{ 508 if (hw->phy.ops.get_phy_info) 509 return hw->phy.ops.get_phy_info(hw); 510 511 return 0; 512} 513 514static inline s32 igc_reset_phy(struct igc_hw *hw) 515{ 516 if (hw->phy.ops.reset) 517 return hw->phy.ops.reset(hw); 518 519 return 0; 520} 521 522static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 523{ 524 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 525} 526 527enum igc_ring_flags_t { 528 IGC_RING_FLAG_RX_3K_BUFFER, 529 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 530 IGC_RING_FLAG_RX_SCTP_CSUM, 531 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 532 IGC_RING_FLAG_TX_CTX_IDX, 533 IGC_RING_FLAG_TX_DETECT_HANG 534}; 535 536#define ring_uses_large_buffer(ring) \ 537 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 538 539#define ring_uses_build_skb(ring) \ 540 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 541 542static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 543{ 544#if (PAGE_SIZE < 8192) 545 if (ring_uses_large_buffer(ring)) 546 return IGC_RXBUFFER_3072; 547 548 if (ring_uses_build_skb(ring)) 549 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 550#endif 551 return IGC_RXBUFFER_2048; 552} 553 554static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 555{ 556#if (PAGE_SIZE < 8192) 557 if (ring_uses_large_buffer(ring)) 558 return 1; 559#endif 560 return 0; 561} 562 563static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 564{ 565 if (hw->phy.ops.read_reg) 566 return hw->phy.ops.read_reg(hw, offset, data); 567 568 return -EOPNOTSUPP; 569} 570 571void igc_reinit_locked(struct igc_adapter *); 572struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 573 u32 location); 574int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 575void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 576 577void igc_ptp_init(struct igc_adapter *adapter); 578void igc_ptp_reset(struct igc_adapter *adapter); 579void igc_ptp_suspend(struct igc_adapter *adapter); 580void igc_ptp_stop(struct igc_adapter *adapter); 581void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, __le32 *va, 582 struct sk_buff *skb); 583int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 584int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 585void igc_ptp_tx_hang(struct igc_adapter *adapter); 586void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 587 588#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 589 590#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 591 592#define IGC_RX_DESC(R, i) \ 593 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 594#define IGC_TX_DESC(R, i) \ 595 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 596#define IGC_TX_CTXTDESC(R, i) \ 597 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 598 599#endif /* _IGC_H_ */ 600