1// SPDX-License-Identifier: GPL-2.0+ 2/* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4#include <linux/module.h> 5#include <linux/device.h> 6#include <linux/pci.h> 7#include <linux/ptp_classify.h> 8 9#include "igb.h" 10 11#define INCVALUE_MASK 0x7fffffff 12#define ISGN 0x80000000 13 14/* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 * 55 * SYSTIM is converted to real time using a timecounter. As 56 * timecounter_cyc2time() allows old timestamps, the timecounter needs 57 * to be updated at least once per half of the SYSTIM interval. 58 * Scheduling of delayed work is not very accurate, and also the NIC 59 * clock can be adjusted to run up to 6% faster and the system clock 60 * up to 10% slower, so we aim for 6 minutes to be sure the actual 61 * interval in the NIC time is shorter than 9.16 minutes. 62 */ 63 64#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6) 65#define IGB_PTP_TX_TIMEOUT (HZ * 15) 66#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 67#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 68#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 69#define IGB_NBITS_82580 40 70 71static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 72 73/* SYSTIM read access for the 82576 */ 74static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 75{ 76 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 77 struct e1000_hw *hw = &igb->hw; 78 u64 val; 79 u32 lo, hi; 80 81 lo = rd32(E1000_SYSTIML); 82 hi = rd32(E1000_SYSTIMH); 83 84 val = ((u64) hi) << 32; 85 val |= lo; 86 87 return val; 88} 89 90/* SYSTIM read access for the 82580 */ 91static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 92{ 93 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 94 struct e1000_hw *hw = &igb->hw; 95 u32 lo, hi; 96 u64 val; 97 98 /* The timestamp latches on lowest register read. For the 82580 99 * the lowest register is SYSTIMR instead of SYSTIML. However we only 100 * need to provide nanosecond resolution, so we just ignore it. 101 */ 102 rd32(E1000_SYSTIMR); 103 lo = rd32(E1000_SYSTIML); 104 hi = rd32(E1000_SYSTIMH); 105 106 val = ((u64) hi) << 32; 107 val |= lo; 108 109 return val; 110} 111 112/* SYSTIM read access for I210/I211 */ 113static void igb_ptp_read_i210(struct igb_adapter *adapter, 114 struct timespec64 *ts) 115{ 116 struct e1000_hw *hw = &adapter->hw; 117 u32 sec, nsec; 118 119 /* The timestamp latches on lowest register read. For I210/I211, the 120 * lowest register is SYSTIMR. Since we only need to provide nanosecond 121 * resolution, we can ignore it. 122 */ 123 rd32(E1000_SYSTIMR); 124 nsec = rd32(E1000_SYSTIML); 125 sec = rd32(E1000_SYSTIMH); 126 127 ts->tv_sec = sec; 128 ts->tv_nsec = nsec; 129} 130 131static void igb_ptp_write_i210(struct igb_adapter *adapter, 132 const struct timespec64 *ts) 133{ 134 struct e1000_hw *hw = &adapter->hw; 135 136 /* Writing the SYSTIMR register is not necessary as it only provides 137 * sub-nanosecond resolution. 138 */ 139 wr32(E1000_SYSTIML, ts->tv_nsec); 140 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 141} 142 143/** 144 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 145 * @adapter: board private structure 146 * @hwtstamps: timestamp structure to update 147 * @systim: unsigned 64bit system time value. 148 * 149 * We need to convert the system time value stored in the RX/TXSTMP registers 150 * into a hwtstamp which can be used by the upper level timestamping functions. 151 * 152 * The 'tmreg_lock' spinlock is used to protect the consistency of the 153 * system time value. This is needed because reading the 64 bit time 154 * value involves reading two (or three) 32 bit registers. The first 155 * read latches the value. Ditto for writing. 156 * 157 * In addition, here have extended the system time with an overflow 158 * counter in software. 159 **/ 160static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 161 struct skb_shared_hwtstamps *hwtstamps, 162 u64 systim) 163{ 164 unsigned long flags; 165 u64 ns; 166 167 switch (adapter->hw.mac.type) { 168 case e1000_82576: 169 case e1000_82580: 170 case e1000_i354: 171 case e1000_i350: 172 spin_lock_irqsave(&adapter->tmreg_lock, flags); 173 174 ns = timecounter_cyc2time(&adapter->tc, systim); 175 176 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 177 178 memset(hwtstamps, 0, sizeof(*hwtstamps)); 179 hwtstamps->hwtstamp = ns_to_ktime(ns); 180 break; 181 case e1000_i210: 182 case e1000_i211: 183 memset(hwtstamps, 0, sizeof(*hwtstamps)); 184 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 185 hwtstamps->hwtstamp = ktime_set(systim >> 32, 186 systim & 0xFFFFFFFF); 187 break; 188 default: 189 break; 190 } 191} 192 193/* PTP clock operations */ 194static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 195{ 196 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 197 ptp_caps); 198 struct e1000_hw *hw = &igb->hw; 199 int neg_adj = 0; 200 u64 rate; 201 u32 incvalue; 202 203 if (ppb < 0) { 204 neg_adj = 1; 205 ppb = -ppb; 206 } 207 rate = ppb; 208 rate <<= 14; 209 rate = div_u64(rate, 1953125); 210 211 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 212 213 if (neg_adj) 214 incvalue -= rate; 215 else 216 incvalue += rate; 217 218 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 219 220 return 0; 221} 222 223static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 224{ 225 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 226 ptp_caps); 227 struct e1000_hw *hw = &igb->hw; 228 int neg_adj = 0; 229 u64 rate; 230 u32 inca; 231 232 if (scaled_ppm < 0) { 233 neg_adj = 1; 234 scaled_ppm = -scaled_ppm; 235 } 236 rate = scaled_ppm; 237 rate <<= 13; 238 rate = div_u64(rate, 15625); 239 240 inca = rate & INCVALUE_MASK; 241 if (neg_adj) 242 inca |= ISGN; 243 244 wr32(E1000_TIMINCA, inca); 245 246 return 0; 247} 248 249static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 250{ 251 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 252 ptp_caps); 253 unsigned long flags; 254 255 spin_lock_irqsave(&igb->tmreg_lock, flags); 256 timecounter_adjtime(&igb->tc, delta); 257 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 258 259 return 0; 260} 261 262static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 263{ 264 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 265 ptp_caps); 266 unsigned long flags; 267 struct timespec64 now, then = ns_to_timespec64(delta); 268 269 spin_lock_irqsave(&igb->tmreg_lock, flags); 270 271 igb_ptp_read_i210(igb, &now); 272 now = timespec64_add(now, then); 273 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 274 275 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 276 277 return 0; 278} 279 280static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, 281 struct timespec64 *ts, 282 struct ptp_system_timestamp *sts) 283{ 284 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 285 ptp_caps); 286 struct e1000_hw *hw = &igb->hw; 287 unsigned long flags; 288 u32 lo, hi; 289 u64 ns; 290 291 spin_lock_irqsave(&igb->tmreg_lock, flags); 292 293 ptp_read_system_prets(sts); 294 lo = rd32(E1000_SYSTIML); 295 ptp_read_system_postts(sts); 296 hi = rd32(E1000_SYSTIMH); 297 298 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 299 300 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 301 302 *ts = ns_to_timespec64(ns); 303 304 return 0; 305} 306 307static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, 308 struct timespec64 *ts, 309 struct ptp_system_timestamp *sts) 310{ 311 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 312 ptp_caps); 313 struct e1000_hw *hw = &igb->hw; 314 unsigned long flags; 315 u32 lo, hi; 316 u64 ns; 317 318 spin_lock_irqsave(&igb->tmreg_lock, flags); 319 320 ptp_read_system_prets(sts); 321 rd32(E1000_SYSTIMR); 322 ptp_read_system_postts(sts); 323 lo = rd32(E1000_SYSTIML); 324 hi = rd32(E1000_SYSTIMH); 325 326 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 327 328 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 329 330 *ts = ns_to_timespec64(ns); 331 332 return 0; 333} 334 335static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, 336 struct timespec64 *ts, 337 struct ptp_system_timestamp *sts) 338{ 339 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 340 ptp_caps); 341 struct e1000_hw *hw = &igb->hw; 342 unsigned long flags; 343 344 spin_lock_irqsave(&igb->tmreg_lock, flags); 345 346 ptp_read_system_prets(sts); 347 rd32(E1000_SYSTIMR); 348 ptp_read_system_postts(sts); 349 ts->tv_nsec = rd32(E1000_SYSTIML); 350 ts->tv_sec = rd32(E1000_SYSTIMH); 351 352 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 353 354 return 0; 355} 356 357static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 358 const struct timespec64 *ts) 359{ 360 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 361 ptp_caps); 362 unsigned long flags; 363 u64 ns; 364 365 ns = timespec64_to_ns(ts); 366 367 spin_lock_irqsave(&igb->tmreg_lock, flags); 368 369 timecounter_init(&igb->tc, &igb->cc, ns); 370 371 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 372 373 return 0; 374} 375 376static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 377 const struct timespec64 *ts) 378{ 379 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 380 ptp_caps); 381 unsigned long flags; 382 383 spin_lock_irqsave(&igb->tmreg_lock, flags); 384 385 igb_ptp_write_i210(igb, ts); 386 387 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 388 389 return 0; 390} 391 392static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 393{ 394 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 395 static const u32 mask[IGB_N_SDP] = { 396 E1000_CTRL_SDP0_DIR, 397 E1000_CTRL_SDP1_DIR, 398 E1000_CTRL_EXT_SDP2_DIR, 399 E1000_CTRL_EXT_SDP3_DIR, 400 }; 401 402 if (input) 403 *ptr &= ~mask[pin]; 404 else 405 *ptr |= mask[pin]; 406} 407 408static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 409{ 410 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 412 }; 413 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 415 }; 416 static const u32 ts_sdp_en[IGB_N_SDP] = { 417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 418 }; 419 struct e1000_hw *hw = &igb->hw; 420 u32 ctrl, ctrl_ext, tssdp = 0; 421 422 ctrl = rd32(E1000_CTRL); 423 ctrl_ext = rd32(E1000_CTRL_EXT); 424 tssdp = rd32(E1000_TSSDP); 425 426 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 427 428 /* Make sure this pin is not enabled as an output. */ 429 tssdp &= ~ts_sdp_en[pin]; 430 431 if (chan == 1) { 432 tssdp &= ~AUX1_SEL_SDP3; 433 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 434 } else { 435 tssdp &= ~AUX0_SEL_SDP3; 436 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 437 } 438 439 wr32(E1000_TSSDP, tssdp); 440 wr32(E1000_CTRL, ctrl); 441 wr32(E1000_CTRL_EXT, ctrl_ext); 442} 443 444static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 445{ 446 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 447 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 448 }; 449 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 450 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 451 }; 452 static const u32 ts_sdp_en[IGB_N_SDP] = { 453 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 454 }; 455 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 456 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 457 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 458 }; 459 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 460 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 461 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 462 }; 463 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 464 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 465 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 466 }; 467 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 468 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 469 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 470 }; 471 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 472 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 473 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 474 }; 475 struct e1000_hw *hw = &igb->hw; 476 u32 ctrl, ctrl_ext, tssdp = 0; 477 478 ctrl = rd32(E1000_CTRL); 479 ctrl_ext = rd32(E1000_CTRL_EXT); 480 tssdp = rd32(E1000_TSSDP); 481 482 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 483 484 /* Make sure this pin is not enabled as an input. */ 485 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 486 tssdp &= ~AUX0_TS_SDP_EN; 487 488 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 489 tssdp &= ~AUX1_TS_SDP_EN; 490 491 tssdp &= ~ts_sdp_sel_clr[pin]; 492 if (freq) { 493 if (chan == 1) 494 tssdp |= ts_sdp_sel_fc1[pin]; 495 else 496 tssdp |= ts_sdp_sel_fc0[pin]; 497 } else { 498 if (chan == 1) 499 tssdp |= ts_sdp_sel_tt1[pin]; 500 else 501 tssdp |= ts_sdp_sel_tt0[pin]; 502 } 503 tssdp |= ts_sdp_en[pin]; 504 505 wr32(E1000_TSSDP, tssdp); 506 wr32(E1000_CTRL, ctrl); 507 wr32(E1000_CTRL_EXT, ctrl_ext); 508} 509 510static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 511 struct ptp_clock_request *rq, int on) 512{ 513 struct igb_adapter *igb = 514 container_of(ptp, struct igb_adapter, ptp_caps); 515 struct e1000_hw *hw = &igb->hw; 516 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 517 unsigned long flags; 518 struct timespec64 ts; 519 int use_freq = 0, pin = -1; 520 s64 ns; 521 522 switch (rq->type) { 523 case PTP_CLK_REQ_EXTTS: 524 /* Reject requests with unsupported flags */ 525 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 526 PTP_RISING_EDGE | 527 PTP_FALLING_EDGE | 528 PTP_STRICT_FLAGS)) 529 return -EOPNOTSUPP; 530 531 /* Reject requests failing to enable both edges. */ 532 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 533 (rq->extts.flags & PTP_ENABLE_FEATURE) && 534 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) 535 return -EOPNOTSUPP; 536 537 if (on) { 538 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 539 rq->extts.index); 540 if (pin < 0) 541 return -EBUSY; 542 } 543 if (rq->extts.index == 1) { 544 tsauxc_mask = TSAUXC_EN_TS1; 545 tsim_mask = TSINTR_AUTT1; 546 } else { 547 tsauxc_mask = TSAUXC_EN_TS0; 548 tsim_mask = TSINTR_AUTT0; 549 } 550 spin_lock_irqsave(&igb->tmreg_lock, flags); 551 tsauxc = rd32(E1000_TSAUXC); 552 tsim = rd32(E1000_TSIM); 553 if (on) { 554 igb_pin_extts(igb, rq->extts.index, pin); 555 tsauxc |= tsauxc_mask; 556 tsim |= tsim_mask; 557 } else { 558 tsauxc &= ~tsauxc_mask; 559 tsim &= ~tsim_mask; 560 } 561 wr32(E1000_TSAUXC, tsauxc); 562 wr32(E1000_TSIM, tsim); 563 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 564 return 0; 565 566 case PTP_CLK_REQ_PEROUT: 567 /* Reject requests with unsupported flags */ 568 if (rq->perout.flags) 569 return -EOPNOTSUPP; 570 571 if (on) { 572 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 573 rq->perout.index); 574 if (pin < 0) 575 return -EBUSY; 576 } 577 ts.tv_sec = rq->perout.period.sec; 578 ts.tv_nsec = rq->perout.period.nsec; 579 ns = timespec64_to_ns(&ts); 580 ns = ns >> 1; 581 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 582 (ns == 250000000LL) || (ns == 500000000LL))) { 583 if (ns < 8LL) 584 return -EINVAL; 585 use_freq = 1; 586 } 587 ts = ns_to_timespec64(ns); 588 if (rq->perout.index == 1) { 589 if (use_freq) { 590 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 591 tsim_mask = 0; 592 } else { 593 tsauxc_mask = TSAUXC_EN_TT1; 594 tsim_mask = TSINTR_TT1; 595 } 596 trgttiml = E1000_TRGTTIML1; 597 trgttimh = E1000_TRGTTIMH1; 598 freqout = E1000_FREQOUT1; 599 } else { 600 if (use_freq) { 601 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 602 tsim_mask = 0; 603 } else { 604 tsauxc_mask = TSAUXC_EN_TT0; 605 tsim_mask = TSINTR_TT0; 606 } 607 trgttiml = E1000_TRGTTIML0; 608 trgttimh = E1000_TRGTTIMH0; 609 freqout = E1000_FREQOUT0; 610 } 611 spin_lock_irqsave(&igb->tmreg_lock, flags); 612 tsauxc = rd32(E1000_TSAUXC); 613 tsim = rd32(E1000_TSIM); 614 if (rq->perout.index == 1) { 615 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 616 tsim &= ~TSINTR_TT1; 617 } else { 618 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 619 tsim &= ~TSINTR_TT0; 620 } 621 if (on) { 622 int i = rq->perout.index; 623 igb_pin_perout(igb, i, pin, use_freq); 624 igb->perout[i].start.tv_sec = rq->perout.start.sec; 625 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 626 igb->perout[i].period.tv_sec = ts.tv_sec; 627 igb->perout[i].period.tv_nsec = ts.tv_nsec; 628 wr32(trgttimh, rq->perout.start.sec); 629 wr32(trgttiml, rq->perout.start.nsec); 630 if (use_freq) 631 wr32(freqout, ns); 632 tsauxc |= tsauxc_mask; 633 tsim |= tsim_mask; 634 } 635 wr32(E1000_TSAUXC, tsauxc); 636 wr32(E1000_TSIM, tsim); 637 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 638 return 0; 639 640 case PTP_CLK_REQ_PPS: 641 spin_lock_irqsave(&igb->tmreg_lock, flags); 642 tsim = rd32(E1000_TSIM); 643 if (on) 644 tsim |= TSINTR_SYS_WRAP; 645 else 646 tsim &= ~TSINTR_SYS_WRAP; 647 igb->pps_sys_wrap_on = !!on; 648 wr32(E1000_TSIM, tsim); 649 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 650 return 0; 651 } 652 653 return -EOPNOTSUPP; 654} 655 656static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 657 struct ptp_clock_request *rq, int on) 658{ 659 return -EOPNOTSUPP; 660} 661 662static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 663 enum ptp_pin_function func, unsigned int chan) 664{ 665 switch (func) { 666 case PTP_PF_NONE: 667 case PTP_PF_EXTTS: 668 case PTP_PF_PEROUT: 669 break; 670 case PTP_PF_PHYSYNC: 671 return -1; 672 } 673 return 0; 674} 675 676/** 677 * igb_ptp_tx_work 678 * @work: pointer to work struct 679 * 680 * This work function polls the TSYNCTXCTL valid bit to determine when a 681 * timestamp has been taken for the current stored skb. 682 **/ 683static void igb_ptp_tx_work(struct work_struct *work) 684{ 685 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 686 ptp_tx_work); 687 struct e1000_hw *hw = &adapter->hw; 688 u32 tsynctxctl; 689 690 if (!adapter->ptp_tx_skb) 691 return; 692 693 if (time_is_before_jiffies(adapter->ptp_tx_start + 694 IGB_PTP_TX_TIMEOUT)) { 695 dev_kfree_skb_any(adapter->ptp_tx_skb); 696 adapter->ptp_tx_skb = NULL; 697 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 698 adapter->tx_hwtstamp_timeouts++; 699 /* Clear the tx valid bit in TSYNCTXCTL register to enable 700 * interrupt 701 */ 702 rd32(E1000_TXSTMPH); 703 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 704 return; 705 } 706 707 tsynctxctl = rd32(E1000_TSYNCTXCTL); 708 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 709 igb_ptp_tx_hwtstamp(adapter); 710 else 711 /* reschedule to check later */ 712 schedule_work(&adapter->ptp_tx_work); 713} 714 715static void igb_ptp_overflow_check(struct work_struct *work) 716{ 717 struct igb_adapter *igb = 718 container_of(work, struct igb_adapter, ptp_overflow_work.work); 719 struct timespec64 ts; 720 u64 ns; 721 722 /* Update the timecounter */ 723 ns = timecounter_read(&igb->tc); 724 725 ts = ns_to_timespec64(ns); 726 pr_debug("igb overflow check at %lld.%09lu\n", 727 (long long) ts.tv_sec, ts.tv_nsec); 728 729 schedule_delayed_work(&igb->ptp_overflow_work, 730 IGB_SYSTIM_OVERFLOW_PERIOD); 731} 732 733/** 734 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 735 * @adapter: private network adapter structure 736 * 737 * This watchdog task is scheduled to detect error case where hardware has 738 * dropped an Rx packet that was timestamped when the ring is full. The 739 * particular error is rare but leaves the device in a state unable to timestamp 740 * any future packets. 741 **/ 742void igb_ptp_rx_hang(struct igb_adapter *adapter) 743{ 744 struct e1000_hw *hw = &adapter->hw; 745 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 746 unsigned long rx_event; 747 748 /* Other hardware uses per-packet timestamps */ 749 if (hw->mac.type != e1000_82576) 750 return; 751 752 /* If we don't have a valid timestamp in the registers, just update the 753 * timeout counter and exit 754 */ 755 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 756 adapter->last_rx_ptp_check = jiffies; 757 return; 758 } 759 760 /* Determine the most recent watchdog or rx_timestamp event */ 761 rx_event = adapter->last_rx_ptp_check; 762 if (time_after(adapter->last_rx_timestamp, rx_event)) 763 rx_event = adapter->last_rx_timestamp; 764 765 /* Only need to read the high RXSTMP register to clear the lock */ 766 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 767 rd32(E1000_RXSTMPH); 768 adapter->last_rx_ptp_check = jiffies; 769 adapter->rx_hwtstamp_cleared++; 770 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 771 } 772} 773 774/** 775 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 776 * @adapter: private network adapter structure 777 */ 778void igb_ptp_tx_hang(struct igb_adapter *adapter) 779{ 780 struct e1000_hw *hw = &adapter->hw; 781 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 782 IGB_PTP_TX_TIMEOUT); 783 784 if (!adapter->ptp_tx_skb) 785 return; 786 787 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 788 return; 789 790 /* If we haven't received a timestamp within the timeout, it is 791 * reasonable to assume that it will never occur, so we can unlock the 792 * timestamp bit when this occurs. 793 */ 794 if (timeout) { 795 cancel_work_sync(&adapter->ptp_tx_work); 796 dev_kfree_skb_any(adapter->ptp_tx_skb); 797 adapter->ptp_tx_skb = NULL; 798 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 799 adapter->tx_hwtstamp_timeouts++; 800 /* Clear the tx valid bit in TSYNCTXCTL register to enable 801 * interrupt 802 */ 803 rd32(E1000_TXSTMPH); 804 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 805 } 806} 807 808/** 809 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 810 * @adapter: Board private structure. 811 * 812 * If we were asked to do hardware stamping and such a time stamp is 813 * available, then it must have been for this skb here because we only 814 * allow only one such packet into the queue. 815 **/ 816static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 817{ 818 struct sk_buff *skb = adapter->ptp_tx_skb; 819 struct e1000_hw *hw = &adapter->hw; 820 struct skb_shared_hwtstamps shhwtstamps; 821 u64 regval; 822 int adjust = 0; 823 824 regval = rd32(E1000_TXSTMPL); 825 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 826 827 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 828 /* adjust timestamp for the TX latency based on link speed */ 829 if (adapter->hw.mac.type == e1000_i210) { 830 switch (adapter->link_speed) { 831 case SPEED_10: 832 adjust = IGB_I210_TX_LATENCY_10; 833 break; 834 case SPEED_100: 835 adjust = IGB_I210_TX_LATENCY_100; 836 break; 837 case SPEED_1000: 838 adjust = IGB_I210_TX_LATENCY_1000; 839 break; 840 } 841 } 842 843 shhwtstamps.hwtstamp = 844 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 845 846 /* Clear the lock early before calling skb_tstamp_tx so that 847 * applications are not woken up before the lock bit is clear. We use 848 * a copy of the skb pointer to ensure other threads can't change it 849 * while we're notifying the stack. 850 */ 851 adapter->ptp_tx_skb = NULL; 852 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 853 854 /* Notify the stack and free the skb after we've unlocked */ 855 skb_tstamp_tx(skb, &shhwtstamps); 856 dev_kfree_skb_any(skb); 857} 858 859#define IGB_RET_PTP_DISABLED 1 860#define IGB_RET_PTP_INVALID 2 861 862/** 863 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 864 * @q_vector: Pointer to interrupt specific structure 865 * @va: Pointer to address containing Rx buffer 866 * @skb: Buffer containing timestamp and packet 867 * 868 * This function is meant to retrieve a timestamp from the first buffer of an 869 * incoming frame. The value is stored in little endian format starting on 870 * byte 8 871 * 872 * Returns: 0 if success, nonzero if failure 873 **/ 874int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 875 struct sk_buff *skb) 876{ 877 struct igb_adapter *adapter = q_vector->adapter; 878 __le64 *regval = (__le64 *)va; 879 int adjust = 0; 880 881 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 882 return IGB_RET_PTP_DISABLED; 883 884 /* The timestamp is recorded in little endian format. 885 * DWORD: 0 1 2 3 886 * Field: Reserved Reserved SYSTIML SYSTIMH 887 */ 888 889 /* check reserved dwords are zero, be/le doesn't matter for zero */ 890 if (regval[0]) 891 return IGB_RET_PTP_INVALID; 892 893 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), 894 le64_to_cpu(regval[1])); 895 896 /* adjust timestamp for the RX latency based on link speed */ 897 if (adapter->hw.mac.type == e1000_i210) { 898 switch (adapter->link_speed) { 899 case SPEED_10: 900 adjust = IGB_I210_RX_LATENCY_10; 901 break; 902 case SPEED_100: 903 adjust = IGB_I210_RX_LATENCY_100; 904 break; 905 case SPEED_1000: 906 adjust = IGB_I210_RX_LATENCY_1000; 907 break; 908 } 909 } 910 skb_hwtstamps(skb)->hwtstamp = 911 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 912 913 return 0; 914} 915 916/** 917 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 918 * @q_vector: Pointer to interrupt specific structure 919 * @skb: Buffer containing timestamp and packet 920 * 921 * This function is meant to retrieve a timestamp from the internal registers 922 * of the adapter and store it in the skb. 923 **/ 924void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) 925{ 926 struct igb_adapter *adapter = q_vector->adapter; 927 struct e1000_hw *hw = &adapter->hw; 928 int adjust = 0; 929 u64 regval; 930 931 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 932 return; 933 934 /* If this bit is set, then the RX registers contain the time stamp. No 935 * other packet will be time stamped until we read these registers, so 936 * read the registers to make them available again. Because only one 937 * packet can be time stamped at a time, we know that the register 938 * values must belong to this one here and therefore we don't need to 939 * compare any of the additional attributes stored for it. 940 * 941 * If nothing went wrong, then it should have a shared tx_flags that we 942 * can turn into a skb_shared_hwtstamps. 943 */ 944 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 945 return; 946 947 regval = rd32(E1000_RXSTMPL); 948 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 949 950 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 951 952 /* adjust timestamp for the RX latency based on link speed */ 953 if (adapter->hw.mac.type == e1000_i210) { 954 switch (adapter->link_speed) { 955 case SPEED_10: 956 adjust = IGB_I210_RX_LATENCY_10; 957 break; 958 case SPEED_100: 959 adjust = IGB_I210_RX_LATENCY_100; 960 break; 961 case SPEED_1000: 962 adjust = IGB_I210_RX_LATENCY_1000; 963 break; 964 } 965 } 966 skb_hwtstamps(skb)->hwtstamp = 967 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 968 969 /* Update the last_rx_timestamp timer in order to enable watchdog check 970 * for error case of latched timestamp on a dropped packet. 971 */ 972 adapter->last_rx_timestamp = jiffies; 973} 974 975/** 976 * igb_ptp_get_ts_config - get hardware time stamping config 977 * @netdev: netdev struct 978 * @ifr: interface struct 979 * 980 * Get the hwtstamp_config settings to return to the user. Rather than attempt 981 * to deconstruct the settings from the registers, just return a shadow copy 982 * of the last known settings. 983 **/ 984int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 985{ 986 struct igb_adapter *adapter = netdev_priv(netdev); 987 struct hwtstamp_config *config = &adapter->tstamp_config; 988 989 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 990 -EFAULT : 0; 991} 992 993/** 994 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 995 * @adapter: networking device structure 996 * @config: hwtstamp configuration 997 * 998 * Outgoing time stamping can be enabled and disabled. Play nice and 999 * disable it when requested, although it shouldn't case any overhead 1000 * when no packet needs it. At most one packet in the queue may be 1001 * marked for time stamping, otherwise it would be impossible to tell 1002 * for sure to which packet the hardware time stamp belongs. 1003 * 1004 * Incoming time stamping has to be configured via the hardware 1005 * filters. Not all combinations are supported, in particular event 1006 * type has to be specified. Matching the kind of event packet is 1007 * not supported, with the exception of "all V2 events regardless of 1008 * level 2 or 4". 1009 */ 1010static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 1011 struct hwtstamp_config *config) 1012{ 1013 struct e1000_hw *hw = &adapter->hw; 1014 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 1015 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1016 u32 tsync_rx_cfg = 0; 1017 bool is_l4 = false; 1018 bool is_l2 = false; 1019 u32 regval; 1020 1021 /* reserved for future extensions */ 1022 if (config->flags) 1023 return -EINVAL; 1024 1025 switch (config->tx_type) { 1026 case HWTSTAMP_TX_OFF: 1027 tsync_tx_ctl = 0; 1028 case HWTSTAMP_TX_ON: 1029 break; 1030 default: 1031 return -ERANGE; 1032 } 1033 1034 switch (config->rx_filter) { 1035 case HWTSTAMP_FILTER_NONE: 1036 tsync_rx_ctl = 0; 1037 break; 1038 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1039 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1040 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 1041 is_l4 = true; 1042 break; 1043 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1044 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1045 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 1046 is_l4 = true; 1047 break; 1048 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1049 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1050 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1051 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1052 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1053 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1054 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1055 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1056 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1057 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 1058 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1059 is_l2 = true; 1060 is_l4 = true; 1061 break; 1062 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1063 case HWTSTAMP_FILTER_NTP_ALL: 1064 case HWTSTAMP_FILTER_ALL: 1065 /* 82576 cannot timestamp all packets, which it needs to do to 1066 * support both V1 Sync and Delay_Req messages 1067 */ 1068 if (hw->mac.type != e1000_82576) { 1069 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1070 config->rx_filter = HWTSTAMP_FILTER_ALL; 1071 break; 1072 } 1073 fallthrough; 1074 default: 1075 config->rx_filter = HWTSTAMP_FILTER_NONE; 1076 return -ERANGE; 1077 } 1078 1079 if (hw->mac.type == e1000_82575) { 1080 if (tsync_rx_ctl | tsync_tx_ctl) 1081 return -EINVAL; 1082 return 0; 1083 } 1084 1085 /* Per-packet timestamping only works if all packets are 1086 * timestamped, so enable timestamping in all packets as 1087 * long as one Rx filter was configured. 1088 */ 1089 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1090 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1091 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1092 config->rx_filter = HWTSTAMP_FILTER_ALL; 1093 is_l2 = true; 1094 is_l4 = true; 1095 1096 if ((hw->mac.type == e1000_i210) || 1097 (hw->mac.type == e1000_i211)) { 1098 regval = rd32(E1000_RXPBS); 1099 regval |= E1000_RXPBS_CFG_TS_EN; 1100 wr32(E1000_RXPBS, regval); 1101 } 1102 } 1103 1104 /* enable/disable TX */ 1105 regval = rd32(E1000_TSYNCTXCTL); 1106 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1107 regval |= tsync_tx_ctl; 1108 wr32(E1000_TSYNCTXCTL, regval); 1109 1110 /* enable/disable RX */ 1111 regval = rd32(E1000_TSYNCRXCTL); 1112 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1113 regval |= tsync_rx_ctl; 1114 wr32(E1000_TSYNCRXCTL, regval); 1115 1116 /* define which PTP packets are time stamped */ 1117 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1118 1119 /* define ethertype filter for timestamped packets */ 1120 if (is_l2) 1121 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1122 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1123 E1000_ETQF_1588 | /* enable timestamping */ 1124 ETH_P_1588)); /* 1588 eth protocol type */ 1125 else 1126 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1127 1128 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1129 if (is_l4) { 1130 u32 ftqf = (IPPROTO_UDP /* UDP */ 1131 | E1000_FTQF_VF_BP /* VF not compared */ 1132 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1133 | E1000_FTQF_MASK); /* mask all inputs */ 1134 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1135 1136 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 1137 wr32(E1000_IMIREXT(3), 1138 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1139 if (hw->mac.type == e1000_82576) { 1140 /* enable source port check */ 1141 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 1142 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1143 } 1144 wr32(E1000_FTQF(3), ftqf); 1145 } else { 1146 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1147 } 1148 wrfl(); 1149 1150 /* clear TX/RX time stamp registers, just to be sure */ 1151 regval = rd32(E1000_TXSTMPL); 1152 regval = rd32(E1000_TXSTMPH); 1153 regval = rd32(E1000_RXSTMPL); 1154 regval = rd32(E1000_RXSTMPH); 1155 1156 return 0; 1157} 1158 1159/** 1160 * igb_ptp_set_ts_config - set hardware time stamping config 1161 * @netdev: netdev struct 1162 * @ifr: interface struct 1163 * 1164 **/ 1165int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1166{ 1167 struct igb_adapter *adapter = netdev_priv(netdev); 1168 struct hwtstamp_config config; 1169 int err; 1170 1171 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1172 return -EFAULT; 1173 1174 err = igb_ptp_set_timestamp_mode(adapter, &config); 1175 if (err) 1176 return err; 1177 1178 /* save these settings for future reference */ 1179 memcpy(&adapter->tstamp_config, &config, 1180 sizeof(adapter->tstamp_config)); 1181 1182 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1183 -EFAULT : 0; 1184} 1185 1186/** 1187 * igb_ptp_init - Initialize PTP functionality 1188 * @adapter: Board private structure 1189 * 1190 * This function is called at device probe to initialize the PTP 1191 * functionality. 1192 */ 1193void igb_ptp_init(struct igb_adapter *adapter) 1194{ 1195 struct e1000_hw *hw = &adapter->hw; 1196 struct net_device *netdev = adapter->netdev; 1197 int i; 1198 1199 switch (hw->mac.type) { 1200 case e1000_82576: 1201 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1202 adapter->ptp_caps.owner = THIS_MODULE; 1203 adapter->ptp_caps.max_adj = 999999881; 1204 adapter->ptp_caps.n_ext_ts = 0; 1205 adapter->ptp_caps.pps = 0; 1206 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1207 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1208 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; 1209 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1210 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1211 adapter->cc.read = igb_ptp_read_82576; 1212 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1213 adapter->cc.mult = 1; 1214 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1215 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1216 break; 1217 case e1000_82580: 1218 case e1000_i354: 1219 case e1000_i350: 1220 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1221 adapter->ptp_caps.owner = THIS_MODULE; 1222 adapter->ptp_caps.max_adj = 62499999; 1223 adapter->ptp_caps.n_ext_ts = 0; 1224 adapter->ptp_caps.pps = 0; 1225 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1226 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1227 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; 1228 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1229 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1230 adapter->cc.read = igb_ptp_read_82580; 1231 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1232 adapter->cc.mult = 1; 1233 adapter->cc.shift = 0; 1234 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1235 break; 1236 case e1000_i210: 1237 case e1000_i211: 1238 for (i = 0; i < IGB_N_SDP; i++) { 1239 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1240 1241 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1242 ppd->index = i; 1243 ppd->func = PTP_PF_NONE; 1244 } 1245 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1246 adapter->ptp_caps.owner = THIS_MODULE; 1247 adapter->ptp_caps.max_adj = 62499999; 1248 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1249 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1250 adapter->ptp_caps.n_pins = IGB_N_SDP; 1251 adapter->ptp_caps.pps = 1; 1252 adapter->ptp_caps.pin_config = adapter->sdp_config; 1253 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1254 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1255 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; 1256 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1257 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1258 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1259 break; 1260 default: 1261 adapter->ptp_clock = NULL; 1262 return; 1263 } 1264 1265 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1266 &adapter->pdev->dev); 1267 if (IS_ERR(adapter->ptp_clock)) { 1268 adapter->ptp_clock = NULL; 1269 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1270 } else if (adapter->ptp_clock) { 1271 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1272 adapter->netdev->name); 1273 adapter->ptp_flags |= IGB_PTP_ENABLED; 1274 1275 spin_lock_init(&adapter->tmreg_lock); 1276 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1277 1278 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1279 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1280 igb_ptp_overflow_check); 1281 1282 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1283 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1284 1285 igb_ptp_reset(adapter); 1286 } 1287} 1288 1289/** 1290 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1291 * @adapter: Board private structure 1292 * 1293 * This function stops the overflow check work and PTP Tx timestamp work, and 1294 * will prepare the device for OS suspend. 1295 */ 1296void igb_ptp_suspend(struct igb_adapter *adapter) 1297{ 1298 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1299 return; 1300 1301 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1302 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1303 1304 cancel_work_sync(&adapter->ptp_tx_work); 1305 if (adapter->ptp_tx_skb) { 1306 dev_kfree_skb_any(adapter->ptp_tx_skb); 1307 adapter->ptp_tx_skb = NULL; 1308 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1309 } 1310} 1311 1312/** 1313 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1314 * @adapter: Board private structure. 1315 * 1316 * This function stops the PTP support and cancels the delayed work. 1317 **/ 1318void igb_ptp_stop(struct igb_adapter *adapter) 1319{ 1320 igb_ptp_suspend(adapter); 1321 1322 if (adapter->ptp_clock) { 1323 ptp_clock_unregister(adapter->ptp_clock); 1324 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1325 adapter->netdev->name); 1326 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1327 } 1328} 1329 1330/** 1331 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1332 * @adapter: Board private structure. 1333 * 1334 * This function handles the reset work required to re-enable the PTP device. 1335 **/ 1336void igb_ptp_reset(struct igb_adapter *adapter) 1337{ 1338 struct e1000_hw *hw = &adapter->hw; 1339 unsigned long flags; 1340 1341 /* reset the tstamp_config */ 1342 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1343 1344 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1345 1346 switch (adapter->hw.mac.type) { 1347 case e1000_82576: 1348 /* Dial the nominal frequency. */ 1349 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1350 break; 1351 case e1000_82580: 1352 case e1000_i354: 1353 case e1000_i350: 1354 case e1000_i210: 1355 case e1000_i211: 1356 wr32(E1000_TSAUXC, 0x0); 1357 wr32(E1000_TSSDP, 0x0); 1358 wr32(E1000_TSIM, 1359 TSYNC_INTERRUPTS | 1360 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1361 wr32(E1000_IMS, E1000_IMS_TS); 1362 break; 1363 default: 1364 /* No work to do. */ 1365 goto out; 1366 } 1367 1368 /* Re-initialize the timer. */ 1369 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1370 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1371 1372 igb_ptp_write_i210(adapter, &ts); 1373 } else { 1374 timecounter_init(&adapter->tc, &adapter->cc, 1375 ktime_to_ns(ktime_get_real())); 1376 } 1377out: 1378 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1379 1380 wrfl(); 1381 1382 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1383 schedule_delayed_work(&adapter->ptp_overflow_work, 1384 IGB_SYSTIM_OVERFLOW_PERIOD); 1385} 1386