1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6#include <linux/module.h> 7#include <linux/types.h> 8#include <linux/init.h> 9#include <linux/bitops.h> 10#include <linux/vmalloc.h> 11#include <linux/pagemap.h> 12#include <linux/netdevice.h> 13#include <linux/ipv6.h> 14#include <linux/slab.h> 15#include <net/checksum.h> 16#include <net/ip6_checksum.h> 17#include <net/pkt_sched.h> 18#include <net/pkt_cls.h> 19#include <linux/net_tstamp.h> 20#include <linux/mii.h> 21#include <linux/ethtool.h> 22#include <linux/if.h> 23#include <linux/if_vlan.h> 24#include <linux/pci.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/ip.h> 28#include <linux/tcp.h> 29#include <linux/sctp.h> 30#include <linux/if_ether.h> 31#include <linux/aer.h> 32#include <linux/prefetch.h> 33#include <linux/bpf.h> 34#include <linux/bpf_trace.h> 35#include <linux/pm_runtime.h> 36#include <linux/etherdevice.h> 37#ifdef CONFIG_IGB_DCA 38#include <linux/dca.h> 39#endif 40#include <linux/i2c.h> 41#include "igb.h" 42 43enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46}; 47 48enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51}; 52 53char igb_driver_name[] = "igb"; 54static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61}; 62 63static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101}; 102 103MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105static int igb_setup_all_tx_resources(struct igb_adapter *); 106static int igb_setup_all_rx_resources(struct igb_adapter *); 107static void igb_free_all_tx_resources(struct igb_adapter *); 108static void igb_free_all_rx_resources(struct igb_adapter *); 109static void igb_setup_mrqc(struct igb_adapter *); 110static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111static void igb_remove(struct pci_dev *pdev); 112static int igb_sw_init(struct igb_adapter *); 113int igb_open(struct net_device *); 114int igb_close(struct net_device *); 115static void igb_configure(struct igb_adapter *); 116static void igb_configure_tx(struct igb_adapter *); 117static void igb_configure_rx(struct igb_adapter *); 118static void igb_clean_all_tx_rings(struct igb_adapter *); 119static void igb_clean_all_rx_rings(struct igb_adapter *); 120static void igb_clean_tx_ring(struct igb_ring *); 121static void igb_clean_rx_ring(struct igb_ring *); 122static void igb_set_rx_mode(struct net_device *); 123static void igb_update_phy_info(struct timer_list *); 124static void igb_watchdog(struct timer_list *); 125static void igb_watchdog_task(struct work_struct *); 126static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129static int igb_change_mtu(struct net_device *, int); 130static int igb_set_mac(struct net_device *, void *); 131static void igb_set_uta(struct igb_adapter *adapter, bool set); 132static irqreturn_t igb_intr(int irq, void *); 133static irqreturn_t igb_intr_msi(int irq, void *); 134static irqreturn_t igb_msix_other(int irq, void *); 135static irqreturn_t igb_msix_ring(int irq, void *); 136#ifdef CONFIG_IGB_DCA 137static void igb_update_dca(struct igb_q_vector *); 138static void igb_setup_dca(struct igb_adapter *); 139#endif /* CONFIG_IGB_DCA */ 140static int igb_poll(struct napi_struct *, int); 141static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142static int igb_clean_rx_irq(struct igb_q_vector *, int); 143static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145static void igb_reset_task(struct work_struct *); 146static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150static void igb_restore_vlan(struct igb_adapter *); 151static void igb_rar_set_index(struct igb_adapter *, u32); 152static void igb_ping_all_vfs(struct igb_adapter *); 153static void igb_msg_task(struct igb_adapter *); 154static void igb_vmm_control(struct igb_adapter *); 155static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156static void igb_flush_mac_table(struct igb_adapter *); 157static int igb_available_rars(struct igb_adapter *, u8); 158static void igb_set_default_mac_filter(struct igb_adapter *); 159static int igb_uc_sync(struct net_device *, const unsigned char *); 160static int igb_uc_unsync(struct net_device *, const unsigned char *); 161static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172static void igb_check_vf_rate_limit(struct igb_adapter *); 173static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176#ifdef CONFIG_PCI_IOV 177static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179static int igb_disable_sriov(struct pci_dev *dev); 180static int igb_pci_disable_sriov(struct pci_dev *dev); 181#endif 182 183static int igb_suspend(struct device *); 184static int igb_resume(struct device *); 185static int igb_runtime_suspend(struct device *dev); 186static int igb_runtime_resume(struct device *dev); 187static int igb_runtime_idle(struct device *dev); 188static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192}; 193static void igb_shutdown(struct pci_dev *); 194static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195#ifdef CONFIG_IGB_DCA 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201}; 202#endif 203#ifdef CONFIG_PCI_IOV 204static unsigned int max_vfs; 205module_param(max_vfs, uint, 0); 206MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207#endif /* CONFIG_PCI_IOV */ 208 209static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212static void igb_io_resume(struct pci_dev *); 213 214static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218}; 219 220static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227#ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229#endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233}; 234 235MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237MODULE_LICENSE("GPL v2"); 238 239#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240static int debug = -1; 241module_param(debug, int, 0); 242MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244struct igb_reg_info { 245 u32 ofs; 246 char *name; 247}; 248 249static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283}; 284 285/* igb_regdump - register printout routine */ 286static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287{ 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349} 350 351/* igb_dump - Print registers, Tx-rings and Rx-rings */ 352static void igb_dump(struct igb_adapter *adapter) 353{ 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { u64 a; u64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548exit: 549 return; 550} 551 552/** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558static int igb_get_i2c_data(void *data) 559{ 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565} 566 567/** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574static void igb_set_i2c_data(void *data, int state) 575{ 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) 581 i2cctl |= E1000_I2C_DATA_OUT; 582 else 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 585 i2cctl &= ~E1000_I2C_DATA_OE_N; 586 i2cctl |= E1000_I2C_CLK_OE_N; 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 590} 591 592/** 593 * igb_set_i2c_clk - Sets the I2C SCL clock 594 * @data: pointer to hardware structure 595 * @state: state to set clock 596 * 597 * Sets the I2C clock line to state 598 **/ 599static void igb_set_i2c_clk(void *data, int state) 600{ 601 struct igb_adapter *adapter = (struct igb_adapter *)data; 602 struct e1000_hw *hw = &adapter->hw; 603 s32 i2cctl = rd32(E1000_I2CPARAMS); 604 605 if (state) { 606 i2cctl |= E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } else { 609 i2cctl &= ~E1000_I2C_CLK_OUT; 610 i2cctl &= ~E1000_I2C_CLK_OE_N; 611 } 612 wr32(E1000_I2CPARAMS, i2cctl); 613 wrfl(); 614} 615 616/** 617 * igb_get_i2c_clk - Gets the I2C SCL clock state 618 * @data: pointer to hardware structure 619 * 620 * Gets the I2C clock state 621 **/ 622static int igb_get_i2c_clk(void *data) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 return !!(i2cctl & E1000_I2C_CLK_IN); 629} 630 631static const struct i2c_algo_bit_data igb_i2c_algo = { 632 .setsda = igb_set_i2c_data, 633 .setscl = igb_set_i2c_clk, 634 .getsda = igb_get_i2c_data, 635 .getscl = igb_get_i2c_clk, 636 .udelay = 5, 637 .timeout = 20, 638}; 639 640/** 641 * igb_get_hw_dev - return device 642 * @hw: pointer to hardware structure 643 * 644 * used by hardware layer to print debugging information 645 **/ 646struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 647{ 648 struct igb_adapter *adapter = hw->back; 649 return adapter->netdev; 650} 651 652/** 653 * igb_init_module - Driver Registration Routine 654 * 655 * igb_init_module is the first routine called when the driver is 656 * loaded. All it does is register with the PCI subsystem. 657 **/ 658static int __init igb_init_module(void) 659{ 660 int ret; 661 662 pr_info("%s\n", igb_driver_string); 663 pr_info("%s\n", igb_copyright); 664 665#ifdef CONFIG_IGB_DCA 666 dca_register_notify(&dca_notifier); 667#endif 668 ret = pci_register_driver(&igb_driver); 669 return ret; 670} 671 672module_init(igb_init_module); 673 674/** 675 * igb_exit_module - Driver Exit Cleanup Routine 676 * 677 * igb_exit_module is called just before the driver is removed 678 * from memory. 679 **/ 680static void __exit igb_exit_module(void) 681{ 682#ifdef CONFIG_IGB_DCA 683 dca_unregister_notify(&dca_notifier); 684#endif 685 pci_unregister_driver(&igb_driver); 686} 687 688module_exit(igb_exit_module); 689 690#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 691/** 692 * igb_cache_ring_register - Descriptor ring to register mapping 693 * @adapter: board private structure to initialize 694 * 695 * Once we know the feature-set enabled for the device, we'll cache 696 * the register offset the descriptor ring is assigned to. 697 **/ 698static void igb_cache_ring_register(struct igb_adapter *adapter) 699{ 700 int i = 0, j = 0; 701 u32 rbase_offset = adapter->vfs_allocated_count; 702 703 switch (adapter->hw.mac.type) { 704 case e1000_82576: 705 /* The queues are allocated for virtualization such that VF 0 706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 707 * In order to avoid collision we start at the first free queue 708 * and continue consuming queues in the same sequence 709 */ 710 if (adapter->vfs_allocated_count) { 711 for (; i < adapter->rss_queues; i++) 712 adapter->rx_ring[i]->reg_idx = rbase_offset + 713 Q_IDX_82576(i); 714 } 715 fallthrough; 716 case e1000_82575: 717 case e1000_82580: 718 case e1000_i350: 719 case e1000_i354: 720 case e1000_i210: 721 case e1000_i211: 722 default: 723 for (; i < adapter->num_rx_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 725 for (; j < adapter->num_tx_queues; j++) 726 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 727 break; 728 } 729} 730 731u32 igb_rd32(struct e1000_hw *hw, u32 reg) 732{ 733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 735 u32 value = 0; 736 737 if (E1000_REMOVED(hw_addr)) 738 return ~value; 739 740 value = readl(&hw_addr[reg]); 741 742 /* reads should not return all F's */ 743 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 744 struct net_device *netdev = igb->netdev; 745 hw->hw_addr = NULL; 746 netdev_err(netdev, "PCIe link lost\n"); 747 WARN(pci_device_is_present(igb->pdev), 748 "igb: Failed to read reg 0x%x!\n", reg); 749 } 750 751 return value; 752} 753 754/** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768{ 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778} 779 780#define IGB_N0_QUEUE -1 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782{ 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = BIT(msix_vector); 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = BIT(msix_vector); 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857} 858 859/** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866static void igb_configure_msix(struct igb_adapter *adapter) 867{ 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = BIT(vector); 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923} 924 925/** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932static int igb_request_msix(struct igb_adapter *adapter) 933{ 934 unsigned int num_q_vectors = adapter->num_q_vectors; 935 struct net_device *netdev = adapter->netdev; 936 int i, err = 0, vector = 0, free_vector = 0; 937 938 err = request_irq(adapter->msix_entries[vector].vector, 939 igb_msix_other, 0, netdev->name, adapter); 940 if (err) 941 goto err_out; 942 943 if (num_q_vectors > MAX_Q_VECTORS) { 944 num_q_vectors = MAX_Q_VECTORS; 945 dev_warn(&adapter->pdev->dev, 946 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 947 adapter->num_q_vectors, MAX_Q_VECTORS); 948 } 949 for (i = 0; i < num_q_vectors; i++) { 950 struct igb_q_vector *q_vector = adapter->q_vector[i]; 951 952 vector++; 953 954 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 955 956 if (q_vector->rx.ring && q_vector->tx.ring) 957 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 958 q_vector->rx.ring->queue_index); 959 else if (q_vector->tx.ring) 960 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 961 q_vector->tx.ring->queue_index); 962 else if (q_vector->rx.ring) 963 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 964 q_vector->rx.ring->queue_index); 965 else 966 sprintf(q_vector->name, "%s-unused", netdev->name); 967 968 err = request_irq(adapter->msix_entries[vector].vector, 969 igb_msix_ring, 0, q_vector->name, 970 q_vector); 971 if (err) 972 goto err_free; 973 } 974 975 igb_configure_msix(adapter); 976 return 0; 977 978err_free: 979 /* free already assigned IRQs */ 980 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 981 982 vector--; 983 for (i = 0; i < vector; i++) { 984 free_irq(adapter->msix_entries[free_vector++].vector, 985 adapter->q_vector[i]); 986 } 987err_out: 988 return err; 989} 990 991/** 992 * igb_free_q_vector - Free memory allocated for specific interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be freed 995 * 996 * This function frees the memory allocated to the q_vector. 997 **/ 998static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 999{ 1000 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1001 1002 adapter->q_vector[v_idx] = NULL; 1003 1004 /* igb_get_stats64() might access the rings on this vector, 1005 * we must wait a grace period before freeing it. 1006 */ 1007 if (q_vector) 1008 kfree_rcu(q_vector, rcu); 1009} 1010 1011/** 1012 * igb_reset_q_vector - Reset config for interrupt vector 1013 * @adapter: board private structure to initialize 1014 * @v_idx: Index of vector to be reset 1015 * 1016 * If NAPI is enabled it will delete any references to the 1017 * NAPI struct. This is preparation for igb_free_q_vector. 1018 **/ 1019static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1020{ 1021 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1022 1023 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1024 * allocated. So, q_vector is NULL so we should stop here. 1025 */ 1026 if (!q_vector) 1027 return; 1028 1029 if (q_vector->tx.ring) 1030 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1031 1032 if (q_vector->rx.ring) 1033 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1034 1035 netif_napi_del(&q_vector->napi); 1036 1037} 1038 1039static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1040{ 1041 int v_idx = adapter->num_q_vectors; 1042 1043 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1044 pci_disable_msix(adapter->pdev); 1045 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1046 pci_disable_msi(adapter->pdev); 1047 1048 while (v_idx--) 1049 igb_reset_q_vector(adapter, v_idx); 1050} 1051 1052/** 1053 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1054 * @adapter: board private structure to initialize 1055 * 1056 * This function frees the memory allocated to the q_vectors. In addition if 1057 * NAPI is enabled it will delete any references to the NAPI struct prior 1058 * to freeing the q_vector. 1059 **/ 1060static void igb_free_q_vectors(struct igb_adapter *adapter) 1061{ 1062 int v_idx = adapter->num_q_vectors; 1063 1064 adapter->num_tx_queues = 0; 1065 adapter->num_rx_queues = 0; 1066 adapter->num_q_vectors = 0; 1067 1068 while (v_idx--) { 1069 igb_reset_q_vector(adapter, v_idx); 1070 igb_free_q_vector(adapter, v_idx); 1071 } 1072} 1073 1074/** 1075 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1076 * @adapter: board private structure to initialize 1077 * 1078 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1079 * MSI-X interrupts allocated. 1080 */ 1081static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1082{ 1083 igb_free_q_vectors(adapter); 1084 igb_reset_interrupt_capability(adapter); 1085} 1086 1087/** 1088 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1089 * @adapter: board private structure to initialize 1090 * @msix: boolean value of MSIX capability 1091 * 1092 * Attempt to configure interrupts using the best available 1093 * capabilities of the hardware and kernel. 1094 **/ 1095static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1096{ 1097 int err; 1098 int numvecs, i; 1099 1100 if (!msix) 1101 goto msi_only; 1102 adapter->flags |= IGB_FLAG_HAS_MSIX; 1103 1104 /* Number of supported queues. */ 1105 adapter->num_rx_queues = adapter->rss_queues; 1106 if (adapter->vfs_allocated_count) 1107 adapter->num_tx_queues = 1; 1108 else 1109 adapter->num_tx_queues = adapter->rss_queues; 1110 1111 /* start with one vector for every Rx queue */ 1112 numvecs = adapter->num_rx_queues; 1113 1114 /* if Tx handler is separate add 1 for every Tx queue */ 1115 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1116 numvecs += adapter->num_tx_queues; 1117 1118 /* store the number of vectors reserved for queues */ 1119 adapter->num_q_vectors = numvecs; 1120 1121 /* add 1 vector for link status interrupts */ 1122 numvecs++; 1123 for (i = 0; i < numvecs; i++) 1124 adapter->msix_entries[i].entry = i; 1125 1126 err = pci_enable_msix_range(adapter->pdev, 1127 adapter->msix_entries, 1128 numvecs, 1129 numvecs); 1130 if (err > 0) 1131 return; 1132 1133 igb_reset_interrupt_capability(adapter); 1134 1135 /* If we can't do MSI-X, try MSI */ 1136msi_only: 1137 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1138#ifdef CONFIG_PCI_IOV 1139 /* disable SR-IOV for non MSI-X configurations */ 1140 if (adapter->vf_data) { 1141 struct e1000_hw *hw = &adapter->hw; 1142 /* disable iov and allow time for transactions to clear */ 1143 pci_disable_sriov(adapter->pdev); 1144 msleep(500); 1145 1146 kfree(adapter->vf_mac_list); 1147 adapter->vf_mac_list = NULL; 1148 kfree(adapter->vf_data); 1149 adapter->vf_data = NULL; 1150 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1151 wrfl(); 1152 msleep(100); 1153 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1154 } 1155#endif 1156 adapter->vfs_allocated_count = 0; 1157 adapter->rss_queues = 1; 1158 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1159 adapter->num_rx_queues = 1; 1160 adapter->num_tx_queues = 1; 1161 adapter->num_q_vectors = 1; 1162 if (!pci_enable_msi(adapter->pdev)) 1163 adapter->flags |= IGB_FLAG_HAS_MSI; 1164} 1165 1166static void igb_add_ring(struct igb_ring *ring, 1167 struct igb_ring_container *head) 1168{ 1169 head->ring = ring; 1170 head->count++; 1171} 1172 1173/** 1174 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1175 * @adapter: board private structure to initialize 1176 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1177 * @v_idx: index of vector in adapter struct 1178 * @txr_count: total number of Tx rings to allocate 1179 * @txr_idx: index of first Tx ring to allocate 1180 * @rxr_count: total number of Rx rings to allocate 1181 * @rxr_idx: index of first Rx ring to allocate 1182 * 1183 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1184 **/ 1185static int igb_alloc_q_vector(struct igb_adapter *adapter, 1186 int v_count, int v_idx, 1187 int txr_count, int txr_idx, 1188 int rxr_count, int rxr_idx) 1189{ 1190 struct igb_q_vector *q_vector; 1191 struct igb_ring *ring; 1192 int ring_count; 1193 size_t size; 1194 1195 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1196 if (txr_count > 1 || rxr_count > 1) 1197 return -ENOMEM; 1198 1199 ring_count = txr_count + rxr_count; 1200 size = struct_size(q_vector, ring, ring_count); 1201 1202 /* allocate q_vector and rings */ 1203 q_vector = adapter->q_vector[v_idx]; 1204 if (!q_vector) { 1205 q_vector = kzalloc(size, GFP_KERNEL); 1206 } else if (size > ksize(q_vector)) { 1207 struct igb_q_vector *new_q_vector; 1208 1209 new_q_vector = kzalloc(size, GFP_KERNEL); 1210 if (new_q_vector) 1211 kfree_rcu(q_vector, rcu); 1212 q_vector = new_q_vector; 1213 } else { 1214 memset(q_vector, 0, size); 1215 } 1216 if (!q_vector) 1217 return -ENOMEM; 1218 1219 /* initialize NAPI */ 1220 netif_napi_add(adapter->netdev, &q_vector->napi, 1221 igb_poll, 64); 1222 1223 /* tie q_vector and adapter together */ 1224 adapter->q_vector[v_idx] = q_vector; 1225 q_vector->adapter = adapter; 1226 1227 /* initialize work limits */ 1228 q_vector->tx.work_limit = adapter->tx_work_limit; 1229 1230 /* initialize ITR configuration */ 1231 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1232 q_vector->itr_val = IGB_START_ITR; 1233 1234 /* initialize pointer to rings */ 1235 ring = q_vector->ring; 1236 1237 /* intialize ITR */ 1238 if (rxr_count) { 1239 /* rx or rx/tx vector */ 1240 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1241 q_vector->itr_val = adapter->rx_itr_setting; 1242 } else { 1243 /* tx only vector */ 1244 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1245 q_vector->itr_val = adapter->tx_itr_setting; 1246 } 1247 1248 if (txr_count) { 1249 /* assign generic ring traits */ 1250 ring->dev = &adapter->pdev->dev; 1251 ring->netdev = adapter->netdev; 1252 1253 /* configure backlink on ring */ 1254 ring->q_vector = q_vector; 1255 1256 /* update q_vector Tx values */ 1257 igb_add_ring(ring, &q_vector->tx); 1258 1259 /* For 82575, context index must be unique per ring. */ 1260 if (adapter->hw.mac.type == e1000_82575) 1261 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1262 1263 /* apply Tx specific ring traits */ 1264 ring->count = adapter->tx_ring_count; 1265 ring->queue_index = txr_idx; 1266 1267 ring->cbs_enable = false; 1268 ring->idleslope = 0; 1269 ring->sendslope = 0; 1270 ring->hicredit = 0; 1271 ring->locredit = 0; 1272 1273 u64_stats_init(&ring->tx_syncp); 1274 u64_stats_init(&ring->tx_syncp2); 1275 1276 /* assign ring to adapter */ 1277 adapter->tx_ring[txr_idx] = ring; 1278 1279 /* push pointer to next ring */ 1280 ring++; 1281 } 1282 1283 if (rxr_count) { 1284 /* assign generic ring traits */ 1285 ring->dev = &adapter->pdev->dev; 1286 ring->netdev = adapter->netdev; 1287 1288 /* configure backlink on ring */ 1289 ring->q_vector = q_vector; 1290 1291 /* update q_vector Rx values */ 1292 igb_add_ring(ring, &q_vector->rx); 1293 1294 /* set flag indicating ring supports SCTP checksum offload */ 1295 if (adapter->hw.mac.type >= e1000_82576) 1296 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1297 1298 /* On i350, i354, i210, and i211, loopback VLAN packets 1299 * have the tag byte-swapped. 1300 */ 1301 if (adapter->hw.mac.type >= e1000_i350) 1302 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1303 1304 /* apply Rx specific ring traits */ 1305 ring->count = adapter->rx_ring_count; 1306 ring->queue_index = rxr_idx; 1307 1308 u64_stats_init(&ring->rx_syncp); 1309 1310 /* assign ring to adapter */ 1311 adapter->rx_ring[rxr_idx] = ring; 1312 } 1313 1314 return 0; 1315} 1316 1317 1318/** 1319 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1320 * @adapter: board private structure to initialize 1321 * 1322 * We allocate one q_vector per queue interrupt. If allocation fails we 1323 * return -ENOMEM. 1324 **/ 1325static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1326{ 1327 int q_vectors = adapter->num_q_vectors; 1328 int rxr_remaining = adapter->num_rx_queues; 1329 int txr_remaining = adapter->num_tx_queues; 1330 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1331 int err; 1332 1333 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1334 for (; rxr_remaining; v_idx++) { 1335 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1336 0, 0, 1, rxr_idx); 1337 1338 if (err) 1339 goto err_out; 1340 1341 /* update counts and index */ 1342 rxr_remaining--; 1343 rxr_idx++; 1344 } 1345 } 1346 1347 for (; v_idx < q_vectors; v_idx++) { 1348 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1349 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1350 1351 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1352 tqpv, txr_idx, rqpv, rxr_idx); 1353 1354 if (err) 1355 goto err_out; 1356 1357 /* update counts and index */ 1358 rxr_remaining -= rqpv; 1359 txr_remaining -= tqpv; 1360 rxr_idx++; 1361 txr_idx++; 1362 } 1363 1364 return 0; 1365 1366err_out: 1367 adapter->num_tx_queues = 0; 1368 adapter->num_rx_queues = 0; 1369 adapter->num_q_vectors = 0; 1370 1371 while (v_idx--) 1372 igb_free_q_vector(adapter, v_idx); 1373 1374 return -ENOMEM; 1375} 1376 1377/** 1378 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1379 * @adapter: board private structure to initialize 1380 * @msix: boolean value of MSIX capability 1381 * 1382 * This function initializes the interrupts and allocates all of the queues. 1383 **/ 1384static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1385{ 1386 struct pci_dev *pdev = adapter->pdev; 1387 int err; 1388 1389 igb_set_interrupt_capability(adapter, msix); 1390 1391 err = igb_alloc_q_vectors(adapter); 1392 if (err) { 1393 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1394 goto err_alloc_q_vectors; 1395 } 1396 1397 igb_cache_ring_register(adapter); 1398 1399 return 0; 1400 1401err_alloc_q_vectors: 1402 igb_reset_interrupt_capability(adapter); 1403 return err; 1404} 1405 1406/** 1407 * igb_request_irq - initialize interrupts 1408 * @adapter: board private structure to initialize 1409 * 1410 * Attempts to configure interrupts using the best available 1411 * capabilities of the hardware and kernel. 1412 **/ 1413static int igb_request_irq(struct igb_adapter *adapter) 1414{ 1415 struct net_device *netdev = adapter->netdev; 1416 struct pci_dev *pdev = adapter->pdev; 1417 int err = 0; 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1420 err = igb_request_msix(adapter); 1421 if (!err) 1422 goto request_done; 1423 /* fall back to MSI */ 1424 igb_free_all_tx_resources(adapter); 1425 igb_free_all_rx_resources(adapter); 1426 1427 igb_clear_interrupt_scheme(adapter); 1428 err = igb_init_interrupt_scheme(adapter, false); 1429 if (err) 1430 goto request_done; 1431 1432 igb_setup_all_tx_resources(adapter); 1433 igb_setup_all_rx_resources(adapter); 1434 igb_configure(adapter); 1435 } 1436 1437 igb_assign_vector(adapter->q_vector[0], 0); 1438 1439 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1440 err = request_irq(pdev->irq, igb_intr_msi, 0, 1441 netdev->name, adapter); 1442 if (!err) 1443 goto request_done; 1444 1445 /* fall back to legacy interrupts */ 1446 igb_reset_interrupt_capability(adapter); 1447 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1448 } 1449 1450 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1451 netdev->name, adapter); 1452 1453 if (err) 1454 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1455 err); 1456 1457request_done: 1458 return err; 1459} 1460 1461static void igb_free_irq(struct igb_adapter *adapter) 1462{ 1463 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1464 int vector = 0, i; 1465 1466 free_irq(adapter->msix_entries[vector++].vector, adapter); 1467 1468 for (i = 0; i < adapter->num_q_vectors; i++) 1469 free_irq(adapter->msix_entries[vector++].vector, 1470 adapter->q_vector[i]); 1471 } else { 1472 free_irq(adapter->pdev->irq, adapter); 1473 } 1474} 1475 1476/** 1477 * igb_irq_disable - Mask off interrupt generation on the NIC 1478 * @adapter: board private structure 1479 **/ 1480static void igb_irq_disable(struct igb_adapter *adapter) 1481{ 1482 struct e1000_hw *hw = &adapter->hw; 1483 1484 /* we need to be careful when disabling interrupts. The VFs are also 1485 * mapped into these registers and so clearing the bits can cause 1486 * issues on the VF drivers so we only need to clear what we set 1487 */ 1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1489 u32 regval = rd32(E1000_EIAM); 1490 1491 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1492 wr32(E1000_EIMC, adapter->eims_enable_mask); 1493 regval = rd32(E1000_EIAC); 1494 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1495 } 1496 1497 wr32(E1000_IAM, 0); 1498 wr32(E1000_IMC, ~0); 1499 wrfl(); 1500 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1501 int i; 1502 1503 for (i = 0; i < adapter->num_q_vectors; i++) 1504 synchronize_irq(adapter->msix_entries[i].vector); 1505 } else { 1506 synchronize_irq(adapter->pdev->irq); 1507 } 1508} 1509 1510/** 1511 * igb_irq_enable - Enable default interrupt generation settings 1512 * @adapter: board private structure 1513 **/ 1514static void igb_irq_enable(struct igb_adapter *adapter) 1515{ 1516 struct e1000_hw *hw = &adapter->hw; 1517 1518 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1519 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1520 u32 regval = rd32(E1000_EIAC); 1521 1522 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1523 regval = rd32(E1000_EIAM); 1524 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1525 wr32(E1000_EIMS, adapter->eims_enable_mask); 1526 if (adapter->vfs_allocated_count) { 1527 wr32(E1000_MBVFIMR, 0xFF); 1528 ims |= E1000_IMS_VMMB; 1529 } 1530 wr32(E1000_IMS, ims); 1531 } else { 1532 wr32(E1000_IMS, IMS_ENABLE_MASK | 1533 E1000_IMS_DRSTA); 1534 wr32(E1000_IAM, IMS_ENABLE_MASK | 1535 E1000_IMS_DRSTA); 1536 } 1537} 1538 1539static void igb_update_mng_vlan(struct igb_adapter *adapter) 1540{ 1541 struct e1000_hw *hw = &adapter->hw; 1542 u16 pf_id = adapter->vfs_allocated_count; 1543 u16 vid = adapter->hw.mng_cookie.vlan_id; 1544 u16 old_vid = adapter->mng_vlan_id; 1545 1546 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1547 /* add VID to filter table */ 1548 igb_vfta_set(hw, vid, pf_id, true, true); 1549 adapter->mng_vlan_id = vid; 1550 } else { 1551 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1552 } 1553 1554 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1555 (vid != old_vid) && 1556 !test_bit(old_vid, adapter->active_vlans)) { 1557 /* remove VID from filter table */ 1558 igb_vfta_set(hw, vid, pf_id, false, true); 1559 } 1560} 1561 1562/** 1563 * igb_release_hw_control - release control of the h/w to f/w 1564 * @adapter: address of board private structure 1565 * 1566 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1567 * For ASF and Pass Through versions of f/w this means that the 1568 * driver is no longer loaded. 1569 **/ 1570static void igb_release_hw_control(struct igb_adapter *adapter) 1571{ 1572 struct e1000_hw *hw = &adapter->hw; 1573 u32 ctrl_ext; 1574 1575 /* Let firmware take over control of h/w */ 1576 ctrl_ext = rd32(E1000_CTRL_EXT); 1577 wr32(E1000_CTRL_EXT, 1578 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1579} 1580 1581/** 1582 * igb_get_hw_control - get control of the h/w from f/w 1583 * @adapter: address of board private structure 1584 * 1585 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1586 * For ASF and Pass Through versions of f/w this means that 1587 * the driver is loaded. 1588 **/ 1589static void igb_get_hw_control(struct igb_adapter *adapter) 1590{ 1591 struct e1000_hw *hw = &adapter->hw; 1592 u32 ctrl_ext; 1593 1594 /* Let firmware know the driver has taken over */ 1595 ctrl_ext = rd32(E1000_CTRL_EXT); 1596 wr32(E1000_CTRL_EXT, 1597 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1598} 1599 1600static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1601{ 1602 struct net_device *netdev = adapter->netdev; 1603 struct e1000_hw *hw = &adapter->hw; 1604 1605 WARN_ON(hw->mac.type != e1000_i210); 1606 1607 if (enable) 1608 adapter->flags |= IGB_FLAG_FQTSS; 1609 else 1610 adapter->flags &= ~IGB_FLAG_FQTSS; 1611 1612 if (netif_running(netdev)) 1613 schedule_work(&adapter->reset_task); 1614} 1615 1616static bool is_fqtss_enabled(struct igb_adapter *adapter) 1617{ 1618 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1619} 1620 1621static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1622 enum tx_queue_prio prio) 1623{ 1624 u32 val; 1625 1626 WARN_ON(hw->mac.type != e1000_i210); 1627 WARN_ON(queue < 0 || queue > 4); 1628 1629 val = rd32(E1000_I210_TXDCTL(queue)); 1630 1631 if (prio == TX_QUEUE_PRIO_HIGH) 1632 val |= E1000_TXDCTL_PRIORITY; 1633 else 1634 val &= ~E1000_TXDCTL_PRIORITY; 1635 1636 wr32(E1000_I210_TXDCTL(queue), val); 1637} 1638 1639static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1640{ 1641 u32 val; 1642 1643 WARN_ON(hw->mac.type != e1000_i210); 1644 WARN_ON(queue < 0 || queue > 1); 1645 1646 val = rd32(E1000_I210_TQAVCC(queue)); 1647 1648 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1649 val |= E1000_TQAVCC_QUEUEMODE; 1650 else 1651 val &= ~E1000_TQAVCC_QUEUEMODE; 1652 1653 wr32(E1000_I210_TQAVCC(queue), val); 1654} 1655 1656static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1657{ 1658 int i; 1659 1660 for (i = 0; i < adapter->num_tx_queues; i++) { 1661 if (adapter->tx_ring[i]->cbs_enable) 1662 return true; 1663 } 1664 1665 return false; 1666} 1667 1668static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1669{ 1670 int i; 1671 1672 for (i = 0; i < adapter->num_tx_queues; i++) { 1673 if (adapter->tx_ring[i]->launchtime_enable) 1674 return true; 1675 } 1676 1677 return false; 1678} 1679 1680/** 1681 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1682 * @adapter: pointer to adapter struct 1683 * @queue: queue number 1684 * 1685 * Configure CBS and Launchtime for a given hardware queue. 1686 * Parameters are retrieved from the correct Tx ring, so 1687 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1688 * for setting those correctly prior to this function being called. 1689 **/ 1690static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1691{ 1692 struct net_device *netdev = adapter->netdev; 1693 struct e1000_hw *hw = &adapter->hw; 1694 struct igb_ring *ring; 1695 u32 tqavcc, tqavctrl; 1696 u16 value; 1697 1698 WARN_ON(hw->mac.type != e1000_i210); 1699 WARN_ON(queue < 0 || queue > 1); 1700 ring = adapter->tx_ring[queue]; 1701 1702 /* If any of the Qav features is enabled, configure queues as SR and 1703 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1704 * as SP. 1705 */ 1706 if (ring->cbs_enable || ring->launchtime_enable) { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1709 } else { 1710 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1711 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1712 } 1713 1714 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1715 if (ring->cbs_enable || queue == 0) { 1716 /* i210 does not allow the queue 0 to be in the Strict 1717 * Priority mode while the Qav mode is enabled, so, 1718 * instead of disabling strict priority mode, we give 1719 * queue 0 the maximum of credits possible. 1720 * 1721 * See section 8.12.19 of the i210 datasheet, "Note: 1722 * Queue0 QueueMode must be set to 1b when 1723 * TransmitMode is set to Qav." 1724 */ 1725 if (queue == 0 && !ring->cbs_enable) { 1726 /* max "linkspeed" idleslope in kbps */ 1727 ring->idleslope = 1000000; 1728 ring->hicredit = ETH_FRAME_LEN; 1729 } 1730 1731 /* Always set data transfer arbitration to credit-based 1732 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1733 * the queues. 1734 */ 1735 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1736 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1737 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1738 1739 /* According to i210 datasheet section 7.2.7.7, we should set 1740 * the 'idleSlope' field from TQAVCC register following the 1741 * equation: 1742 * 1743 * For 100 Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 0.2 (E1) 1746 * 1747 * For 1000Mbps link speed: 1748 * 1749 * value = BW * 0x7735 * 2 (E2) 1750 * 1751 * E1 and E2 can be merged into one equation as shown below. 1752 * Note that 'link-speed' is in Mbps. 1753 * 1754 * value = BW * 0x7735 * 2 * link-speed 1755 * -------------- (E3) 1756 * 1000 1757 * 1758 * 'BW' is the percentage bandwidth out of full link speed 1759 * which can be found with the following equation. Note that 1760 * idleSlope here is the parameter from this function which 1761 * is in kbps. 1762 * 1763 * BW = idleSlope 1764 * ----------------- (E4) 1765 * link-speed * 1000 1766 * 1767 * That said, we can come up with a generic equation to 1768 * calculate the value we should set it TQAVCC register by 1769 * replacing 'BW' in E3 by E4. The resulting equation is: 1770 * 1771 * value = idleSlope * 0x7735 * 2 * link-speed 1772 * ----------------- -------------- (E5) 1773 * link-speed * 1000 1000 1774 * 1775 * 'link-speed' is present in both sides of the fraction so 1776 * it is canceled out. The final equation is the following: 1777 * 1778 * value = idleSlope * 61034 1779 * ----------------- (E6) 1780 * 1000000 1781 * 1782 * NOTE: For i210, given the above, we can see that idleslope 1783 * is represented in 16.38431 kbps units by the value at 1784 * the TQAVCC register (1Gbps / 61034), which reduces 1785 * the granularity for idleslope increments. 1786 * For instance, if you want to configure a 2576kbps 1787 * idleslope, the value to be written on the register 1788 * would have to be 157.23. If rounded down, you end 1789 * up with less bandwidth available than originally 1790 * required (~2572 kbps). If rounded up, you end up 1791 * with a higher bandwidth (~2589 kbps). Below the 1792 * approach we take is to always round up the 1793 * calculated value, so the resulting bandwidth might 1794 * be slightly higher for some configurations. 1795 */ 1796 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1797 1798 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1799 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1800 tqavcc |= value; 1801 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1802 1803 wr32(E1000_I210_TQAVHC(queue), 1804 0x80000000 + ring->hicredit * 0x7735); 1805 } else { 1806 1807 /* Set idleSlope to zero. */ 1808 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1809 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1810 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1811 1812 /* Set hiCredit to zero. */ 1813 wr32(E1000_I210_TQAVHC(queue), 0); 1814 1815 /* If CBS is not enabled for any queues anymore, then return to 1816 * the default state of Data Transmission Arbitration on 1817 * TQAVCTRL. 1818 */ 1819 if (!is_any_cbs_enabled(adapter)) { 1820 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1821 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1822 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1823 } 1824 } 1825 1826 /* If LaunchTime is enabled, set DataTranTIM. */ 1827 if (ring->launchtime_enable) { 1828 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1829 * for any of the SR queues, and configure fetchtime delta. 1830 * XXX NOTE: 1831 * - LaunchTime will be enabled for all SR queues. 1832 * - A fixed offset can be added relative to the launch 1833 * time of all packets if configured at reg LAUNCH_OS0. 1834 * We are keeping it as 0 for now (default value). 1835 */ 1836 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1837 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1838 E1000_TQAVCTRL_FETCHTIME_DELTA; 1839 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1840 } else { 1841 /* If Launchtime is not enabled for any SR queues anymore, 1842 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1843 * effectively disabling Launchtime. 1844 */ 1845 if (!is_any_txtime_enabled(adapter)) { 1846 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1847 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1848 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1849 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1850 } 1851 } 1852 1853 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1854 * CBS are not configurable by software so we don't do any 'controller 1855 * configuration' in respect to these parameters. 1856 */ 1857 1858 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1859 ring->cbs_enable ? "enabled" : "disabled", 1860 ring->launchtime_enable ? "enabled" : "disabled", 1861 queue, 1862 ring->idleslope, ring->sendslope, 1863 ring->hicredit, ring->locredit); 1864} 1865 1866static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1867 bool enable) 1868{ 1869 struct igb_ring *ring; 1870 1871 if (queue < 0 || queue > adapter->num_tx_queues) 1872 return -EINVAL; 1873 1874 ring = adapter->tx_ring[queue]; 1875 ring->launchtime_enable = enable; 1876 1877 return 0; 1878} 1879 1880static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1881 bool enable, int idleslope, int sendslope, 1882 int hicredit, int locredit) 1883{ 1884 struct igb_ring *ring; 1885 1886 if (queue < 0 || queue > adapter->num_tx_queues) 1887 return -EINVAL; 1888 1889 ring = adapter->tx_ring[queue]; 1890 1891 ring->cbs_enable = enable; 1892 ring->idleslope = idleslope; 1893 ring->sendslope = sendslope; 1894 ring->hicredit = hicredit; 1895 ring->locredit = locredit; 1896 1897 return 0; 1898} 1899 1900/** 1901 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1902 * @adapter: pointer to adapter struct 1903 * 1904 * Configure TQAVCTRL register switching the controller's Tx mode 1905 * if FQTSS mode is enabled or disabled. Additionally, will issue 1906 * a call to igb_config_tx_modes() per queue so any previously saved 1907 * Tx parameters are applied. 1908 **/ 1909static void igb_setup_tx_mode(struct igb_adapter *adapter) 1910{ 1911 struct net_device *netdev = adapter->netdev; 1912 struct e1000_hw *hw = &adapter->hw; 1913 u32 val; 1914 1915 /* Only i210 controller supports changing the transmission mode. */ 1916 if (hw->mac.type != e1000_i210) 1917 return; 1918 1919 if (is_fqtss_enabled(adapter)) { 1920 int i, max_queue; 1921 1922 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1923 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1924 * so SP queues wait for SR ones. 1925 */ 1926 val = rd32(E1000_I210_TQAVCTRL); 1927 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1928 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1929 wr32(E1000_I210_TQAVCTRL, val); 1930 1931 /* Configure Tx and Rx packet buffers sizes as described in 1932 * i210 datasheet section 7.2.7.7. 1933 */ 1934 val = rd32(E1000_TXPBS); 1935 val &= ~I210_TXPBSIZE_MASK; 1936 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1937 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1938 wr32(E1000_TXPBS, val); 1939 1940 val = rd32(E1000_RXPBS); 1941 val &= ~I210_RXPBSIZE_MASK; 1942 val |= I210_RXPBSIZE_PB_30KB; 1943 wr32(E1000_RXPBS, val); 1944 1945 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1946 * register should not exceed the buffer size programmed in 1947 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1948 * so according to the datasheet we should set MAX_TPKT_SIZE to 1949 * 4kB / 64. 1950 * 1951 * However, when we do so, no frame from queue 2 and 3 are 1952 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1953 * or _equal_ to the buffer size programmed in TXPBS. For this 1954 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1955 */ 1956 val = (4096 - 1) / 64; 1957 wr32(E1000_I210_DTXMXPKTSZ, val); 1958 1959 /* Since FQTSS mode is enabled, apply any CBS configuration 1960 * previously set. If no previous CBS configuration has been 1961 * done, then the initial configuration is applied, which means 1962 * CBS is disabled. 1963 */ 1964 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1965 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1966 1967 for (i = 0; i < max_queue; i++) { 1968 igb_config_tx_modes(adapter, i); 1969 } 1970 } else { 1971 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1972 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1973 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1974 1975 val = rd32(E1000_I210_TQAVCTRL); 1976 /* According to Section 8.12.21, the other flags we've set when 1977 * enabling FQTSS are not relevant when disabling FQTSS so we 1978 * don't set they here. 1979 */ 1980 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1981 wr32(E1000_I210_TQAVCTRL, val); 1982 } 1983 1984 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1985 "enabled" : "disabled"); 1986} 1987 1988/** 1989 * igb_configure - configure the hardware for RX and TX 1990 * @adapter: private board structure 1991 **/ 1992static void igb_configure(struct igb_adapter *adapter) 1993{ 1994 struct net_device *netdev = adapter->netdev; 1995 int i; 1996 1997 igb_get_hw_control(adapter); 1998 igb_set_rx_mode(netdev); 1999 igb_setup_tx_mode(adapter); 2000 2001 igb_restore_vlan(adapter); 2002 2003 igb_setup_tctl(adapter); 2004 igb_setup_mrqc(adapter); 2005 igb_setup_rctl(adapter); 2006 2007 igb_nfc_filter_restore(adapter); 2008 igb_configure_tx(adapter); 2009 igb_configure_rx(adapter); 2010 2011 igb_rx_fifo_flush_82575(&adapter->hw); 2012 2013 /* call igb_desc_unused which always leaves 2014 * at least 1 descriptor unused to make sure 2015 * next_to_use != next_to_clean 2016 */ 2017 for (i = 0; i < adapter->num_rx_queues; i++) { 2018 struct igb_ring *ring = adapter->rx_ring[i]; 2019 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2020 } 2021} 2022 2023/** 2024 * igb_power_up_link - Power up the phy/serdes link 2025 * @adapter: address of board private structure 2026 **/ 2027void igb_power_up_link(struct igb_adapter *adapter) 2028{ 2029 igb_reset_phy(&adapter->hw); 2030 2031 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2032 igb_power_up_phy_copper(&adapter->hw); 2033 else 2034 igb_power_up_serdes_link_82575(&adapter->hw); 2035 2036 igb_setup_link(&adapter->hw); 2037} 2038 2039/** 2040 * igb_power_down_link - Power down the phy/serdes link 2041 * @adapter: address of board private structure 2042 */ 2043static void igb_power_down_link(struct igb_adapter *adapter) 2044{ 2045 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2046 igb_power_down_phy_copper_82575(&adapter->hw); 2047 else 2048 igb_shutdown_serdes_link_82575(&adapter->hw); 2049} 2050 2051/** 2052 * Detect and switch function for Media Auto Sense 2053 * @adapter: address of the board private structure 2054 **/ 2055static void igb_check_swap_media(struct igb_adapter *adapter) 2056{ 2057 struct e1000_hw *hw = &adapter->hw; 2058 u32 ctrl_ext, connsw; 2059 bool swap_now = false; 2060 2061 ctrl_ext = rd32(E1000_CTRL_EXT); 2062 connsw = rd32(E1000_CONNSW); 2063 2064 /* need to live swap if current media is copper and we have fiber/serdes 2065 * to go to. 2066 */ 2067 2068 if ((hw->phy.media_type == e1000_media_type_copper) && 2069 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2070 swap_now = true; 2071 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2072 !(connsw & E1000_CONNSW_SERDESD)) { 2073 /* copper signal takes time to appear */ 2074 if (adapter->copper_tries < 4) { 2075 adapter->copper_tries++; 2076 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2077 wr32(E1000_CONNSW, connsw); 2078 return; 2079 } else { 2080 adapter->copper_tries = 0; 2081 if ((connsw & E1000_CONNSW_PHYSD) && 2082 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2083 swap_now = true; 2084 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2085 wr32(E1000_CONNSW, connsw); 2086 } 2087 } 2088 } 2089 2090 if (!swap_now) 2091 return; 2092 2093 switch (hw->phy.media_type) { 2094 case e1000_media_type_copper: 2095 netdev_info(adapter->netdev, 2096 "MAS: changing media to fiber/serdes\n"); 2097 ctrl_ext |= 2098 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2099 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2100 adapter->copper_tries = 0; 2101 break; 2102 case e1000_media_type_internal_serdes: 2103 case e1000_media_type_fiber: 2104 netdev_info(adapter->netdev, 2105 "MAS: changing media to copper\n"); 2106 ctrl_ext &= 2107 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2108 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2109 break; 2110 default: 2111 /* shouldn't get here during regular operation */ 2112 netdev_err(adapter->netdev, 2113 "AMS: Invalid media type found, returning\n"); 2114 break; 2115 } 2116 wr32(E1000_CTRL_EXT, ctrl_ext); 2117} 2118 2119/** 2120 * igb_up - Open the interface and prepare it to handle traffic 2121 * @adapter: board private structure 2122 **/ 2123int igb_up(struct igb_adapter *adapter) 2124{ 2125 struct e1000_hw *hw = &adapter->hw; 2126 int i; 2127 2128 /* hardware has been reset, we need to reload some things */ 2129 igb_configure(adapter); 2130 2131 clear_bit(__IGB_DOWN, &adapter->state); 2132 2133 for (i = 0; i < adapter->num_q_vectors; i++) 2134 napi_enable(&(adapter->q_vector[i]->napi)); 2135 2136 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2137 igb_configure_msix(adapter); 2138 else 2139 igb_assign_vector(adapter->q_vector[0], 0); 2140 2141 /* Clear any pending interrupts. */ 2142 rd32(E1000_TSICR); 2143 rd32(E1000_ICR); 2144 igb_irq_enable(adapter); 2145 2146 /* notify VFs that reset has been completed */ 2147 if (adapter->vfs_allocated_count) { 2148 u32 reg_data = rd32(E1000_CTRL_EXT); 2149 2150 reg_data |= E1000_CTRL_EXT_PFRSTD; 2151 wr32(E1000_CTRL_EXT, reg_data); 2152 } 2153 2154 netif_tx_start_all_queues(adapter->netdev); 2155 2156 /* start the watchdog. */ 2157 hw->mac.get_link_status = 1; 2158 schedule_work(&adapter->watchdog_task); 2159 2160 if ((adapter->flags & IGB_FLAG_EEE) && 2161 (!hw->dev_spec._82575.eee_disable)) 2162 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2163 2164 return 0; 2165} 2166 2167void igb_down(struct igb_adapter *adapter) 2168{ 2169 struct net_device *netdev = adapter->netdev; 2170 struct e1000_hw *hw = &adapter->hw; 2171 u32 tctl, rctl; 2172 int i; 2173 2174 /* signal that we're down so the interrupt handler does not 2175 * reschedule our watchdog timer 2176 */ 2177 set_bit(__IGB_DOWN, &adapter->state); 2178 2179 /* disable receives in the hardware */ 2180 rctl = rd32(E1000_RCTL); 2181 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2182 /* flush and sleep below */ 2183 2184 igb_nfc_filter_exit(adapter); 2185 2186 netif_carrier_off(netdev); 2187 netif_tx_stop_all_queues(netdev); 2188 2189 /* disable transmits in the hardware */ 2190 tctl = rd32(E1000_TCTL); 2191 tctl &= ~E1000_TCTL_EN; 2192 wr32(E1000_TCTL, tctl); 2193 /* flush both disables and wait for them to finish */ 2194 wrfl(); 2195 usleep_range(10000, 11000); 2196 2197 igb_irq_disable(adapter); 2198 2199 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2200 2201 for (i = 0; i < adapter->num_q_vectors; i++) { 2202 if (adapter->q_vector[i]) { 2203 napi_synchronize(&adapter->q_vector[i]->napi); 2204 napi_disable(&adapter->q_vector[i]->napi); 2205 } 2206 } 2207 2208 del_timer_sync(&adapter->watchdog_timer); 2209 del_timer_sync(&adapter->phy_info_timer); 2210 2211 /* record the stats before reset*/ 2212 spin_lock(&adapter->stats64_lock); 2213 igb_update_stats(adapter); 2214 spin_unlock(&adapter->stats64_lock); 2215 2216 adapter->link_speed = 0; 2217 adapter->link_duplex = 0; 2218 2219 if (!pci_channel_offline(adapter->pdev)) 2220 igb_reset(adapter); 2221 2222 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2223 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2224 2225 igb_clean_all_tx_rings(adapter); 2226 igb_clean_all_rx_rings(adapter); 2227#ifdef CONFIG_IGB_DCA 2228 2229 /* since we reset the hardware DCA settings were cleared */ 2230 igb_setup_dca(adapter); 2231#endif 2232} 2233 2234void igb_reinit_locked(struct igb_adapter *adapter) 2235{ 2236 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2237 usleep_range(1000, 2000); 2238 igb_down(adapter); 2239 igb_up(adapter); 2240 clear_bit(__IGB_RESETTING, &adapter->state); 2241} 2242 2243/** igb_enable_mas - Media Autosense re-enable after swap 2244 * 2245 * @adapter: adapter struct 2246 **/ 2247static void igb_enable_mas(struct igb_adapter *adapter) 2248{ 2249 struct e1000_hw *hw = &adapter->hw; 2250 u32 connsw = rd32(E1000_CONNSW); 2251 2252 /* configure for SerDes media detect */ 2253 if ((hw->phy.media_type == e1000_media_type_copper) && 2254 (!(connsw & E1000_CONNSW_SERDESD))) { 2255 connsw |= E1000_CONNSW_ENRGSRC; 2256 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2257 wr32(E1000_CONNSW, connsw); 2258 wrfl(); 2259 } 2260} 2261 2262void igb_reset(struct igb_adapter *adapter) 2263{ 2264 struct pci_dev *pdev = adapter->pdev; 2265 struct e1000_hw *hw = &adapter->hw; 2266 struct e1000_mac_info *mac = &hw->mac; 2267 struct e1000_fc_info *fc = &hw->fc; 2268 u32 pba, hwm; 2269 2270 /* Repartition Pba for greater than 9k mtu 2271 * To take effect CTRL.RST is required. 2272 */ 2273 switch (mac->type) { 2274 case e1000_i350: 2275 case e1000_i354: 2276 case e1000_82580: 2277 pba = rd32(E1000_RXPBS); 2278 pba = igb_rxpbs_adjust_82580(pba); 2279 break; 2280 case e1000_82576: 2281 pba = rd32(E1000_RXPBS); 2282 pba &= E1000_RXPBS_SIZE_MASK_82576; 2283 break; 2284 case e1000_82575: 2285 case e1000_i210: 2286 case e1000_i211: 2287 default: 2288 pba = E1000_PBA_34K; 2289 break; 2290 } 2291 2292 if (mac->type == e1000_82575) { 2293 u32 min_rx_space, min_tx_space, needed_tx_space; 2294 2295 /* write Rx PBA so that hardware can report correct Tx PBA */ 2296 wr32(E1000_PBA, pba); 2297 2298 /* To maintain wire speed transmits, the Tx FIFO should be 2299 * large enough to accommodate two full transmit packets, 2300 * rounded up to the next 1KB and expressed in KB. Likewise, 2301 * the Rx FIFO should be large enough to accommodate at least 2302 * one full receive packet and is similarly rounded up and 2303 * expressed in KB. 2304 */ 2305 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2306 2307 /* The Tx FIFO also stores 16 bytes of information about the Tx 2308 * but don't include Ethernet FCS because hardware appends it. 2309 * We only need to round down to the nearest 512 byte block 2310 * count since the value we care about is 2 frames, not 1. 2311 */ 2312 min_tx_space = adapter->max_frame_size; 2313 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2314 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2315 2316 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2317 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2318 2319 /* If current Tx allocation is less than the min Tx FIFO size, 2320 * and the min Tx FIFO size is less than the current Rx FIFO 2321 * allocation, take space away from current Rx allocation. 2322 */ 2323 if (needed_tx_space < pba) { 2324 pba -= needed_tx_space; 2325 2326 /* if short on Rx space, Rx wins and must trump Tx 2327 * adjustment 2328 */ 2329 if (pba < min_rx_space) 2330 pba = min_rx_space; 2331 } 2332 2333 /* adjust PBA for jumbo frames */ 2334 wr32(E1000_PBA, pba); 2335 } 2336 2337 /* flow control settings 2338 * The high water mark must be low enough to fit one full frame 2339 * after transmitting the pause frame. As such we must have enough 2340 * space to allow for us to complete our current transmit and then 2341 * receive the frame that is in progress from the link partner. 2342 * Set it to: 2343 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2344 */ 2345 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2346 2347 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2348 fc->low_water = fc->high_water - 16; 2349 fc->pause_time = 0xFFFF; 2350 fc->send_xon = 1; 2351 fc->current_mode = fc->requested_mode; 2352 2353 /* disable receive for all VFs and wait one second */ 2354 if (adapter->vfs_allocated_count) { 2355 int i; 2356 2357 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2358 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2359 2360 /* ping all the active vfs to let them know we are going down */ 2361 igb_ping_all_vfs(adapter); 2362 2363 /* disable transmits and receives */ 2364 wr32(E1000_VFRE, 0); 2365 wr32(E1000_VFTE, 0); 2366 } 2367 2368 /* Allow time for pending master requests to run */ 2369 hw->mac.ops.reset_hw(hw); 2370 wr32(E1000_WUC, 0); 2371 2372 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2373 /* need to resetup here after media swap */ 2374 adapter->ei.get_invariants(hw); 2375 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2376 } 2377 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2378 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2379 igb_enable_mas(adapter); 2380 } 2381 if (hw->mac.ops.init_hw(hw)) 2382 dev_err(&pdev->dev, "Hardware Error\n"); 2383 2384 /* RAR registers were cleared during init_hw, clear mac table */ 2385 igb_flush_mac_table(adapter); 2386 __dev_uc_unsync(adapter->netdev, NULL); 2387 2388 /* Recover default RAR entry */ 2389 igb_set_default_mac_filter(adapter); 2390 2391 /* Flow control settings reset on hardware reset, so guarantee flow 2392 * control is off when forcing speed. 2393 */ 2394 if (!hw->mac.autoneg) 2395 igb_force_mac_fc(hw); 2396 2397 igb_init_dmac(adapter, pba); 2398#ifdef CONFIG_IGB_HWMON 2399 /* Re-initialize the thermal sensor on i350 devices. */ 2400 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2401 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2402 /* If present, re-initialize the external thermal sensor 2403 * interface. 2404 */ 2405 if (adapter->ets) 2406 mac->ops.init_thermal_sensor_thresh(hw); 2407 } 2408 } 2409#endif 2410 /* Re-establish EEE setting */ 2411 if (hw->phy.media_type == e1000_media_type_copper) { 2412 switch (mac->type) { 2413 case e1000_i350: 2414 case e1000_i210: 2415 case e1000_i211: 2416 igb_set_eee_i350(hw, true, true); 2417 break; 2418 case e1000_i354: 2419 igb_set_eee_i354(hw, true, true); 2420 break; 2421 default: 2422 break; 2423 } 2424 } 2425 if (!netif_running(adapter->netdev)) 2426 igb_power_down_link(adapter); 2427 2428 igb_update_mng_vlan(adapter); 2429 2430 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2431 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2432 2433 /* Re-enable PTP, where applicable. */ 2434 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2435 igb_ptp_reset(adapter); 2436 2437 igb_get_phy_info(hw); 2438} 2439 2440static netdev_features_t igb_fix_features(struct net_device *netdev, 2441 netdev_features_t features) 2442{ 2443 /* Since there is no support for separate Rx/Tx vlan accel 2444 * enable/disable make sure Tx flag is always in same state as Rx. 2445 */ 2446 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2447 features |= NETIF_F_HW_VLAN_CTAG_TX; 2448 else 2449 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2450 2451 return features; 2452} 2453 2454static int igb_set_features(struct net_device *netdev, 2455 netdev_features_t features) 2456{ 2457 netdev_features_t changed = netdev->features ^ features; 2458 struct igb_adapter *adapter = netdev_priv(netdev); 2459 2460 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2461 igb_vlan_mode(netdev, features); 2462 2463 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2464 return 0; 2465 2466 if (!(features & NETIF_F_NTUPLE)) { 2467 struct hlist_node *node2; 2468 struct igb_nfc_filter *rule; 2469 2470 spin_lock(&adapter->nfc_lock); 2471 hlist_for_each_entry_safe(rule, node2, 2472 &adapter->nfc_filter_list, nfc_node) { 2473 igb_erase_filter(adapter, rule); 2474 hlist_del(&rule->nfc_node); 2475 kfree(rule); 2476 } 2477 spin_unlock(&adapter->nfc_lock); 2478 adapter->nfc_filter_count = 0; 2479 } 2480 2481 netdev->features = features; 2482 2483 if (netif_running(netdev)) 2484 igb_reinit_locked(adapter); 2485 else 2486 igb_reset(adapter); 2487 2488 return 1; 2489} 2490 2491static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2492 struct net_device *dev, 2493 const unsigned char *addr, u16 vid, 2494 u16 flags, 2495 struct netlink_ext_ack *extack) 2496{ 2497 /* guarantee we can provide a unique filter for the unicast address */ 2498 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2499 struct igb_adapter *adapter = netdev_priv(dev); 2500 int vfn = adapter->vfs_allocated_count; 2501 2502 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2503 return -ENOMEM; 2504 } 2505 2506 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2507} 2508 2509#define IGB_MAX_MAC_HDR_LEN 127 2510#define IGB_MAX_NETWORK_HDR_LEN 511 2511 2512static netdev_features_t 2513igb_features_check(struct sk_buff *skb, struct net_device *dev, 2514 netdev_features_t features) 2515{ 2516 unsigned int network_hdr_len, mac_hdr_len; 2517 2518 /* Make certain the headers can be described by a context descriptor */ 2519 mac_hdr_len = skb_network_header(skb) - skb->data; 2520 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2521 return features & ~(NETIF_F_HW_CSUM | 2522 NETIF_F_SCTP_CRC | 2523 NETIF_F_GSO_UDP_L4 | 2524 NETIF_F_HW_VLAN_CTAG_TX | 2525 NETIF_F_TSO | 2526 NETIF_F_TSO6); 2527 2528 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2529 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2530 return features & ~(NETIF_F_HW_CSUM | 2531 NETIF_F_SCTP_CRC | 2532 NETIF_F_GSO_UDP_L4 | 2533 NETIF_F_TSO | 2534 NETIF_F_TSO6); 2535 2536 /* We can only support IPV4 TSO in tunnels if we can mangle the 2537 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2538 */ 2539 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2540 features &= ~NETIF_F_TSO; 2541 2542 return features; 2543} 2544 2545static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2546{ 2547 if (!is_fqtss_enabled(adapter)) { 2548 enable_fqtss(adapter, true); 2549 return; 2550 } 2551 2552 igb_config_tx_modes(adapter, queue); 2553 2554 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2555 enable_fqtss(adapter, false); 2556} 2557 2558static int igb_offload_cbs(struct igb_adapter *adapter, 2559 struct tc_cbs_qopt_offload *qopt) 2560{ 2561 struct e1000_hw *hw = &adapter->hw; 2562 int err; 2563 2564 /* CBS offloading is only supported by i210 controller. */ 2565 if (hw->mac.type != e1000_i210) 2566 return -EOPNOTSUPP; 2567 2568 /* CBS offloading is only supported by queue 0 and queue 1. */ 2569 if (qopt->queue < 0 || qopt->queue > 1) 2570 return -EINVAL; 2571 2572 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2573 qopt->idleslope, qopt->sendslope, 2574 qopt->hicredit, qopt->locredit); 2575 if (err) 2576 return err; 2577 2578 igb_offload_apply(adapter, qopt->queue); 2579 2580 return 0; 2581} 2582 2583#define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2584#define VLAN_PRIO_FULL_MASK (0x07) 2585 2586static int igb_parse_cls_flower(struct igb_adapter *adapter, 2587 struct flow_cls_offload *f, 2588 int traffic_class, 2589 struct igb_nfc_filter *input) 2590{ 2591 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2592 struct flow_dissector *dissector = rule->match.dissector; 2593 struct netlink_ext_ack *extack = f->common.extack; 2594 2595 if (dissector->used_keys & 2596 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2597 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2598 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2599 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2600 NL_SET_ERR_MSG_MOD(extack, 2601 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2602 return -EOPNOTSUPP; 2603 } 2604 2605 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2606 struct flow_match_eth_addrs match; 2607 2608 flow_rule_match_eth_addrs(rule, &match); 2609 if (!is_zero_ether_addr(match.mask->dst)) { 2610 if (!is_broadcast_ether_addr(match.mask->dst)) { 2611 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2612 return -EINVAL; 2613 } 2614 2615 input->filter.match_flags |= 2616 IGB_FILTER_FLAG_DST_MAC_ADDR; 2617 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2618 } 2619 2620 if (!is_zero_ether_addr(match.mask->src)) { 2621 if (!is_broadcast_ether_addr(match.mask->src)) { 2622 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2623 return -EINVAL; 2624 } 2625 2626 input->filter.match_flags |= 2627 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2628 ether_addr_copy(input->filter.src_addr, match.key->src); 2629 } 2630 } 2631 2632 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2633 struct flow_match_basic match; 2634 2635 flow_rule_match_basic(rule, &match); 2636 if (match.mask->n_proto) { 2637 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2638 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2639 return -EINVAL; 2640 } 2641 2642 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2643 input->filter.etype = match.key->n_proto; 2644 } 2645 } 2646 2647 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2648 struct flow_match_vlan match; 2649 2650 flow_rule_match_vlan(rule, &match); 2651 if (match.mask->vlan_priority) { 2652 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2653 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2654 return -EINVAL; 2655 } 2656 2657 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2658 input->filter.vlan_tci = 2659 (__force __be16)match.key->vlan_priority; 2660 } 2661 } 2662 2663 input->action = traffic_class; 2664 input->cookie = f->cookie; 2665 2666 return 0; 2667} 2668 2669static int igb_configure_clsflower(struct igb_adapter *adapter, 2670 struct flow_cls_offload *cls_flower) 2671{ 2672 struct netlink_ext_ack *extack = cls_flower->common.extack; 2673 struct igb_nfc_filter *filter, *f; 2674 int err, tc; 2675 2676 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2677 if (tc < 0) { 2678 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2679 return -EINVAL; 2680 } 2681 2682 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2683 if (!filter) 2684 return -ENOMEM; 2685 2686 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2687 if (err < 0) 2688 goto err_parse; 2689 2690 spin_lock(&adapter->nfc_lock); 2691 2692 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2693 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2694 err = -EEXIST; 2695 NL_SET_ERR_MSG_MOD(extack, 2696 "This filter is already set in ethtool"); 2697 goto err_locked; 2698 } 2699 } 2700 2701 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2702 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2703 err = -EEXIST; 2704 NL_SET_ERR_MSG_MOD(extack, 2705 "This filter is already set in cls_flower"); 2706 goto err_locked; 2707 } 2708 } 2709 2710 err = igb_add_filter(adapter, filter); 2711 if (err < 0) { 2712 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2713 goto err_locked; 2714 } 2715 2716 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2717 2718 spin_unlock(&adapter->nfc_lock); 2719 2720 return 0; 2721 2722err_locked: 2723 spin_unlock(&adapter->nfc_lock); 2724 2725err_parse: 2726 kfree(filter); 2727 2728 return err; 2729} 2730 2731static int igb_delete_clsflower(struct igb_adapter *adapter, 2732 struct flow_cls_offload *cls_flower) 2733{ 2734 struct igb_nfc_filter *filter; 2735 int err; 2736 2737 spin_lock(&adapter->nfc_lock); 2738 2739 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2740 if (filter->cookie == cls_flower->cookie) 2741 break; 2742 2743 if (!filter) { 2744 err = -ENOENT; 2745 goto out; 2746 } 2747 2748 err = igb_erase_filter(adapter, filter); 2749 if (err < 0) 2750 goto out; 2751 2752 hlist_del(&filter->nfc_node); 2753 kfree(filter); 2754 2755out: 2756 spin_unlock(&adapter->nfc_lock); 2757 2758 return err; 2759} 2760 2761static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2762 struct flow_cls_offload *cls_flower) 2763{ 2764 switch (cls_flower->command) { 2765 case FLOW_CLS_REPLACE: 2766 return igb_configure_clsflower(adapter, cls_flower); 2767 case FLOW_CLS_DESTROY: 2768 return igb_delete_clsflower(adapter, cls_flower); 2769 case FLOW_CLS_STATS: 2770 return -EOPNOTSUPP; 2771 default: 2772 return -EOPNOTSUPP; 2773 } 2774} 2775 2776static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2777 void *cb_priv) 2778{ 2779 struct igb_adapter *adapter = cb_priv; 2780 2781 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2782 return -EOPNOTSUPP; 2783 2784 switch (type) { 2785 case TC_SETUP_CLSFLOWER: 2786 return igb_setup_tc_cls_flower(adapter, type_data); 2787 2788 default: 2789 return -EOPNOTSUPP; 2790 } 2791} 2792 2793static int igb_offload_txtime(struct igb_adapter *adapter, 2794 struct tc_etf_qopt_offload *qopt) 2795{ 2796 struct e1000_hw *hw = &adapter->hw; 2797 int err; 2798 2799 /* Launchtime offloading is only supported by i210 controller. */ 2800 if (hw->mac.type != e1000_i210) 2801 return -EOPNOTSUPP; 2802 2803 /* Launchtime offloading is only supported by queues 0 and 1. */ 2804 if (qopt->queue < 0 || qopt->queue > 1) 2805 return -EINVAL; 2806 2807 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2808 if (err) 2809 return err; 2810 2811 igb_offload_apply(adapter, qopt->queue); 2812 2813 return 0; 2814} 2815 2816static LIST_HEAD(igb_block_cb_list); 2817 2818static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2819 void *type_data) 2820{ 2821 struct igb_adapter *adapter = netdev_priv(dev); 2822 2823 switch (type) { 2824 case TC_SETUP_QDISC_CBS: 2825 return igb_offload_cbs(adapter, type_data); 2826 case TC_SETUP_BLOCK: 2827 return flow_block_cb_setup_simple(type_data, 2828 &igb_block_cb_list, 2829 igb_setup_tc_block_cb, 2830 adapter, adapter, true); 2831 2832 case TC_SETUP_QDISC_ETF: 2833 return igb_offload_txtime(adapter, type_data); 2834 2835 default: 2836 return -EOPNOTSUPP; 2837 } 2838} 2839 2840static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2841{ 2842 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2843 struct igb_adapter *adapter = netdev_priv(dev); 2844 struct bpf_prog *prog = bpf->prog, *old_prog; 2845 bool running = netif_running(dev); 2846 bool need_reset; 2847 2848 /* verify igb ring attributes are sufficient for XDP */ 2849 for (i = 0; i < adapter->num_rx_queues; i++) { 2850 struct igb_ring *ring = adapter->rx_ring[i]; 2851 2852 if (frame_size > igb_rx_bufsz(ring)) { 2853 NL_SET_ERR_MSG_MOD(bpf->extack, 2854 "The RX buffer size is too small for the frame size"); 2855 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2856 igb_rx_bufsz(ring), frame_size); 2857 return -EINVAL; 2858 } 2859 } 2860 2861 old_prog = xchg(&adapter->xdp_prog, prog); 2862 need_reset = (!!prog != !!old_prog); 2863 2864 /* device is up and bpf is added/removed, must setup the RX queues */ 2865 if (need_reset && running) { 2866 igb_close(dev); 2867 } else { 2868 for (i = 0; i < adapter->num_rx_queues; i++) 2869 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2870 adapter->xdp_prog); 2871 } 2872 2873 if (old_prog) 2874 bpf_prog_put(old_prog); 2875 2876 /* bpf is just replaced, RXQ and MTU are already setup */ 2877 if (!need_reset) 2878 return 0; 2879 2880 if (running) 2881 igb_open(dev); 2882 2883 return 0; 2884} 2885 2886static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2887{ 2888 switch (xdp->command) { 2889 case XDP_SETUP_PROG: 2890 return igb_xdp_setup(dev, xdp); 2891 default: 2892 return -EINVAL; 2893 } 2894} 2895 2896static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2897{ 2898 /* Force memory writes to complete before letting h/w know there 2899 * are new descriptors to fetch. 2900 */ 2901 wmb(); 2902 writel(ring->next_to_use, ring->tail); 2903} 2904 2905static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2906{ 2907 unsigned int r_idx = smp_processor_id(); 2908 2909 if (r_idx >= adapter->num_tx_queues) 2910 r_idx = r_idx % adapter->num_tx_queues; 2911 2912 return adapter->tx_ring[r_idx]; 2913} 2914 2915static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2916{ 2917 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2918 int cpu = smp_processor_id(); 2919 struct igb_ring *tx_ring; 2920 struct netdev_queue *nq; 2921 u32 ret; 2922 2923 if (unlikely(!xdpf)) 2924 return IGB_XDP_CONSUMED; 2925 2926 /* During program transitions its possible adapter->xdp_prog is assigned 2927 * but ring has not been configured yet. In this case simply abort xmit. 2928 */ 2929 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2930 if (unlikely(!tx_ring)) 2931 return IGB_XDP_CONSUMED; 2932 2933 nq = txring_txq(tx_ring); 2934 __netif_tx_lock(nq, cpu); 2935 /* Avoid transmit queue timeout since we share it with the slow path */ 2936 nq->trans_start = jiffies; 2937 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2938 __netif_tx_unlock(nq); 2939 2940 return ret; 2941} 2942 2943static int igb_xdp_xmit(struct net_device *dev, int n, 2944 struct xdp_frame **frames, u32 flags) 2945{ 2946 struct igb_adapter *adapter = netdev_priv(dev); 2947 int cpu = smp_processor_id(); 2948 struct igb_ring *tx_ring; 2949 struct netdev_queue *nq; 2950 int drops = 0; 2951 int i; 2952 2953 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2954 return -ENETDOWN; 2955 2956 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2957 return -EINVAL; 2958 2959 /* During program transitions its possible adapter->xdp_prog is assigned 2960 * but ring has not been configured yet. In this case simply abort xmit. 2961 */ 2962 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2963 if (unlikely(!tx_ring)) 2964 return -ENXIO; 2965 2966 nq = txring_txq(tx_ring); 2967 __netif_tx_lock(nq, cpu); 2968 2969 /* Avoid transmit queue timeout since we share it with the slow path */ 2970 nq->trans_start = jiffies; 2971 2972 for (i = 0; i < n; i++) { 2973 struct xdp_frame *xdpf = frames[i]; 2974 int err; 2975 2976 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2977 if (err != IGB_XDP_TX) { 2978 xdp_return_frame_rx_napi(xdpf); 2979 drops++; 2980 } 2981 } 2982 2983 __netif_tx_unlock(nq); 2984 2985 if (unlikely(flags & XDP_XMIT_FLUSH)) 2986 igb_xdp_ring_update_tail(tx_ring); 2987 2988 return n - drops; 2989} 2990 2991static const struct net_device_ops igb_netdev_ops = { 2992 .ndo_open = igb_open, 2993 .ndo_stop = igb_close, 2994 .ndo_start_xmit = igb_xmit_frame, 2995 .ndo_get_stats64 = igb_get_stats64, 2996 .ndo_set_rx_mode = igb_set_rx_mode, 2997 .ndo_set_mac_address = igb_set_mac, 2998 .ndo_change_mtu = igb_change_mtu, 2999 .ndo_do_ioctl = igb_ioctl, 3000 .ndo_tx_timeout = igb_tx_timeout, 3001 .ndo_validate_addr = eth_validate_addr, 3002 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3003 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3004 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3005 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3006 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3007 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3008 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3009 .ndo_get_vf_config = igb_ndo_get_vf_config, 3010 .ndo_fix_features = igb_fix_features, 3011 .ndo_set_features = igb_set_features, 3012 .ndo_fdb_add = igb_ndo_fdb_add, 3013 .ndo_features_check = igb_features_check, 3014 .ndo_setup_tc = igb_setup_tc, 3015 .ndo_bpf = igb_xdp, 3016 .ndo_xdp_xmit = igb_xdp_xmit, 3017}; 3018 3019/** 3020 * igb_set_fw_version - Configure version string for ethtool 3021 * @adapter: adapter struct 3022 **/ 3023void igb_set_fw_version(struct igb_adapter *adapter) 3024{ 3025 struct e1000_hw *hw = &adapter->hw; 3026 struct e1000_fw_version fw; 3027 3028 igb_get_fw_version(hw, &fw); 3029 3030 switch (hw->mac.type) { 3031 case e1000_i210: 3032 case e1000_i211: 3033 if (!(igb_get_flash_presence_i210(hw))) { 3034 snprintf(adapter->fw_version, 3035 sizeof(adapter->fw_version), 3036 "%2d.%2d-%d", 3037 fw.invm_major, fw.invm_minor, 3038 fw.invm_img_type); 3039 break; 3040 } 3041 fallthrough; 3042 default: 3043 /* if option is rom valid, display its version too */ 3044 if (fw.or_valid) { 3045 snprintf(adapter->fw_version, 3046 sizeof(adapter->fw_version), 3047 "%d.%d, 0x%08x, %d.%d.%d", 3048 fw.eep_major, fw.eep_minor, fw.etrack_id, 3049 fw.or_major, fw.or_build, fw.or_patch); 3050 /* no option rom */ 3051 } else if (fw.etrack_id != 0X0000) { 3052 snprintf(adapter->fw_version, 3053 sizeof(adapter->fw_version), 3054 "%d.%d, 0x%08x", 3055 fw.eep_major, fw.eep_minor, fw.etrack_id); 3056 } else { 3057 snprintf(adapter->fw_version, 3058 sizeof(adapter->fw_version), 3059 "%d.%d.%d", 3060 fw.eep_major, fw.eep_minor, fw.eep_build); 3061 } 3062 break; 3063 } 3064} 3065 3066/** 3067 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3068 * 3069 * @adapter: adapter struct 3070 **/ 3071static void igb_init_mas(struct igb_adapter *adapter) 3072{ 3073 struct e1000_hw *hw = &adapter->hw; 3074 u16 eeprom_data; 3075 3076 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3077 switch (hw->bus.func) { 3078 case E1000_FUNC_0: 3079 if (eeprom_data & IGB_MAS_ENABLE_0) { 3080 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3081 netdev_info(adapter->netdev, 3082 "MAS: Enabling Media Autosense for port %d\n", 3083 hw->bus.func); 3084 } 3085 break; 3086 case E1000_FUNC_1: 3087 if (eeprom_data & IGB_MAS_ENABLE_1) { 3088 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3089 netdev_info(adapter->netdev, 3090 "MAS: Enabling Media Autosense for port %d\n", 3091 hw->bus.func); 3092 } 3093 break; 3094 case E1000_FUNC_2: 3095 if (eeprom_data & IGB_MAS_ENABLE_2) { 3096 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3097 netdev_info(adapter->netdev, 3098 "MAS: Enabling Media Autosense for port %d\n", 3099 hw->bus.func); 3100 } 3101 break; 3102 case E1000_FUNC_3: 3103 if (eeprom_data & IGB_MAS_ENABLE_3) { 3104 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3105 netdev_info(adapter->netdev, 3106 "MAS: Enabling Media Autosense for port %d\n", 3107 hw->bus.func); 3108 } 3109 break; 3110 default: 3111 /* Shouldn't get here */ 3112 netdev_err(adapter->netdev, 3113 "MAS: Invalid port configuration, returning\n"); 3114 break; 3115 } 3116} 3117 3118/** 3119 * igb_init_i2c - Init I2C interface 3120 * @adapter: pointer to adapter structure 3121 **/ 3122static s32 igb_init_i2c(struct igb_adapter *adapter) 3123{ 3124 s32 status = 0; 3125 3126 /* I2C interface supported on i350 devices */ 3127 if (adapter->hw.mac.type != e1000_i350) 3128 return 0; 3129 3130 /* Initialize the i2c bus which is controlled by the registers. 3131 * This bus will use the i2c_algo_bit structue that implements 3132 * the protocol through toggling of the 4 bits in the register. 3133 */ 3134 adapter->i2c_adap.owner = THIS_MODULE; 3135 adapter->i2c_algo = igb_i2c_algo; 3136 adapter->i2c_algo.data = adapter; 3137 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3138 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3139 strlcpy(adapter->i2c_adap.name, "igb BB", 3140 sizeof(adapter->i2c_adap.name)); 3141 status = i2c_bit_add_bus(&adapter->i2c_adap); 3142 return status; 3143} 3144 3145/** 3146 * igb_probe - Device Initialization Routine 3147 * @pdev: PCI device information struct 3148 * @ent: entry in igb_pci_tbl 3149 * 3150 * Returns 0 on success, negative on failure 3151 * 3152 * igb_probe initializes an adapter identified by a pci_dev structure. 3153 * The OS initialization, configuring of the adapter private structure, 3154 * and a hardware reset occur. 3155 **/ 3156static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3157{ 3158 struct net_device *netdev; 3159 struct igb_adapter *adapter; 3160 struct e1000_hw *hw; 3161 u16 eeprom_data = 0; 3162 s32 ret_val; 3163 static int global_quad_port_a; /* global quad port a indication */ 3164 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3165 int err, pci_using_dac; 3166 u8 part_str[E1000_PBANUM_LENGTH]; 3167 3168 /* Catch broken hardware that put the wrong VF device ID in 3169 * the PCIe SR-IOV capability. 3170 */ 3171 if (pdev->is_virtfn) { 3172 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3173 pci_name(pdev), pdev->vendor, pdev->device); 3174 return -EINVAL; 3175 } 3176 3177 err = pci_enable_device_mem(pdev); 3178 if (err) 3179 return err; 3180 3181 pci_using_dac = 0; 3182 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3183 if (!err) { 3184 pci_using_dac = 1; 3185 } else { 3186 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3187 if (err) { 3188 dev_err(&pdev->dev, 3189 "No usable DMA configuration, aborting\n"); 3190 goto err_dma; 3191 } 3192 } 3193 3194 err = pci_request_mem_regions(pdev, igb_driver_name); 3195 if (err) 3196 goto err_pci_reg; 3197 3198 pci_enable_pcie_error_reporting(pdev); 3199 3200 pci_set_master(pdev); 3201 pci_save_state(pdev); 3202 3203 err = -ENOMEM; 3204 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3205 IGB_MAX_TX_QUEUES); 3206 if (!netdev) 3207 goto err_alloc_etherdev; 3208 3209 SET_NETDEV_DEV(netdev, &pdev->dev); 3210 3211 pci_set_drvdata(pdev, netdev); 3212 adapter = netdev_priv(netdev); 3213 adapter->netdev = netdev; 3214 adapter->pdev = pdev; 3215 hw = &adapter->hw; 3216 hw->back = adapter; 3217 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3218 3219 err = -EIO; 3220 adapter->io_addr = pci_iomap(pdev, 0, 0); 3221 if (!adapter->io_addr) 3222 goto err_ioremap; 3223 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3224 hw->hw_addr = adapter->io_addr; 3225 3226 netdev->netdev_ops = &igb_netdev_ops; 3227 igb_set_ethtool_ops(netdev); 3228 netdev->watchdog_timeo = 5 * HZ; 3229 3230 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3231 3232 netdev->mem_start = pci_resource_start(pdev, 0); 3233 netdev->mem_end = pci_resource_end(pdev, 0); 3234 3235 /* PCI config space info */ 3236 hw->vendor_id = pdev->vendor; 3237 hw->device_id = pdev->device; 3238 hw->revision_id = pdev->revision; 3239 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3240 hw->subsystem_device_id = pdev->subsystem_device; 3241 3242 /* Copy the default MAC, PHY and NVM function pointers */ 3243 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3244 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3245 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3246 /* Initialize skew-specific constants */ 3247 err = ei->get_invariants(hw); 3248 if (err) 3249 goto err_sw_init; 3250 3251 /* setup the private structure */ 3252 err = igb_sw_init(adapter); 3253 if (err) 3254 goto err_sw_init; 3255 3256 igb_get_bus_info_pcie(hw); 3257 3258 hw->phy.autoneg_wait_to_complete = false; 3259 3260 /* Copper options */ 3261 if (hw->phy.media_type == e1000_media_type_copper) { 3262 hw->phy.mdix = AUTO_ALL_MODES; 3263 hw->phy.disable_polarity_correction = false; 3264 hw->phy.ms_type = e1000_ms_hw_default; 3265 } 3266 3267 if (igb_check_reset_block(hw)) 3268 dev_info(&pdev->dev, 3269 "PHY reset is blocked due to SOL/IDER session.\n"); 3270 3271 /* features is initialized to 0 in allocation, it might have bits 3272 * set by igb_sw_init so we should use an or instead of an 3273 * assignment. 3274 */ 3275 netdev->features |= NETIF_F_SG | 3276 NETIF_F_TSO | 3277 NETIF_F_TSO6 | 3278 NETIF_F_RXHASH | 3279 NETIF_F_RXCSUM | 3280 NETIF_F_HW_CSUM; 3281 3282 if (hw->mac.type >= e1000_82576) 3283 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3284 3285 if (hw->mac.type >= e1000_i350) 3286 netdev->features |= NETIF_F_HW_TC; 3287 3288#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3289 NETIF_F_GSO_GRE_CSUM | \ 3290 NETIF_F_GSO_IPXIP4 | \ 3291 NETIF_F_GSO_IPXIP6 | \ 3292 NETIF_F_GSO_UDP_TUNNEL | \ 3293 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3294 3295 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3296 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3297 3298 /* copy netdev features into list of user selectable features */ 3299 netdev->hw_features |= netdev->features | 3300 NETIF_F_HW_VLAN_CTAG_RX | 3301 NETIF_F_HW_VLAN_CTAG_TX | 3302 NETIF_F_RXALL; 3303 3304 if (hw->mac.type >= e1000_i350) 3305 netdev->hw_features |= NETIF_F_NTUPLE; 3306 3307 if (pci_using_dac) 3308 netdev->features |= NETIF_F_HIGHDMA; 3309 3310 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3311 netdev->mpls_features |= NETIF_F_HW_CSUM; 3312 netdev->hw_enc_features |= netdev->vlan_features; 3313 3314 /* set this bit last since it cannot be part of vlan_features */ 3315 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3316 NETIF_F_HW_VLAN_CTAG_RX | 3317 NETIF_F_HW_VLAN_CTAG_TX; 3318 3319 netdev->priv_flags |= IFF_SUPP_NOFCS; 3320 3321 netdev->priv_flags |= IFF_UNICAST_FLT; 3322 3323 /* MTU range: 68 - 9216 */ 3324 netdev->min_mtu = ETH_MIN_MTU; 3325 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3326 3327 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3328 3329 /* before reading the NVM, reset the controller to put the device in a 3330 * known good starting state 3331 */ 3332 hw->mac.ops.reset_hw(hw); 3333 3334 /* make sure the NVM is good , i211/i210 parts can have special NVM 3335 * that doesn't contain a checksum 3336 */ 3337 switch (hw->mac.type) { 3338 case e1000_i210: 3339 case e1000_i211: 3340 if (igb_get_flash_presence_i210(hw)) { 3341 if (hw->nvm.ops.validate(hw) < 0) { 3342 dev_err(&pdev->dev, 3343 "The NVM Checksum Is Not Valid\n"); 3344 err = -EIO; 3345 goto err_eeprom; 3346 } 3347 } 3348 break; 3349 default: 3350 if (hw->nvm.ops.validate(hw) < 0) { 3351 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3352 err = -EIO; 3353 goto err_eeprom; 3354 } 3355 break; 3356 } 3357 3358 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3359 /* copy the MAC address out of the NVM */ 3360 if (hw->mac.ops.read_mac_addr(hw)) 3361 dev_err(&pdev->dev, "NVM Read Error\n"); 3362 } 3363 3364 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3365 3366 if (!is_valid_ether_addr(netdev->dev_addr)) { 3367 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3368 err = -EIO; 3369 goto err_eeprom; 3370 } 3371 3372 igb_set_default_mac_filter(adapter); 3373 3374 /* get firmware version for ethtool -i */ 3375 igb_set_fw_version(adapter); 3376 3377 /* configure RXPBSIZE and TXPBSIZE */ 3378 if (hw->mac.type == e1000_i210) { 3379 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3380 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3381 } 3382 3383 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3384 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3385 3386 INIT_WORK(&adapter->reset_task, igb_reset_task); 3387 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3388 3389 /* Initialize link properties that are user-changeable */ 3390 adapter->fc_autoneg = true; 3391 hw->mac.autoneg = true; 3392 hw->phy.autoneg_advertised = 0x2f; 3393 3394 hw->fc.requested_mode = e1000_fc_default; 3395 hw->fc.current_mode = e1000_fc_default; 3396 3397 igb_validate_mdi_setting(hw); 3398 3399 /* By default, support wake on port A */ 3400 if (hw->bus.func == 0) 3401 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3402 3403 /* Check the NVM for wake support on non-port A ports */ 3404 if (hw->mac.type >= e1000_82580) 3405 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3406 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3407 &eeprom_data); 3408 else if (hw->bus.func == 1) 3409 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3410 3411 if (eeprom_data & IGB_EEPROM_APME) 3412 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3413 3414 /* now that we have the eeprom settings, apply the special cases where 3415 * the eeprom may be wrong or the board simply won't support wake on 3416 * lan on a particular port 3417 */ 3418 switch (pdev->device) { 3419 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3420 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3421 break; 3422 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3423 case E1000_DEV_ID_82576_FIBER: 3424 case E1000_DEV_ID_82576_SERDES: 3425 /* Wake events only supported on port A for dual fiber 3426 * regardless of eeprom setting 3427 */ 3428 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3429 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3430 break; 3431 case E1000_DEV_ID_82576_QUAD_COPPER: 3432 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3433 /* if quad port adapter, disable WoL on all but port A */ 3434 if (global_quad_port_a != 0) 3435 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3436 else 3437 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3438 /* Reset for multiple quad port adapters */ 3439 if (++global_quad_port_a == 4) 3440 global_quad_port_a = 0; 3441 break; 3442 default: 3443 /* If the device can't wake, don't set software support */ 3444 if (!device_can_wakeup(&adapter->pdev->dev)) 3445 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3446 } 3447 3448 /* initialize the wol settings based on the eeprom settings */ 3449 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3450 adapter->wol |= E1000_WUFC_MAG; 3451 3452 /* Some vendors want WoL disabled by default, but still supported */ 3453 if ((hw->mac.type == e1000_i350) && 3454 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3455 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3456 adapter->wol = 0; 3457 } 3458 3459 /* Some vendors want the ability to Use the EEPROM setting as 3460 * enable/disable only, and not for capability 3461 */ 3462 if (((hw->mac.type == e1000_i350) || 3463 (hw->mac.type == e1000_i354)) && 3464 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3465 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3466 adapter->wol = 0; 3467 } 3468 if (hw->mac.type == e1000_i350) { 3469 if (((pdev->subsystem_device == 0x5001) || 3470 (pdev->subsystem_device == 0x5002)) && 3471 (hw->bus.func == 0)) { 3472 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3473 adapter->wol = 0; 3474 } 3475 if (pdev->subsystem_device == 0x1F52) 3476 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3477 } 3478 3479 device_set_wakeup_enable(&adapter->pdev->dev, 3480 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3481 3482 /* reset the hardware with the new settings */ 3483 igb_reset(adapter); 3484 3485 /* Init the I2C interface */ 3486 err = igb_init_i2c(adapter); 3487 if (err) { 3488 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3489 goto err_eeprom; 3490 } 3491 3492 /* let the f/w know that the h/w is now under the control of the 3493 * driver. 3494 */ 3495 igb_get_hw_control(adapter); 3496 3497 strcpy(netdev->name, "eth%d"); 3498 err = register_netdev(netdev); 3499 if (err) 3500 goto err_register; 3501 3502 /* carrier off reporting is important to ethtool even BEFORE open */ 3503 netif_carrier_off(netdev); 3504 3505#ifdef CONFIG_IGB_DCA 3506 if (dca_add_requester(&pdev->dev) == 0) { 3507 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3508 dev_info(&pdev->dev, "DCA enabled\n"); 3509 igb_setup_dca(adapter); 3510 } 3511 3512#endif 3513#ifdef CONFIG_IGB_HWMON 3514 /* Initialize the thermal sensor on i350 devices. */ 3515 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3516 u16 ets_word; 3517 3518 /* Read the NVM to determine if this i350 device supports an 3519 * external thermal sensor. 3520 */ 3521 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3522 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3523 adapter->ets = true; 3524 else 3525 adapter->ets = false; 3526 if (igb_sysfs_init(adapter)) 3527 dev_err(&pdev->dev, 3528 "failed to allocate sysfs resources\n"); 3529 } else { 3530 adapter->ets = false; 3531 } 3532#endif 3533 /* Check if Media Autosense is enabled */ 3534 adapter->ei = *ei; 3535 if (hw->dev_spec._82575.mas_capable) 3536 igb_init_mas(adapter); 3537 3538 /* do hw tstamp init after resetting */ 3539 igb_ptp_init(adapter); 3540 3541 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3542 /* print bus type/speed/width info, not applicable to i354 */ 3543 if (hw->mac.type != e1000_i354) { 3544 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3545 netdev->name, 3546 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3547 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3548 "unknown"), 3549 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3550 "Width x4" : 3551 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3552 "Width x2" : 3553 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3554 "Width x1" : "unknown"), netdev->dev_addr); 3555 } 3556 3557 if ((hw->mac.type == e1000_82576 && 3558 rd32(E1000_EECD) & E1000_EECD_PRES) || 3559 (hw->mac.type >= e1000_i210 || 3560 igb_get_flash_presence_i210(hw))) { 3561 ret_val = igb_read_part_string(hw, part_str, 3562 E1000_PBANUM_LENGTH); 3563 } else { 3564 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3565 } 3566 3567 if (ret_val) 3568 strcpy(part_str, "Unknown"); 3569 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3570 dev_info(&pdev->dev, 3571 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3572 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3573 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3574 adapter->num_rx_queues, adapter->num_tx_queues); 3575 if (hw->phy.media_type == e1000_media_type_copper) { 3576 switch (hw->mac.type) { 3577 case e1000_i350: 3578 case e1000_i210: 3579 case e1000_i211: 3580 /* Enable EEE for internal copper PHY devices */ 3581 err = igb_set_eee_i350(hw, true, true); 3582 if ((!err) && 3583 (!hw->dev_spec._82575.eee_disable)) { 3584 adapter->eee_advert = 3585 MDIO_EEE_100TX | MDIO_EEE_1000T; 3586 adapter->flags |= IGB_FLAG_EEE; 3587 } 3588 break; 3589 case e1000_i354: 3590 if ((rd32(E1000_CTRL_EXT) & 3591 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3592 err = igb_set_eee_i354(hw, true, true); 3593 if ((!err) && 3594 (!hw->dev_spec._82575.eee_disable)) { 3595 adapter->eee_advert = 3596 MDIO_EEE_100TX | MDIO_EEE_1000T; 3597 adapter->flags |= IGB_FLAG_EEE; 3598 } 3599 } 3600 break; 3601 default: 3602 break; 3603 } 3604 } 3605 3606 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3607 3608 pm_runtime_put_noidle(&pdev->dev); 3609 return 0; 3610 3611err_register: 3612 igb_release_hw_control(adapter); 3613 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3614err_eeprom: 3615 if (!igb_check_reset_block(hw)) 3616 igb_reset_phy(hw); 3617 3618 if (hw->flash_address) 3619 iounmap(hw->flash_address); 3620err_sw_init: 3621 kfree(adapter->mac_table); 3622 kfree(adapter->shadow_vfta); 3623 igb_clear_interrupt_scheme(adapter); 3624#ifdef CONFIG_PCI_IOV 3625 igb_disable_sriov(pdev); 3626#endif 3627 pci_iounmap(pdev, adapter->io_addr); 3628err_ioremap: 3629 free_netdev(netdev); 3630err_alloc_etherdev: 3631 pci_disable_pcie_error_reporting(pdev); 3632 pci_release_mem_regions(pdev); 3633err_pci_reg: 3634err_dma: 3635 pci_disable_device(pdev); 3636 return err; 3637} 3638 3639#ifdef CONFIG_PCI_IOV 3640static int igb_disable_sriov(struct pci_dev *pdev) 3641{ 3642 struct net_device *netdev = pci_get_drvdata(pdev); 3643 struct igb_adapter *adapter = netdev_priv(netdev); 3644 struct e1000_hw *hw = &adapter->hw; 3645 unsigned long flags; 3646 3647 /* reclaim resources allocated to VFs */ 3648 if (adapter->vf_data) { 3649 /* disable iov and allow time for transactions to clear */ 3650 if (pci_vfs_assigned(pdev)) { 3651 dev_warn(&pdev->dev, 3652 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3653 return -EPERM; 3654 } else { 3655 pci_disable_sriov(pdev); 3656 msleep(500); 3657 } 3658 spin_lock_irqsave(&adapter->vfs_lock, flags); 3659 kfree(adapter->vf_mac_list); 3660 adapter->vf_mac_list = NULL; 3661 kfree(adapter->vf_data); 3662 adapter->vf_data = NULL; 3663 adapter->vfs_allocated_count = 0; 3664 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3665 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3666 wrfl(); 3667 msleep(100); 3668 dev_info(&pdev->dev, "IOV Disabled\n"); 3669 3670 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3671 adapter->flags |= IGB_FLAG_DMAC; 3672 } 3673 3674 return 0; 3675} 3676 3677static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3678{ 3679 struct net_device *netdev = pci_get_drvdata(pdev); 3680 struct igb_adapter *adapter = netdev_priv(netdev); 3681 int old_vfs = pci_num_vf(pdev); 3682 struct vf_mac_filter *mac_list; 3683 int err = 0; 3684 int num_vf_mac_filters, i; 3685 3686 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3687 err = -EPERM; 3688 goto out; 3689 } 3690 if (!num_vfs) 3691 goto out; 3692 3693 if (old_vfs) { 3694 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3695 old_vfs, max_vfs); 3696 adapter->vfs_allocated_count = old_vfs; 3697 } else 3698 adapter->vfs_allocated_count = num_vfs; 3699 3700 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3701 sizeof(struct vf_data_storage), GFP_KERNEL); 3702 3703 /* if allocation failed then we do not support SR-IOV */ 3704 if (!adapter->vf_data) { 3705 adapter->vfs_allocated_count = 0; 3706 err = -ENOMEM; 3707 goto out; 3708 } 3709 3710 /* Due to the limited number of RAR entries calculate potential 3711 * number of MAC filters available for the VFs. Reserve entries 3712 * for PF default MAC, PF MAC filters and at least one RAR entry 3713 * for each VF for VF MAC. 3714 */ 3715 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3716 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3717 adapter->vfs_allocated_count); 3718 3719 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3720 sizeof(struct vf_mac_filter), 3721 GFP_KERNEL); 3722 3723 mac_list = adapter->vf_mac_list; 3724 INIT_LIST_HEAD(&adapter->vf_macs.l); 3725 3726 if (adapter->vf_mac_list) { 3727 /* Initialize list of VF MAC filters */ 3728 for (i = 0; i < num_vf_mac_filters; i++) { 3729 mac_list->vf = -1; 3730 mac_list->free = true; 3731 list_add(&mac_list->l, &adapter->vf_macs.l); 3732 mac_list++; 3733 } 3734 } else { 3735 /* If we could not allocate memory for the VF MAC filters 3736 * we can continue without this feature but warn user. 3737 */ 3738 dev_err(&pdev->dev, 3739 "Unable to allocate memory for VF MAC filter list\n"); 3740 } 3741 3742 /* only call pci_enable_sriov() if no VFs are allocated already */ 3743 if (!old_vfs) { 3744 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3745 if (err) 3746 goto err_out; 3747 } 3748 dev_info(&pdev->dev, "%d VFs allocated\n", 3749 adapter->vfs_allocated_count); 3750 for (i = 0; i < adapter->vfs_allocated_count; i++) 3751 igb_vf_configure(adapter, i); 3752 3753 /* DMA Coalescing is not supported in IOV mode. */ 3754 adapter->flags &= ~IGB_FLAG_DMAC; 3755 goto out; 3756 3757err_out: 3758 kfree(adapter->vf_mac_list); 3759 adapter->vf_mac_list = NULL; 3760 kfree(adapter->vf_data); 3761 adapter->vf_data = NULL; 3762 adapter->vfs_allocated_count = 0; 3763out: 3764 return err; 3765} 3766 3767#endif 3768/** 3769 * igb_remove_i2c - Cleanup I2C interface 3770 * @adapter: pointer to adapter structure 3771 **/ 3772static void igb_remove_i2c(struct igb_adapter *adapter) 3773{ 3774 /* free the adapter bus structure */ 3775 i2c_del_adapter(&adapter->i2c_adap); 3776} 3777 3778/** 3779 * igb_remove - Device Removal Routine 3780 * @pdev: PCI device information struct 3781 * 3782 * igb_remove is called by the PCI subsystem to alert the driver 3783 * that it should release a PCI device. The could be caused by a 3784 * Hot-Plug event, or because the driver is going to be removed from 3785 * memory. 3786 **/ 3787static void igb_remove(struct pci_dev *pdev) 3788{ 3789 struct net_device *netdev = pci_get_drvdata(pdev); 3790 struct igb_adapter *adapter = netdev_priv(netdev); 3791 struct e1000_hw *hw = &adapter->hw; 3792 3793 pm_runtime_get_noresume(&pdev->dev); 3794#ifdef CONFIG_IGB_HWMON 3795 igb_sysfs_exit(adapter); 3796#endif 3797 igb_remove_i2c(adapter); 3798 igb_ptp_stop(adapter); 3799 /* The watchdog timer may be rescheduled, so explicitly 3800 * disable watchdog from being rescheduled. 3801 */ 3802 set_bit(__IGB_DOWN, &adapter->state); 3803 del_timer_sync(&adapter->watchdog_timer); 3804 del_timer_sync(&adapter->phy_info_timer); 3805 3806 cancel_work_sync(&adapter->reset_task); 3807 cancel_work_sync(&adapter->watchdog_task); 3808 3809#ifdef CONFIG_IGB_DCA 3810 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3811 dev_info(&pdev->dev, "DCA disabled\n"); 3812 dca_remove_requester(&pdev->dev); 3813 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3814 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3815 } 3816#endif 3817 3818 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3819 * would have already happened in close and is redundant. 3820 */ 3821 igb_release_hw_control(adapter); 3822 3823#ifdef CONFIG_PCI_IOV 3824 igb_disable_sriov(pdev); 3825#endif 3826 3827 unregister_netdev(netdev); 3828 3829 igb_clear_interrupt_scheme(adapter); 3830 3831 pci_iounmap(pdev, adapter->io_addr); 3832 if (hw->flash_address) 3833 iounmap(hw->flash_address); 3834 pci_release_mem_regions(pdev); 3835 3836 kfree(adapter->mac_table); 3837 kfree(adapter->shadow_vfta); 3838 free_netdev(netdev); 3839 3840 pci_disable_pcie_error_reporting(pdev); 3841 3842 pci_disable_device(pdev); 3843} 3844 3845/** 3846 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3847 * @adapter: board private structure to initialize 3848 * 3849 * This function initializes the vf specific data storage and then attempts to 3850 * allocate the VFs. The reason for ordering it this way is because it is much 3851 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3852 * the memory for the VFs. 3853 **/ 3854static void igb_probe_vfs(struct igb_adapter *adapter) 3855{ 3856#ifdef CONFIG_PCI_IOV 3857 struct pci_dev *pdev = adapter->pdev; 3858 struct e1000_hw *hw = &adapter->hw; 3859 3860 /* Virtualization features not supported on i210 and 82580 family. */ 3861 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3862 (hw->mac.type == e1000_82580)) 3863 return; 3864 3865 /* Of the below we really only want the effect of getting 3866 * IGB_FLAG_HAS_MSIX set (if available), without which 3867 * igb_enable_sriov() has no effect. 3868 */ 3869 igb_set_interrupt_capability(adapter, true); 3870 igb_reset_interrupt_capability(adapter); 3871 3872 pci_sriov_set_totalvfs(pdev, 7); 3873 igb_enable_sriov(pdev, max_vfs); 3874 3875#endif /* CONFIG_PCI_IOV */ 3876} 3877 3878unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3879{ 3880 struct e1000_hw *hw = &adapter->hw; 3881 unsigned int max_rss_queues; 3882 3883 /* Determine the maximum number of RSS queues supported. */ 3884 switch (hw->mac.type) { 3885 case e1000_i211: 3886 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3887 break; 3888 case e1000_82575: 3889 case e1000_i210: 3890 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3891 break; 3892 case e1000_i350: 3893 /* I350 cannot do RSS and SR-IOV at the same time */ 3894 if (!!adapter->vfs_allocated_count) { 3895 max_rss_queues = 1; 3896 break; 3897 } 3898 fallthrough; 3899 case e1000_82576: 3900 if (!!adapter->vfs_allocated_count) { 3901 max_rss_queues = 2; 3902 break; 3903 } 3904 fallthrough; 3905 case e1000_82580: 3906 case e1000_i354: 3907 default: 3908 max_rss_queues = IGB_MAX_RX_QUEUES; 3909 break; 3910 } 3911 3912 return max_rss_queues; 3913} 3914 3915static void igb_init_queue_configuration(struct igb_adapter *adapter) 3916{ 3917 u32 max_rss_queues; 3918 3919 max_rss_queues = igb_get_max_rss_queues(adapter); 3920 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3921 3922 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3923} 3924 3925void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3926 const u32 max_rss_queues) 3927{ 3928 struct e1000_hw *hw = &adapter->hw; 3929 3930 /* Determine if we need to pair queues. */ 3931 switch (hw->mac.type) { 3932 case e1000_82575: 3933 case e1000_i211: 3934 /* Device supports enough interrupts without queue pairing. */ 3935 break; 3936 case e1000_82576: 3937 case e1000_82580: 3938 case e1000_i350: 3939 case e1000_i354: 3940 case e1000_i210: 3941 default: 3942 /* If rss_queues > half of max_rss_queues, pair the queues in 3943 * order to conserve interrupts due to limited supply. 3944 */ 3945 if (adapter->rss_queues > (max_rss_queues / 2)) 3946 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3947 else 3948 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3949 break; 3950 } 3951} 3952 3953/** 3954 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3955 * @adapter: board private structure to initialize 3956 * 3957 * igb_sw_init initializes the Adapter private data structure. 3958 * Fields are initialized based on PCI device information and 3959 * OS network device settings (MTU size). 3960 **/ 3961static int igb_sw_init(struct igb_adapter *adapter) 3962{ 3963 struct e1000_hw *hw = &adapter->hw; 3964 struct net_device *netdev = adapter->netdev; 3965 struct pci_dev *pdev = adapter->pdev; 3966 3967 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3968 3969 /* set default ring sizes */ 3970 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3971 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3972 3973 /* set default ITR values */ 3974 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3975 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3976 3977 /* set default work limits */ 3978 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3979 3980 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3981 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3982 3983 spin_lock_init(&adapter->nfc_lock); 3984 spin_lock_init(&adapter->stats64_lock); 3985 3986 /* init spinlock to avoid concurrency of VF resources */ 3987 spin_lock_init(&adapter->vfs_lock); 3988#ifdef CONFIG_PCI_IOV 3989 switch (hw->mac.type) { 3990 case e1000_82576: 3991 case e1000_i350: 3992 if (max_vfs > 7) { 3993 dev_warn(&pdev->dev, 3994 "Maximum of 7 VFs per PF, using max\n"); 3995 max_vfs = adapter->vfs_allocated_count = 7; 3996 } else 3997 adapter->vfs_allocated_count = max_vfs; 3998 if (adapter->vfs_allocated_count) 3999 dev_warn(&pdev->dev, 4000 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4001 break; 4002 default: 4003 break; 4004 } 4005#endif /* CONFIG_PCI_IOV */ 4006 4007 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4008 adapter->flags |= IGB_FLAG_HAS_MSIX; 4009 4010 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4011 sizeof(struct igb_mac_addr), 4012 GFP_KERNEL); 4013 if (!adapter->mac_table) 4014 return -ENOMEM; 4015 4016 igb_probe_vfs(adapter); 4017 4018 igb_init_queue_configuration(adapter); 4019 4020 /* Setup and initialize a copy of the hw vlan table array */ 4021 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4022 GFP_KERNEL); 4023 if (!adapter->shadow_vfta) 4024 return -ENOMEM; 4025 4026 /* This call may decrease the number of queues */ 4027 if (igb_init_interrupt_scheme(adapter, true)) { 4028 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4029 return -ENOMEM; 4030 } 4031 4032 /* Explicitly disable IRQ since the NIC can be in any state. */ 4033 igb_irq_disable(adapter); 4034 4035 if (hw->mac.type >= e1000_i350) 4036 adapter->flags &= ~IGB_FLAG_DMAC; 4037 4038 set_bit(__IGB_DOWN, &adapter->state); 4039 return 0; 4040} 4041 4042/** 4043 * igb_open - Called when a network interface is made active 4044 * @netdev: network interface device structure 4045 * @resuming: indicates whether we are in a resume call 4046 * 4047 * Returns 0 on success, negative value on failure 4048 * 4049 * The open entry point is called when a network interface is made 4050 * active by the system (IFF_UP). At this point all resources needed 4051 * for transmit and receive operations are allocated, the interrupt 4052 * handler is registered with the OS, the watchdog timer is started, 4053 * and the stack is notified that the interface is ready. 4054 **/ 4055static int __igb_open(struct net_device *netdev, bool resuming) 4056{ 4057 struct igb_adapter *adapter = netdev_priv(netdev); 4058 struct e1000_hw *hw = &adapter->hw; 4059 struct pci_dev *pdev = adapter->pdev; 4060 int err; 4061 int i; 4062 4063 /* disallow open during test */ 4064 if (test_bit(__IGB_TESTING, &adapter->state)) { 4065 WARN_ON(resuming); 4066 return -EBUSY; 4067 } 4068 4069 if (!resuming) 4070 pm_runtime_get_sync(&pdev->dev); 4071 4072 netif_carrier_off(netdev); 4073 4074 /* allocate transmit descriptors */ 4075 err = igb_setup_all_tx_resources(adapter); 4076 if (err) 4077 goto err_setup_tx; 4078 4079 /* allocate receive descriptors */ 4080 err = igb_setup_all_rx_resources(adapter); 4081 if (err) 4082 goto err_setup_rx; 4083 4084 igb_power_up_link(adapter); 4085 4086 /* before we allocate an interrupt, we must be ready to handle it. 4087 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4088 * as soon as we call pci_request_irq, so we have to setup our 4089 * clean_rx handler before we do so. 4090 */ 4091 igb_configure(adapter); 4092 4093 err = igb_request_irq(adapter); 4094 if (err) 4095 goto err_req_irq; 4096 4097 /* Notify the stack of the actual queue counts. */ 4098 err = netif_set_real_num_tx_queues(adapter->netdev, 4099 adapter->num_tx_queues); 4100 if (err) 4101 goto err_set_queues; 4102 4103 err = netif_set_real_num_rx_queues(adapter->netdev, 4104 adapter->num_rx_queues); 4105 if (err) 4106 goto err_set_queues; 4107 4108 /* From here on the code is the same as igb_up() */ 4109 clear_bit(__IGB_DOWN, &adapter->state); 4110 4111 for (i = 0; i < adapter->num_q_vectors; i++) 4112 napi_enable(&(adapter->q_vector[i]->napi)); 4113 4114 /* Clear any pending interrupts. */ 4115 rd32(E1000_TSICR); 4116 rd32(E1000_ICR); 4117 4118 igb_irq_enable(adapter); 4119 4120 /* notify VFs that reset has been completed */ 4121 if (adapter->vfs_allocated_count) { 4122 u32 reg_data = rd32(E1000_CTRL_EXT); 4123 4124 reg_data |= E1000_CTRL_EXT_PFRSTD; 4125 wr32(E1000_CTRL_EXT, reg_data); 4126 } 4127 4128 netif_tx_start_all_queues(netdev); 4129 4130 if (!resuming) 4131 pm_runtime_put(&pdev->dev); 4132 4133 /* start the watchdog. */ 4134 hw->mac.get_link_status = 1; 4135 schedule_work(&adapter->watchdog_task); 4136 4137 return 0; 4138 4139err_set_queues: 4140 igb_free_irq(adapter); 4141err_req_irq: 4142 igb_release_hw_control(adapter); 4143 igb_power_down_link(adapter); 4144 igb_free_all_rx_resources(adapter); 4145err_setup_rx: 4146 igb_free_all_tx_resources(adapter); 4147err_setup_tx: 4148 igb_reset(adapter); 4149 if (!resuming) 4150 pm_runtime_put(&pdev->dev); 4151 4152 return err; 4153} 4154 4155int igb_open(struct net_device *netdev) 4156{ 4157 return __igb_open(netdev, false); 4158} 4159 4160/** 4161 * igb_close - Disables a network interface 4162 * @netdev: network interface device structure 4163 * @suspending: indicates we are in a suspend call 4164 * 4165 * Returns 0, this is not allowed to fail 4166 * 4167 * The close entry point is called when an interface is de-activated 4168 * by the OS. The hardware is still under the driver's control, but 4169 * needs to be disabled. A global MAC reset is issued to stop the 4170 * hardware, and all transmit and receive resources are freed. 4171 **/ 4172static int __igb_close(struct net_device *netdev, bool suspending) 4173{ 4174 struct igb_adapter *adapter = netdev_priv(netdev); 4175 struct pci_dev *pdev = adapter->pdev; 4176 4177 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4178 4179 if (!suspending) 4180 pm_runtime_get_sync(&pdev->dev); 4181 4182 igb_down(adapter); 4183 igb_free_irq(adapter); 4184 4185 igb_free_all_tx_resources(adapter); 4186 igb_free_all_rx_resources(adapter); 4187 4188 if (!suspending) 4189 pm_runtime_put_sync(&pdev->dev); 4190 return 0; 4191} 4192 4193int igb_close(struct net_device *netdev) 4194{ 4195 if (netif_device_present(netdev) || netdev->dismantle) 4196 return __igb_close(netdev, false); 4197 return 0; 4198} 4199 4200/** 4201 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4202 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4203 * 4204 * Return 0 on success, negative on failure 4205 **/ 4206int igb_setup_tx_resources(struct igb_ring *tx_ring) 4207{ 4208 struct device *dev = tx_ring->dev; 4209 int size; 4210 4211 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4212 4213 tx_ring->tx_buffer_info = vmalloc(size); 4214 if (!tx_ring->tx_buffer_info) 4215 goto err; 4216 4217 /* round up to nearest 4K */ 4218 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4219 tx_ring->size = ALIGN(tx_ring->size, 4096); 4220 4221 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4222 &tx_ring->dma, GFP_KERNEL); 4223 if (!tx_ring->desc) 4224 goto err; 4225 4226 tx_ring->next_to_use = 0; 4227 tx_ring->next_to_clean = 0; 4228 4229 return 0; 4230 4231err: 4232 vfree(tx_ring->tx_buffer_info); 4233 tx_ring->tx_buffer_info = NULL; 4234 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4235 return -ENOMEM; 4236} 4237 4238/** 4239 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4240 * (Descriptors) for all queues 4241 * @adapter: board private structure 4242 * 4243 * Return 0 on success, negative on failure 4244 **/ 4245static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4246{ 4247 struct pci_dev *pdev = adapter->pdev; 4248 int i, err = 0; 4249 4250 for (i = 0; i < adapter->num_tx_queues; i++) { 4251 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4252 if (err) { 4253 dev_err(&pdev->dev, 4254 "Allocation for Tx Queue %u failed\n", i); 4255 for (i--; i >= 0; i--) 4256 igb_free_tx_resources(adapter->tx_ring[i]); 4257 break; 4258 } 4259 } 4260 4261 return err; 4262} 4263 4264/** 4265 * igb_setup_tctl - configure the transmit control registers 4266 * @adapter: Board private structure 4267 **/ 4268void igb_setup_tctl(struct igb_adapter *adapter) 4269{ 4270 struct e1000_hw *hw = &adapter->hw; 4271 u32 tctl; 4272 4273 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4274 wr32(E1000_TXDCTL(0), 0); 4275 4276 /* Program the Transmit Control Register */ 4277 tctl = rd32(E1000_TCTL); 4278 tctl &= ~E1000_TCTL_CT; 4279 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4280 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4281 4282 igb_config_collision_dist(hw); 4283 4284 /* Enable transmits */ 4285 tctl |= E1000_TCTL_EN; 4286 4287 wr32(E1000_TCTL, tctl); 4288} 4289 4290/** 4291 * igb_configure_tx_ring - Configure transmit ring after Reset 4292 * @adapter: board private structure 4293 * @ring: tx ring to configure 4294 * 4295 * Configure a transmit ring after a reset. 4296 **/ 4297void igb_configure_tx_ring(struct igb_adapter *adapter, 4298 struct igb_ring *ring) 4299{ 4300 struct e1000_hw *hw = &adapter->hw; 4301 u32 txdctl = 0; 4302 u64 tdba = ring->dma; 4303 int reg_idx = ring->reg_idx; 4304 4305 wr32(E1000_TDLEN(reg_idx), 4306 ring->count * sizeof(union e1000_adv_tx_desc)); 4307 wr32(E1000_TDBAL(reg_idx), 4308 tdba & 0x00000000ffffffffULL); 4309 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4310 4311 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4312 wr32(E1000_TDH(reg_idx), 0); 4313 writel(0, ring->tail); 4314 4315 txdctl |= IGB_TX_PTHRESH; 4316 txdctl |= IGB_TX_HTHRESH << 8; 4317 txdctl |= IGB_TX_WTHRESH << 16; 4318 4319 /* reinitialize tx_buffer_info */ 4320 memset(ring->tx_buffer_info, 0, 4321 sizeof(struct igb_tx_buffer) * ring->count); 4322 4323 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4324 wr32(E1000_TXDCTL(reg_idx), txdctl); 4325} 4326 4327/** 4328 * igb_configure_tx - Configure transmit Unit after Reset 4329 * @adapter: board private structure 4330 * 4331 * Configure the Tx unit of the MAC after a reset. 4332 **/ 4333static void igb_configure_tx(struct igb_adapter *adapter) 4334{ 4335 struct e1000_hw *hw = &adapter->hw; 4336 int i; 4337 4338 /* disable the queues */ 4339 for (i = 0; i < adapter->num_tx_queues; i++) 4340 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4341 4342 wrfl(); 4343 usleep_range(10000, 20000); 4344 4345 for (i = 0; i < adapter->num_tx_queues; i++) 4346 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4347} 4348 4349/** 4350 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4351 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4352 * 4353 * Returns 0 on success, negative on failure 4354 **/ 4355int igb_setup_rx_resources(struct igb_ring *rx_ring) 4356{ 4357 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4358 struct device *dev = rx_ring->dev; 4359 int size; 4360 4361 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4362 4363 rx_ring->rx_buffer_info = vmalloc(size); 4364 if (!rx_ring->rx_buffer_info) 4365 goto err; 4366 4367 /* Round up to nearest 4K */ 4368 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4369 rx_ring->size = ALIGN(rx_ring->size, 4096); 4370 4371 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4372 &rx_ring->dma, GFP_KERNEL); 4373 if (!rx_ring->desc) 4374 goto err; 4375 4376 rx_ring->next_to_alloc = 0; 4377 rx_ring->next_to_clean = 0; 4378 rx_ring->next_to_use = 0; 4379 4380 rx_ring->xdp_prog = adapter->xdp_prog; 4381 4382 /* XDP RX-queue info */ 4383 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4384 rx_ring->queue_index) < 0) 4385 goto err; 4386 4387 return 0; 4388 4389err: 4390 vfree(rx_ring->rx_buffer_info); 4391 rx_ring->rx_buffer_info = NULL; 4392 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4393 return -ENOMEM; 4394} 4395 4396/** 4397 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4398 * (Descriptors) for all queues 4399 * @adapter: board private structure 4400 * 4401 * Return 0 on success, negative on failure 4402 **/ 4403static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4404{ 4405 struct pci_dev *pdev = adapter->pdev; 4406 int i, err = 0; 4407 4408 for (i = 0; i < adapter->num_rx_queues; i++) { 4409 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4410 if (err) { 4411 dev_err(&pdev->dev, 4412 "Allocation for Rx Queue %u failed\n", i); 4413 for (i--; i >= 0; i--) 4414 igb_free_rx_resources(adapter->rx_ring[i]); 4415 break; 4416 } 4417 } 4418 4419 return err; 4420} 4421 4422/** 4423 * igb_setup_mrqc - configure the multiple receive queue control registers 4424 * @adapter: Board private structure 4425 **/ 4426static void igb_setup_mrqc(struct igb_adapter *adapter) 4427{ 4428 struct e1000_hw *hw = &adapter->hw; 4429 u32 mrqc, rxcsum; 4430 u32 j, num_rx_queues; 4431 u32 rss_key[10]; 4432 4433 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4434 for (j = 0; j < 10; j++) 4435 wr32(E1000_RSSRK(j), rss_key[j]); 4436 4437 num_rx_queues = adapter->rss_queues; 4438 4439 switch (hw->mac.type) { 4440 case e1000_82576: 4441 /* 82576 supports 2 RSS queues for SR-IOV */ 4442 if (adapter->vfs_allocated_count) 4443 num_rx_queues = 2; 4444 break; 4445 default: 4446 break; 4447 } 4448 4449 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4450 for (j = 0; j < IGB_RETA_SIZE; j++) 4451 adapter->rss_indir_tbl[j] = 4452 (j * num_rx_queues) / IGB_RETA_SIZE; 4453 adapter->rss_indir_tbl_init = num_rx_queues; 4454 } 4455 igb_write_rss_indir_tbl(adapter); 4456 4457 /* Disable raw packet checksumming so that RSS hash is placed in 4458 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4459 * offloads as they are enabled by default 4460 */ 4461 rxcsum = rd32(E1000_RXCSUM); 4462 rxcsum |= E1000_RXCSUM_PCSD; 4463 4464 if (adapter->hw.mac.type >= e1000_82576) 4465 /* Enable Receive Checksum Offload for SCTP */ 4466 rxcsum |= E1000_RXCSUM_CRCOFL; 4467 4468 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4469 wr32(E1000_RXCSUM, rxcsum); 4470 4471 /* Generate RSS hash based on packet types, TCP/UDP 4472 * port numbers and/or IPv4/v6 src and dst addresses 4473 */ 4474 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4475 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4476 E1000_MRQC_RSS_FIELD_IPV6 | 4477 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4478 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4479 4480 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4481 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4482 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4483 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4484 4485 /* If VMDq is enabled then we set the appropriate mode for that, else 4486 * we default to RSS so that an RSS hash is calculated per packet even 4487 * if we are only using one queue 4488 */ 4489 if (adapter->vfs_allocated_count) { 4490 if (hw->mac.type > e1000_82575) { 4491 /* Set the default pool for the PF's first queue */ 4492 u32 vtctl = rd32(E1000_VT_CTL); 4493 4494 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4495 E1000_VT_CTL_DISABLE_DEF_POOL); 4496 vtctl |= adapter->vfs_allocated_count << 4497 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4498 wr32(E1000_VT_CTL, vtctl); 4499 } 4500 if (adapter->rss_queues > 1) 4501 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4502 else 4503 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4504 } else { 4505 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4506 } 4507 igb_vmm_control(adapter); 4508 4509 wr32(E1000_MRQC, mrqc); 4510} 4511 4512/** 4513 * igb_setup_rctl - configure the receive control registers 4514 * @adapter: Board private structure 4515 **/ 4516void igb_setup_rctl(struct igb_adapter *adapter) 4517{ 4518 struct e1000_hw *hw = &adapter->hw; 4519 u32 rctl; 4520 4521 rctl = rd32(E1000_RCTL); 4522 4523 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4524 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4525 4526 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4527 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4528 4529 /* enable stripping of CRC. It's unlikely this will break BMC 4530 * redirection as it did with e1000. Newer features require 4531 * that the HW strips the CRC. 4532 */ 4533 rctl |= E1000_RCTL_SECRC; 4534 4535 /* disable store bad packets and clear size bits. */ 4536 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4537 4538 /* enable LPE to allow for reception of jumbo frames */ 4539 rctl |= E1000_RCTL_LPE; 4540 4541 /* disable queue 0 to prevent tail write w/o re-config */ 4542 wr32(E1000_RXDCTL(0), 0); 4543 4544 /* Attention!!! For SR-IOV PF driver operations you must enable 4545 * queue drop for all VF and PF queues to prevent head of line blocking 4546 * if an un-trusted VF does not provide descriptors to hardware. 4547 */ 4548 if (adapter->vfs_allocated_count) { 4549 /* set all queue drop enable bits */ 4550 wr32(E1000_QDE, ALL_QUEUES); 4551 } 4552 4553 /* This is useful for sniffing bad packets. */ 4554 if (adapter->netdev->features & NETIF_F_RXALL) { 4555 /* UPE and MPE will be handled by normal PROMISC logic 4556 * in e1000e_set_rx_mode 4557 */ 4558 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4559 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4560 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4561 4562 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4563 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4564 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4565 * and that breaks VLANs. 4566 */ 4567 } 4568 4569 wr32(E1000_RCTL, rctl); 4570} 4571 4572static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4573 int vfn) 4574{ 4575 struct e1000_hw *hw = &adapter->hw; 4576 u32 vmolr; 4577 4578 if (size > MAX_JUMBO_FRAME_SIZE) 4579 size = MAX_JUMBO_FRAME_SIZE; 4580 4581 vmolr = rd32(E1000_VMOLR(vfn)); 4582 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4583 vmolr |= size | E1000_VMOLR_LPE; 4584 wr32(E1000_VMOLR(vfn), vmolr); 4585 4586 return 0; 4587} 4588 4589static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4590 int vfn, bool enable) 4591{ 4592 struct e1000_hw *hw = &adapter->hw; 4593 u32 val, reg; 4594 4595 if (hw->mac.type < e1000_82576) 4596 return; 4597 4598 if (hw->mac.type == e1000_i350) 4599 reg = E1000_DVMOLR(vfn); 4600 else 4601 reg = E1000_VMOLR(vfn); 4602 4603 val = rd32(reg); 4604 if (enable) 4605 val |= E1000_VMOLR_STRVLAN; 4606 else 4607 val &= ~(E1000_VMOLR_STRVLAN); 4608 wr32(reg, val); 4609} 4610 4611static inline void igb_set_vmolr(struct igb_adapter *adapter, 4612 int vfn, bool aupe) 4613{ 4614 struct e1000_hw *hw = &adapter->hw; 4615 u32 vmolr; 4616 4617 /* This register exists only on 82576 and newer so if we are older then 4618 * we should exit and do nothing 4619 */ 4620 if (hw->mac.type < e1000_82576) 4621 return; 4622 4623 vmolr = rd32(E1000_VMOLR(vfn)); 4624 if (aupe) 4625 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4626 else 4627 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4628 4629 /* clear all bits that might not be set */ 4630 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4631 4632 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4633 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4634 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4635 * multicast packets 4636 */ 4637 if (vfn <= adapter->vfs_allocated_count) 4638 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4639 4640 wr32(E1000_VMOLR(vfn), vmolr); 4641} 4642 4643/** 4644 * igb_setup_srrctl - configure the split and replication receive control 4645 * registers 4646 * @adapter: Board private structure 4647 * @ring: receive ring to be configured 4648 **/ 4649void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4650{ 4651 struct e1000_hw *hw = &adapter->hw; 4652 int reg_idx = ring->reg_idx; 4653 u32 srrctl = 0; 4654 4655 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4656 if (ring_uses_large_buffer(ring)) 4657 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4658 else 4659 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4660 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4661 if (hw->mac.type >= e1000_82580) 4662 srrctl |= E1000_SRRCTL_TIMESTAMP; 4663 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4664 * queues and rx flow control is disabled 4665 */ 4666 if (adapter->vfs_allocated_count || 4667 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4668 adapter->num_rx_queues > 1)) 4669 srrctl |= E1000_SRRCTL_DROP_EN; 4670 4671 wr32(E1000_SRRCTL(reg_idx), srrctl); 4672} 4673 4674/** 4675 * igb_configure_rx_ring - Configure a receive ring after Reset 4676 * @adapter: board private structure 4677 * @ring: receive ring to be configured 4678 * 4679 * Configure the Rx unit of the MAC after a reset. 4680 **/ 4681void igb_configure_rx_ring(struct igb_adapter *adapter, 4682 struct igb_ring *ring) 4683{ 4684 struct e1000_hw *hw = &adapter->hw; 4685 union e1000_adv_rx_desc *rx_desc; 4686 u64 rdba = ring->dma; 4687 int reg_idx = ring->reg_idx; 4688 u32 rxdctl = 0; 4689 4690 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4691 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4692 MEM_TYPE_PAGE_SHARED, NULL)); 4693 4694 /* disable the queue */ 4695 wr32(E1000_RXDCTL(reg_idx), 0); 4696 4697 /* Set DMA base address registers */ 4698 wr32(E1000_RDBAL(reg_idx), 4699 rdba & 0x00000000ffffffffULL); 4700 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4701 wr32(E1000_RDLEN(reg_idx), 4702 ring->count * sizeof(union e1000_adv_rx_desc)); 4703 4704 /* initialize head and tail */ 4705 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4706 wr32(E1000_RDH(reg_idx), 0); 4707 writel(0, ring->tail); 4708 4709 /* set descriptor configuration */ 4710 igb_setup_srrctl(adapter, ring); 4711 4712 /* set filtering for VMDQ pools */ 4713 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4714 4715 rxdctl |= IGB_RX_PTHRESH; 4716 rxdctl |= IGB_RX_HTHRESH << 8; 4717 rxdctl |= IGB_RX_WTHRESH << 16; 4718 4719 /* initialize rx_buffer_info */ 4720 memset(ring->rx_buffer_info, 0, 4721 sizeof(struct igb_rx_buffer) * ring->count); 4722 4723 /* initialize Rx descriptor 0 */ 4724 rx_desc = IGB_RX_DESC(ring, 0); 4725 rx_desc->wb.upper.length = 0; 4726 4727 /* enable receive descriptor fetching */ 4728 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4729 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4730} 4731 4732static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4733 struct igb_ring *rx_ring) 4734{ 4735#if (PAGE_SIZE < 8192) 4736 struct e1000_hw *hw = &adapter->hw; 4737#endif 4738 4739 /* set build_skb and buffer size flags */ 4740 clear_ring_build_skb_enabled(rx_ring); 4741 clear_ring_uses_large_buffer(rx_ring); 4742 4743 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4744 return; 4745 4746 set_ring_build_skb_enabled(rx_ring); 4747 4748#if (PAGE_SIZE < 8192) 4749 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4750 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4751 set_ring_uses_large_buffer(rx_ring); 4752#endif 4753} 4754 4755/** 4756 * igb_configure_rx - Configure receive Unit after Reset 4757 * @adapter: board private structure 4758 * 4759 * Configure the Rx unit of the MAC after a reset. 4760 **/ 4761static void igb_configure_rx(struct igb_adapter *adapter) 4762{ 4763 int i; 4764 4765 /* set the correct pool for the PF default MAC address in entry 0 */ 4766 igb_set_default_mac_filter(adapter); 4767 4768 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4769 * the Base and Length of the Rx Descriptor Ring 4770 */ 4771 for (i = 0; i < adapter->num_rx_queues; i++) { 4772 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4773 4774 igb_set_rx_buffer_len(adapter, rx_ring); 4775 igb_configure_rx_ring(adapter, rx_ring); 4776 } 4777} 4778 4779/** 4780 * igb_free_tx_resources - Free Tx Resources per Queue 4781 * @tx_ring: Tx descriptor ring for a specific queue 4782 * 4783 * Free all transmit software resources 4784 **/ 4785void igb_free_tx_resources(struct igb_ring *tx_ring) 4786{ 4787 igb_clean_tx_ring(tx_ring); 4788 4789 vfree(tx_ring->tx_buffer_info); 4790 tx_ring->tx_buffer_info = NULL; 4791 4792 /* if not set, then don't free */ 4793 if (!tx_ring->desc) 4794 return; 4795 4796 dma_free_coherent(tx_ring->dev, tx_ring->size, 4797 tx_ring->desc, tx_ring->dma); 4798 4799 tx_ring->desc = NULL; 4800} 4801 4802/** 4803 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4804 * @adapter: board private structure 4805 * 4806 * Free all transmit software resources 4807 **/ 4808static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4809{ 4810 int i; 4811 4812 for (i = 0; i < adapter->num_tx_queues; i++) 4813 if (adapter->tx_ring[i]) 4814 igb_free_tx_resources(adapter->tx_ring[i]); 4815} 4816 4817/** 4818 * igb_clean_tx_ring - Free Tx Buffers 4819 * @tx_ring: ring to be cleaned 4820 **/ 4821static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4822{ 4823 u16 i = tx_ring->next_to_clean; 4824 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4825 4826 while (i != tx_ring->next_to_use) { 4827 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4828 4829 /* Free all the Tx ring sk_buffs or xdp frames */ 4830 if (tx_buffer->type == IGB_TYPE_SKB) 4831 dev_kfree_skb_any(tx_buffer->skb); 4832 else 4833 xdp_return_frame(tx_buffer->xdpf); 4834 4835 /* unmap skb header data */ 4836 dma_unmap_single(tx_ring->dev, 4837 dma_unmap_addr(tx_buffer, dma), 4838 dma_unmap_len(tx_buffer, len), 4839 DMA_TO_DEVICE); 4840 4841 /* check for eop_desc to determine the end of the packet */ 4842 eop_desc = tx_buffer->next_to_watch; 4843 tx_desc = IGB_TX_DESC(tx_ring, i); 4844 4845 /* unmap remaining buffers */ 4846 while (tx_desc != eop_desc) { 4847 tx_buffer++; 4848 tx_desc++; 4849 i++; 4850 if (unlikely(i == tx_ring->count)) { 4851 i = 0; 4852 tx_buffer = tx_ring->tx_buffer_info; 4853 tx_desc = IGB_TX_DESC(tx_ring, 0); 4854 } 4855 4856 /* unmap any remaining paged data */ 4857 if (dma_unmap_len(tx_buffer, len)) 4858 dma_unmap_page(tx_ring->dev, 4859 dma_unmap_addr(tx_buffer, dma), 4860 dma_unmap_len(tx_buffer, len), 4861 DMA_TO_DEVICE); 4862 } 4863 4864 tx_buffer->next_to_watch = NULL; 4865 4866 /* move us one more past the eop_desc for start of next pkt */ 4867 tx_buffer++; 4868 i++; 4869 if (unlikely(i == tx_ring->count)) { 4870 i = 0; 4871 tx_buffer = tx_ring->tx_buffer_info; 4872 } 4873 } 4874 4875 /* reset BQL for queue */ 4876 netdev_tx_reset_queue(txring_txq(tx_ring)); 4877 4878 /* reset next_to_use and next_to_clean */ 4879 tx_ring->next_to_use = 0; 4880 tx_ring->next_to_clean = 0; 4881} 4882 4883/** 4884 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4885 * @adapter: board private structure 4886 **/ 4887static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4888{ 4889 int i; 4890 4891 for (i = 0; i < adapter->num_tx_queues; i++) 4892 if (adapter->tx_ring[i]) 4893 igb_clean_tx_ring(adapter->tx_ring[i]); 4894} 4895 4896/** 4897 * igb_free_rx_resources - Free Rx Resources 4898 * @rx_ring: ring to clean the resources from 4899 * 4900 * Free all receive software resources 4901 **/ 4902void igb_free_rx_resources(struct igb_ring *rx_ring) 4903{ 4904 igb_clean_rx_ring(rx_ring); 4905 4906 rx_ring->xdp_prog = NULL; 4907 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4908 vfree(rx_ring->rx_buffer_info); 4909 rx_ring->rx_buffer_info = NULL; 4910 4911 /* if not set, then don't free */ 4912 if (!rx_ring->desc) 4913 return; 4914 4915 dma_free_coherent(rx_ring->dev, rx_ring->size, 4916 rx_ring->desc, rx_ring->dma); 4917 4918 rx_ring->desc = NULL; 4919} 4920 4921/** 4922 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4923 * @adapter: board private structure 4924 * 4925 * Free all receive software resources 4926 **/ 4927static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4928{ 4929 int i; 4930 4931 for (i = 0; i < adapter->num_rx_queues; i++) 4932 if (adapter->rx_ring[i]) 4933 igb_free_rx_resources(adapter->rx_ring[i]); 4934} 4935 4936/** 4937 * igb_clean_rx_ring - Free Rx Buffers per Queue 4938 * @rx_ring: ring to free buffers from 4939 **/ 4940static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4941{ 4942 u16 i = rx_ring->next_to_clean; 4943 4944 dev_kfree_skb(rx_ring->skb); 4945 rx_ring->skb = NULL; 4946 4947 /* Free all the Rx ring sk_buffs */ 4948 while (i != rx_ring->next_to_alloc) { 4949 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4950 4951 /* Invalidate cache lines that may have been written to by 4952 * device so that we avoid corrupting memory. 4953 */ 4954 dma_sync_single_range_for_cpu(rx_ring->dev, 4955 buffer_info->dma, 4956 buffer_info->page_offset, 4957 igb_rx_bufsz(rx_ring), 4958 DMA_FROM_DEVICE); 4959 4960 /* free resources associated with mapping */ 4961 dma_unmap_page_attrs(rx_ring->dev, 4962 buffer_info->dma, 4963 igb_rx_pg_size(rx_ring), 4964 DMA_FROM_DEVICE, 4965 IGB_RX_DMA_ATTR); 4966 __page_frag_cache_drain(buffer_info->page, 4967 buffer_info->pagecnt_bias); 4968 4969 i++; 4970 if (i == rx_ring->count) 4971 i = 0; 4972 } 4973 4974 rx_ring->next_to_alloc = 0; 4975 rx_ring->next_to_clean = 0; 4976 rx_ring->next_to_use = 0; 4977} 4978 4979/** 4980 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4981 * @adapter: board private structure 4982 **/ 4983static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4984{ 4985 int i; 4986 4987 for (i = 0; i < adapter->num_rx_queues; i++) 4988 if (adapter->rx_ring[i]) 4989 igb_clean_rx_ring(adapter->rx_ring[i]); 4990} 4991 4992/** 4993 * igb_set_mac - Change the Ethernet Address of the NIC 4994 * @netdev: network interface device structure 4995 * @p: pointer to an address structure 4996 * 4997 * Returns 0 on success, negative on failure 4998 **/ 4999static int igb_set_mac(struct net_device *netdev, void *p) 5000{ 5001 struct igb_adapter *adapter = netdev_priv(netdev); 5002 struct e1000_hw *hw = &adapter->hw; 5003 struct sockaddr *addr = p; 5004 5005 if (!is_valid_ether_addr(addr->sa_data)) 5006 return -EADDRNOTAVAIL; 5007 5008 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 5009 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5010 5011 /* set the correct pool for the new PF MAC address in entry 0 */ 5012 igb_set_default_mac_filter(adapter); 5013 5014 return 0; 5015} 5016 5017/** 5018 * igb_write_mc_addr_list - write multicast addresses to MTA 5019 * @netdev: network interface device structure 5020 * 5021 * Writes multicast address list to the MTA hash table. 5022 * Returns: -ENOMEM on failure 5023 * 0 on no addresses written 5024 * X on writing X addresses to MTA 5025 **/ 5026static int igb_write_mc_addr_list(struct net_device *netdev) 5027{ 5028 struct igb_adapter *adapter = netdev_priv(netdev); 5029 struct e1000_hw *hw = &adapter->hw; 5030 struct netdev_hw_addr *ha; 5031 u8 *mta_list; 5032 int i; 5033 5034 if (netdev_mc_empty(netdev)) { 5035 /* nothing to program, so clear mc list */ 5036 igb_update_mc_addr_list(hw, NULL, 0); 5037 igb_restore_vf_multicasts(adapter); 5038 return 0; 5039 } 5040 5041 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5042 if (!mta_list) 5043 return -ENOMEM; 5044 5045 /* The shared function expects a packed array of only addresses. */ 5046 i = 0; 5047 netdev_for_each_mc_addr(ha, netdev) 5048 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5049 5050 igb_update_mc_addr_list(hw, mta_list, i); 5051 kfree(mta_list); 5052 5053 return netdev_mc_count(netdev); 5054} 5055 5056static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5057{ 5058 struct e1000_hw *hw = &adapter->hw; 5059 u32 i, pf_id; 5060 5061 switch (hw->mac.type) { 5062 case e1000_i210: 5063 case e1000_i211: 5064 case e1000_i350: 5065 /* VLAN filtering needed for VLAN prio filter */ 5066 if (adapter->netdev->features & NETIF_F_NTUPLE) 5067 break; 5068 fallthrough; 5069 case e1000_82576: 5070 case e1000_82580: 5071 case e1000_i354: 5072 /* VLAN filtering needed for pool filtering */ 5073 if (adapter->vfs_allocated_count) 5074 break; 5075 fallthrough; 5076 default: 5077 return 1; 5078 } 5079 5080 /* We are already in VLAN promisc, nothing to do */ 5081 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5082 return 0; 5083 5084 if (!adapter->vfs_allocated_count) 5085 goto set_vfta; 5086 5087 /* Add PF to all active pools */ 5088 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5089 5090 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5091 u32 vlvf = rd32(E1000_VLVF(i)); 5092 5093 vlvf |= BIT(pf_id); 5094 wr32(E1000_VLVF(i), vlvf); 5095 } 5096 5097set_vfta: 5098 /* Set all bits in the VLAN filter table array */ 5099 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5100 hw->mac.ops.write_vfta(hw, i, ~0U); 5101 5102 /* Set flag so we don't redo unnecessary work */ 5103 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5104 5105 return 0; 5106} 5107 5108#define VFTA_BLOCK_SIZE 8 5109static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5110{ 5111 struct e1000_hw *hw = &adapter->hw; 5112 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5113 u32 vid_start = vfta_offset * 32; 5114 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5115 u32 i, vid, word, bits, pf_id; 5116 5117 /* guarantee that we don't scrub out management VLAN */ 5118 vid = adapter->mng_vlan_id; 5119 if (vid >= vid_start && vid < vid_end) 5120 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5121 5122 if (!adapter->vfs_allocated_count) 5123 goto set_vfta; 5124 5125 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5126 5127 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5128 u32 vlvf = rd32(E1000_VLVF(i)); 5129 5130 /* pull VLAN ID from VLVF */ 5131 vid = vlvf & VLAN_VID_MASK; 5132 5133 /* only concern ourselves with a certain range */ 5134 if (vid < vid_start || vid >= vid_end) 5135 continue; 5136 5137 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5138 /* record VLAN ID in VFTA */ 5139 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5140 5141 /* if PF is part of this then continue */ 5142 if (test_bit(vid, adapter->active_vlans)) 5143 continue; 5144 } 5145 5146 /* remove PF from the pool */ 5147 bits = ~BIT(pf_id); 5148 bits &= rd32(E1000_VLVF(i)); 5149 wr32(E1000_VLVF(i), bits); 5150 } 5151 5152set_vfta: 5153 /* extract values from active_vlans and write back to VFTA */ 5154 for (i = VFTA_BLOCK_SIZE; i--;) { 5155 vid = (vfta_offset + i) * 32; 5156 word = vid / BITS_PER_LONG; 5157 bits = vid % BITS_PER_LONG; 5158 5159 vfta[i] |= adapter->active_vlans[word] >> bits; 5160 5161 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5162 } 5163} 5164 5165static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5166{ 5167 u32 i; 5168 5169 /* We are not in VLAN promisc, nothing to do */ 5170 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5171 return; 5172 5173 /* Set flag so we don't redo unnecessary work */ 5174 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5175 5176 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5177 igb_scrub_vfta(adapter, i); 5178} 5179 5180/** 5181 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5182 * @netdev: network interface device structure 5183 * 5184 * The set_rx_mode entry point is called whenever the unicast or multicast 5185 * address lists or the network interface flags are updated. This routine is 5186 * responsible for configuring the hardware for proper unicast, multicast, 5187 * promiscuous mode, and all-multi behavior. 5188 **/ 5189static void igb_set_rx_mode(struct net_device *netdev) 5190{ 5191 struct igb_adapter *adapter = netdev_priv(netdev); 5192 struct e1000_hw *hw = &adapter->hw; 5193 unsigned int vfn = adapter->vfs_allocated_count; 5194 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5195 int count; 5196 5197 /* Check for Promiscuous and All Multicast modes */ 5198 if (netdev->flags & IFF_PROMISC) { 5199 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5200 vmolr |= E1000_VMOLR_MPME; 5201 5202 /* enable use of UTA filter to force packets to default pool */ 5203 if (hw->mac.type == e1000_82576) 5204 vmolr |= E1000_VMOLR_ROPE; 5205 } else { 5206 if (netdev->flags & IFF_ALLMULTI) { 5207 rctl |= E1000_RCTL_MPE; 5208 vmolr |= E1000_VMOLR_MPME; 5209 } else { 5210 /* Write addresses to the MTA, if the attempt fails 5211 * then we should just turn on promiscuous mode so 5212 * that we can at least receive multicast traffic 5213 */ 5214 count = igb_write_mc_addr_list(netdev); 5215 if (count < 0) { 5216 rctl |= E1000_RCTL_MPE; 5217 vmolr |= E1000_VMOLR_MPME; 5218 } else if (count) { 5219 vmolr |= E1000_VMOLR_ROMPE; 5220 } 5221 } 5222 } 5223 5224 /* Write addresses to available RAR registers, if there is not 5225 * sufficient space to store all the addresses then enable 5226 * unicast promiscuous mode 5227 */ 5228 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5229 rctl |= E1000_RCTL_UPE; 5230 vmolr |= E1000_VMOLR_ROPE; 5231 } 5232 5233 /* enable VLAN filtering by default */ 5234 rctl |= E1000_RCTL_VFE; 5235 5236 /* disable VLAN filtering for modes that require it */ 5237 if ((netdev->flags & IFF_PROMISC) || 5238 (netdev->features & NETIF_F_RXALL)) { 5239 /* if we fail to set all rules then just clear VFE */ 5240 if (igb_vlan_promisc_enable(adapter)) 5241 rctl &= ~E1000_RCTL_VFE; 5242 } else { 5243 igb_vlan_promisc_disable(adapter); 5244 } 5245 5246 /* update state of unicast, multicast, and VLAN filtering modes */ 5247 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5248 E1000_RCTL_VFE); 5249 wr32(E1000_RCTL, rctl); 5250 5251#if (PAGE_SIZE < 8192) 5252 if (!adapter->vfs_allocated_count) { 5253 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5254 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5255 } 5256#endif 5257 wr32(E1000_RLPML, rlpml); 5258 5259 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5260 * the VMOLR to enable the appropriate modes. Without this workaround 5261 * we will have issues with VLAN tag stripping not being done for frames 5262 * that are only arriving because we are the default pool 5263 */ 5264 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5265 return; 5266 5267 /* set UTA to appropriate mode */ 5268 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5269 5270 vmolr |= rd32(E1000_VMOLR(vfn)) & 5271 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5272 5273 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5274 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5275#if (PAGE_SIZE < 8192) 5276 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5277 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5278 else 5279#endif 5280 vmolr |= MAX_JUMBO_FRAME_SIZE; 5281 vmolr |= E1000_VMOLR_LPE; 5282 5283 wr32(E1000_VMOLR(vfn), vmolr); 5284 5285 igb_restore_vf_multicasts(adapter); 5286} 5287 5288static void igb_check_wvbr(struct igb_adapter *adapter) 5289{ 5290 struct e1000_hw *hw = &adapter->hw; 5291 u32 wvbr = 0; 5292 5293 switch (hw->mac.type) { 5294 case e1000_82576: 5295 case e1000_i350: 5296 wvbr = rd32(E1000_WVBR); 5297 if (!wvbr) 5298 return; 5299 break; 5300 default: 5301 break; 5302 } 5303 5304 adapter->wvbr |= wvbr; 5305} 5306 5307#define IGB_STAGGERED_QUEUE_OFFSET 8 5308 5309static void igb_spoof_check(struct igb_adapter *adapter) 5310{ 5311 int j; 5312 5313 if (!adapter->wvbr) 5314 return; 5315 5316 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5317 if (adapter->wvbr & BIT(j) || 5318 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5319 dev_warn(&adapter->pdev->dev, 5320 "Spoof event(s) detected on VF %d\n", j); 5321 adapter->wvbr &= 5322 ~(BIT(j) | 5323 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5324 } 5325 } 5326} 5327 5328/* Need to wait a few seconds after link up to get diagnostic information from 5329 * the phy 5330 */ 5331static void igb_update_phy_info(struct timer_list *t) 5332{ 5333 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5334 igb_get_phy_info(&adapter->hw); 5335} 5336 5337/** 5338 * igb_has_link - check shared code for link and determine up/down 5339 * @adapter: pointer to driver private info 5340 **/ 5341bool igb_has_link(struct igb_adapter *adapter) 5342{ 5343 struct e1000_hw *hw = &adapter->hw; 5344 bool link_active = false; 5345 5346 /* get_link_status is set on LSC (link status) interrupt or 5347 * rx sequence error interrupt. get_link_status will stay 5348 * false until the e1000_check_for_link establishes link 5349 * for copper adapters ONLY 5350 */ 5351 switch (hw->phy.media_type) { 5352 case e1000_media_type_copper: 5353 if (!hw->mac.get_link_status) 5354 return true; 5355 fallthrough; 5356 case e1000_media_type_internal_serdes: 5357 hw->mac.ops.check_for_link(hw); 5358 link_active = !hw->mac.get_link_status; 5359 break; 5360 default: 5361 case e1000_media_type_unknown: 5362 break; 5363 } 5364 5365 if (((hw->mac.type == e1000_i210) || 5366 (hw->mac.type == e1000_i211)) && 5367 (hw->phy.id == I210_I_PHY_ID)) { 5368 if (!netif_carrier_ok(adapter->netdev)) { 5369 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5370 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5371 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5372 adapter->link_check_timeout = jiffies; 5373 } 5374 } 5375 5376 return link_active; 5377} 5378 5379static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5380{ 5381 bool ret = false; 5382 u32 ctrl_ext, thstat; 5383 5384 /* check for thermal sensor event on i350 copper only */ 5385 if (hw->mac.type == e1000_i350) { 5386 thstat = rd32(E1000_THSTAT); 5387 ctrl_ext = rd32(E1000_CTRL_EXT); 5388 5389 if ((hw->phy.media_type == e1000_media_type_copper) && 5390 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5391 ret = !!(thstat & event); 5392 } 5393 5394 return ret; 5395} 5396 5397/** 5398 * igb_check_lvmmc - check for malformed packets received 5399 * and indicated in LVMMC register 5400 * @adapter: pointer to adapter 5401 **/ 5402static void igb_check_lvmmc(struct igb_adapter *adapter) 5403{ 5404 struct e1000_hw *hw = &adapter->hw; 5405 u32 lvmmc; 5406 5407 lvmmc = rd32(E1000_LVMMC); 5408 if (lvmmc) { 5409 if (unlikely(net_ratelimit())) { 5410 netdev_warn(adapter->netdev, 5411 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5412 lvmmc); 5413 } 5414 } 5415} 5416 5417/** 5418 * igb_watchdog - Timer Call-back 5419 * @t: pointer to timer_list containing our private info pointer 5420 **/ 5421static void igb_watchdog(struct timer_list *t) 5422{ 5423 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5424 /* Do the rest outside of interrupt context */ 5425 schedule_work(&adapter->watchdog_task); 5426} 5427 5428static void igb_watchdog_task(struct work_struct *work) 5429{ 5430 struct igb_adapter *adapter = container_of(work, 5431 struct igb_adapter, 5432 watchdog_task); 5433 struct e1000_hw *hw = &adapter->hw; 5434 struct e1000_phy_info *phy = &hw->phy; 5435 struct net_device *netdev = adapter->netdev; 5436 u32 link; 5437 int i; 5438 u32 connsw; 5439 u16 phy_data, retry_count = 20; 5440 5441 link = igb_has_link(adapter); 5442 5443 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5444 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5445 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5446 else 5447 link = false; 5448 } 5449 5450 /* Force link down if we have fiber to swap to */ 5451 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5452 if (hw->phy.media_type == e1000_media_type_copper) { 5453 connsw = rd32(E1000_CONNSW); 5454 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5455 link = 0; 5456 } 5457 } 5458 if (link) { 5459 /* Perform a reset if the media type changed. */ 5460 if (hw->dev_spec._82575.media_changed) { 5461 hw->dev_spec._82575.media_changed = false; 5462 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5463 igb_reset(adapter); 5464 } 5465 /* Cancel scheduled suspend requests. */ 5466 pm_runtime_resume(netdev->dev.parent); 5467 5468 if (!netif_carrier_ok(netdev)) { 5469 u32 ctrl; 5470 5471 hw->mac.ops.get_speed_and_duplex(hw, 5472 &adapter->link_speed, 5473 &adapter->link_duplex); 5474 5475 ctrl = rd32(E1000_CTRL); 5476 /* Links status message must follow this format */ 5477 netdev_info(netdev, 5478 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5479 netdev->name, 5480 adapter->link_speed, 5481 adapter->link_duplex == FULL_DUPLEX ? 5482 "Full" : "Half", 5483 (ctrl & E1000_CTRL_TFCE) && 5484 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5485 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5486 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5487 5488 /* disable EEE if enabled */ 5489 if ((adapter->flags & IGB_FLAG_EEE) && 5490 (adapter->link_duplex == HALF_DUPLEX)) { 5491 dev_info(&adapter->pdev->dev, 5492 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5493 adapter->hw.dev_spec._82575.eee_disable = true; 5494 adapter->flags &= ~IGB_FLAG_EEE; 5495 } 5496 5497 /* check if SmartSpeed worked */ 5498 igb_check_downshift(hw); 5499 if (phy->speed_downgraded) 5500 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5501 5502 /* check for thermal sensor event */ 5503 if (igb_thermal_sensor_event(hw, 5504 E1000_THSTAT_LINK_THROTTLE)) 5505 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5506 5507 /* adjust timeout factor according to speed/duplex */ 5508 adapter->tx_timeout_factor = 1; 5509 switch (adapter->link_speed) { 5510 case SPEED_10: 5511 adapter->tx_timeout_factor = 14; 5512 break; 5513 case SPEED_100: 5514 /* maybe add some timeout factor ? */ 5515 break; 5516 } 5517 5518 if (adapter->link_speed != SPEED_1000 || 5519 !hw->phy.ops.read_reg) 5520 goto no_wait; 5521 5522 /* wait for Remote receiver status OK */ 5523retry_read_status: 5524 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5525 &phy_data)) { 5526 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5527 retry_count) { 5528 msleep(100); 5529 retry_count--; 5530 goto retry_read_status; 5531 } else if (!retry_count) { 5532 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5533 } 5534 } else { 5535 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5536 } 5537no_wait: 5538 netif_carrier_on(netdev); 5539 5540 igb_ping_all_vfs(adapter); 5541 igb_check_vf_rate_limit(adapter); 5542 5543 /* link state has changed, schedule phy info update */ 5544 if (!test_bit(__IGB_DOWN, &adapter->state)) 5545 mod_timer(&adapter->phy_info_timer, 5546 round_jiffies(jiffies + 2 * HZ)); 5547 } 5548 } else { 5549 if (netif_carrier_ok(netdev)) { 5550 adapter->link_speed = 0; 5551 adapter->link_duplex = 0; 5552 5553 /* check for thermal sensor event */ 5554 if (igb_thermal_sensor_event(hw, 5555 E1000_THSTAT_PWR_DOWN)) { 5556 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5557 } 5558 5559 /* Links status message must follow this format */ 5560 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5561 netdev->name); 5562 netif_carrier_off(netdev); 5563 5564 igb_ping_all_vfs(adapter); 5565 5566 /* link state has changed, schedule phy info update */ 5567 if (!test_bit(__IGB_DOWN, &adapter->state)) 5568 mod_timer(&adapter->phy_info_timer, 5569 round_jiffies(jiffies + 2 * HZ)); 5570 5571 /* link is down, time to check for alternate media */ 5572 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5573 igb_check_swap_media(adapter); 5574 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5575 schedule_work(&adapter->reset_task); 5576 /* return immediately */ 5577 return; 5578 } 5579 } 5580 pm_schedule_suspend(netdev->dev.parent, 5581 MSEC_PER_SEC * 5); 5582 5583 /* also check for alternate media here */ 5584 } else if (!netif_carrier_ok(netdev) && 5585 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5586 igb_check_swap_media(adapter); 5587 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5588 schedule_work(&adapter->reset_task); 5589 /* return immediately */ 5590 return; 5591 } 5592 } 5593 } 5594 5595 spin_lock(&adapter->stats64_lock); 5596 igb_update_stats(adapter); 5597 spin_unlock(&adapter->stats64_lock); 5598 5599 for (i = 0; i < adapter->num_tx_queues; i++) { 5600 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5601 if (!netif_carrier_ok(netdev)) { 5602 /* We've lost link, so the controller stops DMA, 5603 * but we've got queued Tx work that's never going 5604 * to get done, so reset controller to flush Tx. 5605 * (Do the reset outside of interrupt context). 5606 */ 5607 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5608 adapter->tx_timeout_count++; 5609 schedule_work(&adapter->reset_task); 5610 /* return immediately since reset is imminent */ 5611 return; 5612 } 5613 } 5614 5615 /* Force detection of hung controller every watchdog period */ 5616 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5617 } 5618 5619 /* Cause software interrupt to ensure Rx ring is cleaned */ 5620 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5621 u32 eics = 0; 5622 5623 for (i = 0; i < adapter->num_q_vectors; i++) 5624 eics |= adapter->q_vector[i]->eims_value; 5625 wr32(E1000_EICS, eics); 5626 } else { 5627 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5628 } 5629 5630 igb_spoof_check(adapter); 5631 igb_ptp_rx_hang(adapter); 5632 igb_ptp_tx_hang(adapter); 5633 5634 /* Check LVMMC register on i350/i354 only */ 5635 if ((adapter->hw.mac.type == e1000_i350) || 5636 (adapter->hw.mac.type == e1000_i354)) 5637 igb_check_lvmmc(adapter); 5638 5639 /* Reset the timer */ 5640 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5641 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5642 mod_timer(&adapter->watchdog_timer, 5643 round_jiffies(jiffies + HZ)); 5644 else 5645 mod_timer(&adapter->watchdog_timer, 5646 round_jiffies(jiffies + 2 * HZ)); 5647 } 5648} 5649 5650enum latency_range { 5651 lowest_latency = 0, 5652 low_latency = 1, 5653 bulk_latency = 2, 5654 latency_invalid = 255 5655}; 5656 5657/** 5658 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5659 * @q_vector: pointer to q_vector 5660 * 5661 * Stores a new ITR value based on strictly on packet size. This 5662 * algorithm is less sophisticated than that used in igb_update_itr, 5663 * due to the difficulty of synchronizing statistics across multiple 5664 * receive rings. The divisors and thresholds used by this function 5665 * were determined based on theoretical maximum wire speed and testing 5666 * data, in order to minimize response time while increasing bulk 5667 * throughput. 5668 * This functionality is controlled by ethtool's coalescing settings. 5669 * NOTE: This function is called only when operating in a multiqueue 5670 * receive environment. 5671 **/ 5672static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5673{ 5674 int new_val = q_vector->itr_val; 5675 int avg_wire_size = 0; 5676 struct igb_adapter *adapter = q_vector->adapter; 5677 unsigned int packets; 5678 5679 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5680 * ints/sec - ITR timer value of 120 ticks. 5681 */ 5682 if (adapter->link_speed != SPEED_1000) { 5683 new_val = IGB_4K_ITR; 5684 goto set_itr_val; 5685 } 5686 5687 packets = q_vector->rx.total_packets; 5688 if (packets) 5689 avg_wire_size = q_vector->rx.total_bytes / packets; 5690 5691 packets = q_vector->tx.total_packets; 5692 if (packets) 5693 avg_wire_size = max_t(u32, avg_wire_size, 5694 q_vector->tx.total_bytes / packets); 5695 5696 /* if avg_wire_size isn't set no work was done */ 5697 if (!avg_wire_size) 5698 goto clear_counts; 5699 5700 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5701 avg_wire_size += 24; 5702 5703 /* Don't starve jumbo frames */ 5704 avg_wire_size = min(avg_wire_size, 3000); 5705 5706 /* Give a little boost to mid-size frames */ 5707 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5708 new_val = avg_wire_size / 3; 5709 else 5710 new_val = avg_wire_size / 2; 5711 5712 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5713 if (new_val < IGB_20K_ITR && 5714 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5715 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5716 new_val = IGB_20K_ITR; 5717 5718set_itr_val: 5719 if (new_val != q_vector->itr_val) { 5720 q_vector->itr_val = new_val; 5721 q_vector->set_itr = 1; 5722 } 5723clear_counts: 5724 q_vector->rx.total_bytes = 0; 5725 q_vector->rx.total_packets = 0; 5726 q_vector->tx.total_bytes = 0; 5727 q_vector->tx.total_packets = 0; 5728} 5729 5730/** 5731 * igb_update_itr - update the dynamic ITR value based on statistics 5732 * @q_vector: pointer to q_vector 5733 * @ring_container: ring info to update the itr for 5734 * 5735 * Stores a new ITR value based on packets and byte 5736 * counts during the last interrupt. The advantage of per interrupt 5737 * computation is faster updates and more accurate ITR for the current 5738 * traffic pattern. Constants in this function were computed 5739 * based on theoretical maximum wire speed and thresholds were set based 5740 * on testing data as well as attempting to minimize response time 5741 * while increasing bulk throughput. 5742 * This functionality is controlled by ethtool's coalescing settings. 5743 * NOTE: These calculations are only valid when operating in a single- 5744 * queue environment. 5745 **/ 5746static void igb_update_itr(struct igb_q_vector *q_vector, 5747 struct igb_ring_container *ring_container) 5748{ 5749 unsigned int packets = ring_container->total_packets; 5750 unsigned int bytes = ring_container->total_bytes; 5751 u8 itrval = ring_container->itr; 5752 5753 /* no packets, exit with status unchanged */ 5754 if (packets == 0) 5755 return; 5756 5757 switch (itrval) { 5758 case lowest_latency: 5759 /* handle TSO and jumbo frames */ 5760 if (bytes/packets > 8000) 5761 itrval = bulk_latency; 5762 else if ((packets < 5) && (bytes > 512)) 5763 itrval = low_latency; 5764 break; 5765 case low_latency: /* 50 usec aka 20000 ints/s */ 5766 if (bytes > 10000) { 5767 /* this if handles the TSO accounting */ 5768 if (bytes/packets > 8000) 5769 itrval = bulk_latency; 5770 else if ((packets < 10) || ((bytes/packets) > 1200)) 5771 itrval = bulk_latency; 5772 else if ((packets > 35)) 5773 itrval = lowest_latency; 5774 } else if (bytes/packets > 2000) { 5775 itrval = bulk_latency; 5776 } else if (packets <= 2 && bytes < 512) { 5777 itrval = lowest_latency; 5778 } 5779 break; 5780 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5781 if (bytes > 25000) { 5782 if (packets > 35) 5783 itrval = low_latency; 5784 } else if (bytes < 1500) { 5785 itrval = low_latency; 5786 } 5787 break; 5788 } 5789 5790 /* clear work counters since we have the values we need */ 5791 ring_container->total_bytes = 0; 5792 ring_container->total_packets = 0; 5793 5794 /* write updated itr to ring container */ 5795 ring_container->itr = itrval; 5796} 5797 5798static void igb_set_itr(struct igb_q_vector *q_vector) 5799{ 5800 struct igb_adapter *adapter = q_vector->adapter; 5801 u32 new_itr = q_vector->itr_val; 5802 u8 current_itr = 0; 5803 5804 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5805 if (adapter->link_speed != SPEED_1000) { 5806 current_itr = 0; 5807 new_itr = IGB_4K_ITR; 5808 goto set_itr_now; 5809 } 5810 5811 igb_update_itr(q_vector, &q_vector->tx); 5812 igb_update_itr(q_vector, &q_vector->rx); 5813 5814 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5815 5816 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5817 if (current_itr == lowest_latency && 5818 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5819 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5820 current_itr = low_latency; 5821 5822 switch (current_itr) { 5823 /* counts and packets in update_itr are dependent on these numbers */ 5824 case lowest_latency: 5825 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5826 break; 5827 case low_latency: 5828 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5829 break; 5830 case bulk_latency: 5831 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5832 break; 5833 default: 5834 break; 5835 } 5836 5837set_itr_now: 5838 if (new_itr != q_vector->itr_val) { 5839 /* this attempts to bias the interrupt rate towards Bulk 5840 * by adding intermediate steps when interrupt rate is 5841 * increasing 5842 */ 5843 new_itr = new_itr > q_vector->itr_val ? 5844 max((new_itr * q_vector->itr_val) / 5845 (new_itr + (q_vector->itr_val >> 2)), 5846 new_itr) : new_itr; 5847 /* Don't write the value here; it resets the adapter's 5848 * internal timer, and causes us to delay far longer than 5849 * we should between interrupts. Instead, we write the ITR 5850 * value at the beginning of the next interrupt so the timing 5851 * ends up being correct. 5852 */ 5853 q_vector->itr_val = new_itr; 5854 q_vector->set_itr = 1; 5855 } 5856} 5857 5858static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5859 struct igb_tx_buffer *first, 5860 u32 vlan_macip_lens, u32 type_tucmd, 5861 u32 mss_l4len_idx) 5862{ 5863 struct e1000_adv_tx_context_desc *context_desc; 5864 u16 i = tx_ring->next_to_use; 5865 struct timespec64 ts; 5866 5867 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5868 5869 i++; 5870 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5871 5872 /* set bits to identify this as an advanced context descriptor */ 5873 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5874 5875 /* For 82575, context index must be unique per ring. */ 5876 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5877 mss_l4len_idx |= tx_ring->reg_idx << 4; 5878 5879 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5880 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5881 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5882 5883 /* We assume there is always a valid tx time available. Invalid times 5884 * should have been handled by the upper layers. 5885 */ 5886 if (tx_ring->launchtime_enable) { 5887 ts = ktime_to_timespec64(first->skb->tstamp); 5888 skb_txtime_consumed(first->skb); 5889 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5890 } else { 5891 context_desc->seqnum_seed = 0; 5892 } 5893} 5894 5895static int igb_tso(struct igb_ring *tx_ring, 5896 struct igb_tx_buffer *first, 5897 u8 *hdr_len) 5898{ 5899 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5900 struct sk_buff *skb = first->skb; 5901 union { 5902 struct iphdr *v4; 5903 struct ipv6hdr *v6; 5904 unsigned char *hdr; 5905 } ip; 5906 union { 5907 struct tcphdr *tcp; 5908 struct udphdr *udp; 5909 unsigned char *hdr; 5910 } l4; 5911 u32 paylen, l4_offset; 5912 int err; 5913 5914 if (skb->ip_summed != CHECKSUM_PARTIAL) 5915 return 0; 5916 5917 if (!skb_is_gso(skb)) 5918 return 0; 5919 5920 err = skb_cow_head(skb, 0); 5921 if (err < 0) 5922 return err; 5923 5924 ip.hdr = skb_network_header(skb); 5925 l4.hdr = skb_checksum_start(skb); 5926 5927 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5928 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5929 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5930 5931 /* initialize outer IP header fields */ 5932 if (ip.v4->version == 4) { 5933 unsigned char *csum_start = skb_checksum_start(skb); 5934 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5935 5936 /* IP header will have to cancel out any data that 5937 * is not a part of the outer IP header 5938 */ 5939 ip.v4->check = csum_fold(csum_partial(trans_start, 5940 csum_start - trans_start, 5941 0)); 5942 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5943 5944 ip.v4->tot_len = 0; 5945 first->tx_flags |= IGB_TX_FLAGS_TSO | 5946 IGB_TX_FLAGS_CSUM | 5947 IGB_TX_FLAGS_IPV4; 5948 } else { 5949 ip.v6->payload_len = 0; 5950 first->tx_flags |= IGB_TX_FLAGS_TSO | 5951 IGB_TX_FLAGS_CSUM; 5952 } 5953 5954 /* determine offset of inner transport header */ 5955 l4_offset = l4.hdr - skb->data; 5956 5957 /* remove payload length from inner checksum */ 5958 paylen = skb->len - l4_offset; 5959 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5960 /* compute length of segmentation header */ 5961 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5962 csum_replace_by_diff(&l4.tcp->check, 5963 (__force __wsum)htonl(paylen)); 5964 } else { 5965 /* compute length of segmentation header */ 5966 *hdr_len = sizeof(*l4.udp) + l4_offset; 5967 csum_replace_by_diff(&l4.udp->check, 5968 (__force __wsum)htonl(paylen)); 5969 } 5970 5971 /* update gso size and bytecount with header size */ 5972 first->gso_segs = skb_shinfo(skb)->gso_segs; 5973 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5974 5975 /* MSS L4LEN IDX */ 5976 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5977 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5978 5979 /* VLAN MACLEN IPLEN */ 5980 vlan_macip_lens = l4.hdr - ip.hdr; 5981 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5982 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5983 5984 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5985 type_tucmd, mss_l4len_idx); 5986 5987 return 1; 5988} 5989 5990static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5991{ 5992 unsigned int offset = 0; 5993 5994 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5995 5996 return offset == skb_checksum_start_offset(skb); 5997} 5998 5999static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6000{ 6001 struct sk_buff *skb = first->skb; 6002 u32 vlan_macip_lens = 0; 6003 u32 type_tucmd = 0; 6004 6005 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6006csum_failed: 6007 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6008 !tx_ring->launchtime_enable) 6009 return; 6010 goto no_csum; 6011 } 6012 6013 switch (skb->csum_offset) { 6014 case offsetof(struct tcphdr, check): 6015 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6016 fallthrough; 6017 case offsetof(struct udphdr, check): 6018 break; 6019 case offsetof(struct sctphdr, checksum): 6020 /* validate that this is actually an SCTP request */ 6021 if (((first->protocol == htons(ETH_P_IP)) && 6022 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 6023 ((first->protocol == htons(ETH_P_IPV6)) && 6024 igb_ipv6_csum_is_sctp(skb))) { 6025 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6026 break; 6027 } 6028 fallthrough; 6029 default: 6030 skb_checksum_help(skb); 6031 goto csum_failed; 6032 } 6033 6034 /* update TX checksum flag */ 6035 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6036 vlan_macip_lens = skb_checksum_start_offset(skb) - 6037 skb_network_offset(skb); 6038no_csum: 6039 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6040 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6041 6042 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6043} 6044 6045#define IGB_SET_FLAG(_input, _flag, _result) \ 6046 ((_flag <= _result) ? \ 6047 ((u32)(_input & _flag) * (_result / _flag)) : \ 6048 ((u32)(_input & _flag) / (_flag / _result))) 6049 6050static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6051{ 6052 /* set type for advanced descriptor with frame checksum insertion */ 6053 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6054 E1000_ADVTXD_DCMD_DEXT | 6055 E1000_ADVTXD_DCMD_IFCS; 6056 6057 /* set HW vlan bit if vlan is present */ 6058 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6059 (E1000_ADVTXD_DCMD_VLE)); 6060 6061 /* set segmentation bits for TSO */ 6062 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6063 (E1000_ADVTXD_DCMD_TSE)); 6064 6065 /* set timestamp bit if present */ 6066 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6067 (E1000_ADVTXD_MAC_TSTAMP)); 6068 6069 /* insert frame checksum */ 6070 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6071 6072 return cmd_type; 6073} 6074 6075static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6076 union e1000_adv_tx_desc *tx_desc, 6077 u32 tx_flags, unsigned int paylen) 6078{ 6079 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6080 6081 /* 82575 requires a unique index per ring */ 6082 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6083 olinfo_status |= tx_ring->reg_idx << 4; 6084 6085 /* insert L4 checksum */ 6086 olinfo_status |= IGB_SET_FLAG(tx_flags, 6087 IGB_TX_FLAGS_CSUM, 6088 (E1000_TXD_POPTS_TXSM << 8)); 6089 6090 /* insert IPv4 checksum */ 6091 olinfo_status |= IGB_SET_FLAG(tx_flags, 6092 IGB_TX_FLAGS_IPV4, 6093 (E1000_TXD_POPTS_IXSM << 8)); 6094 6095 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6096} 6097 6098static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6099{ 6100 struct net_device *netdev = tx_ring->netdev; 6101 6102 netif_stop_subqueue(netdev, tx_ring->queue_index); 6103 6104 /* Herbert's original patch had: 6105 * smp_mb__after_netif_stop_queue(); 6106 * but since that doesn't exist yet, just open code it. 6107 */ 6108 smp_mb(); 6109 6110 /* We need to check again in a case another CPU has just 6111 * made room available. 6112 */ 6113 if (igb_desc_unused(tx_ring) < size) 6114 return -EBUSY; 6115 6116 /* A reprieve! */ 6117 netif_wake_subqueue(netdev, tx_ring->queue_index); 6118 6119 u64_stats_update_begin(&tx_ring->tx_syncp2); 6120 tx_ring->tx_stats.restart_queue2++; 6121 u64_stats_update_end(&tx_ring->tx_syncp2); 6122 6123 return 0; 6124} 6125 6126static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6127{ 6128 if (igb_desc_unused(tx_ring) >= size) 6129 return 0; 6130 return __igb_maybe_stop_tx(tx_ring, size); 6131} 6132 6133static int igb_tx_map(struct igb_ring *tx_ring, 6134 struct igb_tx_buffer *first, 6135 const u8 hdr_len) 6136{ 6137 struct sk_buff *skb = first->skb; 6138 struct igb_tx_buffer *tx_buffer; 6139 union e1000_adv_tx_desc *tx_desc; 6140 skb_frag_t *frag; 6141 dma_addr_t dma; 6142 unsigned int data_len, size; 6143 u32 tx_flags = first->tx_flags; 6144 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6145 u16 i = tx_ring->next_to_use; 6146 6147 tx_desc = IGB_TX_DESC(tx_ring, i); 6148 6149 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6150 6151 size = skb_headlen(skb); 6152 data_len = skb->data_len; 6153 6154 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6155 6156 tx_buffer = first; 6157 6158 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6159 if (dma_mapping_error(tx_ring->dev, dma)) 6160 goto dma_error; 6161 6162 /* record length, and DMA address */ 6163 dma_unmap_len_set(tx_buffer, len, size); 6164 dma_unmap_addr_set(tx_buffer, dma, dma); 6165 6166 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6167 6168 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6169 tx_desc->read.cmd_type_len = 6170 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6171 6172 i++; 6173 tx_desc++; 6174 if (i == tx_ring->count) { 6175 tx_desc = IGB_TX_DESC(tx_ring, 0); 6176 i = 0; 6177 } 6178 tx_desc->read.olinfo_status = 0; 6179 6180 dma += IGB_MAX_DATA_PER_TXD; 6181 size -= IGB_MAX_DATA_PER_TXD; 6182 6183 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6184 } 6185 6186 if (likely(!data_len)) 6187 break; 6188 6189 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6190 6191 i++; 6192 tx_desc++; 6193 if (i == tx_ring->count) { 6194 tx_desc = IGB_TX_DESC(tx_ring, 0); 6195 i = 0; 6196 } 6197 tx_desc->read.olinfo_status = 0; 6198 6199 size = skb_frag_size(frag); 6200 data_len -= size; 6201 6202 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6203 size, DMA_TO_DEVICE); 6204 6205 tx_buffer = &tx_ring->tx_buffer_info[i]; 6206 } 6207 6208 /* write last descriptor with RS and EOP bits */ 6209 cmd_type |= size | IGB_TXD_DCMD; 6210 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6211 6212 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6213 6214 /* set the timestamp */ 6215 first->time_stamp = jiffies; 6216 6217 skb_tx_timestamp(skb); 6218 6219 /* Force memory writes to complete before letting h/w know there 6220 * are new descriptors to fetch. (Only applicable for weak-ordered 6221 * memory model archs, such as IA-64). 6222 * 6223 * We also need this memory barrier to make certain all of the 6224 * status bits have been updated before next_to_watch is written. 6225 */ 6226 dma_wmb(); 6227 6228 /* set next_to_watch value indicating a packet is present */ 6229 first->next_to_watch = tx_desc; 6230 6231 i++; 6232 if (i == tx_ring->count) 6233 i = 0; 6234 6235 tx_ring->next_to_use = i; 6236 6237 /* Make sure there is space in the ring for the next send. */ 6238 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6239 6240 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6241 writel(i, tx_ring->tail); 6242 } 6243 return 0; 6244 6245dma_error: 6246 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6247 tx_buffer = &tx_ring->tx_buffer_info[i]; 6248 6249 /* clear dma mappings for failed tx_buffer_info map */ 6250 while (tx_buffer != first) { 6251 if (dma_unmap_len(tx_buffer, len)) 6252 dma_unmap_page(tx_ring->dev, 6253 dma_unmap_addr(tx_buffer, dma), 6254 dma_unmap_len(tx_buffer, len), 6255 DMA_TO_DEVICE); 6256 dma_unmap_len_set(tx_buffer, len, 0); 6257 6258 if (i-- == 0) 6259 i += tx_ring->count; 6260 tx_buffer = &tx_ring->tx_buffer_info[i]; 6261 } 6262 6263 if (dma_unmap_len(tx_buffer, len)) 6264 dma_unmap_single(tx_ring->dev, 6265 dma_unmap_addr(tx_buffer, dma), 6266 dma_unmap_len(tx_buffer, len), 6267 DMA_TO_DEVICE); 6268 dma_unmap_len_set(tx_buffer, len, 0); 6269 6270 dev_kfree_skb_any(tx_buffer->skb); 6271 tx_buffer->skb = NULL; 6272 6273 tx_ring->next_to_use = i; 6274 6275 return -1; 6276} 6277 6278int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6279 struct igb_ring *tx_ring, 6280 struct xdp_frame *xdpf) 6281{ 6282 union e1000_adv_tx_desc *tx_desc; 6283 u32 len, cmd_type, olinfo_status; 6284 struct igb_tx_buffer *tx_buffer; 6285 dma_addr_t dma; 6286 u16 i; 6287 6288 len = xdpf->len; 6289 6290 if (unlikely(!igb_desc_unused(tx_ring))) 6291 return IGB_XDP_CONSUMED; 6292 6293 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE); 6294 if (dma_mapping_error(tx_ring->dev, dma)) 6295 return IGB_XDP_CONSUMED; 6296 6297 /* record the location of the first descriptor for this packet */ 6298 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6299 tx_buffer->bytecount = len; 6300 tx_buffer->gso_segs = 1; 6301 tx_buffer->protocol = 0; 6302 6303 i = tx_ring->next_to_use; 6304 tx_desc = IGB_TX_DESC(tx_ring, i); 6305 6306 dma_unmap_len_set(tx_buffer, len, len); 6307 dma_unmap_addr_set(tx_buffer, dma, dma); 6308 tx_buffer->type = IGB_TYPE_XDP; 6309 tx_buffer->xdpf = xdpf; 6310 6311 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6312 6313 /* put descriptor type bits */ 6314 cmd_type = E1000_ADVTXD_DTYP_DATA | 6315 E1000_ADVTXD_DCMD_DEXT | 6316 E1000_ADVTXD_DCMD_IFCS; 6317 cmd_type |= len | IGB_TXD_DCMD; 6318 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6319 6320 olinfo_status = len << E1000_ADVTXD_PAYLEN_SHIFT; 6321 /* 82575 requires a unique index per ring */ 6322 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6323 olinfo_status |= tx_ring->reg_idx << 4; 6324 6325 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6326 6327 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount); 6328 6329 /* set the timestamp */ 6330 tx_buffer->time_stamp = jiffies; 6331 6332 /* Avoid any potential race with xdp_xmit and cleanup */ 6333 smp_wmb(); 6334 6335 /* set next_to_watch value indicating a packet is present */ 6336 i++; 6337 if (i == tx_ring->count) 6338 i = 0; 6339 6340 tx_buffer->next_to_watch = tx_desc; 6341 tx_ring->next_to_use = i; 6342 6343 /* Make sure there is space in the ring for the next send. */ 6344 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6345 6346 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6347 writel(i, tx_ring->tail); 6348 6349 return IGB_XDP_TX; 6350} 6351 6352netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6353 struct igb_ring *tx_ring) 6354{ 6355 struct igb_tx_buffer *first; 6356 int tso; 6357 u32 tx_flags = 0; 6358 unsigned short f; 6359 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6360 __be16 protocol = vlan_get_protocol(skb); 6361 u8 hdr_len = 0; 6362 6363 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6364 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6365 * + 2 desc gap to keep tail from touching head, 6366 * + 1 desc for context descriptor, 6367 * otherwise try next time 6368 */ 6369 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6370 count += TXD_USE_COUNT(skb_frag_size( 6371 &skb_shinfo(skb)->frags[f])); 6372 6373 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6374 /* this is a hard error */ 6375 return NETDEV_TX_BUSY; 6376 } 6377 6378 /* record the location of the first descriptor for this packet */ 6379 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6380 first->type = IGB_TYPE_SKB; 6381 first->skb = skb; 6382 first->bytecount = skb->len; 6383 first->gso_segs = 1; 6384 6385 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6386 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6387 6388 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6389 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6390 &adapter->state)) { 6391 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6392 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6393 6394 adapter->ptp_tx_skb = skb_get(skb); 6395 adapter->ptp_tx_start = jiffies; 6396 if (adapter->hw.mac.type == e1000_82576) 6397 schedule_work(&adapter->ptp_tx_work); 6398 } else { 6399 adapter->tx_hwtstamp_skipped++; 6400 } 6401 } 6402 6403 if (skb_vlan_tag_present(skb)) { 6404 tx_flags |= IGB_TX_FLAGS_VLAN; 6405 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6406 } 6407 6408 /* record initial flags and protocol */ 6409 first->tx_flags = tx_flags; 6410 first->protocol = protocol; 6411 6412 tso = igb_tso(tx_ring, first, &hdr_len); 6413 if (tso < 0) 6414 goto out_drop; 6415 else if (!tso) 6416 igb_tx_csum(tx_ring, first); 6417 6418 if (igb_tx_map(tx_ring, first, hdr_len)) 6419 goto cleanup_tx_tstamp; 6420 6421 return NETDEV_TX_OK; 6422 6423out_drop: 6424 dev_kfree_skb_any(first->skb); 6425 first->skb = NULL; 6426cleanup_tx_tstamp: 6427 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6428 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6429 6430 dev_kfree_skb_any(adapter->ptp_tx_skb); 6431 adapter->ptp_tx_skb = NULL; 6432 if (adapter->hw.mac.type == e1000_82576) 6433 cancel_work_sync(&adapter->ptp_tx_work); 6434 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6435 } 6436 6437 return NETDEV_TX_OK; 6438} 6439 6440static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6441 struct sk_buff *skb) 6442{ 6443 unsigned int r_idx = skb->queue_mapping; 6444 6445 if (r_idx >= adapter->num_tx_queues) 6446 r_idx = r_idx % adapter->num_tx_queues; 6447 6448 return adapter->tx_ring[r_idx]; 6449} 6450 6451static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6452 struct net_device *netdev) 6453{ 6454 struct igb_adapter *adapter = netdev_priv(netdev); 6455 6456 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6457 * in order to meet this minimum size requirement. 6458 */ 6459 if (skb_put_padto(skb, 17)) 6460 return NETDEV_TX_OK; 6461 6462 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6463} 6464 6465/** 6466 * igb_tx_timeout - Respond to a Tx Hang 6467 * @netdev: network interface device structure 6468 * @txqueue: number of the Tx queue that hung (unused) 6469 **/ 6470static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6471{ 6472 struct igb_adapter *adapter = netdev_priv(netdev); 6473 struct e1000_hw *hw = &adapter->hw; 6474 6475 /* Do the reset outside of interrupt context */ 6476 adapter->tx_timeout_count++; 6477 6478 if (hw->mac.type >= e1000_82580) 6479 hw->dev_spec._82575.global_device_reset = true; 6480 6481 schedule_work(&adapter->reset_task); 6482 wr32(E1000_EICS, 6483 (adapter->eims_enable_mask & ~adapter->eims_other)); 6484} 6485 6486static void igb_reset_task(struct work_struct *work) 6487{ 6488 struct igb_adapter *adapter; 6489 adapter = container_of(work, struct igb_adapter, reset_task); 6490 6491 rtnl_lock(); 6492 /* If we're already down or resetting, just bail */ 6493 if (test_bit(__IGB_DOWN, &adapter->state) || 6494 test_bit(__IGB_RESETTING, &adapter->state)) { 6495 rtnl_unlock(); 6496 return; 6497 } 6498 6499 igb_dump(adapter); 6500 netdev_err(adapter->netdev, "Reset adapter\n"); 6501 igb_reinit_locked(adapter); 6502 rtnl_unlock(); 6503} 6504 6505/** 6506 * igb_get_stats64 - Get System Network Statistics 6507 * @netdev: network interface device structure 6508 * @stats: rtnl_link_stats64 pointer 6509 **/ 6510static void igb_get_stats64(struct net_device *netdev, 6511 struct rtnl_link_stats64 *stats) 6512{ 6513 struct igb_adapter *adapter = netdev_priv(netdev); 6514 6515 spin_lock(&adapter->stats64_lock); 6516 igb_update_stats(adapter); 6517 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6518 spin_unlock(&adapter->stats64_lock); 6519} 6520 6521/** 6522 * igb_change_mtu - Change the Maximum Transfer Unit 6523 * @netdev: network interface device structure 6524 * @new_mtu: new value for maximum frame size 6525 * 6526 * Returns 0 on success, negative on failure 6527 **/ 6528static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6529{ 6530 struct igb_adapter *adapter = netdev_priv(netdev); 6531 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6532 6533 if (adapter->xdp_prog) { 6534 int i; 6535 6536 for (i = 0; i < adapter->num_rx_queues; i++) { 6537 struct igb_ring *ring = adapter->rx_ring[i]; 6538 6539 if (max_frame > igb_rx_bufsz(ring)) { 6540 netdev_warn(adapter->netdev, 6541 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6542 max_frame); 6543 return -EINVAL; 6544 } 6545 } 6546 } 6547 6548 /* adjust max frame to be at least the size of a standard frame */ 6549 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6550 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6551 6552 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6553 usleep_range(1000, 2000); 6554 6555 /* igb_down has a dependency on max_frame_size */ 6556 adapter->max_frame_size = max_frame; 6557 6558 if (netif_running(netdev)) 6559 igb_down(adapter); 6560 6561 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6562 netdev->mtu, new_mtu); 6563 netdev->mtu = new_mtu; 6564 6565 if (netif_running(netdev)) 6566 igb_up(adapter); 6567 else 6568 igb_reset(adapter); 6569 6570 clear_bit(__IGB_RESETTING, &adapter->state); 6571 6572 return 0; 6573} 6574 6575/** 6576 * igb_update_stats - Update the board statistics counters 6577 * @adapter: board private structure 6578 **/ 6579void igb_update_stats(struct igb_adapter *adapter) 6580{ 6581 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6582 struct e1000_hw *hw = &adapter->hw; 6583 struct pci_dev *pdev = adapter->pdev; 6584 u32 reg, mpc; 6585 int i; 6586 u64 bytes, packets; 6587 unsigned int start; 6588 u64 _bytes, _packets; 6589 6590 /* Prevent stats update while adapter is being reset, or if the pci 6591 * connection is down. 6592 */ 6593 if (adapter->link_speed == 0) 6594 return; 6595 if (pci_channel_offline(pdev)) 6596 return; 6597 6598 bytes = 0; 6599 packets = 0; 6600 6601 rcu_read_lock(); 6602 for (i = 0; i < adapter->num_rx_queues; i++) { 6603 struct igb_ring *ring = adapter->rx_ring[i]; 6604 u32 rqdpc = rd32(E1000_RQDPC(i)); 6605 if (hw->mac.type >= e1000_i210) 6606 wr32(E1000_RQDPC(i), 0); 6607 6608 if (rqdpc) { 6609 ring->rx_stats.drops += rqdpc; 6610 net_stats->rx_fifo_errors += rqdpc; 6611 } 6612 6613 do { 6614 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6615 _bytes = ring->rx_stats.bytes; 6616 _packets = ring->rx_stats.packets; 6617 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6618 bytes += _bytes; 6619 packets += _packets; 6620 } 6621 6622 net_stats->rx_bytes = bytes; 6623 net_stats->rx_packets = packets; 6624 6625 bytes = 0; 6626 packets = 0; 6627 for (i = 0; i < adapter->num_tx_queues; i++) { 6628 struct igb_ring *ring = adapter->tx_ring[i]; 6629 do { 6630 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6631 _bytes = ring->tx_stats.bytes; 6632 _packets = ring->tx_stats.packets; 6633 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6634 bytes += _bytes; 6635 packets += _packets; 6636 } 6637 net_stats->tx_bytes = bytes; 6638 net_stats->tx_packets = packets; 6639 rcu_read_unlock(); 6640 6641 /* read stats registers */ 6642 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6643 adapter->stats.gprc += rd32(E1000_GPRC); 6644 adapter->stats.gorc += rd32(E1000_GORCL); 6645 rd32(E1000_GORCH); /* clear GORCL */ 6646 adapter->stats.bprc += rd32(E1000_BPRC); 6647 adapter->stats.mprc += rd32(E1000_MPRC); 6648 adapter->stats.roc += rd32(E1000_ROC); 6649 6650 adapter->stats.prc64 += rd32(E1000_PRC64); 6651 adapter->stats.prc127 += rd32(E1000_PRC127); 6652 adapter->stats.prc255 += rd32(E1000_PRC255); 6653 adapter->stats.prc511 += rd32(E1000_PRC511); 6654 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6655 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6656 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6657 adapter->stats.sec += rd32(E1000_SEC); 6658 6659 mpc = rd32(E1000_MPC); 6660 adapter->stats.mpc += mpc; 6661 net_stats->rx_fifo_errors += mpc; 6662 adapter->stats.scc += rd32(E1000_SCC); 6663 adapter->stats.ecol += rd32(E1000_ECOL); 6664 adapter->stats.mcc += rd32(E1000_MCC); 6665 adapter->stats.latecol += rd32(E1000_LATECOL); 6666 adapter->stats.dc += rd32(E1000_DC); 6667 adapter->stats.rlec += rd32(E1000_RLEC); 6668 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6669 adapter->stats.xontxc += rd32(E1000_XONTXC); 6670 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6671 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6672 adapter->stats.fcruc += rd32(E1000_FCRUC); 6673 adapter->stats.gptc += rd32(E1000_GPTC); 6674 adapter->stats.gotc += rd32(E1000_GOTCL); 6675 rd32(E1000_GOTCH); /* clear GOTCL */ 6676 adapter->stats.rnbc += rd32(E1000_RNBC); 6677 adapter->stats.ruc += rd32(E1000_RUC); 6678 adapter->stats.rfc += rd32(E1000_RFC); 6679 adapter->stats.rjc += rd32(E1000_RJC); 6680 adapter->stats.tor += rd32(E1000_TORH); 6681 adapter->stats.tot += rd32(E1000_TOTH); 6682 adapter->stats.tpr += rd32(E1000_TPR); 6683 6684 adapter->stats.ptc64 += rd32(E1000_PTC64); 6685 adapter->stats.ptc127 += rd32(E1000_PTC127); 6686 adapter->stats.ptc255 += rd32(E1000_PTC255); 6687 adapter->stats.ptc511 += rd32(E1000_PTC511); 6688 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6689 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6690 6691 adapter->stats.mptc += rd32(E1000_MPTC); 6692 adapter->stats.bptc += rd32(E1000_BPTC); 6693 6694 adapter->stats.tpt += rd32(E1000_TPT); 6695 adapter->stats.colc += rd32(E1000_COLC); 6696 6697 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6698 /* read internal phy specific stats */ 6699 reg = rd32(E1000_CTRL_EXT); 6700 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6701 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6702 6703 /* this stat has invalid values on i210/i211 */ 6704 if ((hw->mac.type != e1000_i210) && 6705 (hw->mac.type != e1000_i211)) 6706 adapter->stats.tncrs += rd32(E1000_TNCRS); 6707 } 6708 6709 adapter->stats.tsctc += rd32(E1000_TSCTC); 6710 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6711 6712 adapter->stats.iac += rd32(E1000_IAC); 6713 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6714 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6715 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6716 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6717 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6718 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6719 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6720 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6721 6722 /* Fill out the OS statistics structure */ 6723 net_stats->multicast = adapter->stats.mprc; 6724 net_stats->collisions = adapter->stats.colc; 6725 6726 /* Rx Errors */ 6727 6728 /* RLEC on some newer hardware can be incorrect so build 6729 * our own version based on RUC and ROC 6730 */ 6731 net_stats->rx_errors = adapter->stats.rxerrc + 6732 adapter->stats.crcerrs + adapter->stats.algnerrc + 6733 adapter->stats.ruc + adapter->stats.roc + 6734 adapter->stats.cexterr; 6735 net_stats->rx_length_errors = adapter->stats.ruc + 6736 adapter->stats.roc; 6737 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6738 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6739 net_stats->rx_missed_errors = adapter->stats.mpc; 6740 6741 /* Tx Errors */ 6742 net_stats->tx_errors = adapter->stats.ecol + 6743 adapter->stats.latecol; 6744 net_stats->tx_aborted_errors = adapter->stats.ecol; 6745 net_stats->tx_window_errors = adapter->stats.latecol; 6746 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6747 6748 /* Tx Dropped needs to be maintained elsewhere */ 6749 6750 /* Management Stats */ 6751 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6752 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6753 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6754 6755 /* OS2BMC Stats */ 6756 reg = rd32(E1000_MANC); 6757 if (reg & E1000_MANC_EN_BMC2OS) { 6758 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6759 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6760 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6761 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6762 } 6763} 6764 6765static void igb_tsync_interrupt(struct igb_adapter *adapter) 6766{ 6767 struct e1000_hw *hw = &adapter->hw; 6768 struct ptp_clock_event event; 6769 struct timespec64 ts; 6770 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6771 6772 if (tsicr & TSINTR_SYS_WRAP) { 6773 event.type = PTP_CLOCK_PPS; 6774 if (adapter->ptp_caps.pps) 6775 ptp_clock_event(adapter->ptp_clock, &event); 6776 ack |= TSINTR_SYS_WRAP; 6777 } 6778 6779 if (tsicr & E1000_TSICR_TXTS) { 6780 /* retrieve hardware timestamp */ 6781 schedule_work(&adapter->ptp_tx_work); 6782 ack |= E1000_TSICR_TXTS; 6783 } 6784 6785 if (tsicr & TSINTR_TT0) { 6786 spin_lock(&adapter->tmreg_lock); 6787 ts = timespec64_add(adapter->perout[0].start, 6788 adapter->perout[0].period); 6789 /* u32 conversion of tv_sec is safe until y2106 */ 6790 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6791 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6792 tsauxc = rd32(E1000_TSAUXC); 6793 tsauxc |= TSAUXC_EN_TT0; 6794 wr32(E1000_TSAUXC, tsauxc); 6795 adapter->perout[0].start = ts; 6796 spin_unlock(&adapter->tmreg_lock); 6797 ack |= TSINTR_TT0; 6798 } 6799 6800 if (tsicr & TSINTR_TT1) { 6801 spin_lock(&adapter->tmreg_lock); 6802 ts = timespec64_add(adapter->perout[1].start, 6803 adapter->perout[1].period); 6804 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6805 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6806 tsauxc = rd32(E1000_TSAUXC); 6807 tsauxc |= TSAUXC_EN_TT1; 6808 wr32(E1000_TSAUXC, tsauxc); 6809 adapter->perout[1].start = ts; 6810 spin_unlock(&adapter->tmreg_lock); 6811 ack |= TSINTR_TT1; 6812 } 6813 6814 if (tsicr & TSINTR_AUTT0) { 6815 nsec = rd32(E1000_AUXSTMPL0); 6816 sec = rd32(E1000_AUXSTMPH0); 6817 event.type = PTP_CLOCK_EXTTS; 6818 event.index = 0; 6819 event.timestamp = sec * 1000000000ULL + nsec; 6820 ptp_clock_event(adapter->ptp_clock, &event); 6821 ack |= TSINTR_AUTT0; 6822 } 6823 6824 if (tsicr & TSINTR_AUTT1) { 6825 nsec = rd32(E1000_AUXSTMPL1); 6826 sec = rd32(E1000_AUXSTMPH1); 6827 event.type = PTP_CLOCK_EXTTS; 6828 event.index = 1; 6829 event.timestamp = sec * 1000000000ULL + nsec; 6830 ptp_clock_event(adapter->ptp_clock, &event); 6831 ack |= TSINTR_AUTT1; 6832 } 6833 6834 /* acknowledge the interrupts */ 6835 wr32(E1000_TSICR, ack); 6836} 6837 6838static irqreturn_t igb_msix_other(int irq, void *data) 6839{ 6840 struct igb_adapter *adapter = data; 6841 struct e1000_hw *hw = &adapter->hw; 6842 u32 icr = rd32(E1000_ICR); 6843 /* reading ICR causes bit 31 of EICR to be cleared */ 6844 6845 if (icr & E1000_ICR_DRSTA) 6846 schedule_work(&adapter->reset_task); 6847 6848 if (icr & E1000_ICR_DOUTSYNC) { 6849 /* HW is reporting DMA is out of sync */ 6850 adapter->stats.doosync++; 6851 /* The DMA Out of Sync is also indication of a spoof event 6852 * in IOV mode. Check the Wrong VM Behavior register to 6853 * see if it is really a spoof event. 6854 */ 6855 igb_check_wvbr(adapter); 6856 } 6857 6858 /* Check for a mailbox event */ 6859 if (icr & E1000_ICR_VMMB) 6860 igb_msg_task(adapter); 6861 6862 if (icr & E1000_ICR_LSC) { 6863 hw->mac.get_link_status = 1; 6864 /* guard against interrupt when we're going down */ 6865 if (!test_bit(__IGB_DOWN, &adapter->state)) 6866 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6867 } 6868 6869 if (icr & E1000_ICR_TS) 6870 igb_tsync_interrupt(adapter); 6871 6872 wr32(E1000_EIMS, adapter->eims_other); 6873 6874 return IRQ_HANDLED; 6875} 6876 6877static void igb_write_itr(struct igb_q_vector *q_vector) 6878{ 6879 struct igb_adapter *adapter = q_vector->adapter; 6880 u32 itr_val = q_vector->itr_val & 0x7FFC; 6881 6882 if (!q_vector->set_itr) 6883 return; 6884 6885 if (!itr_val) 6886 itr_val = 0x4; 6887 6888 if (adapter->hw.mac.type == e1000_82575) 6889 itr_val |= itr_val << 16; 6890 else 6891 itr_val |= E1000_EITR_CNT_IGNR; 6892 6893 writel(itr_val, q_vector->itr_register); 6894 q_vector->set_itr = 0; 6895} 6896 6897static irqreturn_t igb_msix_ring(int irq, void *data) 6898{ 6899 struct igb_q_vector *q_vector = data; 6900 6901 /* Write the ITR value calculated from the previous interrupt. */ 6902 igb_write_itr(q_vector); 6903 6904 napi_schedule(&q_vector->napi); 6905 6906 return IRQ_HANDLED; 6907} 6908 6909#ifdef CONFIG_IGB_DCA 6910static void igb_update_tx_dca(struct igb_adapter *adapter, 6911 struct igb_ring *tx_ring, 6912 int cpu) 6913{ 6914 struct e1000_hw *hw = &adapter->hw; 6915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6916 6917 if (hw->mac.type != e1000_82575) 6918 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6919 6920 /* We can enable relaxed ordering for reads, but not writes when 6921 * DCA is enabled. This is due to a known issue in some chipsets 6922 * which will cause the DCA tag to be cleared. 6923 */ 6924 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6925 E1000_DCA_TXCTRL_DATA_RRO_EN | 6926 E1000_DCA_TXCTRL_DESC_DCA_EN; 6927 6928 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6929} 6930 6931static void igb_update_rx_dca(struct igb_adapter *adapter, 6932 struct igb_ring *rx_ring, 6933 int cpu) 6934{ 6935 struct e1000_hw *hw = &adapter->hw; 6936 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6937 6938 if (hw->mac.type != e1000_82575) 6939 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6940 6941 /* We can enable relaxed ordering for reads, but not writes when 6942 * DCA is enabled. This is due to a known issue in some chipsets 6943 * which will cause the DCA tag to be cleared. 6944 */ 6945 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6946 E1000_DCA_RXCTRL_DESC_DCA_EN; 6947 6948 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6949} 6950 6951static void igb_update_dca(struct igb_q_vector *q_vector) 6952{ 6953 struct igb_adapter *adapter = q_vector->adapter; 6954 int cpu = get_cpu(); 6955 6956 if (q_vector->cpu == cpu) 6957 goto out_no_update; 6958 6959 if (q_vector->tx.ring) 6960 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6961 6962 if (q_vector->rx.ring) 6963 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6964 6965 q_vector->cpu = cpu; 6966out_no_update: 6967 put_cpu(); 6968} 6969 6970static void igb_setup_dca(struct igb_adapter *adapter) 6971{ 6972 struct e1000_hw *hw = &adapter->hw; 6973 int i; 6974 6975 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6976 return; 6977 6978 /* Always use CB2 mode, difference is masked in the CB driver. */ 6979 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6980 6981 for (i = 0; i < adapter->num_q_vectors; i++) { 6982 adapter->q_vector[i]->cpu = -1; 6983 igb_update_dca(adapter->q_vector[i]); 6984 } 6985} 6986 6987static int __igb_notify_dca(struct device *dev, void *data) 6988{ 6989 struct net_device *netdev = dev_get_drvdata(dev); 6990 struct igb_adapter *adapter = netdev_priv(netdev); 6991 struct pci_dev *pdev = adapter->pdev; 6992 struct e1000_hw *hw = &adapter->hw; 6993 unsigned long event = *(unsigned long *)data; 6994 6995 switch (event) { 6996 case DCA_PROVIDER_ADD: 6997 /* if already enabled, don't do it again */ 6998 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6999 break; 7000 if (dca_add_requester(dev) == 0) { 7001 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7002 dev_info(&pdev->dev, "DCA enabled\n"); 7003 igb_setup_dca(adapter); 7004 break; 7005 } 7006 fallthrough; /* since DCA is disabled. */ 7007 case DCA_PROVIDER_REMOVE: 7008 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7009 /* without this a class_device is left 7010 * hanging around in the sysfs model 7011 */ 7012 dca_remove_requester(dev); 7013 dev_info(&pdev->dev, "DCA disabled\n"); 7014 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7015 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7016 } 7017 break; 7018 } 7019 7020 return 0; 7021} 7022 7023static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7024 void *p) 7025{ 7026 int ret_val; 7027 7028 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7029 __igb_notify_dca); 7030 7031 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7032} 7033#endif /* CONFIG_IGB_DCA */ 7034 7035#ifdef CONFIG_PCI_IOV 7036static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7037{ 7038 unsigned char mac_addr[ETH_ALEN]; 7039 7040 eth_zero_addr(mac_addr); 7041 igb_set_vf_mac(adapter, vf, mac_addr); 7042 7043 /* By default spoof check is enabled for all VFs */ 7044 adapter->vf_data[vf].spoofchk_enabled = true; 7045 7046 /* By default VFs are not trusted */ 7047 adapter->vf_data[vf].trusted = false; 7048 7049 return 0; 7050} 7051 7052#endif 7053static void igb_ping_all_vfs(struct igb_adapter *adapter) 7054{ 7055 struct e1000_hw *hw = &adapter->hw; 7056 u32 ping; 7057 int i; 7058 7059 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7060 ping = E1000_PF_CONTROL_MSG; 7061 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7062 ping |= E1000_VT_MSGTYPE_CTS; 7063 igb_write_mbx(hw, &ping, 1, i); 7064 } 7065} 7066 7067static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7068{ 7069 struct e1000_hw *hw = &adapter->hw; 7070 u32 vmolr = rd32(E1000_VMOLR(vf)); 7071 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7072 7073 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7074 IGB_VF_FLAG_MULTI_PROMISC); 7075 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7076 7077 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7078 vmolr |= E1000_VMOLR_MPME; 7079 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7080 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7081 } else { 7082 /* if we have hashes and we are clearing a multicast promisc 7083 * flag we need to write the hashes to the MTA as this step 7084 * was previously skipped 7085 */ 7086 if (vf_data->num_vf_mc_hashes > 30) { 7087 vmolr |= E1000_VMOLR_MPME; 7088 } else if (vf_data->num_vf_mc_hashes) { 7089 int j; 7090 7091 vmolr |= E1000_VMOLR_ROMPE; 7092 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7093 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7094 } 7095 } 7096 7097 wr32(E1000_VMOLR(vf), vmolr); 7098 7099 /* there are flags left unprocessed, likely not supported */ 7100 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7101 return -EINVAL; 7102 7103 return 0; 7104} 7105 7106static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7107 u32 *msgbuf, u32 vf) 7108{ 7109 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7110 u16 *hash_list = (u16 *)&msgbuf[1]; 7111 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7112 int i; 7113 7114 /* salt away the number of multicast addresses assigned 7115 * to this VF for later use to restore when the PF multi cast 7116 * list changes 7117 */ 7118 vf_data->num_vf_mc_hashes = n; 7119 7120 /* only up to 30 hash values supported */ 7121 if (n > 30) 7122 n = 30; 7123 7124 /* store the hashes for later use */ 7125 for (i = 0; i < n; i++) 7126 vf_data->vf_mc_hashes[i] = hash_list[i]; 7127 7128 /* Flush and reset the mta with the new values */ 7129 igb_set_rx_mode(adapter->netdev); 7130 7131 return 0; 7132} 7133 7134static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7135{ 7136 struct e1000_hw *hw = &adapter->hw; 7137 struct vf_data_storage *vf_data; 7138 int i, j; 7139 7140 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7141 u32 vmolr = rd32(E1000_VMOLR(i)); 7142 7143 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7144 7145 vf_data = &adapter->vf_data[i]; 7146 7147 if ((vf_data->num_vf_mc_hashes > 30) || 7148 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7149 vmolr |= E1000_VMOLR_MPME; 7150 } else if (vf_data->num_vf_mc_hashes) { 7151 vmolr |= E1000_VMOLR_ROMPE; 7152 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7153 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7154 } 7155 wr32(E1000_VMOLR(i), vmolr); 7156 } 7157} 7158 7159static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7160{ 7161 struct e1000_hw *hw = &adapter->hw; 7162 u32 pool_mask, vlvf_mask, i; 7163 7164 /* create mask for VF and other pools */ 7165 pool_mask = E1000_VLVF_POOLSEL_MASK; 7166 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7167 7168 /* drop PF from pool bits */ 7169 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7170 adapter->vfs_allocated_count); 7171 7172 /* Find the vlan filter for this id */ 7173 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7174 u32 vlvf = rd32(E1000_VLVF(i)); 7175 u32 vfta_mask, vid, vfta; 7176 7177 /* remove the vf from the pool */ 7178 if (!(vlvf & vlvf_mask)) 7179 continue; 7180 7181 /* clear out bit from VLVF */ 7182 vlvf ^= vlvf_mask; 7183 7184 /* if other pools are present, just remove ourselves */ 7185 if (vlvf & pool_mask) 7186 goto update_vlvfb; 7187 7188 /* if PF is present, leave VFTA */ 7189 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7190 goto update_vlvf; 7191 7192 vid = vlvf & E1000_VLVF_VLANID_MASK; 7193 vfta_mask = BIT(vid % 32); 7194 7195 /* clear bit from VFTA */ 7196 vfta = adapter->shadow_vfta[vid / 32]; 7197 if (vfta & vfta_mask) 7198 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7199update_vlvf: 7200 /* clear pool selection enable */ 7201 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7202 vlvf &= E1000_VLVF_POOLSEL_MASK; 7203 else 7204 vlvf = 0; 7205update_vlvfb: 7206 /* clear pool bits */ 7207 wr32(E1000_VLVF(i), vlvf); 7208 } 7209} 7210 7211static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7212{ 7213 u32 vlvf; 7214 int idx; 7215 7216 /* short cut the special case */ 7217 if (vlan == 0) 7218 return 0; 7219 7220 /* Search for the VLAN id in the VLVF entries */ 7221 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7222 vlvf = rd32(E1000_VLVF(idx)); 7223 if ((vlvf & VLAN_VID_MASK) == vlan) 7224 break; 7225 } 7226 7227 return idx; 7228} 7229 7230static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7231{ 7232 struct e1000_hw *hw = &adapter->hw; 7233 u32 bits, pf_id; 7234 int idx; 7235 7236 idx = igb_find_vlvf_entry(hw, vid); 7237 if (!idx) 7238 return; 7239 7240 /* See if any other pools are set for this VLAN filter 7241 * entry other than the PF. 7242 */ 7243 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7244 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7245 bits &= rd32(E1000_VLVF(idx)); 7246 7247 /* Disable the filter so this falls into the default pool. */ 7248 if (!bits) { 7249 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7250 wr32(E1000_VLVF(idx), BIT(pf_id)); 7251 else 7252 wr32(E1000_VLVF(idx), 0); 7253 } 7254} 7255 7256static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7257 bool add, u32 vf) 7258{ 7259 int pf_id = adapter->vfs_allocated_count; 7260 struct e1000_hw *hw = &adapter->hw; 7261 int err; 7262 7263 /* If VLAN overlaps with one the PF is currently monitoring make 7264 * sure that we are able to allocate a VLVF entry. This may be 7265 * redundant but it guarantees PF will maintain visibility to 7266 * the VLAN. 7267 */ 7268 if (add && test_bit(vid, adapter->active_vlans)) { 7269 err = igb_vfta_set(hw, vid, pf_id, true, false); 7270 if (err) 7271 return err; 7272 } 7273 7274 err = igb_vfta_set(hw, vid, vf, add, false); 7275 7276 if (add && !err) 7277 return err; 7278 7279 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7280 * we may need to drop the PF pool bit in order to allow us to free 7281 * up the VLVF resources. 7282 */ 7283 if (test_bit(vid, adapter->active_vlans) || 7284 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7285 igb_update_pf_vlvf(adapter, vid); 7286 7287 return err; 7288} 7289 7290static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7291{ 7292 struct e1000_hw *hw = &adapter->hw; 7293 7294 if (vid) 7295 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7296 else 7297 wr32(E1000_VMVIR(vf), 0); 7298} 7299 7300static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7301 u16 vlan, u8 qos) 7302{ 7303 int err; 7304 7305 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7306 if (err) 7307 return err; 7308 7309 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7310 igb_set_vmolr(adapter, vf, !vlan); 7311 7312 /* revoke access to previous VLAN */ 7313 if (vlan != adapter->vf_data[vf].pf_vlan) 7314 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7315 false, vf); 7316 7317 adapter->vf_data[vf].pf_vlan = vlan; 7318 adapter->vf_data[vf].pf_qos = qos; 7319 igb_set_vf_vlan_strip(adapter, vf, true); 7320 dev_info(&adapter->pdev->dev, 7321 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7322 if (test_bit(__IGB_DOWN, &adapter->state)) { 7323 dev_warn(&adapter->pdev->dev, 7324 "The VF VLAN has been set, but the PF device is not up.\n"); 7325 dev_warn(&adapter->pdev->dev, 7326 "Bring the PF device up before attempting to use the VF device.\n"); 7327 } 7328 7329 return err; 7330} 7331 7332static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7333{ 7334 /* Restore tagless access via VLAN 0 */ 7335 igb_set_vf_vlan(adapter, 0, true, vf); 7336 7337 igb_set_vmvir(adapter, 0, vf); 7338 igb_set_vmolr(adapter, vf, true); 7339 7340 /* Remove any PF assigned VLAN */ 7341 if (adapter->vf_data[vf].pf_vlan) 7342 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7343 false, vf); 7344 7345 adapter->vf_data[vf].pf_vlan = 0; 7346 adapter->vf_data[vf].pf_qos = 0; 7347 igb_set_vf_vlan_strip(adapter, vf, false); 7348 7349 return 0; 7350} 7351 7352static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7353 u16 vlan, u8 qos, __be16 vlan_proto) 7354{ 7355 struct igb_adapter *adapter = netdev_priv(netdev); 7356 7357 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7358 return -EINVAL; 7359 7360 if (vlan_proto != htons(ETH_P_8021Q)) 7361 return -EPROTONOSUPPORT; 7362 7363 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7364 igb_disable_port_vlan(adapter, vf); 7365} 7366 7367static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7368{ 7369 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7370 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7371 int ret; 7372 7373 if (adapter->vf_data[vf].pf_vlan) 7374 return -1; 7375 7376 /* VLAN 0 is a special case, don't allow it to be removed */ 7377 if (!vid && !add) 7378 return 0; 7379 7380 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7381 if (!ret) 7382 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7383 return ret; 7384} 7385 7386static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7387{ 7388 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7389 7390 /* clear flags - except flag that indicates PF has set the MAC */ 7391 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7392 vf_data->last_nack = jiffies; 7393 7394 /* reset vlans for device */ 7395 igb_clear_vf_vfta(adapter, vf); 7396 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7397 igb_set_vmvir(adapter, vf_data->pf_vlan | 7398 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7399 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7400 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7401 7402 /* reset multicast table array for vf */ 7403 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7404 7405 /* Flush and reset the mta with the new values */ 7406 igb_set_rx_mode(adapter->netdev); 7407} 7408 7409static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7410{ 7411 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7412 7413 /* clear mac address as we were hotplug removed/added */ 7414 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7415 eth_zero_addr(vf_mac); 7416 7417 /* process remaining reset events */ 7418 igb_vf_reset(adapter, vf); 7419} 7420 7421static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7422{ 7423 struct e1000_hw *hw = &adapter->hw; 7424 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7425 u32 reg, msgbuf[3] = {}; 7426 u8 *addr = (u8 *)(&msgbuf[1]); 7427 7428 /* process all the same items cleared in a function level reset */ 7429 igb_vf_reset(adapter, vf); 7430 7431 /* set vf mac address */ 7432 igb_set_vf_mac(adapter, vf, vf_mac); 7433 7434 /* enable transmit and receive for vf */ 7435 reg = rd32(E1000_VFTE); 7436 wr32(E1000_VFTE, reg | BIT(vf)); 7437 reg = rd32(E1000_VFRE); 7438 wr32(E1000_VFRE, reg | BIT(vf)); 7439 7440 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7441 7442 /* reply to reset with ack and vf mac address */ 7443 if (!is_zero_ether_addr(vf_mac)) { 7444 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7445 memcpy(addr, vf_mac, ETH_ALEN); 7446 } else { 7447 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7448 } 7449 igb_write_mbx(hw, msgbuf, 3, vf); 7450} 7451 7452static void igb_flush_mac_table(struct igb_adapter *adapter) 7453{ 7454 struct e1000_hw *hw = &adapter->hw; 7455 int i; 7456 7457 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7458 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7459 eth_zero_addr(adapter->mac_table[i].addr); 7460 adapter->mac_table[i].queue = 0; 7461 igb_rar_set_index(adapter, i); 7462 } 7463} 7464 7465static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7466{ 7467 struct e1000_hw *hw = &adapter->hw; 7468 /* do not count rar entries reserved for VFs MAC addresses */ 7469 int rar_entries = hw->mac.rar_entry_count - 7470 adapter->vfs_allocated_count; 7471 int i, count = 0; 7472 7473 for (i = 0; i < rar_entries; i++) { 7474 /* do not count default entries */ 7475 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7476 continue; 7477 7478 /* do not count "in use" entries for different queues */ 7479 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7480 (adapter->mac_table[i].queue != queue)) 7481 continue; 7482 7483 count++; 7484 } 7485 7486 return count; 7487} 7488 7489/* Set default MAC address for the PF in the first RAR entry */ 7490static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7491{ 7492 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7493 7494 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7495 mac_table->queue = adapter->vfs_allocated_count; 7496 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7497 7498 igb_rar_set_index(adapter, 0); 7499} 7500 7501/* If the filter to be added and an already existing filter express 7502 * the same address and address type, it should be possible to only 7503 * override the other configurations, for example the queue to steer 7504 * traffic. 7505 */ 7506static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7507 const u8 *addr, const u8 flags) 7508{ 7509 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7510 return true; 7511 7512 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7513 (flags & IGB_MAC_STATE_SRC_ADDR)) 7514 return false; 7515 7516 if (!ether_addr_equal(addr, entry->addr)) 7517 return false; 7518 7519 return true; 7520} 7521 7522/* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7523 * 'flags' is used to indicate what kind of match is made, match is by 7524 * default for the destination address, if matching by source address 7525 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7526 */ 7527static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7528 const u8 *addr, const u8 queue, 7529 const u8 flags) 7530{ 7531 struct e1000_hw *hw = &adapter->hw; 7532 int rar_entries = hw->mac.rar_entry_count - 7533 adapter->vfs_allocated_count; 7534 int i; 7535 7536 if (is_zero_ether_addr(addr)) 7537 return -EINVAL; 7538 7539 /* Search for the first empty entry in the MAC table. 7540 * Do not touch entries at the end of the table reserved for the VF MAC 7541 * addresses. 7542 */ 7543 for (i = 0; i < rar_entries; i++) { 7544 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7545 addr, flags)) 7546 continue; 7547 7548 ether_addr_copy(adapter->mac_table[i].addr, addr); 7549 adapter->mac_table[i].queue = queue; 7550 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7551 7552 igb_rar_set_index(adapter, i); 7553 return i; 7554 } 7555 7556 return -ENOSPC; 7557} 7558 7559static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7560 const u8 queue) 7561{ 7562 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7563} 7564 7565/* Remove a MAC filter for 'addr' directing matching traffic to 7566 * 'queue', 'flags' is used to indicate what kind of match need to be 7567 * removed, match is by default for the destination address, if 7568 * matching by source address is to be removed the flag 7569 * IGB_MAC_STATE_SRC_ADDR can be used. 7570 */ 7571static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7572 const u8 *addr, const u8 queue, 7573 const u8 flags) 7574{ 7575 struct e1000_hw *hw = &adapter->hw; 7576 int rar_entries = hw->mac.rar_entry_count - 7577 adapter->vfs_allocated_count; 7578 int i; 7579 7580 if (is_zero_ether_addr(addr)) 7581 return -EINVAL; 7582 7583 /* Search for matching entry in the MAC table based on given address 7584 * and queue. Do not touch entries at the end of the table reserved 7585 * for the VF MAC addresses. 7586 */ 7587 for (i = 0; i < rar_entries; i++) { 7588 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7589 continue; 7590 if ((adapter->mac_table[i].state & flags) != flags) 7591 continue; 7592 if (adapter->mac_table[i].queue != queue) 7593 continue; 7594 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7595 continue; 7596 7597 /* When a filter for the default address is "deleted", 7598 * we return it to its initial configuration 7599 */ 7600 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7601 adapter->mac_table[i].state = 7602 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7603 adapter->mac_table[i].queue = 7604 adapter->vfs_allocated_count; 7605 } else { 7606 adapter->mac_table[i].state = 0; 7607 adapter->mac_table[i].queue = 0; 7608 eth_zero_addr(adapter->mac_table[i].addr); 7609 } 7610 7611 igb_rar_set_index(adapter, i); 7612 return 0; 7613 } 7614 7615 return -ENOENT; 7616} 7617 7618static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7619 const u8 queue) 7620{ 7621 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7622} 7623 7624int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7625 const u8 *addr, u8 queue, u8 flags) 7626{ 7627 struct e1000_hw *hw = &adapter->hw; 7628 7629 /* In theory, this should be supported on 82575 as well, but 7630 * that part wasn't easily accessible during development. 7631 */ 7632 if (hw->mac.type != e1000_i210) 7633 return -EOPNOTSUPP; 7634 7635 return igb_add_mac_filter_flags(adapter, addr, queue, 7636 IGB_MAC_STATE_QUEUE_STEERING | flags); 7637} 7638 7639int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7640 const u8 *addr, u8 queue, u8 flags) 7641{ 7642 return igb_del_mac_filter_flags(adapter, addr, queue, 7643 IGB_MAC_STATE_QUEUE_STEERING | flags); 7644} 7645 7646static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7647{ 7648 struct igb_adapter *adapter = netdev_priv(netdev); 7649 int ret; 7650 7651 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7652 7653 return min_t(int, ret, 0); 7654} 7655 7656static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7657{ 7658 struct igb_adapter *adapter = netdev_priv(netdev); 7659 7660 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7661 7662 return 0; 7663} 7664 7665static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7666 const u32 info, const u8 *addr) 7667{ 7668 struct pci_dev *pdev = adapter->pdev; 7669 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7670 struct list_head *pos; 7671 struct vf_mac_filter *entry = NULL; 7672 int ret = 0; 7673 7674 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7675 !vf_data->trusted) { 7676 dev_warn(&pdev->dev, 7677 "VF %d requested MAC filter but is administratively denied\n", 7678 vf); 7679 return -EINVAL; 7680 } 7681 if (!is_valid_ether_addr(addr)) { 7682 dev_warn(&pdev->dev, 7683 "VF %d attempted to set invalid MAC filter\n", 7684 vf); 7685 return -EINVAL; 7686 } 7687 7688 switch (info) { 7689 case E1000_VF_MAC_FILTER_CLR: 7690 /* remove all unicast MAC filters related to the current VF */ 7691 list_for_each(pos, &adapter->vf_macs.l) { 7692 entry = list_entry(pos, struct vf_mac_filter, l); 7693 if (entry->vf == vf) { 7694 entry->vf = -1; 7695 entry->free = true; 7696 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7697 } 7698 } 7699 break; 7700 case E1000_VF_MAC_FILTER_ADD: 7701 /* try to find empty slot in the list */ 7702 list_for_each(pos, &adapter->vf_macs.l) { 7703 entry = list_entry(pos, struct vf_mac_filter, l); 7704 if (entry->free) 7705 break; 7706 } 7707 7708 if (entry && entry->free) { 7709 entry->free = false; 7710 entry->vf = vf; 7711 ether_addr_copy(entry->vf_mac, addr); 7712 7713 ret = igb_add_mac_filter(adapter, addr, vf); 7714 ret = min_t(int, ret, 0); 7715 } else { 7716 ret = -ENOSPC; 7717 } 7718 7719 if (ret == -ENOSPC) 7720 dev_warn(&pdev->dev, 7721 "VF %d has requested MAC filter but there is no space for it\n", 7722 vf); 7723 break; 7724 default: 7725 ret = -EINVAL; 7726 break; 7727 } 7728 7729 return ret; 7730} 7731 7732static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7733{ 7734 struct pci_dev *pdev = adapter->pdev; 7735 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7736 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7737 7738 /* The VF MAC Address is stored in a packed array of bytes 7739 * starting at the second 32 bit word of the msg array 7740 */ 7741 unsigned char *addr = (unsigned char *)&msg[1]; 7742 int ret = 0; 7743 7744 if (!info) { 7745 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7746 !vf_data->trusted) { 7747 dev_warn(&pdev->dev, 7748 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7749 vf); 7750 return -EINVAL; 7751 } 7752 7753 if (!is_valid_ether_addr(addr)) { 7754 dev_warn(&pdev->dev, 7755 "VF %d attempted to set invalid MAC\n", 7756 vf); 7757 return -EINVAL; 7758 } 7759 7760 ret = igb_set_vf_mac(adapter, vf, addr); 7761 } else { 7762 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7763 } 7764 7765 return ret; 7766} 7767 7768static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7769{ 7770 struct e1000_hw *hw = &adapter->hw; 7771 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7772 u32 msg = E1000_VT_MSGTYPE_NACK; 7773 7774 /* if device isn't clear to send it shouldn't be reading either */ 7775 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7776 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7777 igb_write_mbx(hw, &msg, 1, vf); 7778 vf_data->last_nack = jiffies; 7779 } 7780} 7781 7782static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7783{ 7784 struct pci_dev *pdev = adapter->pdev; 7785 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7786 struct e1000_hw *hw = &adapter->hw; 7787 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7788 s32 retval; 7789 7790 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7791 7792 if (retval) { 7793 /* if receive failed revoke VF CTS stats and restart init */ 7794 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7795 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7796 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7797 goto unlock; 7798 goto out; 7799 } 7800 7801 /* this is a message we already processed, do nothing */ 7802 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7803 goto unlock; 7804 7805 /* until the vf completes a reset it should not be 7806 * allowed to start any configuration. 7807 */ 7808 if (msgbuf[0] == E1000_VF_RESET) { 7809 /* unlocks mailbox */ 7810 igb_vf_reset_msg(adapter, vf); 7811 return; 7812 } 7813 7814 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7815 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7816 goto unlock; 7817 retval = -1; 7818 goto out; 7819 } 7820 7821 switch ((msgbuf[0] & 0xFFFF)) { 7822 case E1000_VF_SET_MAC_ADDR: 7823 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7824 break; 7825 case E1000_VF_SET_PROMISC: 7826 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7827 break; 7828 case E1000_VF_SET_MULTICAST: 7829 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7830 break; 7831 case E1000_VF_SET_LPE: 7832 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7833 break; 7834 case E1000_VF_SET_VLAN: 7835 retval = -1; 7836 if (vf_data->pf_vlan) 7837 dev_warn(&pdev->dev, 7838 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7839 vf); 7840 else 7841 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7842 break; 7843 default: 7844 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7845 retval = -1; 7846 break; 7847 } 7848 7849 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7850out: 7851 /* notify the VF of the results of what it sent us */ 7852 if (retval) 7853 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7854 else 7855 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7856 7857 /* unlocks mailbox */ 7858 igb_write_mbx(hw, msgbuf, 1, vf); 7859 return; 7860 7861unlock: 7862 igb_unlock_mbx(hw, vf); 7863} 7864 7865static void igb_msg_task(struct igb_adapter *adapter) 7866{ 7867 struct e1000_hw *hw = &adapter->hw; 7868 unsigned long flags; 7869 u32 vf; 7870 7871 spin_lock_irqsave(&adapter->vfs_lock, flags); 7872 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7873 /* process any reset requests */ 7874 if (!igb_check_for_rst(hw, vf)) 7875 igb_vf_reset_event(adapter, vf); 7876 7877 /* process any messages pending */ 7878 if (!igb_check_for_msg(hw, vf)) 7879 igb_rcv_msg_from_vf(adapter, vf); 7880 7881 /* process any acks */ 7882 if (!igb_check_for_ack(hw, vf)) 7883 igb_rcv_ack_from_vf(adapter, vf); 7884 } 7885 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 7886} 7887 7888/** 7889 * igb_set_uta - Set unicast filter table address 7890 * @adapter: board private structure 7891 * @set: boolean indicating if we are setting or clearing bits 7892 * 7893 * The unicast table address is a register array of 32-bit registers. 7894 * The table is meant to be used in a way similar to how the MTA is used 7895 * however due to certain limitations in the hardware it is necessary to 7896 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7897 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7898 **/ 7899static void igb_set_uta(struct igb_adapter *adapter, bool set) 7900{ 7901 struct e1000_hw *hw = &adapter->hw; 7902 u32 uta = set ? ~0 : 0; 7903 int i; 7904 7905 /* we only need to do this if VMDq is enabled */ 7906 if (!adapter->vfs_allocated_count) 7907 return; 7908 7909 for (i = hw->mac.uta_reg_count; i--;) 7910 array_wr32(E1000_UTA, i, uta); 7911} 7912 7913/** 7914 * igb_intr_msi - Interrupt Handler 7915 * @irq: interrupt number 7916 * @data: pointer to a network interface device structure 7917 **/ 7918static irqreturn_t igb_intr_msi(int irq, void *data) 7919{ 7920 struct igb_adapter *adapter = data; 7921 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7922 struct e1000_hw *hw = &adapter->hw; 7923 /* read ICR disables interrupts using IAM */ 7924 u32 icr = rd32(E1000_ICR); 7925 7926 igb_write_itr(q_vector); 7927 7928 if (icr & E1000_ICR_DRSTA) 7929 schedule_work(&adapter->reset_task); 7930 7931 if (icr & E1000_ICR_DOUTSYNC) { 7932 /* HW is reporting DMA is out of sync */ 7933 adapter->stats.doosync++; 7934 } 7935 7936 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7937 hw->mac.get_link_status = 1; 7938 if (!test_bit(__IGB_DOWN, &adapter->state)) 7939 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7940 } 7941 7942 if (icr & E1000_ICR_TS) 7943 igb_tsync_interrupt(adapter); 7944 7945 napi_schedule(&q_vector->napi); 7946 7947 return IRQ_HANDLED; 7948} 7949 7950/** 7951 * igb_intr - Legacy Interrupt Handler 7952 * @irq: interrupt number 7953 * @data: pointer to a network interface device structure 7954 **/ 7955static irqreturn_t igb_intr(int irq, void *data) 7956{ 7957 struct igb_adapter *adapter = data; 7958 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7959 struct e1000_hw *hw = &adapter->hw; 7960 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7961 * need for the IMC write 7962 */ 7963 u32 icr = rd32(E1000_ICR); 7964 7965 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7966 * not set, then the adapter didn't send an interrupt 7967 */ 7968 if (!(icr & E1000_ICR_INT_ASSERTED)) 7969 return IRQ_NONE; 7970 7971 igb_write_itr(q_vector); 7972 7973 if (icr & E1000_ICR_DRSTA) 7974 schedule_work(&adapter->reset_task); 7975 7976 if (icr & E1000_ICR_DOUTSYNC) { 7977 /* HW is reporting DMA is out of sync */ 7978 adapter->stats.doosync++; 7979 } 7980 7981 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7982 hw->mac.get_link_status = 1; 7983 /* guard against interrupt when we're going down */ 7984 if (!test_bit(__IGB_DOWN, &adapter->state)) 7985 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7986 } 7987 7988 if (icr & E1000_ICR_TS) 7989 igb_tsync_interrupt(adapter); 7990 7991 napi_schedule(&q_vector->napi); 7992 7993 return IRQ_HANDLED; 7994} 7995 7996static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7997{ 7998 struct igb_adapter *adapter = q_vector->adapter; 7999 struct e1000_hw *hw = &adapter->hw; 8000 8001 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8002 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8003 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8004 igb_set_itr(q_vector); 8005 else 8006 igb_update_ring_itr(q_vector); 8007 } 8008 8009 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8010 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8011 wr32(E1000_EIMS, q_vector->eims_value); 8012 else 8013 igb_irq_enable(adapter); 8014 } 8015} 8016 8017/** 8018 * igb_poll - NAPI Rx polling callback 8019 * @napi: napi polling structure 8020 * @budget: count of how many packets we should handle 8021 **/ 8022static int igb_poll(struct napi_struct *napi, int budget) 8023{ 8024 struct igb_q_vector *q_vector = container_of(napi, 8025 struct igb_q_vector, 8026 napi); 8027 bool clean_complete = true; 8028 int work_done = 0; 8029 8030#ifdef CONFIG_IGB_DCA 8031 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8032 igb_update_dca(q_vector); 8033#endif 8034 if (q_vector->tx.ring) 8035 clean_complete = igb_clean_tx_irq(q_vector, budget); 8036 8037 if (q_vector->rx.ring) { 8038 int cleaned = igb_clean_rx_irq(q_vector, budget); 8039 8040 work_done += cleaned; 8041 if (cleaned >= budget) 8042 clean_complete = false; 8043 } 8044 8045 /* If all work not completed, return budget and keep polling */ 8046 if (!clean_complete) 8047 return budget; 8048 8049 /* Exit the polling mode, but don't re-enable interrupts if stack might 8050 * poll us due to busy-polling 8051 */ 8052 if (likely(napi_complete_done(napi, work_done))) 8053 igb_ring_irq_enable(q_vector); 8054 8055 return work_done; 8056} 8057 8058/** 8059 * igb_clean_tx_irq - Reclaim resources after transmit completes 8060 * @q_vector: pointer to q_vector containing needed info 8061 * @napi_budget: Used to determine if we are in netpoll 8062 * 8063 * returns true if ring is completely cleaned 8064 **/ 8065static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8066{ 8067 struct igb_adapter *adapter = q_vector->adapter; 8068 struct igb_ring *tx_ring = q_vector->tx.ring; 8069 struct igb_tx_buffer *tx_buffer; 8070 union e1000_adv_tx_desc *tx_desc; 8071 unsigned int total_bytes = 0, total_packets = 0; 8072 unsigned int budget = q_vector->tx.work_limit; 8073 unsigned int i = tx_ring->next_to_clean; 8074 8075 if (test_bit(__IGB_DOWN, &adapter->state)) 8076 return true; 8077 8078 tx_buffer = &tx_ring->tx_buffer_info[i]; 8079 tx_desc = IGB_TX_DESC(tx_ring, i); 8080 i -= tx_ring->count; 8081 8082 do { 8083 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8084 8085 /* if next_to_watch is not set then there is no work pending */ 8086 if (!eop_desc) 8087 break; 8088 8089 /* prevent any other reads prior to eop_desc */ 8090 smp_rmb(); 8091 8092 /* if DD is not set pending work has not been completed */ 8093 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8094 break; 8095 8096 /* clear next_to_watch to prevent false hangs */ 8097 tx_buffer->next_to_watch = NULL; 8098 8099 /* update the statistics for this packet */ 8100 total_bytes += tx_buffer->bytecount; 8101 total_packets += tx_buffer->gso_segs; 8102 8103 /* free the skb */ 8104 if (tx_buffer->type == IGB_TYPE_SKB) 8105 napi_consume_skb(tx_buffer->skb, napi_budget); 8106 else 8107 xdp_return_frame(tx_buffer->xdpf); 8108 8109 /* unmap skb header data */ 8110 dma_unmap_single(tx_ring->dev, 8111 dma_unmap_addr(tx_buffer, dma), 8112 dma_unmap_len(tx_buffer, len), 8113 DMA_TO_DEVICE); 8114 8115 /* clear tx_buffer data */ 8116 dma_unmap_len_set(tx_buffer, len, 0); 8117 8118 /* clear last DMA location and unmap remaining buffers */ 8119 while (tx_desc != eop_desc) { 8120 tx_buffer++; 8121 tx_desc++; 8122 i++; 8123 if (unlikely(!i)) { 8124 i -= tx_ring->count; 8125 tx_buffer = tx_ring->tx_buffer_info; 8126 tx_desc = IGB_TX_DESC(tx_ring, 0); 8127 } 8128 8129 /* unmap any remaining paged data */ 8130 if (dma_unmap_len(tx_buffer, len)) { 8131 dma_unmap_page(tx_ring->dev, 8132 dma_unmap_addr(tx_buffer, dma), 8133 dma_unmap_len(tx_buffer, len), 8134 DMA_TO_DEVICE); 8135 dma_unmap_len_set(tx_buffer, len, 0); 8136 } 8137 } 8138 8139 /* move us one more past the eop_desc for start of next pkt */ 8140 tx_buffer++; 8141 tx_desc++; 8142 i++; 8143 if (unlikely(!i)) { 8144 i -= tx_ring->count; 8145 tx_buffer = tx_ring->tx_buffer_info; 8146 tx_desc = IGB_TX_DESC(tx_ring, 0); 8147 } 8148 8149 /* issue prefetch for next Tx descriptor */ 8150 prefetch(tx_desc); 8151 8152 /* update budget accounting */ 8153 budget--; 8154 } while (likely(budget)); 8155 8156 netdev_tx_completed_queue(txring_txq(tx_ring), 8157 total_packets, total_bytes); 8158 i += tx_ring->count; 8159 tx_ring->next_to_clean = i; 8160 u64_stats_update_begin(&tx_ring->tx_syncp); 8161 tx_ring->tx_stats.bytes += total_bytes; 8162 tx_ring->tx_stats.packets += total_packets; 8163 u64_stats_update_end(&tx_ring->tx_syncp); 8164 q_vector->tx.total_bytes += total_bytes; 8165 q_vector->tx.total_packets += total_packets; 8166 8167 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8168 struct e1000_hw *hw = &adapter->hw; 8169 8170 /* Detect a transmit hang in hardware, this serializes the 8171 * check with the clearing of time_stamp and movement of i 8172 */ 8173 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8174 if (tx_buffer->next_to_watch && 8175 time_after(jiffies, tx_buffer->time_stamp + 8176 (adapter->tx_timeout_factor * HZ)) && 8177 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8178 8179 /* detected Tx unit hang */ 8180 dev_err(tx_ring->dev, 8181 "Detected Tx Unit Hang\n" 8182 " Tx Queue <%d>\n" 8183 " TDH <%x>\n" 8184 " TDT <%x>\n" 8185 " next_to_use <%x>\n" 8186 " next_to_clean <%x>\n" 8187 "buffer_info[next_to_clean]\n" 8188 " time_stamp <%lx>\n" 8189 " next_to_watch <%p>\n" 8190 " jiffies <%lx>\n" 8191 " desc.status <%x>\n", 8192 tx_ring->queue_index, 8193 rd32(E1000_TDH(tx_ring->reg_idx)), 8194 readl(tx_ring->tail), 8195 tx_ring->next_to_use, 8196 tx_ring->next_to_clean, 8197 tx_buffer->time_stamp, 8198 tx_buffer->next_to_watch, 8199 jiffies, 8200 tx_buffer->next_to_watch->wb.status); 8201 netif_stop_subqueue(tx_ring->netdev, 8202 tx_ring->queue_index); 8203 8204 /* we are about to reset, no point in enabling stuff */ 8205 return true; 8206 } 8207 } 8208 8209#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8210 if (unlikely(total_packets && 8211 netif_carrier_ok(tx_ring->netdev) && 8212 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8213 /* Make sure that anybody stopping the queue after this 8214 * sees the new next_to_clean. 8215 */ 8216 smp_mb(); 8217 if (__netif_subqueue_stopped(tx_ring->netdev, 8218 tx_ring->queue_index) && 8219 !(test_bit(__IGB_DOWN, &adapter->state))) { 8220 netif_wake_subqueue(tx_ring->netdev, 8221 tx_ring->queue_index); 8222 8223 u64_stats_update_begin(&tx_ring->tx_syncp); 8224 tx_ring->tx_stats.restart_queue++; 8225 u64_stats_update_end(&tx_ring->tx_syncp); 8226 } 8227 } 8228 8229 return !!budget; 8230} 8231 8232/** 8233 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8234 * @rx_ring: rx descriptor ring to store buffers on 8235 * @old_buff: donor buffer to have page reused 8236 * 8237 * Synchronizes page for reuse by the adapter 8238 **/ 8239static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8240 struct igb_rx_buffer *old_buff) 8241{ 8242 struct igb_rx_buffer *new_buff; 8243 u16 nta = rx_ring->next_to_alloc; 8244 8245 new_buff = &rx_ring->rx_buffer_info[nta]; 8246 8247 /* update, and store next to alloc */ 8248 nta++; 8249 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8250 8251 /* Transfer page from old buffer to new buffer. 8252 * Move each member individually to avoid possible store 8253 * forwarding stalls. 8254 */ 8255 new_buff->dma = old_buff->dma; 8256 new_buff->page = old_buff->page; 8257 new_buff->page_offset = old_buff->page_offset; 8258 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8259} 8260 8261static inline bool igb_page_is_reserved(struct page *page) 8262{ 8263 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 8264} 8265 8266static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8267 int rx_buf_pgcnt) 8268{ 8269 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8270 struct page *page = rx_buffer->page; 8271 8272 /* avoid re-using remote pages */ 8273 if (unlikely(igb_page_is_reserved(page))) 8274 return false; 8275 8276#if (PAGE_SIZE < 8192) 8277 /* if we are only owner of page we can reuse it */ 8278 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8279 return false; 8280#else 8281#define IGB_LAST_OFFSET \ 8282 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8283 8284 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8285 return false; 8286#endif 8287 8288 /* If we have drained the page fragment pool we need to update 8289 * the pagecnt_bias and page count so that we fully restock the 8290 * number of references the driver holds. 8291 */ 8292 if (unlikely(pagecnt_bias == 1)) { 8293 page_ref_add(page, USHRT_MAX - 1); 8294 rx_buffer->pagecnt_bias = USHRT_MAX; 8295 } 8296 8297 return true; 8298} 8299 8300/** 8301 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8302 * @rx_ring: rx descriptor ring to transact packets on 8303 * @rx_buffer: buffer containing page to add 8304 * @skb: sk_buff to place the data into 8305 * @size: size of buffer to be added 8306 * 8307 * This function will add the data contained in rx_buffer->page to the skb. 8308 **/ 8309static void igb_add_rx_frag(struct igb_ring *rx_ring, 8310 struct igb_rx_buffer *rx_buffer, 8311 struct sk_buff *skb, 8312 unsigned int size) 8313{ 8314#if (PAGE_SIZE < 8192) 8315 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8316#else 8317 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8318 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8319 SKB_DATA_ALIGN(size); 8320#endif 8321 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8322 rx_buffer->page_offset, size, truesize); 8323#if (PAGE_SIZE < 8192) 8324 rx_buffer->page_offset ^= truesize; 8325#else 8326 rx_buffer->page_offset += truesize; 8327#endif 8328} 8329 8330static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8331 struct igb_rx_buffer *rx_buffer, 8332 struct xdp_buff *xdp, 8333 union e1000_adv_rx_desc *rx_desc) 8334{ 8335#if (PAGE_SIZE < 8192) 8336 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8337#else 8338 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8339 xdp->data_hard_start); 8340#endif 8341 unsigned int size = xdp->data_end - xdp->data; 8342 unsigned int headlen; 8343 struct sk_buff *skb; 8344 8345 /* prefetch first cache line of first page */ 8346 net_prefetch(xdp->data); 8347 8348 /* allocate a skb to store the frags */ 8349 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8350 if (unlikely(!skb)) 8351 return NULL; 8352 8353 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8354 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, xdp->data, skb)) { 8355 xdp->data += IGB_TS_HDR_LEN; 8356 size -= IGB_TS_HDR_LEN; 8357 } 8358 } 8359 8360 /* Determine available headroom for copy */ 8361 headlen = size; 8362 if (headlen > IGB_RX_HDR_LEN) 8363 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8364 8365 /* align pull length to size of long to optimize memcpy performance */ 8366 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8367 8368 /* update all of the pointers */ 8369 size -= headlen; 8370 if (size) { 8371 skb_add_rx_frag(skb, 0, rx_buffer->page, 8372 (xdp->data + headlen) - page_address(rx_buffer->page), 8373 size, truesize); 8374#if (PAGE_SIZE < 8192) 8375 rx_buffer->page_offset ^= truesize; 8376#else 8377 rx_buffer->page_offset += truesize; 8378#endif 8379 } else { 8380 rx_buffer->pagecnt_bias++; 8381 } 8382 8383 return skb; 8384} 8385 8386static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8387 struct igb_rx_buffer *rx_buffer, 8388 struct xdp_buff *xdp, 8389 union e1000_adv_rx_desc *rx_desc) 8390{ 8391#if (PAGE_SIZE < 8192) 8392 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8393#else 8394 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8395 SKB_DATA_ALIGN(xdp->data_end - 8396 xdp->data_hard_start); 8397#endif 8398 unsigned int metasize = xdp->data - xdp->data_meta; 8399 struct sk_buff *skb; 8400 8401 /* prefetch first cache line of first page */ 8402 net_prefetch(xdp->data_meta); 8403 8404 /* build an skb around the page buffer */ 8405 skb = build_skb(xdp->data_hard_start, truesize); 8406 if (unlikely(!skb)) 8407 return NULL; 8408 8409 /* update pointers within the skb to store the data */ 8410 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8411 __skb_put(skb, xdp->data_end - xdp->data); 8412 8413 if (metasize) 8414 skb_metadata_set(skb, metasize); 8415 8416 /* pull timestamp out of packet data */ 8417 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8418 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb)) 8419 __skb_pull(skb, IGB_TS_HDR_LEN); 8420 } 8421 8422 /* update buffer offset */ 8423#if (PAGE_SIZE < 8192) 8424 rx_buffer->page_offset ^= truesize; 8425#else 8426 rx_buffer->page_offset += truesize; 8427#endif 8428 8429 return skb; 8430} 8431 8432static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8433 struct igb_ring *rx_ring, 8434 struct xdp_buff *xdp) 8435{ 8436 int err, result = IGB_XDP_PASS; 8437 struct bpf_prog *xdp_prog; 8438 u32 act; 8439 8440 rcu_read_lock(); 8441 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8442 8443 if (!xdp_prog) 8444 goto xdp_out; 8445 8446 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8447 8448 act = bpf_prog_run_xdp(xdp_prog, xdp); 8449 switch (act) { 8450 case XDP_PASS: 8451 break; 8452 case XDP_TX: 8453 result = igb_xdp_xmit_back(adapter, xdp); 8454 if (result == IGB_XDP_CONSUMED) 8455 goto out_failure; 8456 break; 8457 case XDP_REDIRECT: 8458 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8459 if (err) 8460 goto out_failure; 8461 result = IGB_XDP_REDIR; 8462 break; 8463 default: 8464 bpf_warn_invalid_xdp_action(act); 8465 fallthrough; 8466 case XDP_ABORTED: 8467out_failure: 8468 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8469 fallthrough; 8470 case XDP_DROP: 8471 result = IGB_XDP_CONSUMED; 8472 break; 8473 } 8474xdp_out: 8475 rcu_read_unlock(); 8476 return ERR_PTR(-result); 8477} 8478 8479static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8480 unsigned int size) 8481{ 8482 unsigned int truesize; 8483 8484#if (PAGE_SIZE < 8192) 8485 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8486#else 8487 truesize = ring_uses_build_skb(rx_ring) ? 8488 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8489 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8490 SKB_DATA_ALIGN(size); 8491#endif 8492 return truesize; 8493} 8494 8495static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8496 struct igb_rx_buffer *rx_buffer, 8497 unsigned int size) 8498{ 8499 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8500#if (PAGE_SIZE < 8192) 8501 rx_buffer->page_offset ^= truesize; 8502#else 8503 rx_buffer->page_offset += truesize; 8504#endif 8505} 8506 8507static inline void igb_rx_checksum(struct igb_ring *ring, 8508 union e1000_adv_rx_desc *rx_desc, 8509 struct sk_buff *skb) 8510{ 8511 skb_checksum_none_assert(skb); 8512 8513 /* Ignore Checksum bit is set */ 8514 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8515 return; 8516 8517 /* Rx checksum disabled via ethtool */ 8518 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8519 return; 8520 8521 /* TCP/UDP checksum error bit is set */ 8522 if (igb_test_staterr(rx_desc, 8523 E1000_RXDEXT_STATERR_TCPE | 8524 E1000_RXDEXT_STATERR_IPE)) { 8525 /* work around errata with sctp packets where the TCPE aka 8526 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8527 * packets, (aka let the stack check the crc32c) 8528 */ 8529 if (!((skb->len == 60) && 8530 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8531 u64_stats_update_begin(&ring->rx_syncp); 8532 ring->rx_stats.csum_err++; 8533 u64_stats_update_end(&ring->rx_syncp); 8534 } 8535 /* let the stack verify checksum errors */ 8536 return; 8537 } 8538 /* It must be a TCP or UDP packet with a valid checksum */ 8539 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8540 E1000_RXD_STAT_UDPCS)) 8541 skb->ip_summed = CHECKSUM_UNNECESSARY; 8542 8543 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8544 le32_to_cpu(rx_desc->wb.upper.status_error)); 8545} 8546 8547static inline void igb_rx_hash(struct igb_ring *ring, 8548 union e1000_adv_rx_desc *rx_desc, 8549 struct sk_buff *skb) 8550{ 8551 if (ring->netdev->features & NETIF_F_RXHASH) 8552 skb_set_hash(skb, 8553 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8554 PKT_HASH_TYPE_L3); 8555} 8556 8557/** 8558 * igb_is_non_eop - process handling of non-EOP buffers 8559 * @rx_ring: Rx ring being processed 8560 * @rx_desc: Rx descriptor for current buffer 8561 * 8562 * This function updates next to clean. If the buffer is an EOP buffer 8563 * this function exits returning false, otherwise it will place the 8564 * sk_buff in the next buffer to be chained and return true indicating 8565 * that this is in fact a non-EOP buffer. 8566 **/ 8567static bool igb_is_non_eop(struct igb_ring *rx_ring, 8568 union e1000_adv_rx_desc *rx_desc) 8569{ 8570 u32 ntc = rx_ring->next_to_clean + 1; 8571 8572 /* fetch, update, and store next to clean */ 8573 ntc = (ntc < rx_ring->count) ? ntc : 0; 8574 rx_ring->next_to_clean = ntc; 8575 8576 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8577 8578 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8579 return false; 8580 8581 return true; 8582} 8583 8584/** 8585 * igb_cleanup_headers - Correct corrupted or empty headers 8586 * @rx_ring: rx descriptor ring packet is being transacted on 8587 * @rx_desc: pointer to the EOP Rx descriptor 8588 * @skb: pointer to current skb being fixed 8589 * 8590 * Address the case where we are pulling data in on pages only 8591 * and as such no data is present in the skb header. 8592 * 8593 * In addition if skb is not at least 60 bytes we need to pad it so that 8594 * it is large enough to qualify as a valid Ethernet frame. 8595 * 8596 * Returns true if an error was encountered and skb was freed. 8597 **/ 8598static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8599 union e1000_adv_rx_desc *rx_desc, 8600 struct sk_buff *skb) 8601{ 8602 /* XDP packets use error pointer so abort at this point */ 8603 if (IS_ERR(skb)) 8604 return true; 8605 8606 if (unlikely((igb_test_staterr(rx_desc, 8607 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8608 struct net_device *netdev = rx_ring->netdev; 8609 if (!(netdev->features & NETIF_F_RXALL)) { 8610 dev_kfree_skb_any(skb); 8611 return true; 8612 } 8613 } 8614 8615 /* if eth_skb_pad returns an error the skb was freed */ 8616 if (eth_skb_pad(skb)) 8617 return true; 8618 8619 return false; 8620} 8621 8622/** 8623 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8624 * @rx_ring: rx descriptor ring packet is being transacted on 8625 * @rx_desc: pointer to the EOP Rx descriptor 8626 * @skb: pointer to current skb being populated 8627 * 8628 * This function checks the ring, descriptor, and packet information in 8629 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8630 * other fields within the skb. 8631 **/ 8632static void igb_process_skb_fields(struct igb_ring *rx_ring, 8633 union e1000_adv_rx_desc *rx_desc, 8634 struct sk_buff *skb) 8635{ 8636 struct net_device *dev = rx_ring->netdev; 8637 8638 igb_rx_hash(rx_ring, rx_desc, skb); 8639 8640 igb_rx_checksum(rx_ring, rx_desc, skb); 8641 8642 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8643 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8644 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8645 8646 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8647 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8648 u16 vid; 8649 8650 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8651 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8652 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8653 else 8654 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8655 8656 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8657 } 8658 8659 skb_record_rx_queue(skb, rx_ring->queue_index); 8660 8661 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8662} 8663 8664static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8665{ 8666 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8667} 8668 8669static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8670 const unsigned int size, int *rx_buf_pgcnt) 8671{ 8672 struct igb_rx_buffer *rx_buffer; 8673 8674 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8675 *rx_buf_pgcnt = 8676#if (PAGE_SIZE < 8192) 8677 page_count(rx_buffer->page); 8678#else 8679 0; 8680#endif 8681 prefetchw(rx_buffer->page); 8682 8683 /* we are reusing so sync this buffer for CPU use */ 8684 dma_sync_single_range_for_cpu(rx_ring->dev, 8685 rx_buffer->dma, 8686 rx_buffer->page_offset, 8687 size, 8688 DMA_FROM_DEVICE); 8689 8690 rx_buffer->pagecnt_bias--; 8691 8692 return rx_buffer; 8693} 8694 8695static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8696 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8697{ 8698 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8699 /* hand second half of page back to the ring */ 8700 igb_reuse_rx_page(rx_ring, rx_buffer); 8701 } else { 8702 /* We are not reusing the buffer so unmap it and free 8703 * any references we are holding to it 8704 */ 8705 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8706 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8707 IGB_RX_DMA_ATTR); 8708 __page_frag_cache_drain(rx_buffer->page, 8709 rx_buffer->pagecnt_bias); 8710 } 8711 8712 /* clear contents of rx_buffer */ 8713 rx_buffer->page = NULL; 8714} 8715 8716static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8717{ 8718 struct igb_adapter *adapter = q_vector->adapter; 8719 struct igb_ring *rx_ring = q_vector->rx.ring; 8720 struct sk_buff *skb = rx_ring->skb; 8721 unsigned int total_bytes = 0, total_packets = 0; 8722 u16 cleaned_count = igb_desc_unused(rx_ring); 8723 unsigned int xdp_xmit = 0; 8724 struct xdp_buff xdp; 8725 int rx_buf_pgcnt; 8726 8727 xdp.rxq = &rx_ring->xdp_rxq; 8728 8729 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8730#if (PAGE_SIZE < 8192) 8731 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8732#endif 8733 8734 while (likely(total_packets < budget)) { 8735 union e1000_adv_rx_desc *rx_desc; 8736 struct igb_rx_buffer *rx_buffer; 8737 unsigned int size; 8738 8739 /* return some buffers to hardware, one at a time is too slow */ 8740 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8741 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8742 cleaned_count = 0; 8743 } 8744 8745 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8746 size = le16_to_cpu(rx_desc->wb.upper.length); 8747 if (!size) 8748 break; 8749 8750 /* This memory barrier is needed to keep us from reading 8751 * any other fields out of the rx_desc until we know the 8752 * descriptor has been written back 8753 */ 8754 dma_rmb(); 8755 8756 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8757 8758 /* retrieve a buffer from the ring */ 8759 if (!skb) { 8760 xdp.data = page_address(rx_buffer->page) + 8761 rx_buffer->page_offset; 8762 xdp.data_meta = xdp.data; 8763 xdp.data_hard_start = xdp.data - 8764 igb_rx_offset(rx_ring); 8765 xdp.data_end = xdp.data + size; 8766#if (PAGE_SIZE > 4096) 8767 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8768 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8769#endif 8770 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8771 } 8772 8773 if (IS_ERR(skb)) { 8774 unsigned int xdp_res = -PTR_ERR(skb); 8775 8776 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8777 xdp_xmit |= xdp_res; 8778 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8779 } else { 8780 rx_buffer->pagecnt_bias++; 8781 } 8782 total_packets++; 8783 total_bytes += size; 8784 } else if (skb) 8785 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8786 else if (ring_uses_build_skb(rx_ring)) 8787 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, rx_desc); 8788 else 8789 skb = igb_construct_skb(rx_ring, rx_buffer, 8790 &xdp, rx_desc); 8791 8792 /* exit if we failed to retrieve a buffer */ 8793 if (!skb) { 8794 rx_ring->rx_stats.alloc_failed++; 8795 rx_buffer->pagecnt_bias++; 8796 break; 8797 } 8798 8799 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8800 cleaned_count++; 8801 8802 /* fetch next buffer in frame if non-eop */ 8803 if (igb_is_non_eop(rx_ring, rx_desc)) 8804 continue; 8805 8806 /* verify the packet layout is correct */ 8807 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8808 skb = NULL; 8809 continue; 8810 } 8811 8812 /* probably a little skewed due to removing CRC */ 8813 total_bytes += skb->len; 8814 8815 /* populate checksum, timestamp, VLAN, and protocol */ 8816 igb_process_skb_fields(rx_ring, rx_desc, skb); 8817 8818 napi_gro_receive(&q_vector->napi, skb); 8819 8820 /* reset skb pointer */ 8821 skb = NULL; 8822 8823 /* update budget accounting */ 8824 total_packets++; 8825 } 8826 8827 /* place incomplete frames back on ring for completion */ 8828 rx_ring->skb = skb; 8829 8830 if (xdp_xmit & IGB_XDP_REDIR) 8831 xdp_do_flush(); 8832 8833 if (xdp_xmit & IGB_XDP_TX) { 8834 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8835 8836 igb_xdp_ring_update_tail(tx_ring); 8837 } 8838 8839 u64_stats_update_begin(&rx_ring->rx_syncp); 8840 rx_ring->rx_stats.packets += total_packets; 8841 rx_ring->rx_stats.bytes += total_bytes; 8842 u64_stats_update_end(&rx_ring->rx_syncp); 8843 q_vector->rx.total_packets += total_packets; 8844 q_vector->rx.total_bytes += total_bytes; 8845 8846 if (cleaned_count) 8847 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8848 8849 return total_packets; 8850} 8851 8852static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8853 struct igb_rx_buffer *bi) 8854{ 8855 struct page *page = bi->page; 8856 dma_addr_t dma; 8857 8858 /* since we are recycling buffers we should seldom need to alloc */ 8859 if (likely(page)) 8860 return true; 8861 8862 /* alloc new page for storage */ 8863 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8864 if (unlikely(!page)) { 8865 rx_ring->rx_stats.alloc_failed++; 8866 return false; 8867 } 8868 8869 /* map page for use */ 8870 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8871 igb_rx_pg_size(rx_ring), 8872 DMA_FROM_DEVICE, 8873 IGB_RX_DMA_ATTR); 8874 8875 /* if mapping failed free memory back to system since 8876 * there isn't much point in holding memory we can't use 8877 */ 8878 if (dma_mapping_error(rx_ring->dev, dma)) { 8879 __free_pages(page, igb_rx_pg_order(rx_ring)); 8880 8881 rx_ring->rx_stats.alloc_failed++; 8882 return false; 8883 } 8884 8885 bi->dma = dma; 8886 bi->page = page; 8887 bi->page_offset = igb_rx_offset(rx_ring); 8888 page_ref_add(page, USHRT_MAX - 1); 8889 bi->pagecnt_bias = USHRT_MAX; 8890 8891 return true; 8892} 8893 8894/** 8895 * igb_alloc_rx_buffers - Replace used receive buffers 8896 * @rx_ring: rx descriptor ring to allocate new receive buffers 8897 * @cleaned_count: count of buffers to allocate 8898 **/ 8899void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8900{ 8901 union e1000_adv_rx_desc *rx_desc; 8902 struct igb_rx_buffer *bi; 8903 u16 i = rx_ring->next_to_use; 8904 u16 bufsz; 8905 8906 /* nothing to do */ 8907 if (!cleaned_count) 8908 return; 8909 8910 rx_desc = IGB_RX_DESC(rx_ring, i); 8911 bi = &rx_ring->rx_buffer_info[i]; 8912 i -= rx_ring->count; 8913 8914 bufsz = igb_rx_bufsz(rx_ring); 8915 8916 do { 8917 if (!igb_alloc_mapped_page(rx_ring, bi)) 8918 break; 8919 8920 /* sync the buffer for use by the device */ 8921 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8922 bi->page_offset, bufsz, 8923 DMA_FROM_DEVICE); 8924 8925 /* Refresh the desc even if buffer_addrs didn't change 8926 * because each write-back erases this info. 8927 */ 8928 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8929 8930 rx_desc++; 8931 bi++; 8932 i++; 8933 if (unlikely(!i)) { 8934 rx_desc = IGB_RX_DESC(rx_ring, 0); 8935 bi = rx_ring->rx_buffer_info; 8936 i -= rx_ring->count; 8937 } 8938 8939 /* clear the length for the next_to_use descriptor */ 8940 rx_desc->wb.upper.length = 0; 8941 8942 cleaned_count--; 8943 } while (cleaned_count); 8944 8945 i += rx_ring->count; 8946 8947 if (rx_ring->next_to_use != i) { 8948 /* record the next descriptor to use */ 8949 rx_ring->next_to_use = i; 8950 8951 /* update next to alloc since we have filled the ring */ 8952 rx_ring->next_to_alloc = i; 8953 8954 /* Force memory writes to complete before letting h/w 8955 * know there are new descriptors to fetch. (Only 8956 * applicable for weak-ordered memory model archs, 8957 * such as IA-64). 8958 */ 8959 dma_wmb(); 8960 writel(i, rx_ring->tail); 8961 } 8962} 8963 8964/** 8965 * igb_mii_ioctl - 8966 * @netdev: pointer to netdev struct 8967 * @ifr: interface structure 8968 * @cmd: ioctl command to execute 8969 **/ 8970static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8971{ 8972 struct igb_adapter *adapter = netdev_priv(netdev); 8973 struct mii_ioctl_data *data = if_mii(ifr); 8974 8975 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8976 return -EOPNOTSUPP; 8977 8978 switch (cmd) { 8979 case SIOCGMIIPHY: 8980 data->phy_id = adapter->hw.phy.addr; 8981 break; 8982 case SIOCGMIIREG: 8983 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8984 &data->val_out)) 8985 return -EIO; 8986 break; 8987 case SIOCSMIIREG: 8988 default: 8989 return -EOPNOTSUPP; 8990 } 8991 return 0; 8992} 8993 8994/** 8995 * igb_ioctl - 8996 * @netdev: pointer to netdev struct 8997 * @ifr: interface structure 8998 * @cmd: ioctl command to execute 8999 **/ 9000static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9001{ 9002 switch (cmd) { 9003 case SIOCGMIIPHY: 9004 case SIOCGMIIREG: 9005 case SIOCSMIIREG: 9006 return igb_mii_ioctl(netdev, ifr, cmd); 9007 case SIOCGHWTSTAMP: 9008 return igb_ptp_get_ts_config(netdev, ifr); 9009 case SIOCSHWTSTAMP: 9010 return igb_ptp_set_ts_config(netdev, ifr); 9011 default: 9012 return -EOPNOTSUPP; 9013 } 9014} 9015 9016void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9017{ 9018 struct igb_adapter *adapter = hw->back; 9019 9020 pci_read_config_word(adapter->pdev, reg, value); 9021} 9022 9023void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9024{ 9025 struct igb_adapter *adapter = hw->back; 9026 9027 pci_write_config_word(adapter->pdev, reg, *value); 9028} 9029 9030s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9031{ 9032 struct igb_adapter *adapter = hw->back; 9033 9034 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9035 return -E1000_ERR_CONFIG; 9036 9037 return 0; 9038} 9039 9040s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9041{ 9042 struct igb_adapter *adapter = hw->back; 9043 9044 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9045 return -E1000_ERR_CONFIG; 9046 9047 return 0; 9048} 9049 9050static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9051{ 9052 struct igb_adapter *adapter = netdev_priv(netdev); 9053 struct e1000_hw *hw = &adapter->hw; 9054 u32 ctrl, rctl; 9055 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9056 9057 if (enable) { 9058 /* enable VLAN tag insert/strip */ 9059 ctrl = rd32(E1000_CTRL); 9060 ctrl |= E1000_CTRL_VME; 9061 wr32(E1000_CTRL, ctrl); 9062 9063 /* Disable CFI check */ 9064 rctl = rd32(E1000_RCTL); 9065 rctl &= ~E1000_RCTL_CFIEN; 9066 wr32(E1000_RCTL, rctl); 9067 } else { 9068 /* disable VLAN tag insert/strip */ 9069 ctrl = rd32(E1000_CTRL); 9070 ctrl &= ~E1000_CTRL_VME; 9071 wr32(E1000_CTRL, ctrl); 9072 } 9073 9074 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9075} 9076 9077static int igb_vlan_rx_add_vid(struct net_device *netdev, 9078 __be16 proto, u16 vid) 9079{ 9080 struct igb_adapter *adapter = netdev_priv(netdev); 9081 struct e1000_hw *hw = &adapter->hw; 9082 int pf_id = adapter->vfs_allocated_count; 9083 9084 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9085 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9086 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9087 9088 set_bit(vid, adapter->active_vlans); 9089 9090 return 0; 9091} 9092 9093static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9094 __be16 proto, u16 vid) 9095{ 9096 struct igb_adapter *adapter = netdev_priv(netdev); 9097 int pf_id = adapter->vfs_allocated_count; 9098 struct e1000_hw *hw = &adapter->hw; 9099 9100 /* remove VID from filter table */ 9101 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9102 igb_vfta_set(hw, vid, pf_id, false, true); 9103 9104 clear_bit(vid, adapter->active_vlans); 9105 9106 return 0; 9107} 9108 9109static void igb_restore_vlan(struct igb_adapter *adapter) 9110{ 9111 u16 vid = 1; 9112 9113 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9114 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9115 9116 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9117 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9118} 9119 9120int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9121{ 9122 struct pci_dev *pdev = adapter->pdev; 9123 struct e1000_mac_info *mac = &adapter->hw.mac; 9124 9125 mac->autoneg = 0; 9126 9127 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9128 * for the switch() below to work 9129 */ 9130 if ((spd & 1) || (dplx & ~1)) 9131 goto err_inval; 9132 9133 /* Fiber NIC's only allow 1000 gbps Full duplex 9134 * and 100Mbps Full duplex for 100baseFx sfp 9135 */ 9136 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9137 switch (spd + dplx) { 9138 case SPEED_10 + DUPLEX_HALF: 9139 case SPEED_10 + DUPLEX_FULL: 9140 case SPEED_100 + DUPLEX_HALF: 9141 goto err_inval; 9142 default: 9143 break; 9144 } 9145 } 9146 9147 switch (spd + dplx) { 9148 case SPEED_10 + DUPLEX_HALF: 9149 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9150 break; 9151 case SPEED_10 + DUPLEX_FULL: 9152 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9153 break; 9154 case SPEED_100 + DUPLEX_HALF: 9155 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9156 break; 9157 case SPEED_100 + DUPLEX_FULL: 9158 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9159 break; 9160 case SPEED_1000 + DUPLEX_FULL: 9161 mac->autoneg = 1; 9162 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9163 break; 9164 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9165 default: 9166 goto err_inval; 9167 } 9168 9169 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9170 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9171 9172 return 0; 9173 9174err_inval: 9175 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9176 return -EINVAL; 9177} 9178 9179static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9180 bool runtime) 9181{ 9182 struct net_device *netdev = pci_get_drvdata(pdev); 9183 struct igb_adapter *adapter = netdev_priv(netdev); 9184 struct e1000_hw *hw = &adapter->hw; 9185 u32 ctrl, rctl, status; 9186 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9187 bool wake; 9188 9189 rtnl_lock(); 9190 netif_device_detach(netdev); 9191 9192 if (netif_running(netdev)) 9193 __igb_close(netdev, true); 9194 9195 igb_ptp_suspend(adapter); 9196 9197 igb_clear_interrupt_scheme(adapter); 9198 rtnl_unlock(); 9199 9200 status = rd32(E1000_STATUS); 9201 if (status & E1000_STATUS_LU) 9202 wufc &= ~E1000_WUFC_LNKC; 9203 9204 if (wufc) { 9205 igb_setup_rctl(adapter); 9206 igb_set_rx_mode(netdev); 9207 9208 /* turn on all-multi mode if wake on multicast is enabled */ 9209 if (wufc & E1000_WUFC_MC) { 9210 rctl = rd32(E1000_RCTL); 9211 rctl |= E1000_RCTL_MPE; 9212 wr32(E1000_RCTL, rctl); 9213 } 9214 9215 ctrl = rd32(E1000_CTRL); 9216 ctrl |= E1000_CTRL_ADVD3WUC; 9217 wr32(E1000_CTRL, ctrl); 9218 9219 /* Allow time for pending master requests to run */ 9220 igb_disable_pcie_master(hw); 9221 9222 wr32(E1000_WUC, E1000_WUC_PME_EN); 9223 wr32(E1000_WUFC, wufc); 9224 } else { 9225 wr32(E1000_WUC, 0); 9226 wr32(E1000_WUFC, 0); 9227 } 9228 9229 wake = wufc || adapter->en_mng_pt; 9230 if (!wake) 9231 igb_power_down_link(adapter); 9232 else 9233 igb_power_up_link(adapter); 9234 9235 if (enable_wake) 9236 *enable_wake = wake; 9237 9238 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9239 * would have already happened in close and is redundant. 9240 */ 9241 igb_release_hw_control(adapter); 9242 9243 pci_disable_device(pdev); 9244 9245 return 0; 9246} 9247 9248static void igb_deliver_wake_packet(struct net_device *netdev) 9249{ 9250 struct igb_adapter *adapter = netdev_priv(netdev); 9251 struct e1000_hw *hw = &adapter->hw; 9252 struct sk_buff *skb; 9253 u32 wupl; 9254 9255 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9256 9257 /* WUPM stores only the first 128 bytes of the wake packet. 9258 * Read the packet only if we have the whole thing. 9259 */ 9260 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9261 return; 9262 9263 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9264 if (!skb) 9265 return; 9266 9267 skb_put(skb, wupl); 9268 9269 /* Ensure reads are 32-bit aligned */ 9270 wupl = roundup(wupl, 4); 9271 9272 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9273 9274 skb->protocol = eth_type_trans(skb, netdev); 9275 netif_rx(skb); 9276} 9277 9278static int __maybe_unused igb_suspend(struct device *dev) 9279{ 9280 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9281} 9282 9283static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9284{ 9285 struct pci_dev *pdev = to_pci_dev(dev); 9286 struct net_device *netdev = pci_get_drvdata(pdev); 9287 struct igb_adapter *adapter = netdev_priv(netdev); 9288 struct e1000_hw *hw = &adapter->hw; 9289 u32 err, val; 9290 9291 pci_set_power_state(pdev, PCI_D0); 9292 pci_restore_state(pdev); 9293 pci_save_state(pdev); 9294 9295 if (!pci_device_is_present(pdev)) 9296 return -ENODEV; 9297 err = pci_enable_device_mem(pdev); 9298 if (err) { 9299 dev_err(&pdev->dev, 9300 "igb: Cannot enable PCI device from suspend\n"); 9301 return err; 9302 } 9303 pci_set_master(pdev); 9304 9305 pci_enable_wake(pdev, PCI_D3hot, 0); 9306 pci_enable_wake(pdev, PCI_D3cold, 0); 9307 9308 if (igb_init_interrupt_scheme(adapter, true)) { 9309 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9310 return -ENOMEM; 9311 } 9312 9313 igb_reset(adapter); 9314 9315 /* let the f/w know that the h/w is now under the control of the 9316 * driver. 9317 */ 9318 igb_get_hw_control(adapter); 9319 9320 val = rd32(E1000_WUS); 9321 if (val & WAKE_PKT_WUS) 9322 igb_deliver_wake_packet(netdev); 9323 9324 wr32(E1000_WUS, ~0); 9325 9326 if (!rpm) 9327 rtnl_lock(); 9328 if (!err && netif_running(netdev)) 9329 err = __igb_open(netdev, true); 9330 9331 if (!err) 9332 netif_device_attach(netdev); 9333 if (!rpm) 9334 rtnl_unlock(); 9335 9336 return err; 9337} 9338 9339static int __maybe_unused igb_resume(struct device *dev) 9340{ 9341 return __igb_resume(dev, false); 9342} 9343 9344static int __maybe_unused igb_runtime_idle(struct device *dev) 9345{ 9346 struct net_device *netdev = dev_get_drvdata(dev); 9347 struct igb_adapter *adapter = netdev_priv(netdev); 9348 9349 if (!igb_has_link(adapter)) 9350 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9351 9352 return -EBUSY; 9353} 9354 9355static int __maybe_unused igb_runtime_suspend(struct device *dev) 9356{ 9357 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9358} 9359 9360static int __maybe_unused igb_runtime_resume(struct device *dev) 9361{ 9362 return __igb_resume(dev, true); 9363} 9364 9365static void igb_shutdown(struct pci_dev *pdev) 9366{ 9367 bool wake; 9368 9369 __igb_shutdown(pdev, &wake, 0); 9370 9371 if (system_state == SYSTEM_POWER_OFF) { 9372 pci_wake_from_d3(pdev, wake); 9373 pci_set_power_state(pdev, PCI_D3hot); 9374 } 9375} 9376 9377#ifdef CONFIG_PCI_IOV 9378static int igb_sriov_reinit(struct pci_dev *dev) 9379{ 9380 struct net_device *netdev = pci_get_drvdata(dev); 9381 struct igb_adapter *adapter = netdev_priv(netdev); 9382 struct pci_dev *pdev = adapter->pdev; 9383 9384 rtnl_lock(); 9385 9386 if (netif_running(netdev)) 9387 igb_close(netdev); 9388 else 9389 igb_reset(adapter); 9390 9391 igb_clear_interrupt_scheme(adapter); 9392 9393 igb_init_queue_configuration(adapter); 9394 9395 if (igb_init_interrupt_scheme(adapter, true)) { 9396 rtnl_unlock(); 9397 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9398 return -ENOMEM; 9399 } 9400 9401 if (netif_running(netdev)) 9402 igb_open(netdev); 9403 9404 rtnl_unlock(); 9405 9406 return 0; 9407} 9408 9409static int igb_pci_disable_sriov(struct pci_dev *dev) 9410{ 9411 int err = igb_disable_sriov(dev); 9412 9413 if (!err) 9414 err = igb_sriov_reinit(dev); 9415 9416 return err; 9417} 9418 9419static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9420{ 9421 int err = igb_enable_sriov(dev, num_vfs); 9422 9423 if (err) 9424 goto out; 9425 9426 err = igb_sriov_reinit(dev); 9427 if (!err) 9428 return num_vfs; 9429 9430out: 9431 return err; 9432} 9433 9434#endif 9435static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9436{ 9437#ifdef CONFIG_PCI_IOV 9438 if (num_vfs == 0) 9439 return igb_pci_disable_sriov(dev); 9440 else 9441 return igb_pci_enable_sriov(dev, num_vfs); 9442#endif 9443 return 0; 9444} 9445 9446/** 9447 * igb_io_error_detected - called when PCI error is detected 9448 * @pdev: Pointer to PCI device 9449 * @state: The current pci connection state 9450 * 9451 * This function is called after a PCI bus error affecting 9452 * this device has been detected. 9453 **/ 9454static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9455 pci_channel_state_t state) 9456{ 9457 struct net_device *netdev = pci_get_drvdata(pdev); 9458 struct igb_adapter *adapter = netdev_priv(netdev); 9459 9460 if (state == pci_channel_io_normal) { 9461 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9462 return PCI_ERS_RESULT_CAN_RECOVER; 9463 } 9464 9465 netif_device_detach(netdev); 9466 9467 if (state == pci_channel_io_perm_failure) 9468 return PCI_ERS_RESULT_DISCONNECT; 9469 9470 if (netif_running(netdev)) 9471 igb_down(adapter); 9472 pci_disable_device(pdev); 9473 9474 /* Request a slot slot reset. */ 9475 return PCI_ERS_RESULT_NEED_RESET; 9476} 9477 9478/** 9479 * igb_io_slot_reset - called after the pci bus has been reset. 9480 * @pdev: Pointer to PCI device 9481 * 9482 * Restart the card from scratch, as if from a cold-boot. Implementation 9483 * resembles the first-half of the __igb_resume routine. 9484 **/ 9485static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9486{ 9487 struct net_device *netdev = pci_get_drvdata(pdev); 9488 struct igb_adapter *adapter = netdev_priv(netdev); 9489 struct e1000_hw *hw = &adapter->hw; 9490 pci_ers_result_t result; 9491 9492 if (pci_enable_device_mem(pdev)) { 9493 dev_err(&pdev->dev, 9494 "Cannot re-enable PCI device after reset.\n"); 9495 result = PCI_ERS_RESULT_DISCONNECT; 9496 } else { 9497 pci_set_master(pdev); 9498 pci_restore_state(pdev); 9499 pci_save_state(pdev); 9500 9501 pci_enable_wake(pdev, PCI_D3hot, 0); 9502 pci_enable_wake(pdev, PCI_D3cold, 0); 9503 9504 /* In case of PCI error, adapter lose its HW address 9505 * so we should re-assign it here. 9506 */ 9507 hw->hw_addr = adapter->io_addr; 9508 9509 igb_reset(adapter); 9510 wr32(E1000_WUS, ~0); 9511 result = PCI_ERS_RESULT_RECOVERED; 9512 } 9513 9514 return result; 9515} 9516 9517/** 9518 * igb_io_resume - called when traffic can start flowing again. 9519 * @pdev: Pointer to PCI device 9520 * 9521 * This callback is called when the error recovery driver tells us that 9522 * its OK to resume normal operation. Implementation resembles the 9523 * second-half of the __igb_resume routine. 9524 */ 9525static void igb_io_resume(struct pci_dev *pdev) 9526{ 9527 struct net_device *netdev = pci_get_drvdata(pdev); 9528 struct igb_adapter *adapter = netdev_priv(netdev); 9529 9530 if (netif_running(netdev)) { 9531 if (igb_up(adapter)) { 9532 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9533 return; 9534 } 9535 } 9536 9537 netif_device_attach(netdev); 9538 9539 /* let the f/w know that the h/w is now under the control of the 9540 * driver. 9541 */ 9542 igb_get_hw_control(adapter); 9543} 9544 9545/** 9546 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9547 * @adapter: Pointer to adapter structure 9548 * @index: Index of the RAR entry which need to be synced with MAC table 9549 **/ 9550static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9551{ 9552 struct e1000_hw *hw = &adapter->hw; 9553 u32 rar_low, rar_high; 9554 u8 *addr = adapter->mac_table[index].addr; 9555 9556 /* HW expects these to be in network order when they are plugged 9557 * into the registers which are little endian. In order to guarantee 9558 * that ordering we need to do an leXX_to_cpup here in order to be 9559 * ready for the byteswap that occurs with writel 9560 */ 9561 rar_low = le32_to_cpup((__le32 *)(addr)); 9562 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9563 9564 /* Indicate to hardware the Address is Valid. */ 9565 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9566 if (is_valid_ether_addr(addr)) 9567 rar_high |= E1000_RAH_AV; 9568 9569 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9570 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9571 9572 switch (hw->mac.type) { 9573 case e1000_82575: 9574 case e1000_i210: 9575 if (adapter->mac_table[index].state & 9576 IGB_MAC_STATE_QUEUE_STEERING) 9577 rar_high |= E1000_RAH_QSEL_ENABLE; 9578 9579 rar_high |= E1000_RAH_POOL_1 * 9580 adapter->mac_table[index].queue; 9581 break; 9582 default: 9583 rar_high |= E1000_RAH_POOL_1 << 9584 adapter->mac_table[index].queue; 9585 break; 9586 } 9587 } 9588 9589 wr32(E1000_RAL(index), rar_low); 9590 wrfl(); 9591 wr32(E1000_RAH(index), rar_high); 9592 wrfl(); 9593} 9594 9595static int igb_set_vf_mac(struct igb_adapter *adapter, 9596 int vf, unsigned char *mac_addr) 9597{ 9598 struct e1000_hw *hw = &adapter->hw; 9599 /* VF MAC addresses start at end of receive addresses and moves 9600 * towards the first, as a result a collision should not be possible 9601 */ 9602 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9603 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9604 9605 ether_addr_copy(vf_mac_addr, mac_addr); 9606 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9607 adapter->mac_table[rar_entry].queue = vf; 9608 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9609 igb_rar_set_index(adapter, rar_entry); 9610 9611 return 0; 9612} 9613 9614static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9615{ 9616 struct igb_adapter *adapter = netdev_priv(netdev); 9617 9618 if (vf >= adapter->vfs_allocated_count) 9619 return -EINVAL; 9620 9621 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9622 * flag and allows to overwrite the MAC via VF netdev. This 9623 * is necessary to allow libvirt a way to restore the original 9624 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9625 * down a VM. 9626 */ 9627 if (is_zero_ether_addr(mac)) { 9628 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9629 dev_info(&adapter->pdev->dev, 9630 "remove administratively set MAC on VF %d\n", 9631 vf); 9632 } else if (is_valid_ether_addr(mac)) { 9633 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9634 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9635 mac, vf); 9636 dev_info(&adapter->pdev->dev, 9637 "Reload the VF driver to make this change effective."); 9638 /* Generate additional warning if PF is down */ 9639 if (test_bit(__IGB_DOWN, &adapter->state)) { 9640 dev_warn(&adapter->pdev->dev, 9641 "The VF MAC address has been set, but the PF device is not up.\n"); 9642 dev_warn(&adapter->pdev->dev, 9643 "Bring the PF device up before attempting to use the VF device.\n"); 9644 } 9645 } else { 9646 return -EINVAL; 9647 } 9648 return igb_set_vf_mac(adapter, vf, mac); 9649} 9650 9651static int igb_link_mbps(int internal_link_speed) 9652{ 9653 switch (internal_link_speed) { 9654 case SPEED_100: 9655 return 100; 9656 case SPEED_1000: 9657 return 1000; 9658 default: 9659 return 0; 9660 } 9661} 9662 9663static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9664 int link_speed) 9665{ 9666 int rf_dec, rf_int; 9667 u32 bcnrc_val; 9668 9669 if (tx_rate != 0) { 9670 /* Calculate the rate factor values to set */ 9671 rf_int = link_speed / tx_rate; 9672 rf_dec = (link_speed - (rf_int * tx_rate)); 9673 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9674 tx_rate; 9675 9676 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9677 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9678 E1000_RTTBCNRC_RF_INT_MASK); 9679 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9680 } else { 9681 bcnrc_val = 0; 9682 } 9683 9684 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9685 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9686 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9687 */ 9688 wr32(E1000_RTTBCNRM, 0x14); 9689 wr32(E1000_RTTBCNRC, bcnrc_val); 9690} 9691 9692static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9693{ 9694 int actual_link_speed, i; 9695 bool reset_rate = false; 9696 9697 /* VF TX rate limit was not set or not supported */ 9698 if ((adapter->vf_rate_link_speed == 0) || 9699 (adapter->hw.mac.type != e1000_82576)) 9700 return; 9701 9702 actual_link_speed = igb_link_mbps(adapter->link_speed); 9703 if (actual_link_speed != adapter->vf_rate_link_speed) { 9704 reset_rate = true; 9705 adapter->vf_rate_link_speed = 0; 9706 dev_info(&adapter->pdev->dev, 9707 "Link speed has been changed. VF Transmit rate is disabled\n"); 9708 } 9709 9710 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9711 if (reset_rate) 9712 adapter->vf_data[i].tx_rate = 0; 9713 9714 igb_set_vf_rate_limit(&adapter->hw, i, 9715 adapter->vf_data[i].tx_rate, 9716 actual_link_speed); 9717 } 9718} 9719 9720static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9721 int min_tx_rate, int max_tx_rate) 9722{ 9723 struct igb_adapter *adapter = netdev_priv(netdev); 9724 struct e1000_hw *hw = &adapter->hw; 9725 int actual_link_speed; 9726 9727 if (hw->mac.type != e1000_82576) 9728 return -EOPNOTSUPP; 9729 9730 if (min_tx_rate) 9731 return -EINVAL; 9732 9733 actual_link_speed = igb_link_mbps(adapter->link_speed); 9734 if ((vf >= adapter->vfs_allocated_count) || 9735 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9736 (max_tx_rate < 0) || 9737 (max_tx_rate > actual_link_speed)) 9738 return -EINVAL; 9739 9740 adapter->vf_rate_link_speed = actual_link_speed; 9741 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9742 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9743 9744 return 0; 9745} 9746 9747static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9748 bool setting) 9749{ 9750 struct igb_adapter *adapter = netdev_priv(netdev); 9751 struct e1000_hw *hw = &adapter->hw; 9752 u32 reg_val, reg_offset; 9753 9754 if (!adapter->vfs_allocated_count) 9755 return -EOPNOTSUPP; 9756 9757 if (vf >= adapter->vfs_allocated_count) 9758 return -EINVAL; 9759 9760 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9761 reg_val = rd32(reg_offset); 9762 if (setting) 9763 reg_val |= (BIT(vf) | 9764 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9765 else 9766 reg_val &= ~(BIT(vf) | 9767 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9768 wr32(reg_offset, reg_val); 9769 9770 adapter->vf_data[vf].spoofchk_enabled = setting; 9771 return 0; 9772} 9773 9774static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9775{ 9776 struct igb_adapter *adapter = netdev_priv(netdev); 9777 9778 if (vf >= adapter->vfs_allocated_count) 9779 return -EINVAL; 9780 if (adapter->vf_data[vf].trusted == setting) 9781 return 0; 9782 9783 adapter->vf_data[vf].trusted = setting; 9784 9785 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9786 vf, setting ? "" : "not "); 9787 return 0; 9788} 9789 9790static int igb_ndo_get_vf_config(struct net_device *netdev, 9791 int vf, struct ifla_vf_info *ivi) 9792{ 9793 struct igb_adapter *adapter = netdev_priv(netdev); 9794 if (vf >= adapter->vfs_allocated_count) 9795 return -EINVAL; 9796 ivi->vf = vf; 9797 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9798 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9799 ivi->min_tx_rate = 0; 9800 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9801 ivi->qos = adapter->vf_data[vf].pf_qos; 9802 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9803 ivi->trusted = adapter->vf_data[vf].trusted; 9804 return 0; 9805} 9806 9807static void igb_vmm_control(struct igb_adapter *adapter) 9808{ 9809 struct e1000_hw *hw = &adapter->hw; 9810 u32 reg; 9811 9812 switch (hw->mac.type) { 9813 case e1000_82575: 9814 case e1000_i210: 9815 case e1000_i211: 9816 case e1000_i354: 9817 default: 9818 /* replication is not supported for 82575 */ 9819 return; 9820 case e1000_82576: 9821 /* notify HW that the MAC is adding vlan tags */ 9822 reg = rd32(E1000_DTXCTL); 9823 reg |= E1000_DTXCTL_VLAN_ADDED; 9824 wr32(E1000_DTXCTL, reg); 9825 fallthrough; 9826 case e1000_82580: 9827 /* enable replication vlan tag stripping */ 9828 reg = rd32(E1000_RPLOLR); 9829 reg |= E1000_RPLOLR_STRVLAN; 9830 wr32(E1000_RPLOLR, reg); 9831 fallthrough; 9832 case e1000_i350: 9833 /* none of the above registers are supported by i350 */ 9834 break; 9835 } 9836 9837 if (adapter->vfs_allocated_count) { 9838 igb_vmdq_set_loopback_pf(hw, true); 9839 igb_vmdq_set_replication_pf(hw, true); 9840 igb_vmdq_set_anti_spoofing_pf(hw, true, 9841 adapter->vfs_allocated_count); 9842 } else { 9843 igb_vmdq_set_loopback_pf(hw, false); 9844 igb_vmdq_set_replication_pf(hw, false); 9845 } 9846} 9847 9848static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9849{ 9850 struct e1000_hw *hw = &adapter->hw; 9851 u32 dmac_thr; 9852 u16 hwm; 9853 u32 reg; 9854 9855 if (hw->mac.type > e1000_82580) { 9856 if (adapter->flags & IGB_FLAG_DMAC) { 9857 /* force threshold to 0. */ 9858 wr32(E1000_DMCTXTH, 0); 9859 9860 /* DMA Coalescing high water mark needs to be greater 9861 * than the Rx threshold. Set hwm to PBA - max frame 9862 * size in 16B units, capping it at PBA - 6KB. 9863 */ 9864 hwm = 64 * (pba - 6); 9865 reg = rd32(E1000_FCRTC); 9866 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9867 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9868 & E1000_FCRTC_RTH_COAL_MASK); 9869 wr32(E1000_FCRTC, reg); 9870 9871 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9872 * frame size, capping it at PBA - 10KB. 9873 */ 9874 dmac_thr = pba - 10; 9875 reg = rd32(E1000_DMACR); 9876 reg &= ~E1000_DMACR_DMACTHR_MASK; 9877 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9878 & E1000_DMACR_DMACTHR_MASK); 9879 9880 /* transition to L0x or L1 if available..*/ 9881 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9882 9883 /* watchdog timer= +-1000 usec in 32usec intervals */ 9884 reg |= (1000 >> 5); 9885 9886 /* Disable BMC-to-OS Watchdog Enable */ 9887 if (hw->mac.type != e1000_i354) 9888 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9889 wr32(E1000_DMACR, reg); 9890 9891 /* no lower threshold to disable 9892 * coalescing(smart fifb)-UTRESH=0 9893 */ 9894 wr32(E1000_DMCRTRH, 0); 9895 9896 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9897 9898 wr32(E1000_DMCTLX, reg); 9899 9900 /* free space in tx packet buffer to wake from 9901 * DMA coal 9902 */ 9903 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9904 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9905 } 9906 9907 if (hw->mac.type >= e1000_i210 || 9908 (adapter->flags & IGB_FLAG_DMAC)) { 9909 reg = rd32(E1000_PCIEMISC); 9910 reg |= E1000_PCIEMISC_LX_DECISION; 9911 wr32(E1000_PCIEMISC, reg); 9912 } /* endif adapter->dmac is not disabled */ 9913 } else if (hw->mac.type == e1000_82580) { 9914 u32 reg = rd32(E1000_PCIEMISC); 9915 9916 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9917 wr32(E1000_DMACR, 0); 9918 } 9919} 9920 9921/** 9922 * igb_read_i2c_byte - Reads 8 bit word over I2C 9923 * @hw: pointer to hardware structure 9924 * @byte_offset: byte offset to read 9925 * @dev_addr: device address 9926 * @data: value read 9927 * 9928 * Performs byte read operation over I2C interface at 9929 * a specified device address. 9930 **/ 9931s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9932 u8 dev_addr, u8 *data) 9933{ 9934 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9935 struct i2c_client *this_client = adapter->i2c_client; 9936 s32 status; 9937 u16 swfw_mask = 0; 9938 9939 if (!this_client) 9940 return E1000_ERR_I2C; 9941 9942 swfw_mask = E1000_SWFW_PHY0_SM; 9943 9944 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9945 return E1000_ERR_SWFW_SYNC; 9946 9947 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9948 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9949 9950 if (status < 0) 9951 return E1000_ERR_I2C; 9952 else { 9953 *data = status; 9954 return 0; 9955 } 9956} 9957 9958/** 9959 * igb_write_i2c_byte - Writes 8 bit word over I2C 9960 * @hw: pointer to hardware structure 9961 * @byte_offset: byte offset to write 9962 * @dev_addr: device address 9963 * @data: value to write 9964 * 9965 * Performs byte write operation over I2C interface at 9966 * a specified device address. 9967 **/ 9968s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9969 u8 dev_addr, u8 data) 9970{ 9971 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9972 struct i2c_client *this_client = adapter->i2c_client; 9973 s32 status; 9974 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9975 9976 if (!this_client) 9977 return E1000_ERR_I2C; 9978 9979 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9980 return E1000_ERR_SWFW_SYNC; 9981 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9982 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9983 9984 if (status) 9985 return E1000_ERR_I2C; 9986 else 9987 return 0; 9988 9989} 9990 9991int igb_reinit_queues(struct igb_adapter *adapter) 9992{ 9993 struct net_device *netdev = adapter->netdev; 9994 struct pci_dev *pdev = adapter->pdev; 9995 int err = 0; 9996 9997 if (netif_running(netdev)) 9998 igb_close(netdev); 9999 10000 igb_reset_interrupt_capability(adapter); 10001 10002 if (igb_init_interrupt_scheme(adapter, true)) { 10003 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10004 return -ENOMEM; 10005 } 10006 10007 if (netif_running(netdev)) 10008 err = igb_open(netdev); 10009 10010 return err; 10011} 10012 10013static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10014{ 10015 struct igb_nfc_filter *rule; 10016 10017 spin_lock(&adapter->nfc_lock); 10018 10019 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10020 igb_erase_filter(adapter, rule); 10021 10022 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10023 igb_erase_filter(adapter, rule); 10024 10025 spin_unlock(&adapter->nfc_lock); 10026} 10027 10028static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10029{ 10030 struct igb_nfc_filter *rule; 10031 10032 spin_lock(&adapter->nfc_lock); 10033 10034 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10035 igb_add_filter(adapter, rule); 10036 10037 spin_unlock(&adapter->nfc_lock); 10038} 10039/* igb_main.c */ 10040