1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4#include <linux/prefetch.h> 5 6#include "iavf.h" 7#include "iavf_trace.h" 8#include "iavf_prototype.h" 9 10static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 11 u32 td_tag) 12{ 13 return cpu_to_le64(IAVF_TX_DESC_DTYPE_DATA | 14 ((u64)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) | 15 ((u64)td_offset << IAVF_TXD_QW1_OFFSET_SHIFT) | 16 ((u64)size << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) | 17 ((u64)td_tag << IAVF_TXD_QW1_L2TAG1_SHIFT)); 18} 19 20#define IAVF_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS) 21 22/** 23 * iavf_unmap_and_free_tx_resource - Release a Tx buffer 24 * @ring: the ring that owns the buffer 25 * @tx_buffer: the buffer to free 26 **/ 27static void iavf_unmap_and_free_tx_resource(struct iavf_ring *ring, 28 struct iavf_tx_buffer *tx_buffer) 29{ 30 if (tx_buffer->skb) { 31 if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB) 32 kfree(tx_buffer->raw_buf); 33 else 34 dev_kfree_skb_any(tx_buffer->skb); 35 if (dma_unmap_len(tx_buffer, len)) 36 dma_unmap_single(ring->dev, 37 dma_unmap_addr(tx_buffer, dma), 38 dma_unmap_len(tx_buffer, len), 39 DMA_TO_DEVICE); 40 } else if (dma_unmap_len(tx_buffer, len)) { 41 dma_unmap_page(ring->dev, 42 dma_unmap_addr(tx_buffer, dma), 43 dma_unmap_len(tx_buffer, len), 44 DMA_TO_DEVICE); 45 } 46 47 tx_buffer->next_to_watch = NULL; 48 tx_buffer->skb = NULL; 49 dma_unmap_len_set(tx_buffer, len, 0); 50 /* tx_buffer must be completely set up in the transmit path */ 51} 52 53/** 54 * iavf_clean_tx_ring - Free any empty Tx buffers 55 * @tx_ring: ring to be cleaned 56 **/ 57void iavf_clean_tx_ring(struct iavf_ring *tx_ring) 58{ 59 unsigned long bi_size; 60 u16 i; 61 62 /* ring already cleared, nothing to do */ 63 if (!tx_ring->tx_bi) 64 return; 65 66 /* Free all the Tx ring sk_buffs */ 67 for (i = 0; i < tx_ring->count; i++) 68 iavf_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 69 70 bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count; 71 memset(tx_ring->tx_bi, 0, bi_size); 72 73 /* Zero out the descriptor ring */ 74 memset(tx_ring->desc, 0, tx_ring->size); 75 76 tx_ring->next_to_use = 0; 77 tx_ring->next_to_clean = 0; 78 79 if (!tx_ring->netdev) 80 return; 81 82 /* cleanup Tx queue statistics */ 83 netdev_tx_reset_queue(txring_txq(tx_ring)); 84} 85 86/** 87 * iavf_free_tx_resources - Free Tx resources per queue 88 * @tx_ring: Tx descriptor ring for a specific queue 89 * 90 * Free all transmit software resources 91 **/ 92void iavf_free_tx_resources(struct iavf_ring *tx_ring) 93{ 94 iavf_clean_tx_ring(tx_ring); 95 kfree(tx_ring->tx_bi); 96 tx_ring->tx_bi = NULL; 97 98 if (tx_ring->desc) { 99 dma_free_coherent(tx_ring->dev, tx_ring->size, 100 tx_ring->desc, tx_ring->dma); 101 tx_ring->desc = NULL; 102 } 103} 104 105/** 106 * iavf_get_tx_pending - how many Tx descriptors not processed 107 * @ring: the ring of descriptors 108 * @in_sw: is tx_pending being checked in SW or HW 109 * 110 * Since there is no access to the ring head register 111 * in XL710, we need to use our local copies 112 **/ 113u32 iavf_get_tx_pending(struct iavf_ring *ring, bool in_sw) 114{ 115 u32 head, tail; 116 117 /* underlying hardware might not allow access and/or always return 118 * 0 for the head/tail registers so just use the cached values 119 */ 120 head = ring->next_to_clean; 121 tail = ring->next_to_use; 122 123 if (head != tail) 124 return (head < tail) ? 125 tail - head : (tail + ring->count - head); 126 127 return 0; 128} 129 130/** 131 * iavf_detect_recover_hung - Function to detect and recover hung_queues 132 * @vsi: pointer to vsi struct with tx queues 133 * 134 * VSI has netdev and netdev has TX queues. This function is to check each of 135 * those TX queues if they are hung, trigger recovery by issuing SW interrupt. 136 **/ 137void iavf_detect_recover_hung(struct iavf_vsi *vsi) 138{ 139 struct iavf_ring *tx_ring = NULL; 140 struct net_device *netdev; 141 unsigned int i; 142 int packets; 143 144 if (!vsi) 145 return; 146 147 if (test_bit(__IAVF_VSI_DOWN, vsi->state)) 148 return; 149 150 netdev = vsi->netdev; 151 if (!netdev) 152 return; 153 154 if (!netif_carrier_ok(netdev)) 155 return; 156 157 for (i = 0; i < vsi->back->num_active_queues; i++) { 158 tx_ring = &vsi->back->tx_rings[i]; 159 if (tx_ring && tx_ring->desc) { 160 /* If packet counter has not changed the queue is 161 * likely stalled, so force an interrupt for this 162 * queue. 163 * 164 * prev_pkt_ctr would be negative if there was no 165 * pending work. 166 */ 167 packets = tx_ring->stats.packets & INT_MAX; 168 if (tx_ring->tx_stats.prev_pkt_ctr == packets) { 169 iavf_force_wb(vsi, tx_ring->q_vector); 170 continue; 171 } 172 173 /* Memory barrier between read of packet count and call 174 * to iavf_get_tx_pending() 175 */ 176 smp_rmb(); 177 tx_ring->tx_stats.prev_pkt_ctr = 178 iavf_get_tx_pending(tx_ring, true) ? packets : -1; 179 } 180 } 181} 182 183#define WB_STRIDE 4 184 185/** 186 * iavf_clean_tx_irq - Reclaim resources after transmit completes 187 * @vsi: the VSI we care about 188 * @tx_ring: Tx ring to clean 189 * @napi_budget: Used to determine if we are in netpoll 190 * 191 * Returns true if there's any budget left (e.g. the clean is finished) 192 **/ 193static bool iavf_clean_tx_irq(struct iavf_vsi *vsi, 194 struct iavf_ring *tx_ring, int napi_budget) 195{ 196 int i = tx_ring->next_to_clean; 197 struct iavf_tx_buffer *tx_buf; 198 struct iavf_tx_desc *tx_desc; 199 unsigned int total_bytes = 0, total_packets = 0; 200 unsigned int budget = vsi->work_limit; 201 202 tx_buf = &tx_ring->tx_bi[i]; 203 tx_desc = IAVF_TX_DESC(tx_ring, i); 204 i -= tx_ring->count; 205 206 do { 207 struct iavf_tx_desc *eop_desc = tx_buf->next_to_watch; 208 209 /* if next_to_watch is not set then there is no work pending */ 210 if (!eop_desc) 211 break; 212 213 /* prevent any other reads prior to eop_desc */ 214 smp_rmb(); 215 216 iavf_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 217 /* if the descriptor isn't done, no work yet to do */ 218 if (!(eop_desc->cmd_type_offset_bsz & 219 cpu_to_le64(IAVF_TX_DESC_DTYPE_DESC_DONE))) 220 break; 221 222 /* clear next_to_watch to prevent false hangs */ 223 tx_buf->next_to_watch = NULL; 224 225 /* update the statistics for this packet */ 226 total_bytes += tx_buf->bytecount; 227 total_packets += tx_buf->gso_segs; 228 229 /* free the skb */ 230 napi_consume_skb(tx_buf->skb, napi_budget); 231 232 /* unmap skb header data */ 233 dma_unmap_single(tx_ring->dev, 234 dma_unmap_addr(tx_buf, dma), 235 dma_unmap_len(tx_buf, len), 236 DMA_TO_DEVICE); 237 238 /* clear tx_buffer data */ 239 tx_buf->skb = NULL; 240 dma_unmap_len_set(tx_buf, len, 0); 241 242 /* unmap remaining buffers */ 243 while (tx_desc != eop_desc) { 244 iavf_trace(clean_tx_irq_unmap, 245 tx_ring, tx_desc, tx_buf); 246 247 tx_buf++; 248 tx_desc++; 249 i++; 250 if (unlikely(!i)) { 251 i -= tx_ring->count; 252 tx_buf = tx_ring->tx_bi; 253 tx_desc = IAVF_TX_DESC(tx_ring, 0); 254 } 255 256 /* unmap any remaining paged data */ 257 if (dma_unmap_len(tx_buf, len)) { 258 dma_unmap_page(tx_ring->dev, 259 dma_unmap_addr(tx_buf, dma), 260 dma_unmap_len(tx_buf, len), 261 DMA_TO_DEVICE); 262 dma_unmap_len_set(tx_buf, len, 0); 263 } 264 } 265 266 /* move us one more past the eop_desc for start of next pkt */ 267 tx_buf++; 268 tx_desc++; 269 i++; 270 if (unlikely(!i)) { 271 i -= tx_ring->count; 272 tx_buf = tx_ring->tx_bi; 273 tx_desc = IAVF_TX_DESC(tx_ring, 0); 274 } 275 276 prefetch(tx_desc); 277 278 /* update budget accounting */ 279 budget--; 280 } while (likely(budget)); 281 282 i += tx_ring->count; 283 tx_ring->next_to_clean = i; 284 u64_stats_update_begin(&tx_ring->syncp); 285 tx_ring->stats.bytes += total_bytes; 286 tx_ring->stats.packets += total_packets; 287 u64_stats_update_end(&tx_ring->syncp); 288 tx_ring->q_vector->tx.total_bytes += total_bytes; 289 tx_ring->q_vector->tx.total_packets += total_packets; 290 291 if (tx_ring->flags & IAVF_TXR_FLAGS_WB_ON_ITR) { 292 /* check to see if there are < 4 descriptors 293 * waiting to be written back, then kick the hardware to force 294 * them to be written back in case we stay in NAPI. 295 * In this mode on X722 we do not enable Interrupt. 296 */ 297 unsigned int j = iavf_get_tx_pending(tx_ring, false); 298 299 if (budget && 300 ((j / WB_STRIDE) == 0) && (j > 0) && 301 !test_bit(__IAVF_VSI_DOWN, vsi->state) && 302 (IAVF_DESC_UNUSED(tx_ring) != tx_ring->count)) 303 tx_ring->arm_wb = true; 304 } 305 306 /* notify netdev of completed buffers */ 307 netdev_tx_completed_queue(txring_txq(tx_ring), 308 total_packets, total_bytes); 309 310#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 311 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 312 (IAVF_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 313 /* Make sure that anybody stopping the queue after this 314 * sees the new next_to_clean. 315 */ 316 smp_mb(); 317 if (__netif_subqueue_stopped(tx_ring->netdev, 318 tx_ring->queue_index) && 319 !test_bit(__IAVF_VSI_DOWN, vsi->state)) { 320 netif_wake_subqueue(tx_ring->netdev, 321 tx_ring->queue_index); 322 ++tx_ring->tx_stats.restart_queue; 323 } 324 } 325 326 return !!budget; 327} 328 329/** 330 * iavf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 331 * @vsi: the VSI we care about 332 * @q_vector: the vector on which to enable writeback 333 * 334 **/ 335static void iavf_enable_wb_on_itr(struct iavf_vsi *vsi, 336 struct iavf_q_vector *q_vector) 337{ 338 u16 flags = q_vector->tx.ring[0].flags; 339 u32 val; 340 341 if (!(flags & IAVF_TXR_FLAGS_WB_ON_ITR)) 342 return; 343 344 if (q_vector->arm_wb_state) 345 return; 346 347 val = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | 348 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */ 349 350 wr32(&vsi->back->hw, 351 IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val); 352 q_vector->arm_wb_state = true; 353} 354 355/** 356 * iavf_force_wb - Issue SW Interrupt so HW does a wb 357 * @vsi: the VSI we care about 358 * @q_vector: the vector on which to force writeback 359 * 360 **/ 361void iavf_force_wb(struct iavf_vsi *vsi, struct iavf_q_vector *q_vector) 362{ 363 u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK | 364 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */ 365 IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK | 366 IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK 367 /* allow 00 to be written to the index */; 368 369 wr32(&vsi->back->hw, 370 IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), 371 val); 372} 373 374static inline bool iavf_container_is_rx(struct iavf_q_vector *q_vector, 375 struct iavf_ring_container *rc) 376{ 377 return &q_vector->rx == rc; 378} 379 380static inline unsigned int iavf_itr_divisor(struct iavf_q_vector *q_vector) 381{ 382 unsigned int divisor; 383 384 switch (q_vector->adapter->link_speed) { 385 case VIRTCHNL_LINK_SPEED_40GB: 386 divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 1024; 387 break; 388 case VIRTCHNL_LINK_SPEED_25GB: 389 case VIRTCHNL_LINK_SPEED_20GB: 390 divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 512; 391 break; 392 default: 393 case VIRTCHNL_LINK_SPEED_10GB: 394 divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 256; 395 break; 396 case VIRTCHNL_LINK_SPEED_1GB: 397 case VIRTCHNL_LINK_SPEED_100MB: 398 divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 32; 399 break; 400 } 401 402 return divisor; 403} 404 405/** 406 * iavf_update_itr - update the dynamic ITR value based on statistics 407 * @q_vector: structure containing interrupt and ring information 408 * @rc: structure containing ring performance data 409 * 410 * Stores a new ITR value based on packets and byte 411 * counts during the last interrupt. The advantage of per interrupt 412 * computation is faster updates and more accurate ITR for the current 413 * traffic pattern. Constants in this function were computed 414 * based on theoretical maximum wire speed and thresholds were set based 415 * on testing data as well as attempting to minimize response time 416 * while increasing bulk throughput. 417 **/ 418static void iavf_update_itr(struct iavf_q_vector *q_vector, 419 struct iavf_ring_container *rc) 420{ 421 unsigned int avg_wire_size, packets, bytes, itr; 422 unsigned long next_update = jiffies; 423 424 /* If we don't have any rings just leave ourselves set for maximum 425 * possible latency so we take ourselves out of the equation. 426 */ 427 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) 428 return; 429 430 /* For Rx we want to push the delay up and default to low latency. 431 * for Tx we want to pull the delay down and default to high latency. 432 */ 433 itr = iavf_container_is_rx(q_vector, rc) ? 434 IAVF_ITR_ADAPTIVE_MIN_USECS | IAVF_ITR_ADAPTIVE_LATENCY : 435 IAVF_ITR_ADAPTIVE_MAX_USECS | IAVF_ITR_ADAPTIVE_LATENCY; 436 437 /* If we didn't update within up to 1 - 2 jiffies we can assume 438 * that either packets are coming in so slow there hasn't been 439 * any work, or that there is so much work that NAPI is dealing 440 * with interrupt moderation and we don't need to do anything. 441 */ 442 if (time_after(next_update, rc->next_update)) 443 goto clear_counts; 444 445 /* If itr_countdown is set it means we programmed an ITR within 446 * the last 4 interrupt cycles. This has a side effect of us 447 * potentially firing an early interrupt. In order to work around 448 * this we need to throw out any data received for a few 449 * interrupts following the update. 450 */ 451 if (q_vector->itr_countdown) { 452 itr = rc->target_itr; 453 goto clear_counts; 454 } 455 456 packets = rc->total_packets; 457 bytes = rc->total_bytes; 458 459 if (iavf_container_is_rx(q_vector, rc)) { 460 /* If Rx there are 1 to 4 packets and bytes are less than 461 * 9000 assume insufficient data to use bulk rate limiting 462 * approach unless Tx is already in bulk rate limiting. We 463 * are likely latency driven. 464 */ 465 if (packets && packets < 4 && bytes < 9000 && 466 (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) { 467 itr = IAVF_ITR_ADAPTIVE_LATENCY; 468 goto adjust_by_size; 469 } 470 } else if (packets < 4) { 471 /* If we have Tx and Rx ITR maxed and Tx ITR is running in 472 * bulk mode and we are receiving 4 or fewer packets just 473 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so 474 * that the Rx can relax. 475 */ 476 if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS && 477 (q_vector->rx.target_itr & IAVF_ITR_MASK) == 478 IAVF_ITR_ADAPTIVE_MAX_USECS) 479 goto clear_counts; 480 } else if (packets > 32) { 481 /* If we have processed over 32 packets in a single interrupt 482 * for Tx assume we need to switch over to "bulk" mode. 483 */ 484 rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY; 485 } 486 487 /* We have no packets to actually measure against. This means 488 * either one of the other queues on this vector is active or 489 * we are a Tx queue doing TSO with too high of an interrupt rate. 490 * 491 * Between 4 and 56 we can assume that our current interrupt delay 492 * is only slightly too low. As such we should increase it by a small 493 * fixed amount. 494 */ 495 if (packets < 56) { 496 itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC; 497 if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) { 498 itr &= IAVF_ITR_ADAPTIVE_LATENCY; 499 itr += IAVF_ITR_ADAPTIVE_MAX_USECS; 500 } 501 goto clear_counts; 502 } 503 504 if (packets <= 256) { 505 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr); 506 itr &= IAVF_ITR_MASK; 507 508 /* Between 56 and 112 is our "goldilocks" zone where we are 509 * working out "just right". Just report that our current 510 * ITR is good for us. 511 */ 512 if (packets <= 112) 513 goto clear_counts; 514 515 /* If packet count is 128 or greater we are likely looking 516 * at a slight overrun of the delay we want. Try halving 517 * our delay to see if that will cut the number of packets 518 * in half per interrupt. 519 */ 520 itr /= 2; 521 itr &= IAVF_ITR_MASK; 522 if (itr < IAVF_ITR_ADAPTIVE_MIN_USECS) 523 itr = IAVF_ITR_ADAPTIVE_MIN_USECS; 524 525 goto clear_counts; 526 } 527 528 /* The paths below assume we are dealing with a bulk ITR since 529 * number of packets is greater than 256. We are just going to have 530 * to compute a value and try to bring the count under control, 531 * though for smaller packet sizes there isn't much we can do as 532 * NAPI polling will likely be kicking in sooner rather than later. 533 */ 534 itr = IAVF_ITR_ADAPTIVE_BULK; 535 536adjust_by_size: 537 /* If packet counts are 256 or greater we can assume we have a gross 538 * overestimation of what the rate should be. Instead of trying to fine 539 * tune it just use the formula below to try and dial in an exact value 540 * give the current packet size of the frame. 541 */ 542 avg_wire_size = bytes / packets; 543 544 /* The following is a crude approximation of: 545 * wmem_default / (size + overhead) = desired_pkts_per_int 546 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 547 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 548 * 549 * Assuming wmem_default is 212992 and overhead is 640 bytes per 550 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 551 * formula down to 552 * 553 * (170 * (size + 24)) / (size + 640) = ITR 554 * 555 * We first do some math on the packet size and then finally bitshift 556 * by 8 after rounding up. We also have to account for PCIe link speed 557 * difference as ITR scales based on this. 558 */ 559 if (avg_wire_size <= 60) { 560 /* Start at 250k ints/sec */ 561 avg_wire_size = 4096; 562 } else if (avg_wire_size <= 380) { 563 /* 250K ints/sec to 60K ints/sec */ 564 avg_wire_size *= 40; 565 avg_wire_size += 1696; 566 } else if (avg_wire_size <= 1084) { 567 /* 60K ints/sec to 36K ints/sec */ 568 avg_wire_size *= 15; 569 avg_wire_size += 11452; 570 } else if (avg_wire_size <= 1980) { 571 /* 36K ints/sec to 30K ints/sec */ 572 avg_wire_size *= 5; 573 avg_wire_size += 22420; 574 } else { 575 /* plateau at a limit of 30K ints/sec */ 576 avg_wire_size = 32256; 577 } 578 579 /* If we are in low latency mode halve our delay which doubles the 580 * rate to somewhere between 100K to 16K ints/sec 581 */ 582 if (itr & IAVF_ITR_ADAPTIVE_LATENCY) 583 avg_wire_size /= 2; 584 585 /* Resultant value is 256 times larger than it needs to be. This 586 * gives us room to adjust the value as needed to either increase 587 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 588 * 589 * Use addition as we have already recorded the new latency flag 590 * for the ITR value. 591 */ 592 itr += DIV_ROUND_UP(avg_wire_size, iavf_itr_divisor(q_vector)) * 593 IAVF_ITR_ADAPTIVE_MIN_INC; 594 595 if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) { 596 itr &= IAVF_ITR_ADAPTIVE_LATENCY; 597 itr += IAVF_ITR_ADAPTIVE_MAX_USECS; 598 } 599 600clear_counts: 601 /* write back value */ 602 rc->target_itr = itr; 603 604 /* next update should occur within next jiffy */ 605 rc->next_update = next_update + 1; 606 607 rc->total_bytes = 0; 608 rc->total_packets = 0; 609} 610 611/** 612 * iavf_setup_tx_descriptors - Allocate the Tx descriptors 613 * @tx_ring: the tx ring to set up 614 * 615 * Return 0 on success, negative on error 616 **/ 617int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring) 618{ 619 struct device *dev = tx_ring->dev; 620 int bi_size; 621 622 if (!dev) 623 return -ENOMEM; 624 625 /* warn if we are about to overwrite the pointer */ 626 WARN_ON(tx_ring->tx_bi); 627 bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count; 628 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 629 if (!tx_ring->tx_bi) 630 goto err; 631 632 /* round up to nearest 4K */ 633 tx_ring->size = tx_ring->count * sizeof(struct iavf_tx_desc); 634 tx_ring->size = ALIGN(tx_ring->size, 4096); 635 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 636 &tx_ring->dma, GFP_KERNEL); 637 if (!tx_ring->desc) { 638 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 639 tx_ring->size); 640 goto err; 641 } 642 643 tx_ring->next_to_use = 0; 644 tx_ring->next_to_clean = 0; 645 tx_ring->tx_stats.prev_pkt_ctr = -1; 646 return 0; 647 648err: 649 kfree(tx_ring->tx_bi); 650 tx_ring->tx_bi = NULL; 651 return -ENOMEM; 652} 653 654/** 655 * iavf_clean_rx_ring - Free Rx buffers 656 * @rx_ring: ring to be cleaned 657 **/ 658void iavf_clean_rx_ring(struct iavf_ring *rx_ring) 659{ 660 unsigned long bi_size; 661 u16 i; 662 663 /* ring already cleared, nothing to do */ 664 if (!rx_ring->rx_bi) 665 return; 666 667 if (rx_ring->skb) { 668 dev_kfree_skb(rx_ring->skb); 669 rx_ring->skb = NULL; 670 } 671 672 /* Free all the Rx ring sk_buffs */ 673 for (i = 0; i < rx_ring->count; i++) { 674 struct iavf_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; 675 676 if (!rx_bi->page) 677 continue; 678 679 /* Invalidate cache lines that may have been written to by 680 * device so that we avoid corrupting memory. 681 */ 682 dma_sync_single_range_for_cpu(rx_ring->dev, 683 rx_bi->dma, 684 rx_bi->page_offset, 685 rx_ring->rx_buf_len, 686 DMA_FROM_DEVICE); 687 688 /* free resources associated with mapping */ 689 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 690 iavf_rx_pg_size(rx_ring), 691 DMA_FROM_DEVICE, 692 IAVF_RX_DMA_ATTR); 693 694 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 695 696 rx_bi->page = NULL; 697 rx_bi->page_offset = 0; 698 } 699 700 bi_size = sizeof(struct iavf_rx_buffer) * rx_ring->count; 701 memset(rx_ring->rx_bi, 0, bi_size); 702 703 /* Zero out the descriptor ring */ 704 memset(rx_ring->desc, 0, rx_ring->size); 705 706 rx_ring->next_to_alloc = 0; 707 rx_ring->next_to_clean = 0; 708 rx_ring->next_to_use = 0; 709} 710 711/** 712 * iavf_free_rx_resources - Free Rx resources 713 * @rx_ring: ring to clean the resources from 714 * 715 * Free all receive software resources 716 **/ 717void iavf_free_rx_resources(struct iavf_ring *rx_ring) 718{ 719 iavf_clean_rx_ring(rx_ring); 720 kfree(rx_ring->rx_bi); 721 rx_ring->rx_bi = NULL; 722 723 if (rx_ring->desc) { 724 dma_free_coherent(rx_ring->dev, rx_ring->size, 725 rx_ring->desc, rx_ring->dma); 726 rx_ring->desc = NULL; 727 } 728} 729 730/** 731 * iavf_setup_rx_descriptors - Allocate Rx descriptors 732 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 733 * 734 * Returns 0 on success, negative on failure 735 **/ 736int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring) 737{ 738 struct device *dev = rx_ring->dev; 739 int bi_size; 740 741 /* warn if we are about to overwrite the pointer */ 742 WARN_ON(rx_ring->rx_bi); 743 bi_size = sizeof(struct iavf_rx_buffer) * rx_ring->count; 744 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 745 if (!rx_ring->rx_bi) 746 goto err; 747 748 u64_stats_init(&rx_ring->syncp); 749 750 /* Round up to nearest 4K */ 751 rx_ring->size = rx_ring->count * sizeof(union iavf_32byte_rx_desc); 752 rx_ring->size = ALIGN(rx_ring->size, 4096); 753 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 754 &rx_ring->dma, GFP_KERNEL); 755 756 if (!rx_ring->desc) { 757 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 758 rx_ring->size); 759 goto err; 760 } 761 762 rx_ring->next_to_alloc = 0; 763 rx_ring->next_to_clean = 0; 764 rx_ring->next_to_use = 0; 765 766 return 0; 767err: 768 kfree(rx_ring->rx_bi); 769 rx_ring->rx_bi = NULL; 770 return -ENOMEM; 771} 772 773/** 774 * iavf_release_rx_desc - Store the new tail and head values 775 * @rx_ring: ring to bump 776 * @val: new head index 777 **/ 778static inline void iavf_release_rx_desc(struct iavf_ring *rx_ring, u32 val) 779{ 780 rx_ring->next_to_use = val; 781 782 /* update next to alloc since we have filled the ring */ 783 rx_ring->next_to_alloc = val; 784 785 /* Force memory writes to complete before letting h/w 786 * know there are new descriptors to fetch. (Only 787 * applicable for weak-ordered memory model archs, 788 * such as IA-64). 789 */ 790 wmb(); 791 writel(val, rx_ring->tail); 792} 793 794/** 795 * iavf_rx_offset - Return expected offset into page to access data 796 * @rx_ring: Ring we are requesting offset of 797 * 798 * Returns the offset value for ring into the data buffer. 799 */ 800static inline unsigned int iavf_rx_offset(struct iavf_ring *rx_ring) 801{ 802 return ring_uses_build_skb(rx_ring) ? IAVF_SKB_PAD : 0; 803} 804 805/** 806 * iavf_alloc_mapped_page - recycle or make a new page 807 * @rx_ring: ring to use 808 * @bi: rx_buffer struct to modify 809 * 810 * Returns true if the page was successfully allocated or 811 * reused. 812 **/ 813static bool iavf_alloc_mapped_page(struct iavf_ring *rx_ring, 814 struct iavf_rx_buffer *bi) 815{ 816 struct page *page = bi->page; 817 dma_addr_t dma; 818 819 /* since we are recycling buffers we should seldom need to alloc */ 820 if (likely(page)) { 821 rx_ring->rx_stats.page_reuse_count++; 822 return true; 823 } 824 825 /* alloc new page for storage */ 826 page = dev_alloc_pages(iavf_rx_pg_order(rx_ring)); 827 if (unlikely(!page)) { 828 rx_ring->rx_stats.alloc_page_failed++; 829 return false; 830 } 831 832 /* map page for use */ 833 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 834 iavf_rx_pg_size(rx_ring), 835 DMA_FROM_DEVICE, 836 IAVF_RX_DMA_ATTR); 837 838 /* if mapping failed free memory back to system since 839 * there isn't much point in holding memory we can't use 840 */ 841 if (dma_mapping_error(rx_ring->dev, dma)) { 842 __free_pages(page, iavf_rx_pg_order(rx_ring)); 843 rx_ring->rx_stats.alloc_page_failed++; 844 return false; 845 } 846 847 bi->dma = dma; 848 bi->page = page; 849 bi->page_offset = iavf_rx_offset(rx_ring); 850 851 /* initialize pagecnt_bias to 1 representing we fully own page */ 852 bi->pagecnt_bias = 1; 853 854 return true; 855} 856 857/** 858 * iavf_receive_skb - Send a completed packet up the stack 859 * @rx_ring: rx ring in play 860 * @skb: packet to send up 861 * @vlan_tag: vlan tag for packet 862 **/ 863static void iavf_receive_skb(struct iavf_ring *rx_ring, 864 struct sk_buff *skb, u16 vlan_tag) 865{ 866 struct iavf_q_vector *q_vector = rx_ring->q_vector; 867 868 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 869 (vlan_tag & VLAN_VID_MASK)) 870 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 871 872 napi_gro_receive(&q_vector->napi, skb); 873} 874 875/** 876 * iavf_alloc_rx_buffers - Replace used receive buffers 877 * @rx_ring: ring to place buffers on 878 * @cleaned_count: number of buffers to replace 879 * 880 * Returns false if all allocations were successful, true if any fail 881 **/ 882bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count) 883{ 884 u16 ntu = rx_ring->next_to_use; 885 union iavf_rx_desc *rx_desc; 886 struct iavf_rx_buffer *bi; 887 888 /* do nothing if no valid netdev defined */ 889 if (!rx_ring->netdev || !cleaned_count) 890 return false; 891 892 rx_desc = IAVF_RX_DESC(rx_ring, ntu); 893 bi = &rx_ring->rx_bi[ntu]; 894 895 do { 896 if (!iavf_alloc_mapped_page(rx_ring, bi)) 897 goto no_buffers; 898 899 /* sync the buffer for use by the device */ 900 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 901 bi->page_offset, 902 rx_ring->rx_buf_len, 903 DMA_FROM_DEVICE); 904 905 /* Refresh the desc even if buffer_addrs didn't change 906 * because each write-back erases this info. 907 */ 908 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 909 910 rx_desc++; 911 bi++; 912 ntu++; 913 if (unlikely(ntu == rx_ring->count)) { 914 rx_desc = IAVF_RX_DESC(rx_ring, 0); 915 bi = rx_ring->rx_bi; 916 ntu = 0; 917 } 918 919 /* clear the status bits for the next_to_use descriptor */ 920 rx_desc->wb.qword1.status_error_len = 0; 921 922 cleaned_count--; 923 } while (cleaned_count); 924 925 if (rx_ring->next_to_use != ntu) 926 iavf_release_rx_desc(rx_ring, ntu); 927 928 return false; 929 930no_buffers: 931 if (rx_ring->next_to_use != ntu) 932 iavf_release_rx_desc(rx_ring, ntu); 933 934 /* make sure to come back via polling to try again after 935 * allocation failure 936 */ 937 return true; 938} 939 940/** 941 * iavf_rx_checksum - Indicate in skb if hw indicated a good cksum 942 * @vsi: the VSI we care about 943 * @skb: skb currently being received and modified 944 * @rx_desc: the receive descriptor 945 **/ 946static inline void iavf_rx_checksum(struct iavf_vsi *vsi, 947 struct sk_buff *skb, 948 union iavf_rx_desc *rx_desc) 949{ 950 struct iavf_rx_ptype_decoded decoded; 951 u32 rx_error, rx_status; 952 bool ipv4, ipv6; 953 u8 ptype; 954 u64 qword; 955 956 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 957 ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT; 958 rx_error = (qword & IAVF_RXD_QW1_ERROR_MASK) >> 959 IAVF_RXD_QW1_ERROR_SHIFT; 960 rx_status = (qword & IAVF_RXD_QW1_STATUS_MASK) >> 961 IAVF_RXD_QW1_STATUS_SHIFT; 962 decoded = decode_rx_desc_ptype(ptype); 963 964 skb->ip_summed = CHECKSUM_NONE; 965 966 skb_checksum_none_assert(skb); 967 968 /* Rx csum enabled and ip headers found? */ 969 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 970 return; 971 972 /* did the hardware decode the packet and checksum? */ 973 if (!(rx_status & BIT(IAVF_RX_DESC_STATUS_L3L4P_SHIFT))) 974 return; 975 976 /* both known and outer_ip must be set for the below code to work */ 977 if (!(decoded.known && decoded.outer_ip)) 978 return; 979 980 ipv4 = (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP) && 981 (decoded.outer_ip_ver == IAVF_RX_PTYPE_OUTER_IPV4); 982 ipv6 = (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP) && 983 (decoded.outer_ip_ver == IAVF_RX_PTYPE_OUTER_IPV6); 984 985 if (ipv4 && 986 (rx_error & (BIT(IAVF_RX_DESC_ERROR_IPE_SHIFT) | 987 BIT(IAVF_RX_DESC_ERROR_EIPE_SHIFT)))) 988 goto checksum_fail; 989 990 /* likely incorrect csum if alternate IP extension headers found */ 991 if (ipv6 && 992 rx_status & BIT(IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 993 /* don't increment checksum err here, non-fatal err */ 994 return; 995 996 /* there was some L4 error, count error and punt packet to the stack */ 997 if (rx_error & BIT(IAVF_RX_DESC_ERROR_L4E_SHIFT)) 998 goto checksum_fail; 999 1000 /* handle packets that were not able to be checksummed due 1001 * to arrival speed, in this case the stack can compute 1002 * the csum. 1003 */ 1004 if (rx_error & BIT(IAVF_RX_DESC_ERROR_PPRS_SHIFT)) 1005 return; 1006 1007 /* Only report checksum unnecessary for TCP, UDP, or SCTP */ 1008 switch (decoded.inner_prot) { 1009 case IAVF_RX_PTYPE_INNER_PROT_TCP: 1010 case IAVF_RX_PTYPE_INNER_PROT_UDP: 1011 case IAVF_RX_PTYPE_INNER_PROT_SCTP: 1012 skb->ip_summed = CHECKSUM_UNNECESSARY; 1013 fallthrough; 1014 default: 1015 break; 1016 } 1017 1018 return; 1019 1020checksum_fail: 1021 vsi->back->hw_csum_rx_error++; 1022} 1023 1024/** 1025 * iavf_ptype_to_htype - get a hash type 1026 * @ptype: the ptype value from the descriptor 1027 * 1028 * Returns a hash type to be used by skb_set_hash 1029 **/ 1030static inline int iavf_ptype_to_htype(u8 ptype) 1031{ 1032 struct iavf_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1033 1034 if (!decoded.known) 1035 return PKT_HASH_TYPE_NONE; 1036 1037 if (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP && 1038 decoded.payload_layer == IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1039 return PKT_HASH_TYPE_L4; 1040 else if (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP && 1041 decoded.payload_layer == IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1042 return PKT_HASH_TYPE_L3; 1043 else 1044 return PKT_HASH_TYPE_L2; 1045} 1046 1047/** 1048 * iavf_rx_hash - set the hash value in the skb 1049 * @ring: descriptor ring 1050 * @rx_desc: specific descriptor 1051 * @skb: skb currently being received and modified 1052 * @rx_ptype: Rx packet type 1053 **/ 1054static inline void iavf_rx_hash(struct iavf_ring *ring, 1055 union iavf_rx_desc *rx_desc, 1056 struct sk_buff *skb, 1057 u8 rx_ptype) 1058{ 1059 u32 hash; 1060 const __le64 rss_mask = 1061 cpu_to_le64((u64)IAVF_RX_DESC_FLTSTAT_RSS_HASH << 1062 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT); 1063 1064 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1065 return; 1066 1067 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1068 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1069 skb_set_hash(skb, hash, iavf_ptype_to_htype(rx_ptype)); 1070 } 1071} 1072 1073/** 1074 * iavf_process_skb_fields - Populate skb header fields from Rx descriptor 1075 * @rx_ring: rx descriptor ring packet is being transacted on 1076 * @rx_desc: pointer to the EOP Rx descriptor 1077 * @skb: pointer to current skb being populated 1078 * @rx_ptype: the packet type decoded by hardware 1079 * 1080 * This function checks the ring, descriptor, and packet information in 1081 * order to populate the hash, checksum, VLAN, protocol, and 1082 * other fields within the skb. 1083 **/ 1084static inline 1085void iavf_process_skb_fields(struct iavf_ring *rx_ring, 1086 union iavf_rx_desc *rx_desc, struct sk_buff *skb, 1087 u8 rx_ptype) 1088{ 1089 iavf_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1090 1091 iavf_rx_checksum(rx_ring->vsi, skb, rx_desc); 1092 1093 skb_record_rx_queue(skb, rx_ring->queue_index); 1094 1095 /* modifies the skb - consumes the enet header */ 1096 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1097} 1098 1099/** 1100 * iavf_cleanup_headers - Correct empty headers 1101 * @rx_ring: rx descriptor ring packet is being transacted on 1102 * @skb: pointer to current skb being fixed 1103 * 1104 * Also address the case where we are pulling data in on pages only 1105 * and as such no data is present in the skb header. 1106 * 1107 * In addition if skb is not at least 60 bytes we need to pad it so that 1108 * it is large enough to qualify as a valid Ethernet frame. 1109 * 1110 * Returns true if an error was encountered and skb was freed. 1111 **/ 1112static bool iavf_cleanup_headers(struct iavf_ring *rx_ring, struct sk_buff *skb) 1113{ 1114 /* if eth_skb_pad returns an error the skb was freed */ 1115 if (eth_skb_pad(skb)) 1116 return true; 1117 1118 return false; 1119} 1120 1121/** 1122 * iavf_reuse_rx_page - page flip buffer and store it back on the ring 1123 * @rx_ring: rx descriptor ring to store buffers on 1124 * @old_buff: donor buffer to have page reused 1125 * 1126 * Synchronizes page for reuse by the adapter 1127 **/ 1128static void iavf_reuse_rx_page(struct iavf_ring *rx_ring, 1129 struct iavf_rx_buffer *old_buff) 1130{ 1131 struct iavf_rx_buffer *new_buff; 1132 u16 nta = rx_ring->next_to_alloc; 1133 1134 new_buff = &rx_ring->rx_bi[nta]; 1135 1136 /* update, and store next to alloc */ 1137 nta++; 1138 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1139 1140 /* transfer page from old buffer to new buffer */ 1141 new_buff->dma = old_buff->dma; 1142 new_buff->page = old_buff->page; 1143 new_buff->page_offset = old_buff->page_offset; 1144 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1145} 1146 1147/** 1148 * iavf_page_is_reusable - check if any reuse is possible 1149 * @page: page struct to check 1150 * 1151 * A page is not reusable if it was allocated under low memory 1152 * conditions, or it's not in the same NUMA node as this CPU. 1153 */ 1154static inline bool iavf_page_is_reusable(struct page *page) 1155{ 1156 return (page_to_nid(page) == numa_mem_id()) && 1157 !page_is_pfmemalloc(page); 1158} 1159 1160/** 1161 * iavf_can_reuse_rx_page - Determine if this page can be reused by 1162 * the adapter for another receive 1163 * 1164 * @rx_buffer: buffer containing the page 1165 * 1166 * If page is reusable, rx_buffer->page_offset is adjusted to point to 1167 * an unused region in the page. 1168 * 1169 * For small pages, @truesize will be a constant value, half the size 1170 * of the memory at page. We'll attempt to alternate between high and 1171 * low halves of the page, with one half ready for use by the hardware 1172 * and the other half being consumed by the stack. We use the page 1173 * ref count to determine whether the stack has finished consuming the 1174 * portion of this page that was passed up with a previous packet. If 1175 * the page ref count is >1, we'll assume the "other" half page is 1176 * still busy, and this page cannot be reused. 1177 * 1178 * For larger pages, @truesize will be the actual space used by the 1179 * received packet (adjusted upward to an even multiple of the cache 1180 * line size). This will advance through the page by the amount 1181 * actually consumed by the received packets while there is still 1182 * space for a buffer. Each region of larger pages will be used at 1183 * most once, after which the page will not be reused. 1184 * 1185 * In either case, if the page is reusable its refcount is increased. 1186 **/ 1187static bool iavf_can_reuse_rx_page(struct iavf_rx_buffer *rx_buffer) 1188{ 1189 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1190 struct page *page = rx_buffer->page; 1191 1192 /* Is any reuse possible? */ 1193 if (unlikely(!iavf_page_is_reusable(page))) 1194 return false; 1195 1196#if (PAGE_SIZE < 8192) 1197 /* if we are only owner of page we can reuse it */ 1198 if (unlikely((page_count(page) - pagecnt_bias) > 1)) 1199 return false; 1200#else 1201#define IAVF_LAST_OFFSET \ 1202 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IAVF_RXBUFFER_2048) 1203 if (rx_buffer->page_offset > IAVF_LAST_OFFSET) 1204 return false; 1205#endif 1206 1207 /* If we have drained the page fragment pool we need to update 1208 * the pagecnt_bias and page count so that we fully restock the 1209 * number of references the driver holds. 1210 */ 1211 if (unlikely(!pagecnt_bias)) { 1212 page_ref_add(page, USHRT_MAX); 1213 rx_buffer->pagecnt_bias = USHRT_MAX; 1214 } 1215 1216 return true; 1217} 1218 1219/** 1220 * iavf_add_rx_frag - Add contents of Rx buffer to sk_buff 1221 * @rx_ring: rx descriptor ring to transact packets on 1222 * @rx_buffer: buffer containing page to add 1223 * @skb: sk_buff to place the data into 1224 * @size: packet length from rx_desc 1225 * 1226 * This function will add the data contained in rx_buffer->page to the skb. 1227 * It will just attach the page as a frag to the skb. 1228 * 1229 * The function will then update the page offset. 1230 **/ 1231static void iavf_add_rx_frag(struct iavf_ring *rx_ring, 1232 struct iavf_rx_buffer *rx_buffer, 1233 struct sk_buff *skb, 1234 unsigned int size) 1235{ 1236#if (PAGE_SIZE < 8192) 1237 unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2; 1238#else 1239 unsigned int truesize = SKB_DATA_ALIGN(size + iavf_rx_offset(rx_ring)); 1240#endif 1241 1242 if (!size) 1243 return; 1244 1245 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1246 rx_buffer->page_offset, size, truesize); 1247 1248 /* page is being used so we must update the page offset */ 1249#if (PAGE_SIZE < 8192) 1250 rx_buffer->page_offset ^= truesize; 1251#else 1252 rx_buffer->page_offset += truesize; 1253#endif 1254} 1255 1256/** 1257 * iavf_get_rx_buffer - Fetch Rx buffer and synchronize data for use 1258 * @rx_ring: rx descriptor ring to transact packets on 1259 * @size: size of buffer to add to skb 1260 * 1261 * This function will pull an Rx buffer from the ring and synchronize it 1262 * for use by the CPU. 1263 */ 1264static struct iavf_rx_buffer *iavf_get_rx_buffer(struct iavf_ring *rx_ring, 1265 const unsigned int size) 1266{ 1267 struct iavf_rx_buffer *rx_buffer; 1268 1269 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; 1270 prefetchw(rx_buffer->page); 1271 if (!size) 1272 return rx_buffer; 1273 1274 /* we are reusing so sync this buffer for CPU use */ 1275 dma_sync_single_range_for_cpu(rx_ring->dev, 1276 rx_buffer->dma, 1277 rx_buffer->page_offset, 1278 size, 1279 DMA_FROM_DEVICE); 1280 1281 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 1282 rx_buffer->pagecnt_bias--; 1283 1284 return rx_buffer; 1285} 1286 1287/** 1288 * iavf_construct_skb - Allocate skb and populate it 1289 * @rx_ring: rx descriptor ring to transact packets on 1290 * @rx_buffer: rx buffer to pull data from 1291 * @size: size of buffer to add to skb 1292 * 1293 * This function allocates an skb. It then populates it with the page 1294 * data from the current receive descriptor, taking care to set up the 1295 * skb correctly. 1296 */ 1297static struct sk_buff *iavf_construct_skb(struct iavf_ring *rx_ring, 1298 struct iavf_rx_buffer *rx_buffer, 1299 unsigned int size) 1300{ 1301 void *va; 1302#if (PAGE_SIZE < 8192) 1303 unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2; 1304#else 1305 unsigned int truesize = SKB_DATA_ALIGN(size); 1306#endif 1307 unsigned int headlen; 1308 struct sk_buff *skb; 1309 1310 if (!rx_buffer) 1311 return NULL; 1312 /* prefetch first cache line of first page */ 1313 va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1314 net_prefetch(va); 1315 1316 /* allocate a skb to store the frags */ 1317 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 1318 IAVF_RX_HDR_SIZE, 1319 GFP_ATOMIC | __GFP_NOWARN); 1320 if (unlikely(!skb)) 1321 return NULL; 1322 1323 /* Determine available headroom for copy */ 1324 headlen = size; 1325 if (headlen > IAVF_RX_HDR_SIZE) 1326 headlen = eth_get_headlen(skb->dev, va, IAVF_RX_HDR_SIZE); 1327 1328 /* align pull length to size of long to optimize memcpy performance */ 1329 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 1330 1331 /* update all of the pointers */ 1332 size -= headlen; 1333 if (size) { 1334 skb_add_rx_frag(skb, 0, rx_buffer->page, 1335 rx_buffer->page_offset + headlen, 1336 size, truesize); 1337 1338 /* buffer is used by skb, update page_offset */ 1339#if (PAGE_SIZE < 8192) 1340 rx_buffer->page_offset ^= truesize; 1341#else 1342 rx_buffer->page_offset += truesize; 1343#endif 1344 } else { 1345 /* buffer is unused, reset bias back to rx_buffer */ 1346 rx_buffer->pagecnt_bias++; 1347 } 1348 1349 return skb; 1350} 1351 1352/** 1353 * iavf_build_skb - Build skb around an existing buffer 1354 * @rx_ring: Rx descriptor ring to transact packets on 1355 * @rx_buffer: Rx buffer to pull data from 1356 * @size: size of buffer to add to skb 1357 * 1358 * This function builds an skb around an existing Rx buffer, taking care 1359 * to set up the skb correctly and avoid any memcpy overhead. 1360 */ 1361static struct sk_buff *iavf_build_skb(struct iavf_ring *rx_ring, 1362 struct iavf_rx_buffer *rx_buffer, 1363 unsigned int size) 1364{ 1365 void *va; 1366#if (PAGE_SIZE < 8192) 1367 unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2; 1368#else 1369 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1370 SKB_DATA_ALIGN(IAVF_SKB_PAD + size); 1371#endif 1372 struct sk_buff *skb; 1373 1374 if (!rx_buffer || !size) 1375 return NULL; 1376 /* prefetch first cache line of first page */ 1377 va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1378 net_prefetch(va); 1379 1380 /* build an skb around the page buffer */ 1381 skb = build_skb(va - IAVF_SKB_PAD, truesize); 1382 if (unlikely(!skb)) 1383 return NULL; 1384 1385 /* update pointers within the skb to store the data */ 1386 skb_reserve(skb, IAVF_SKB_PAD); 1387 __skb_put(skb, size); 1388 1389 /* buffer is used by skb, update page_offset */ 1390#if (PAGE_SIZE < 8192) 1391 rx_buffer->page_offset ^= truesize; 1392#else 1393 rx_buffer->page_offset += truesize; 1394#endif 1395 1396 return skb; 1397} 1398 1399/** 1400 * iavf_put_rx_buffer - Clean up used buffer and either recycle or free 1401 * @rx_ring: rx descriptor ring to transact packets on 1402 * @rx_buffer: rx buffer to pull data from 1403 * 1404 * This function will clean up the contents of the rx_buffer. It will 1405 * either recycle the buffer or unmap it and free the associated resources. 1406 */ 1407static void iavf_put_rx_buffer(struct iavf_ring *rx_ring, 1408 struct iavf_rx_buffer *rx_buffer) 1409{ 1410 if (!rx_buffer) 1411 return; 1412 1413 if (iavf_can_reuse_rx_page(rx_buffer)) { 1414 /* hand second half of page back to the ring */ 1415 iavf_reuse_rx_page(rx_ring, rx_buffer); 1416 rx_ring->rx_stats.page_reuse_count++; 1417 } else { 1418 /* we are not reusing the buffer so unmap it */ 1419 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 1420 iavf_rx_pg_size(rx_ring), 1421 DMA_FROM_DEVICE, IAVF_RX_DMA_ATTR); 1422 __page_frag_cache_drain(rx_buffer->page, 1423 rx_buffer->pagecnt_bias); 1424 } 1425 1426 /* clear contents of buffer_info */ 1427 rx_buffer->page = NULL; 1428} 1429 1430/** 1431 * iavf_is_non_eop - process handling of non-EOP buffers 1432 * @rx_ring: Rx ring being processed 1433 * @rx_desc: Rx descriptor for current buffer 1434 * @skb: Current socket buffer containing buffer in progress 1435 * 1436 * This function updates next to clean. If the buffer is an EOP buffer 1437 * this function exits returning false, otherwise it will place the 1438 * sk_buff in the next buffer to be chained and return true indicating 1439 * that this is in fact a non-EOP buffer. 1440 **/ 1441static bool iavf_is_non_eop(struct iavf_ring *rx_ring, 1442 union iavf_rx_desc *rx_desc, 1443 struct sk_buff *skb) 1444{ 1445 u32 ntc = rx_ring->next_to_clean + 1; 1446 1447 /* fetch, update, and store next to clean */ 1448 ntc = (ntc < rx_ring->count) ? ntc : 0; 1449 rx_ring->next_to_clean = ntc; 1450 1451 prefetch(IAVF_RX_DESC(rx_ring, ntc)); 1452 1453 /* if we are the last buffer then there is nothing else to do */ 1454#define IAVF_RXD_EOF BIT(IAVF_RX_DESC_STATUS_EOF_SHIFT) 1455 if (likely(iavf_test_staterr(rx_desc, IAVF_RXD_EOF))) 1456 return false; 1457 1458 rx_ring->rx_stats.non_eop_descs++; 1459 1460 return true; 1461} 1462 1463/** 1464 * iavf_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1465 * @rx_ring: rx descriptor ring to transact packets on 1466 * @budget: Total limit on number of packets to process 1467 * 1468 * This function provides a "bounce buffer" approach to Rx interrupt 1469 * processing. The advantage to this is that on systems that have 1470 * expensive overhead for IOMMU access this provides a means of avoiding 1471 * it by maintaining the mapping of the page to the system. 1472 * 1473 * Returns amount of work completed 1474 **/ 1475static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget) 1476{ 1477 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1478 struct sk_buff *skb = rx_ring->skb; 1479 u16 cleaned_count = IAVF_DESC_UNUSED(rx_ring); 1480 bool failure = false; 1481 1482 while (likely(total_rx_packets < (unsigned int)budget)) { 1483 struct iavf_rx_buffer *rx_buffer; 1484 union iavf_rx_desc *rx_desc; 1485 unsigned int size; 1486 u16 vlan_tag; 1487 u8 rx_ptype; 1488 u64 qword; 1489 1490 /* return some buffers to hardware, one at a time is too slow */ 1491 if (cleaned_count >= IAVF_RX_BUFFER_WRITE) { 1492 failure = failure || 1493 iavf_alloc_rx_buffers(rx_ring, cleaned_count); 1494 cleaned_count = 0; 1495 } 1496 1497 rx_desc = IAVF_RX_DESC(rx_ring, rx_ring->next_to_clean); 1498 1499 /* status_error_len will always be zero for unused descriptors 1500 * because it's cleared in cleanup, and overlaps with hdr_addr 1501 * which is always zero because packet split isn't used, if the 1502 * hardware wrote DD then the length will be non-zero 1503 */ 1504 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1505 1506 /* This memory barrier is needed to keep us from reading 1507 * any other fields out of the rx_desc until we have 1508 * verified the descriptor has been written back. 1509 */ 1510 dma_rmb(); 1511#define IAVF_RXD_DD BIT(IAVF_RX_DESC_STATUS_DD_SHIFT) 1512 if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD)) 1513 break; 1514 1515 size = (qword & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >> 1516 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT; 1517 1518 iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb); 1519 rx_buffer = iavf_get_rx_buffer(rx_ring, size); 1520 1521 /* retrieve a buffer from the ring */ 1522 if (skb) 1523 iavf_add_rx_frag(rx_ring, rx_buffer, skb, size); 1524 else if (ring_uses_build_skb(rx_ring)) 1525 skb = iavf_build_skb(rx_ring, rx_buffer, size); 1526 else 1527 skb = iavf_construct_skb(rx_ring, rx_buffer, size); 1528 1529 /* exit if we failed to retrieve a buffer */ 1530 if (!skb) { 1531 rx_ring->rx_stats.alloc_buff_failed++; 1532 if (rx_buffer && size) 1533 rx_buffer->pagecnt_bias++; 1534 break; 1535 } 1536 1537 iavf_put_rx_buffer(rx_ring, rx_buffer); 1538 cleaned_count++; 1539 1540 if (iavf_is_non_eop(rx_ring, rx_desc, skb)) 1541 continue; 1542 1543 /* ERR_MASK will only have valid bits if EOP set, and 1544 * what we are doing here is actually checking 1545 * IAVF_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1546 * the error field 1547 */ 1548 if (unlikely(iavf_test_staterr(rx_desc, BIT(IAVF_RXD_QW1_ERROR_SHIFT)))) { 1549 dev_kfree_skb_any(skb); 1550 skb = NULL; 1551 continue; 1552 } 1553 1554 if (iavf_cleanup_headers(rx_ring, skb)) { 1555 skb = NULL; 1556 continue; 1557 } 1558 1559 /* probably a little skewed due to removing CRC */ 1560 total_rx_bytes += skb->len; 1561 1562 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1563 rx_ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >> 1564 IAVF_RXD_QW1_PTYPE_SHIFT; 1565 1566 /* populate checksum, VLAN, and protocol */ 1567 iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 1568 1569 1570 vlan_tag = (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? 1571 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; 1572 1573 iavf_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); 1574 iavf_receive_skb(rx_ring, skb, vlan_tag); 1575 skb = NULL; 1576 1577 /* update budget accounting */ 1578 total_rx_packets++; 1579 } 1580 1581 rx_ring->skb = skb; 1582 1583 u64_stats_update_begin(&rx_ring->syncp); 1584 rx_ring->stats.packets += total_rx_packets; 1585 rx_ring->stats.bytes += total_rx_bytes; 1586 u64_stats_update_end(&rx_ring->syncp); 1587 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1588 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1589 1590 /* guarantee a trip back through this routine if there was a failure */ 1591 return failure ? budget : (int)total_rx_packets; 1592} 1593 1594static inline u32 iavf_buildreg_itr(const int type, u16 itr) 1595{ 1596 u32 val; 1597 1598 /* We don't bother with setting the CLEARPBA bit as the data sheet 1599 * points out doing so is "meaningless since it was already 1600 * auto-cleared". The auto-clearing happens when the interrupt is 1601 * asserted. 1602 * 1603 * Hardware errata 28 for also indicates that writing to a 1604 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear 1605 * an event in the PBA anyway so we need to rely on the automask 1606 * to hold pending events for us until the interrupt is re-enabled 1607 * 1608 * The itr value is reported in microseconds, and the register 1609 * value is recorded in 2 microsecond units. For this reason we 1610 * only need to shift by the interval shift - 1 instead of the 1611 * full value. 1612 */ 1613 itr &= IAVF_ITR_MASK; 1614 1615 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK | 1616 (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | 1617 (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1)); 1618 1619 return val; 1620} 1621 1622/* a small macro to shorten up some long lines */ 1623#define INTREG IAVF_VFINT_DYN_CTLN1 1624 1625/* The act of updating the ITR will cause it to immediately trigger. In order 1626 * to prevent this from throwing off adaptive update statistics we defer the 1627 * update so that it can only happen so often. So after either Tx or Rx are 1628 * updated we make the adaptive scheme wait until either the ITR completely 1629 * expires via the next_update expiration or we have been through at least 1630 * 3 interrupts. 1631 */ 1632#define ITR_COUNTDOWN_START 3 1633 1634/** 1635 * iavf_update_enable_itr - Update itr and re-enable MSIX interrupt 1636 * @vsi: the VSI we care about 1637 * @q_vector: q_vector for which itr is being updated and interrupt enabled 1638 * 1639 **/ 1640static inline void iavf_update_enable_itr(struct iavf_vsi *vsi, 1641 struct iavf_q_vector *q_vector) 1642{ 1643 struct iavf_hw *hw = &vsi->back->hw; 1644 u32 intval; 1645 1646 /* These will do nothing if dynamic updates are not enabled */ 1647 iavf_update_itr(q_vector, &q_vector->tx); 1648 iavf_update_itr(q_vector, &q_vector->rx); 1649 1650 /* This block of logic allows us to get away with only updating 1651 * one ITR value with each interrupt. The idea is to perform a 1652 * pseudo-lazy update with the following criteria. 1653 * 1654 * 1. Rx is given higher priority than Tx if both are in same state 1655 * 2. If we must reduce an ITR that is given highest priority. 1656 * 3. We then give priority to increasing ITR based on amount. 1657 */ 1658 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { 1659 /* Rx ITR needs to be reduced, this is highest priority */ 1660 intval = iavf_buildreg_itr(IAVF_RX_ITR, 1661 q_vector->rx.target_itr); 1662 q_vector->rx.current_itr = q_vector->rx.target_itr; 1663 q_vector->itr_countdown = ITR_COUNTDOWN_START; 1664 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) || 1665 ((q_vector->rx.target_itr - q_vector->rx.current_itr) < 1666 (q_vector->tx.target_itr - q_vector->tx.current_itr))) { 1667 /* Tx ITR needs to be reduced, this is second priority 1668 * Tx ITR needs to be increased more than Rx, fourth priority 1669 */ 1670 intval = iavf_buildreg_itr(IAVF_TX_ITR, 1671 q_vector->tx.target_itr); 1672 q_vector->tx.current_itr = q_vector->tx.target_itr; 1673 q_vector->itr_countdown = ITR_COUNTDOWN_START; 1674 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) { 1675 /* Rx ITR needs to be increased, third priority */ 1676 intval = iavf_buildreg_itr(IAVF_RX_ITR, 1677 q_vector->rx.target_itr); 1678 q_vector->rx.current_itr = q_vector->rx.target_itr; 1679 q_vector->itr_countdown = ITR_COUNTDOWN_START; 1680 } else { 1681 /* No ITR update, lowest priority */ 1682 intval = iavf_buildreg_itr(IAVF_ITR_NONE, 0); 1683 if (q_vector->itr_countdown) 1684 q_vector->itr_countdown--; 1685 } 1686 1687 if (!test_bit(__IAVF_VSI_DOWN, vsi->state)) 1688 wr32(hw, INTREG(q_vector->reg_idx), intval); 1689} 1690 1691/** 1692 * iavf_napi_poll - NAPI polling Rx/Tx cleanup routine 1693 * @napi: napi struct with our devices info in it 1694 * @budget: amount of work driver is allowed to do this pass, in packets 1695 * 1696 * This function will clean all queues associated with a q_vector. 1697 * 1698 * Returns the amount of work done 1699 **/ 1700int iavf_napi_poll(struct napi_struct *napi, int budget) 1701{ 1702 struct iavf_q_vector *q_vector = 1703 container_of(napi, struct iavf_q_vector, napi); 1704 struct iavf_vsi *vsi = q_vector->vsi; 1705 struct iavf_ring *ring; 1706 bool clean_complete = true; 1707 bool arm_wb = false; 1708 int budget_per_ring; 1709 int work_done = 0; 1710 1711 if (test_bit(__IAVF_VSI_DOWN, vsi->state)) { 1712 napi_complete(napi); 1713 return 0; 1714 } 1715 1716 /* Since the actual Tx work is minimal, we can give the Tx a larger 1717 * budget and be more aggressive about cleaning up the Tx descriptors. 1718 */ 1719 iavf_for_each_ring(ring, q_vector->tx) { 1720 if (!iavf_clean_tx_irq(vsi, ring, budget)) { 1721 clean_complete = false; 1722 continue; 1723 } 1724 arm_wb |= ring->arm_wb; 1725 ring->arm_wb = false; 1726 } 1727 1728 /* Handle case where we are called by netpoll with a budget of 0 */ 1729 if (budget <= 0) 1730 goto tx_only; 1731 1732 /* We attempt to distribute budget to each Rx queue fairly, but don't 1733 * allow the budget to go below 1 because that would exit polling early. 1734 */ 1735 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 1736 1737 iavf_for_each_ring(ring, q_vector->rx) { 1738 int cleaned = iavf_clean_rx_irq(ring, budget_per_ring); 1739 1740 work_done += cleaned; 1741 /* if we clean as many as budgeted, we must not be done */ 1742 if (cleaned >= budget_per_ring) 1743 clean_complete = false; 1744 } 1745 1746 /* If work not completed, return budget and polling will return */ 1747 if (!clean_complete) { 1748 int cpu_id = smp_processor_id(); 1749 1750 /* It is possible that the interrupt affinity has changed but, 1751 * if the cpu is pegged at 100%, polling will never exit while 1752 * traffic continues and the interrupt will be stuck on this 1753 * cpu. We check to make sure affinity is correct before we 1754 * continue to poll, otherwise we must stop polling so the 1755 * interrupt can move to the correct cpu. 1756 */ 1757 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { 1758 /* Tell napi that we are done polling */ 1759 napi_complete_done(napi, work_done); 1760 1761 /* Force an interrupt */ 1762 iavf_force_wb(vsi, q_vector); 1763 1764 /* Return budget-1 so that polling stops */ 1765 return budget - 1; 1766 } 1767tx_only: 1768 if (arm_wb) { 1769 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 1770 iavf_enable_wb_on_itr(vsi, q_vector); 1771 } 1772 return budget; 1773 } 1774 1775 if (vsi->back->flags & IAVF_TXR_FLAGS_WB_ON_ITR) 1776 q_vector->arm_wb_state = false; 1777 1778 /* Exit the polling mode, but don't re-enable interrupts if stack might 1779 * poll us due to busy-polling 1780 */ 1781 if (likely(napi_complete_done(napi, work_done))) 1782 iavf_update_enable_itr(vsi, q_vector); 1783 1784 return min(work_done, budget - 1); 1785} 1786 1787/** 1788 * iavf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 1789 * @skb: send buffer 1790 * @tx_ring: ring to send buffer on 1791 * @flags: the tx flags to be set 1792 * 1793 * Checks the skb and set up correspondingly several generic transmit flags 1794 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 1795 * 1796 * Returns error code indicate the frame should be dropped upon error and the 1797 * otherwise returns 0 to indicate the flags has been set properly. 1798 **/ 1799static inline int iavf_tx_prepare_vlan_flags(struct sk_buff *skb, 1800 struct iavf_ring *tx_ring, 1801 u32 *flags) 1802{ 1803 __be16 protocol = skb->protocol; 1804 u32 tx_flags = 0; 1805 1806 if (protocol == htons(ETH_P_8021Q) && 1807 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1808 /* When HW VLAN acceleration is turned off by the user the 1809 * stack sets the protocol to 8021q so that the driver 1810 * can take any steps required to support the SW only 1811 * VLAN handling. In our case the driver doesn't need 1812 * to take any further steps so just set the protocol 1813 * to the encapsulated ethertype. 1814 */ 1815 skb->protocol = vlan_get_protocol(skb); 1816 goto out; 1817 } 1818 1819 /* if we have a HW VLAN tag being added, default to the HW one */ 1820 if (skb_vlan_tag_present(skb)) { 1821 tx_flags |= skb_vlan_tag_get(skb) << IAVF_TX_FLAGS_VLAN_SHIFT; 1822 tx_flags |= IAVF_TX_FLAGS_HW_VLAN; 1823 /* else if it is a SW VLAN, check the next protocol and store the tag */ 1824 } else if (protocol == htons(ETH_P_8021Q)) { 1825 struct vlan_hdr *vhdr, _vhdr; 1826 1827 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 1828 if (!vhdr) 1829 return -EINVAL; 1830 1831 protocol = vhdr->h_vlan_encapsulated_proto; 1832 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IAVF_TX_FLAGS_VLAN_SHIFT; 1833 tx_flags |= IAVF_TX_FLAGS_SW_VLAN; 1834 } 1835 1836out: 1837 *flags = tx_flags; 1838 return 0; 1839} 1840 1841/** 1842 * iavf_tso - set up the tso context descriptor 1843 * @first: pointer to first Tx buffer for xmit 1844 * @hdr_len: ptr to the size of the packet header 1845 * @cd_type_cmd_tso_mss: Quad Word 1 1846 * 1847 * Returns 0 if no TSO can happen, 1 if tso is going, or error 1848 **/ 1849static int iavf_tso(struct iavf_tx_buffer *first, u8 *hdr_len, 1850 u64 *cd_type_cmd_tso_mss) 1851{ 1852 struct sk_buff *skb = first->skb; 1853 u64 cd_cmd, cd_tso_len, cd_mss; 1854 union { 1855 struct iphdr *v4; 1856 struct ipv6hdr *v6; 1857 unsigned char *hdr; 1858 } ip; 1859 union { 1860 struct tcphdr *tcp; 1861 struct udphdr *udp; 1862 unsigned char *hdr; 1863 } l4; 1864 u32 paylen, l4_offset; 1865 u16 gso_segs, gso_size; 1866 int err; 1867 1868 if (skb->ip_summed != CHECKSUM_PARTIAL) 1869 return 0; 1870 1871 if (!skb_is_gso(skb)) 1872 return 0; 1873 1874 err = skb_cow_head(skb, 0); 1875 if (err < 0) 1876 return err; 1877 1878 ip.hdr = skb_network_header(skb); 1879 l4.hdr = skb_transport_header(skb); 1880 1881 /* initialize outer IP header fields */ 1882 if (ip.v4->version == 4) { 1883 ip.v4->tot_len = 0; 1884 ip.v4->check = 0; 1885 } else { 1886 ip.v6->payload_len = 0; 1887 } 1888 1889 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1890 SKB_GSO_GRE_CSUM | 1891 SKB_GSO_IPXIP4 | 1892 SKB_GSO_IPXIP6 | 1893 SKB_GSO_UDP_TUNNEL | 1894 SKB_GSO_UDP_TUNNEL_CSUM)) { 1895 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 1896 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 1897 l4.udp->len = 0; 1898 1899 /* determine offset of outer transport header */ 1900 l4_offset = l4.hdr - skb->data; 1901 1902 /* remove payload length from outer checksum */ 1903 paylen = skb->len - l4_offset; 1904 csum_replace_by_diff(&l4.udp->check, 1905 (__force __wsum)htonl(paylen)); 1906 } 1907 1908 /* reset pointers to inner headers */ 1909 ip.hdr = skb_inner_network_header(skb); 1910 l4.hdr = skb_inner_transport_header(skb); 1911 1912 /* initialize inner IP header fields */ 1913 if (ip.v4->version == 4) { 1914 ip.v4->tot_len = 0; 1915 ip.v4->check = 0; 1916 } else { 1917 ip.v6->payload_len = 0; 1918 } 1919 } 1920 1921 /* determine offset of inner transport header */ 1922 l4_offset = l4.hdr - skb->data; 1923 1924 /* remove payload length from inner checksum */ 1925 paylen = skb->len - l4_offset; 1926 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 1927 1928 /* compute length of segmentation header */ 1929 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 1930 1931 /* pull values out of skb_shinfo */ 1932 gso_size = skb_shinfo(skb)->gso_size; 1933 gso_segs = skb_shinfo(skb)->gso_segs; 1934 1935 /* update GSO size and bytecount with header size */ 1936 first->gso_segs = gso_segs; 1937 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1938 1939 /* find the field values */ 1940 cd_cmd = IAVF_TX_CTX_DESC_TSO; 1941 cd_tso_len = skb->len - *hdr_len; 1942 cd_mss = gso_size; 1943 *cd_type_cmd_tso_mss |= (cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) | 1944 (cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) | 1945 (cd_mss << IAVF_TXD_CTX_QW1_MSS_SHIFT); 1946 return 1; 1947} 1948 1949/** 1950 * iavf_tx_enable_csum - Enable Tx checksum offloads 1951 * @skb: send buffer 1952 * @tx_flags: pointer to Tx flags currently set 1953 * @td_cmd: Tx descriptor command bits to set 1954 * @td_offset: Tx descriptor header offsets to set 1955 * @tx_ring: Tx descriptor ring 1956 * @cd_tunneling: ptr to context desc bits 1957 **/ 1958static int iavf_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 1959 u32 *td_cmd, u32 *td_offset, 1960 struct iavf_ring *tx_ring, 1961 u32 *cd_tunneling) 1962{ 1963 union { 1964 struct iphdr *v4; 1965 struct ipv6hdr *v6; 1966 unsigned char *hdr; 1967 } ip; 1968 union { 1969 struct tcphdr *tcp; 1970 struct udphdr *udp; 1971 unsigned char *hdr; 1972 } l4; 1973 unsigned char *exthdr; 1974 u32 offset, cmd = 0; 1975 __be16 frag_off; 1976 u8 l4_proto = 0; 1977 1978 if (skb->ip_summed != CHECKSUM_PARTIAL) 1979 return 0; 1980 1981 ip.hdr = skb_network_header(skb); 1982 l4.hdr = skb_transport_header(skb); 1983 1984 /* compute outer L2 header size */ 1985 offset = ((ip.hdr - skb->data) / 2) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT; 1986 1987 if (skb->encapsulation) { 1988 u32 tunnel = 0; 1989 /* define outer network header type */ 1990 if (*tx_flags & IAVF_TX_FLAGS_IPV4) { 1991 tunnel |= (*tx_flags & IAVF_TX_FLAGS_TSO) ? 1992 IAVF_TX_CTX_EXT_IP_IPV4 : 1993 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM; 1994 1995 l4_proto = ip.v4->protocol; 1996 } else if (*tx_flags & IAVF_TX_FLAGS_IPV6) { 1997 tunnel |= IAVF_TX_CTX_EXT_IP_IPV6; 1998 1999 exthdr = ip.hdr + sizeof(*ip.v6); 2000 l4_proto = ip.v6->nexthdr; 2001 if (l4.hdr != exthdr) 2002 ipv6_skip_exthdr(skb, exthdr - skb->data, 2003 &l4_proto, &frag_off); 2004 } 2005 2006 /* define outer transport */ 2007 switch (l4_proto) { 2008 case IPPROTO_UDP: 2009 tunnel |= IAVF_TXD_CTX_UDP_TUNNELING; 2010 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL; 2011 break; 2012 case IPPROTO_GRE: 2013 tunnel |= IAVF_TXD_CTX_GRE_TUNNELING; 2014 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL; 2015 break; 2016 case IPPROTO_IPIP: 2017 case IPPROTO_IPV6: 2018 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL; 2019 l4.hdr = skb_inner_network_header(skb); 2020 break; 2021 default: 2022 if (*tx_flags & IAVF_TX_FLAGS_TSO) 2023 return -1; 2024 2025 skb_checksum_help(skb); 2026 return 0; 2027 } 2028 2029 /* compute outer L3 header size */ 2030 tunnel |= ((l4.hdr - ip.hdr) / 4) << 2031 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 2032 2033 /* switch IP header pointer from outer to inner header */ 2034 ip.hdr = skb_inner_network_header(skb); 2035 2036 /* compute tunnel header size */ 2037 tunnel |= ((ip.hdr - l4.hdr) / 2) << 2038 IAVF_TXD_CTX_QW0_NATLEN_SHIFT; 2039 2040 /* indicate if we need to offload outer UDP header */ 2041 if ((*tx_flags & IAVF_TX_FLAGS_TSO) && 2042 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2043 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 2044 tunnel |= IAVF_TXD_CTX_QW0_L4T_CS_MASK; 2045 2046 /* record tunnel offload values */ 2047 *cd_tunneling |= tunnel; 2048 2049 /* switch L4 header pointer from outer to inner */ 2050 l4.hdr = skb_inner_transport_header(skb); 2051 l4_proto = 0; 2052 2053 /* reset type as we transition from outer to inner headers */ 2054 *tx_flags &= ~(IAVF_TX_FLAGS_IPV4 | IAVF_TX_FLAGS_IPV6); 2055 if (ip.v4->version == 4) 2056 *tx_flags |= IAVF_TX_FLAGS_IPV4; 2057 if (ip.v6->version == 6) 2058 *tx_flags |= IAVF_TX_FLAGS_IPV6; 2059 } 2060 2061 /* Enable IP checksum offloads */ 2062 if (*tx_flags & IAVF_TX_FLAGS_IPV4) { 2063 l4_proto = ip.v4->protocol; 2064 /* the stack computes the IP header already, the only time we 2065 * need the hardware to recompute it is in the case of TSO. 2066 */ 2067 cmd |= (*tx_flags & IAVF_TX_FLAGS_TSO) ? 2068 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM : 2069 IAVF_TX_DESC_CMD_IIPT_IPV4; 2070 } else if (*tx_flags & IAVF_TX_FLAGS_IPV6) { 2071 cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6; 2072 2073 exthdr = ip.hdr + sizeof(*ip.v6); 2074 l4_proto = ip.v6->nexthdr; 2075 if (l4.hdr != exthdr) 2076 ipv6_skip_exthdr(skb, exthdr - skb->data, 2077 &l4_proto, &frag_off); 2078 } 2079 2080 /* compute inner L3 header size */ 2081 offset |= ((l4.hdr - ip.hdr) / 4) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT; 2082 2083 /* Enable L4 checksum offloads */ 2084 switch (l4_proto) { 2085 case IPPROTO_TCP: 2086 /* enable checksum offloads */ 2087 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP; 2088 offset |= l4.tcp->doff << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2089 break; 2090 case IPPROTO_SCTP: 2091 /* enable SCTP checksum offload */ 2092 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP; 2093 offset |= (sizeof(struct sctphdr) >> 2) << 2094 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2095 break; 2096 case IPPROTO_UDP: 2097 /* enable UDP checksum offload */ 2098 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP; 2099 offset |= (sizeof(struct udphdr) >> 2) << 2100 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2101 break; 2102 default: 2103 if (*tx_flags & IAVF_TX_FLAGS_TSO) 2104 return -1; 2105 skb_checksum_help(skb); 2106 return 0; 2107 } 2108 2109 *td_cmd |= cmd; 2110 *td_offset |= offset; 2111 2112 return 1; 2113} 2114 2115/** 2116 * iavf_create_tx_ctx Build the Tx context descriptor 2117 * @tx_ring: ring to create the descriptor on 2118 * @cd_type_cmd_tso_mss: Quad Word 1 2119 * @cd_tunneling: Quad Word 0 - bits 0-31 2120 * @cd_l2tag2: Quad Word 0 - bits 32-63 2121 **/ 2122static void iavf_create_tx_ctx(struct iavf_ring *tx_ring, 2123 const u64 cd_type_cmd_tso_mss, 2124 const u32 cd_tunneling, const u32 cd_l2tag2) 2125{ 2126 struct iavf_tx_context_desc *context_desc; 2127 int i = tx_ring->next_to_use; 2128 2129 if ((cd_type_cmd_tso_mss == IAVF_TX_DESC_DTYPE_CONTEXT) && 2130 !cd_tunneling && !cd_l2tag2) 2131 return; 2132 2133 /* grab the next descriptor */ 2134 context_desc = IAVF_TX_CTXTDESC(tx_ring, i); 2135 2136 i++; 2137 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2138 2139 /* cpu_to_le32 and assign to struct fields */ 2140 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2141 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2142 context_desc->rsvd = cpu_to_le16(0); 2143 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2144} 2145 2146/** 2147 * __iavf_chk_linearize - Check if there are more than 8 buffers per packet 2148 * @skb: send buffer 2149 * 2150 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 2151 * and so we need to figure out the cases where we need to linearize the skb. 2152 * 2153 * For TSO we need to count the TSO header and segment payload separately. 2154 * As such we need to check cases where we have 7 fragments or more as we 2155 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 2156 * the segment payload in the first descriptor, and another 7 for the 2157 * fragments. 2158 **/ 2159bool __iavf_chk_linearize(struct sk_buff *skb) 2160{ 2161 const skb_frag_t *frag, *stale; 2162 int nr_frags, sum; 2163 2164 /* no need to check if number of frags is less than 7 */ 2165 nr_frags = skb_shinfo(skb)->nr_frags; 2166 if (nr_frags < (IAVF_MAX_BUFFER_TXD - 1)) 2167 return false; 2168 2169 /* We need to walk through the list and validate that each group 2170 * of 6 fragments totals at least gso_size. 2171 */ 2172 nr_frags -= IAVF_MAX_BUFFER_TXD - 2; 2173 frag = &skb_shinfo(skb)->frags[0]; 2174 2175 /* Initialize size to the negative value of gso_size minus 1. We 2176 * use this as the worst case scenerio in which the frag ahead 2177 * of us only provides one byte which is why we are limited to 6 2178 * descriptors for a single transmit as the header and previous 2179 * fragment are already consuming 2 descriptors. 2180 */ 2181 sum = 1 - skb_shinfo(skb)->gso_size; 2182 2183 /* Add size of frags 0 through 4 to create our initial sum */ 2184 sum += skb_frag_size(frag++); 2185 sum += skb_frag_size(frag++); 2186 sum += skb_frag_size(frag++); 2187 sum += skb_frag_size(frag++); 2188 sum += skb_frag_size(frag++); 2189 2190 /* Walk through fragments adding latest fragment, testing it, and 2191 * then removing stale fragments from the sum. 2192 */ 2193 for (stale = &skb_shinfo(skb)->frags[0];; stale++) { 2194 int stale_size = skb_frag_size(stale); 2195 2196 sum += skb_frag_size(frag++); 2197 2198 /* The stale fragment may present us with a smaller 2199 * descriptor than the actual fragment size. To account 2200 * for that we need to remove all the data on the front and 2201 * figure out what the remainder would be in the last 2202 * descriptor associated with the fragment. 2203 */ 2204 if (stale_size > IAVF_MAX_DATA_PER_TXD) { 2205 int align_pad = -(skb_frag_off(stale)) & 2206 (IAVF_MAX_READ_REQ_SIZE - 1); 2207 2208 sum -= align_pad; 2209 stale_size -= align_pad; 2210 2211 do { 2212 sum -= IAVF_MAX_DATA_PER_TXD_ALIGNED; 2213 stale_size -= IAVF_MAX_DATA_PER_TXD_ALIGNED; 2214 } while (stale_size > IAVF_MAX_DATA_PER_TXD); 2215 } 2216 2217 /* if sum is negative we failed to make sufficient progress */ 2218 if (sum < 0) 2219 return true; 2220 2221 if (!nr_frags--) 2222 break; 2223 2224 sum -= stale_size; 2225 } 2226 2227 return false; 2228} 2229 2230/** 2231 * __iavf_maybe_stop_tx - 2nd level check for tx stop conditions 2232 * @tx_ring: the ring to be checked 2233 * @size: the size buffer we want to assure is available 2234 * 2235 * Returns -EBUSY if a stop is needed, else 0 2236 **/ 2237int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size) 2238{ 2239 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2240 /* Memory barrier before checking head and tail */ 2241 smp_mb(); 2242 2243 /* Check again in a case another CPU has just made room available. */ 2244 if (likely(IAVF_DESC_UNUSED(tx_ring) < size)) 2245 return -EBUSY; 2246 2247 /* A reprieve! - use start_queue because it doesn't call schedule */ 2248 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2249 ++tx_ring->tx_stats.restart_queue; 2250 return 0; 2251} 2252 2253/** 2254 * iavf_tx_map - Build the Tx descriptor 2255 * @tx_ring: ring to send buffer on 2256 * @skb: send buffer 2257 * @first: first buffer info buffer to use 2258 * @tx_flags: collected send information 2259 * @hdr_len: size of the packet header 2260 * @td_cmd: the command field in the descriptor 2261 * @td_offset: offset for checksum or crc 2262 **/ 2263static inline void iavf_tx_map(struct iavf_ring *tx_ring, struct sk_buff *skb, 2264 struct iavf_tx_buffer *first, u32 tx_flags, 2265 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2266{ 2267 unsigned int data_len = skb->data_len; 2268 unsigned int size = skb_headlen(skb); 2269 skb_frag_t *frag; 2270 struct iavf_tx_buffer *tx_bi; 2271 struct iavf_tx_desc *tx_desc; 2272 u16 i = tx_ring->next_to_use; 2273 u32 td_tag = 0; 2274 dma_addr_t dma; 2275 2276 if (tx_flags & IAVF_TX_FLAGS_HW_VLAN) { 2277 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1; 2278 td_tag = (tx_flags & IAVF_TX_FLAGS_VLAN_MASK) >> 2279 IAVF_TX_FLAGS_VLAN_SHIFT; 2280 } 2281 2282 first->tx_flags = tx_flags; 2283 2284 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2285 2286 tx_desc = IAVF_TX_DESC(tx_ring, i); 2287 tx_bi = first; 2288 2289 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2290 unsigned int max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED; 2291 2292 if (dma_mapping_error(tx_ring->dev, dma)) 2293 goto dma_error; 2294 2295 /* record length, and DMA address */ 2296 dma_unmap_len_set(tx_bi, len, size); 2297 dma_unmap_addr_set(tx_bi, dma, dma); 2298 2299 /* align size to end of page */ 2300 max_data += -dma & (IAVF_MAX_READ_REQ_SIZE - 1); 2301 tx_desc->buffer_addr = cpu_to_le64(dma); 2302 2303 while (unlikely(size > IAVF_MAX_DATA_PER_TXD)) { 2304 tx_desc->cmd_type_offset_bsz = 2305 build_ctob(td_cmd, td_offset, 2306 max_data, td_tag); 2307 2308 tx_desc++; 2309 i++; 2310 2311 if (i == tx_ring->count) { 2312 tx_desc = IAVF_TX_DESC(tx_ring, 0); 2313 i = 0; 2314 } 2315 2316 dma += max_data; 2317 size -= max_data; 2318 2319 max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED; 2320 tx_desc->buffer_addr = cpu_to_le64(dma); 2321 } 2322 2323 if (likely(!data_len)) 2324 break; 2325 2326 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 2327 size, td_tag); 2328 2329 tx_desc++; 2330 i++; 2331 2332 if (i == tx_ring->count) { 2333 tx_desc = IAVF_TX_DESC(tx_ring, 0); 2334 i = 0; 2335 } 2336 2337 size = skb_frag_size(frag); 2338 data_len -= size; 2339 2340 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 2341 DMA_TO_DEVICE); 2342 2343 tx_bi = &tx_ring->tx_bi[i]; 2344 } 2345 2346 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 2347 2348 i++; 2349 if (i == tx_ring->count) 2350 i = 0; 2351 2352 tx_ring->next_to_use = i; 2353 2354 iavf_maybe_stop_tx(tx_ring, DESC_NEEDED); 2355 2356 /* write last descriptor with RS and EOP bits */ 2357 td_cmd |= IAVF_TXD_CMD; 2358 tx_desc->cmd_type_offset_bsz = 2359 build_ctob(td_cmd, td_offset, size, td_tag); 2360 2361 skb_tx_timestamp(skb); 2362 2363 /* Force memory writes to complete before letting h/w know there 2364 * are new descriptors to fetch. 2365 * 2366 * We also use this memory barrier to make certain all of the 2367 * status bits have been updated before next_to_watch is written. 2368 */ 2369 wmb(); 2370 2371 /* set next_to_watch value indicating a packet is present */ 2372 first->next_to_watch = tx_desc; 2373 2374 /* notify HW of packet */ 2375 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 2376 writel(i, tx_ring->tail); 2377 } 2378 2379 return; 2380 2381dma_error: 2382 dev_info(tx_ring->dev, "TX DMA map failed\n"); 2383 2384 /* clear dma mappings for failed tx_bi map */ 2385 for (;;) { 2386 tx_bi = &tx_ring->tx_bi[i]; 2387 iavf_unmap_and_free_tx_resource(tx_ring, tx_bi); 2388 if (tx_bi == first) 2389 break; 2390 if (i == 0) 2391 i = tx_ring->count; 2392 i--; 2393 } 2394 2395 tx_ring->next_to_use = i; 2396} 2397 2398/** 2399 * iavf_xmit_frame_ring - Sends buffer on Tx ring 2400 * @skb: send buffer 2401 * @tx_ring: ring to send buffer on 2402 * 2403 * Returns NETDEV_TX_OK if sent, else an error code 2404 **/ 2405static netdev_tx_t iavf_xmit_frame_ring(struct sk_buff *skb, 2406 struct iavf_ring *tx_ring) 2407{ 2408 u64 cd_type_cmd_tso_mss = IAVF_TX_DESC_DTYPE_CONTEXT; 2409 u32 cd_tunneling = 0, cd_l2tag2 = 0; 2410 struct iavf_tx_buffer *first; 2411 u32 td_offset = 0; 2412 u32 tx_flags = 0; 2413 __be16 protocol; 2414 u32 td_cmd = 0; 2415 u8 hdr_len = 0; 2416 int tso, count; 2417 2418 /* prefetch the data, we'll need it later */ 2419 prefetch(skb->data); 2420 2421 iavf_trace(xmit_frame_ring, skb, tx_ring); 2422 2423 count = iavf_xmit_descriptor_count(skb); 2424 if (iavf_chk_linearize(skb, count)) { 2425 if (__skb_linearize(skb)) { 2426 dev_kfree_skb_any(skb); 2427 return NETDEV_TX_OK; 2428 } 2429 count = iavf_txd_use_count(skb->len); 2430 tx_ring->tx_stats.tx_linearize++; 2431 } 2432 2433 /* need: 1 descriptor per page * PAGE_SIZE/IAVF_MAX_DATA_PER_TXD, 2434 * + 1 desc for skb_head_len/IAVF_MAX_DATA_PER_TXD, 2435 * + 4 desc gap to avoid the cache line where head is, 2436 * + 1 desc for context descriptor, 2437 * otherwise try next time 2438 */ 2439 if (iavf_maybe_stop_tx(tx_ring, count + 4 + 1)) { 2440 tx_ring->tx_stats.tx_busy++; 2441 return NETDEV_TX_BUSY; 2442 } 2443 2444 /* record the location of the first descriptor for this packet */ 2445 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 2446 first->skb = skb; 2447 first->bytecount = skb->len; 2448 first->gso_segs = 1; 2449 2450 /* prepare the xmit flags */ 2451 if (iavf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 2452 goto out_drop; 2453 2454 /* obtain protocol of skb */ 2455 protocol = vlan_get_protocol(skb); 2456 2457 /* setup IPv4/IPv6 offloads */ 2458 if (protocol == htons(ETH_P_IP)) 2459 tx_flags |= IAVF_TX_FLAGS_IPV4; 2460 else if (protocol == htons(ETH_P_IPV6)) 2461 tx_flags |= IAVF_TX_FLAGS_IPV6; 2462 2463 tso = iavf_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 2464 2465 if (tso < 0) 2466 goto out_drop; 2467 else if (tso) 2468 tx_flags |= IAVF_TX_FLAGS_TSO; 2469 2470 /* Always offload the checksum, since it's in the data descriptor */ 2471 tso = iavf_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 2472 tx_ring, &cd_tunneling); 2473 if (tso < 0) 2474 goto out_drop; 2475 2476 /* always enable CRC insertion offload */ 2477 td_cmd |= IAVF_TX_DESC_CMD_ICRC; 2478 2479 iavf_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 2480 cd_tunneling, cd_l2tag2); 2481 2482 iavf_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 2483 td_cmd, td_offset); 2484 2485 return NETDEV_TX_OK; 2486 2487out_drop: 2488 iavf_trace(xmit_frame_ring_drop, first->skb, tx_ring); 2489 dev_kfree_skb_any(first->skb); 2490 first->skb = NULL; 2491 return NETDEV_TX_OK; 2492} 2493 2494/** 2495 * iavf_xmit_frame - Selects the correct VSI and Tx queue to send buffer 2496 * @skb: send buffer 2497 * @netdev: network interface device structure 2498 * 2499 * Returns NETDEV_TX_OK if sent, else an error code 2500 **/ 2501netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2502{ 2503 struct iavf_adapter *adapter = netdev_priv(netdev); 2504 struct iavf_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping]; 2505 2506 /* hardware can't handle really short frames, hardware padding works 2507 * beyond this point 2508 */ 2509 if (unlikely(skb->len < IAVF_MIN_TX_LEN)) { 2510 if (skb_pad(skb, IAVF_MIN_TX_LEN - skb->len)) 2511 return NETDEV_TX_OK; 2512 skb->len = IAVF_MIN_TX_LEN; 2513 skb_set_tail_pointer(skb, IAVF_MIN_TX_LEN); 2514 } 2515 2516 return iavf_xmit_frame_ring(skb, tx_ring); 2517} 2518