18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* Copyright(c) 1999 - 2018 Intel Corporation. */ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci#ifndef _E1000E_MANAGE_H_ 58c2ecf20Sopenharmony_ci#define _E1000E_MANAGE_H_ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cibool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 88c2ecf20Sopenharmony_cibool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 98c2ecf20Sopenharmony_cis32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 108c2ecf20Sopenharmony_cibool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cienum e1000_mng_mode { 138c2ecf20Sopenharmony_ci e1000_mng_mode_none = 0, 148c2ecf20Sopenharmony_ci e1000_mng_mode_asf, 158c2ecf20Sopenharmony_ci e1000_mng_mode_pt, 168c2ecf20Sopenharmony_ci e1000_mng_mode_ipmi, 178c2ecf20Sopenharmony_ci e1000_mng_mode_host_if_only 188c2ecf20Sopenharmony_ci}; 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci#define E1000_FACTPS_MNGCG 0x20000000 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define E1000_FWSM_MODE_MASK 0xE 238c2ecf20Sopenharmony_ci#define E1000_FWSM_MODE_SHIFT 1 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define E1000_MNG_IAMT_MODE 0x3 268c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 278c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 288c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 298c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 308c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 318c2ecf20Sopenharmony_ci#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#define E1000_VFTA_ENTRY_SHIFT 5 348c2ecf20Sopenharmony_ci#define E1000_VFTA_ENTRY_MASK 0x7F 358c2ecf20Sopenharmony_ci#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci#define E1000_HICR_EN 0x01 /* Enable bit - RO */ 388c2ecf20Sopenharmony_ci/* Driver sets this bit when done to put command in RAM */ 398c2ecf20Sopenharmony_ci#define E1000_HICR_C 0x02 408c2ecf20Sopenharmony_ci#define E1000_HICR_SV 0x04 /* Status Validity */ 418c2ecf20Sopenharmony_ci#define E1000_HICR_FW_RESET_ENABLE 0x40 428c2ecf20Sopenharmony_ci#define E1000_HICR_FW_RESET 0x80 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci/* Intel(R) Active Management Technology signature */ 458c2ecf20Sopenharmony_ci#define E1000_IAMT_SIGNATURE 0x544D4149 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci#endif 48