1// SPDX-License-Identifier: GPL-2.0+ 2/* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4#include <linux/debugfs.h> 5#include <linux/device.h> 6 7#include "hnae3.h" 8#include "hns3_enet.h" 9 10#define HNS3_DBG_READ_LEN 256 11#define HNS3_DBG_WRITE_LEN 1024 12 13static struct dentry *hns3_dbgfs_root; 14 15static int hns3_dbg_queue_info(struct hnae3_handle *h, 16 const char *cmd_buf) 17{ 18 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 19 struct hns3_nic_priv *priv = h->priv; 20 struct hns3_enet_ring *ring; 21 u32 base_add_l, base_add_h; 22 u32 queue_num, queue_max; 23 u32 value, i; 24 int cnt; 25 26 if (!priv->ring) { 27 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 28 return -EFAULT; 29 } 30 31 queue_max = h->kinfo.num_tqps; 32 cnt = kstrtouint(&cmd_buf[11], 0, &queue_num); 33 if (cnt) 34 queue_num = 0; 35 else 36 queue_max = queue_num + 1; 37 38 dev_info(&h->pdev->dev, "queue info\n"); 39 40 if (queue_num >= h->kinfo.num_tqps) { 41 dev_err(&h->pdev->dev, 42 "Queue number(%u) is out of range(0-%u)\n", queue_num, 43 h->kinfo.num_tqps - 1); 44 return -EINVAL; 45 } 46 47 for (i = queue_num; i < queue_max; i++) { 48 /* Each cycle needs to determine whether the instance is reset, 49 * to prevent reference to invalid memory. And need to ensure 50 * that the following code is executed within 100ms. 51 */ 52 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 53 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 54 return -EPERM; 55 56 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 57 base_add_h = readl_relaxed(ring->tqp->io_base + 58 HNS3_RING_RX_RING_BASEADDR_H_REG); 59 base_add_l = readl_relaxed(ring->tqp->io_base + 60 HNS3_RING_RX_RING_BASEADDR_L_REG); 61 dev_info(&h->pdev->dev, "RX(%u) BASE ADD: 0x%08x%08x\n", i, 62 base_add_h, base_add_l); 63 64 value = readl_relaxed(ring->tqp->io_base + 65 HNS3_RING_RX_RING_BD_NUM_REG); 66 dev_info(&h->pdev->dev, "RX(%u) RING BD NUM: %u\n", i, value); 67 68 value = readl_relaxed(ring->tqp->io_base + 69 HNS3_RING_RX_RING_BD_LEN_REG); 70 dev_info(&h->pdev->dev, "RX(%u) RING BD LEN: %u\n", i, value); 71 72 value = readl_relaxed(ring->tqp->io_base + 73 HNS3_RING_RX_RING_TAIL_REG); 74 dev_info(&h->pdev->dev, "RX(%u) RING TAIL: %u\n", i, value); 75 76 value = readl_relaxed(ring->tqp->io_base + 77 HNS3_RING_RX_RING_HEAD_REG); 78 dev_info(&h->pdev->dev, "RX(%u) RING HEAD: %u\n", i, value); 79 80 value = readl_relaxed(ring->tqp->io_base + 81 HNS3_RING_RX_RING_FBDNUM_REG); 82 dev_info(&h->pdev->dev, "RX(%u) RING FBDNUM: %u\n", i, value); 83 84 value = readl_relaxed(ring->tqp->io_base + 85 HNS3_RING_RX_RING_PKTNUM_RECORD_REG); 86 dev_info(&h->pdev->dev, "RX(%u) RING PKTNUM: %u\n", i, value); 87 88 ring = &priv->ring[i]; 89 base_add_h = readl_relaxed(ring->tqp->io_base + 90 HNS3_RING_TX_RING_BASEADDR_H_REG); 91 base_add_l = readl_relaxed(ring->tqp->io_base + 92 HNS3_RING_TX_RING_BASEADDR_L_REG); 93 dev_info(&h->pdev->dev, "TX(%u) BASE ADD: 0x%08x%08x\n", i, 94 base_add_h, base_add_l); 95 96 value = readl_relaxed(ring->tqp->io_base + 97 HNS3_RING_TX_RING_BD_NUM_REG); 98 dev_info(&h->pdev->dev, "TX(%u) RING BD NUM: %u\n", i, value); 99 100 value = readl_relaxed(ring->tqp->io_base + 101 HNS3_RING_TX_RING_TC_REG); 102 dev_info(&h->pdev->dev, "TX(%u) RING TC: %u\n", i, value); 103 104 value = readl_relaxed(ring->tqp->io_base + 105 HNS3_RING_TX_RING_TAIL_REG); 106 dev_info(&h->pdev->dev, "TX(%u) RING TAIL: %u\n", i, value); 107 108 value = readl_relaxed(ring->tqp->io_base + 109 HNS3_RING_TX_RING_HEAD_REG); 110 dev_info(&h->pdev->dev, "TX(%u) RING HEAD: %u\n", i, value); 111 112 value = readl_relaxed(ring->tqp->io_base + 113 HNS3_RING_TX_RING_FBDNUM_REG); 114 dev_info(&h->pdev->dev, "TX(%u) RING FBDNUM: %u\n", i, value); 115 116 value = readl_relaxed(ring->tqp->io_base + 117 HNS3_RING_TX_RING_OFFSET_REG); 118 dev_info(&h->pdev->dev, "TX(%u) RING OFFSET: %u\n", i, value); 119 120 value = readl_relaxed(ring->tqp->io_base + 121 HNS3_RING_TX_RING_PKTNUM_RECORD_REG); 122 dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n", i, value); 123 124 value = readl_relaxed(ring->tqp->io_base + HNS3_RING_EN_REG); 125 dev_info(&h->pdev->dev, "TX/RX(%u) RING EN: %s\n", i, 126 value ? "enable" : "disable"); 127 128 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) { 129 value = readl_relaxed(ring->tqp->io_base + 130 HNS3_RING_TX_EN_REG); 131 dev_info(&h->pdev->dev, "TX(%u) RING EN: %s\n", i, 132 value ? "enable" : "disable"); 133 134 value = readl_relaxed(ring->tqp->io_base + 135 HNS3_RING_RX_EN_REG); 136 dev_info(&h->pdev->dev, "RX(%u) RING EN: %s\n", i, 137 value ? "enable" : "disable"); 138 } 139 140 dev_info(&h->pdev->dev, "\n"); 141 } 142 143 return 0; 144} 145 146static int hns3_dbg_queue_map(struct hnae3_handle *h) 147{ 148 struct hns3_nic_priv *priv = h->priv; 149 int i; 150 151 if (!h->ae_algo->ops->get_global_queue_id) 152 return -EOPNOTSUPP; 153 154 dev_info(&h->pdev->dev, "map info for queue id and vector id\n"); 155 dev_info(&h->pdev->dev, 156 "local queue id | global queue id | vector id\n"); 157 for (i = 0; i < h->kinfo.num_tqps; i++) { 158 u16 global_qid; 159 160 global_qid = h->ae_algo->ops->get_global_queue_id(h, i); 161 if (!priv->ring || !priv->ring[i].tqp_vector) 162 continue; 163 164 dev_info(&h->pdev->dev, 165 " %4d %4d %4d\n", 166 i, global_qid, priv->ring[i].tqp_vector->vector_irq); 167 } 168 169 return 0; 170} 171 172static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf) 173{ 174 struct hns3_nic_priv *priv = h->priv; 175 struct hns3_desc *rx_desc, *tx_desc; 176 struct device *dev = &h->pdev->dev; 177 struct hns3_enet_ring *ring; 178 u32 tx_index, rx_index; 179 u32 q_num, value; 180 dma_addr_t addr; 181 int cnt; 182 183 cnt = sscanf(&cmd_buf[8], "%u %u", &q_num, &tx_index); 184 if (cnt == 2) { 185 rx_index = tx_index; 186 } else if (cnt != 1) { 187 dev_err(dev, "bd info: bad command string, cnt=%d\n", cnt); 188 return -EINVAL; 189 } 190 191 if (q_num >= h->kinfo.num_tqps) { 192 dev_err(dev, "Queue number(%u) is out of range(0-%u)\n", q_num, 193 h->kinfo.num_tqps - 1); 194 return -EINVAL; 195 } 196 197 ring = &priv->ring[q_num]; 198 value = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 199 tx_index = (cnt == 1) ? value : tx_index; 200 201 if (tx_index >= ring->desc_num) { 202 dev_err(dev, "bd index(%u) is out of range(0-%u)\n", tx_index, 203 ring->desc_num - 1); 204 return -EINVAL; 205 } 206 207 tx_desc = &ring->desc[tx_index]; 208 addr = le64_to_cpu(tx_desc->addr); 209 dev_info(dev, "TX Queue Num: %u, BD Index: %u\n", q_num, tx_index); 210 dev_info(dev, "(TX)addr: %pad\n", &addr); 211 dev_info(dev, "(TX)vlan_tag: %u\n", le16_to_cpu(tx_desc->tx.vlan_tag)); 212 dev_info(dev, "(TX)send_size: %u\n", 213 le16_to_cpu(tx_desc->tx.send_size)); 214 dev_info(dev, "(TX)vlan_tso: %u\n", tx_desc->tx.type_cs_vlan_tso); 215 dev_info(dev, "(TX)l2_len: %u\n", tx_desc->tx.l2_len); 216 dev_info(dev, "(TX)l3_len: %u\n", tx_desc->tx.l3_len); 217 dev_info(dev, "(TX)l4_len: %u\n", tx_desc->tx.l4_len); 218 dev_info(dev, "(TX)vlan_tag: %u\n", 219 le16_to_cpu(tx_desc->tx.outer_vlan_tag)); 220 dev_info(dev, "(TX)tv: %u\n", le16_to_cpu(tx_desc->tx.tv)); 221 dev_info(dev, "(TX)vlan_msec: %u\n", tx_desc->tx.ol_type_vlan_msec); 222 dev_info(dev, "(TX)ol2_len: %u\n", tx_desc->tx.ol2_len); 223 dev_info(dev, "(TX)ol3_len: %u\n", tx_desc->tx.ol3_len); 224 dev_info(dev, "(TX)ol4_len: %u\n", tx_desc->tx.ol4_len); 225 dev_info(dev, "(TX)paylen: %u\n", le32_to_cpu(tx_desc->tx.paylen)); 226 dev_info(dev, "(TX)vld_ra_ri: %u\n", 227 le16_to_cpu(tx_desc->tx.bdtp_fe_sc_vld_ra_ri)); 228 dev_info(dev, "(TX)mss: %u\n", le16_to_cpu(tx_desc->tx.mss)); 229 230 ring = &priv->ring[q_num + h->kinfo.num_tqps]; 231 value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG); 232 rx_index = (cnt == 1) ? value : tx_index; 233 rx_desc = &ring->desc[rx_index]; 234 235 addr = le64_to_cpu(rx_desc->addr); 236 dev_info(dev, "RX Queue Num: %u, BD Index: %u\n", q_num, rx_index); 237 dev_info(dev, "(RX)addr: %pad\n", &addr); 238 dev_info(dev, "(RX)l234_info: %u\n", 239 le32_to_cpu(rx_desc->rx.l234_info)); 240 dev_info(dev, "(RX)pkt_len: %u\n", le16_to_cpu(rx_desc->rx.pkt_len)); 241 dev_info(dev, "(RX)size: %u\n", le16_to_cpu(rx_desc->rx.size)); 242 dev_info(dev, "(RX)rss_hash: %u\n", le32_to_cpu(rx_desc->rx.rss_hash)); 243 dev_info(dev, "(RX)fd_id: %u\n", le16_to_cpu(rx_desc->rx.fd_id)); 244 dev_info(dev, "(RX)vlan_tag: %u\n", le16_to_cpu(rx_desc->rx.vlan_tag)); 245 dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n", 246 le16_to_cpu(rx_desc->rx.o_dm_vlan_id_fb)); 247 dev_info(dev, "(RX)ot_vlan_tag: %u\n", 248 le16_to_cpu(rx_desc->rx.ot_vlan_tag)); 249 dev_info(dev, "(RX)bd_base_info: %u\n", 250 le32_to_cpu(rx_desc->rx.bd_base_info)); 251 252 return 0; 253} 254 255static void hns3_dbg_help(struct hnae3_handle *h) 256{ 257#define HNS3_DBG_BUF_LEN 256 258 259 char printf_buf[HNS3_DBG_BUF_LEN]; 260 261 dev_info(&h->pdev->dev, "available commands\n"); 262 dev_info(&h->pdev->dev, "queue info <number>\n"); 263 dev_info(&h->pdev->dev, "queue map\n"); 264 dev_info(&h->pdev->dev, "bd info <q_num> <bd index>\n"); 265 dev_info(&h->pdev->dev, "dev capability\n"); 266 dev_info(&h->pdev->dev, "dev spec\n"); 267 268 if (!hns3_is_phys_func(h->pdev)) 269 return; 270 271 dev_info(&h->pdev->dev, "dump fd tcam\n"); 272 dev_info(&h->pdev->dev, "dump tc\n"); 273 dev_info(&h->pdev->dev, "dump tm map <q_num>\n"); 274 dev_info(&h->pdev->dev, "dump tm\n"); 275 dev_info(&h->pdev->dev, "dump qos pause cfg\n"); 276 dev_info(&h->pdev->dev, "dump qos pri map\n"); 277 dev_info(&h->pdev->dev, "dump qos buf cfg\n"); 278 dev_info(&h->pdev->dev, "dump mng tbl\n"); 279 dev_info(&h->pdev->dev, "dump reset info\n"); 280 dev_info(&h->pdev->dev, "dump m7 info\n"); 281 dev_info(&h->pdev->dev, "dump ncl_config <offset> <length>(in hex)\n"); 282 dev_info(&h->pdev->dev, "dump mac tnl status\n"); 283 dev_info(&h->pdev->dev, "dump loopback\n"); 284 dev_info(&h->pdev->dev, "dump qs shaper [qs id]\n"); 285 dev_info(&h->pdev->dev, "dump uc mac list <func id>\n"); 286 dev_info(&h->pdev->dev, "dump mc mac list <func id>\n"); 287 dev_info(&h->pdev->dev, "dump intr\n"); 288 289 memset(printf_buf, 0, HNS3_DBG_BUF_LEN); 290 strncat(printf_buf, "dump reg [[bios common] [ssu <port_id>]", 291 HNS3_DBG_BUF_LEN - 1); 292 strncat(printf_buf + strlen(printf_buf), 293 " [igu egu <port_id>] [rpu <tc_queue_num>]", 294 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1); 295 strncat(printf_buf + strlen(printf_buf), 296 " [rtc] [ppp] [rcb] [tqp <queue_num>] [mac]]\n", 297 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1); 298 dev_info(&h->pdev->dev, "%s", printf_buf); 299 300 memset(printf_buf, 0, HNS3_DBG_BUF_LEN); 301 strncat(printf_buf, "dump reg dcb <port_id> <pri_id> <pg_id>", 302 HNS3_DBG_BUF_LEN - 1); 303 strncat(printf_buf + strlen(printf_buf), " <rq_id> <nq_id> <qset_id>\n", 304 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1); 305 dev_info(&h->pdev->dev, "%s", printf_buf); 306} 307 308static void hns3_dbg_dev_caps(struct hnae3_handle *h) 309{ 310 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 311 unsigned long *caps; 312 313 caps = ae_dev->caps; 314 315 dev_info(&h->pdev->dev, "support FD: %s\n", 316 test_bit(HNAE3_DEV_SUPPORT_FD_B, caps) ? "yes" : "no"); 317 dev_info(&h->pdev->dev, "support GRO: %s\n", 318 test_bit(HNAE3_DEV_SUPPORT_GRO_B, caps) ? "yes" : "no"); 319 dev_info(&h->pdev->dev, "support FEC: %s\n", 320 test_bit(HNAE3_DEV_SUPPORT_FEC_B, caps) ? "yes" : "no"); 321 dev_info(&h->pdev->dev, "support UDP GSO: %s\n", 322 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, caps) ? "yes" : "no"); 323 dev_info(&h->pdev->dev, "support PTP: %s\n", 324 test_bit(HNAE3_DEV_SUPPORT_PTP_B, caps) ? "yes" : "no"); 325 dev_info(&h->pdev->dev, "support INT QL: %s\n", 326 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, caps) ? "yes" : "no"); 327} 328 329static void hns3_dbg_dev_specs(struct hnae3_handle *h) 330{ 331 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 332 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 333 struct hnae3_knic_private_info *kinfo = &h->kinfo; 334 struct hns3_nic_priv *priv = h->priv; 335 336 dev_info(priv->dev, "MAC entry num: %u\n", dev_specs->mac_entry_num); 337 dev_info(priv->dev, "MNG entry num: %u\n", dev_specs->mng_entry_num); 338 dev_info(priv->dev, "MAX non tso bd num: %u\n", 339 dev_specs->max_non_tso_bd_num); 340 dev_info(priv->dev, "RSS ind tbl size: %u\n", 341 dev_specs->rss_ind_tbl_size); 342 dev_info(priv->dev, "RSS key size: %u\n", dev_specs->rss_key_size); 343 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 344 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 345 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 346 347 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 348 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 349 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 350 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 351 dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max); 352} 353 354static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer, 355 size_t count, loff_t *ppos) 356{ 357 int uncopy_bytes; 358 char *buf; 359 int len; 360 361 if (*ppos != 0) 362 return 0; 363 364 if (count < HNS3_DBG_READ_LEN) 365 return -ENOSPC; 366 367 buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL); 368 if (!buf) 369 return -ENOMEM; 370 371 len = scnprintf(buf, HNS3_DBG_READ_LEN, "%s\n", 372 "Please echo help to cmd to get help information"); 373 uncopy_bytes = copy_to_user(buffer, buf, len); 374 375 kfree(buf); 376 377 if (uncopy_bytes) 378 return -EFAULT; 379 380 return (*ppos = len); 381} 382 383static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer, 384 size_t count, loff_t *ppos) 385{ 386 struct hnae3_handle *handle = filp->private_data; 387 struct hns3_nic_priv *priv = handle->priv; 388 char *cmd_buf, *cmd_buf_tmp; 389 int uncopied_bytes; 390 int ret = 0; 391 392 if (*ppos != 0) 393 return 0; 394 395 /* Judge if the instance is being reset. */ 396 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 397 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 398 return 0; 399 400 if (count > HNS3_DBG_WRITE_LEN) 401 return -ENOSPC; 402 403 cmd_buf = kzalloc(count + 1, GFP_KERNEL); 404 if (!cmd_buf) 405 return count; 406 407 uncopied_bytes = copy_from_user(cmd_buf, buffer, count); 408 if (uncopied_bytes) { 409 kfree(cmd_buf); 410 return -EFAULT; 411 } 412 413 cmd_buf[count] = '\0'; 414 415 cmd_buf_tmp = strchr(cmd_buf, '\n'); 416 if (cmd_buf_tmp) { 417 *cmd_buf_tmp = '\0'; 418 count = cmd_buf_tmp - cmd_buf + 1; 419 } 420 421 if (strncmp(cmd_buf, "help", 4) == 0) 422 hns3_dbg_help(handle); 423 else if (strncmp(cmd_buf, "queue info", 10) == 0) 424 ret = hns3_dbg_queue_info(handle, cmd_buf); 425 else if (strncmp(cmd_buf, "queue map", 9) == 0) 426 ret = hns3_dbg_queue_map(handle); 427 else if (strncmp(cmd_buf, "bd info", 7) == 0) 428 ret = hns3_dbg_bd_info(handle, cmd_buf); 429 else if (strncmp(cmd_buf, "dev capability", 14) == 0) 430 hns3_dbg_dev_caps(handle); 431 else if (strncmp(cmd_buf, "dev spec", 8) == 0) 432 hns3_dbg_dev_specs(handle); 433 else if (handle->ae_algo->ops->dbg_run_cmd) 434 ret = handle->ae_algo->ops->dbg_run_cmd(handle, cmd_buf); 435 else 436 ret = -EOPNOTSUPP; 437 438 if (ret) 439 hns3_dbg_help(handle); 440 441 kfree(cmd_buf); 442 cmd_buf = NULL; 443 444 return count; 445} 446 447static const struct file_operations hns3_dbg_cmd_fops = { 448 .owner = THIS_MODULE, 449 .open = simple_open, 450 .read = hns3_dbg_cmd_read, 451 .write = hns3_dbg_cmd_write, 452}; 453 454void hns3_dbg_init(struct hnae3_handle *handle) 455{ 456 const char *name = pci_name(handle->pdev); 457 458 handle->hnae3_dbgfs = debugfs_create_dir(name, hns3_dbgfs_root); 459 460 debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle, 461 &hns3_dbg_cmd_fops); 462} 463 464void hns3_dbg_uninit(struct hnae3_handle *handle) 465{ 466 debugfs_remove_recursive(handle->hnae3_dbgfs); 467 handle->hnae3_dbgfs = NULL; 468} 469 470void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 471{ 472 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 473} 474 475void hns3_dbg_unregister_debugfs(void) 476{ 477 debugfs_remove_recursive(hns3_dbgfs_root); 478 hns3_dbgfs_root = NULL; 479} 480