1/* SPDX-License-Identifier: GPL-2.0+ */ 2// Copyright (c) 2016-2017 Hisilicon Limited. 3 4#ifndef __HNAE3_H 5#define __HNAE3_H 6 7/* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24#include <linux/acpi.h> 25#include <linux/dcbnl.h> 26#include <linux/delay.h> 27#include <linux/device.h> 28#include <linux/module.h> 29#include <linux/netdevice.h> 30#include <linux/pci.h> 31#include <linux/types.h> 32 33#define HNAE3_MOD_VERSION "1.0" 34 35#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 36 37/* Device version */ 38#define HNAE3_DEVICE_VERSION_V1 0x00020 39#define HNAE3_DEVICE_VERSION_V2 0x00021 40#define HNAE3_DEVICE_VERSION_V3 0x00030 41 42#define HNAE3_PCI_REVISION_BIT_SIZE 8 43 44/* Device IDs */ 45#define HNAE3_DEV_ID_GE 0xA220 46#define HNAE3_DEV_ID_25GE 0xA221 47#define HNAE3_DEV_ID_25GE_RDMA 0xA222 48#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 49#define HNAE3_DEV_ID_50GE_RDMA 0xA224 50#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 51#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 52#define HNAE3_DEV_ID_200G_RDMA 0xA228 53#define HNAE3_DEV_ID_VF 0xA22E 54#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 55 56#define HNAE3_CLASS_NAME_SIZE 16 57 58#define HNAE3_DEV_INITED_B 0x0 59#define HNAE3_DEV_SUPPORT_ROCE_B 0x1 60#define HNAE3_DEV_SUPPORT_DCB_B 0x2 61#define HNAE3_KNIC_CLIENT_INITED_B 0x3 62#define HNAE3_UNIC_CLIENT_INITED_B 0x4 63#define HNAE3_ROCE_CLIENT_INITED_B 0x5 64 65#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 66 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 67 68#define hnae3_dev_roce_supported(hdev) \ 69 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 70 71#define hnae3_dev_dcb_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 73 74enum HNAE3_DEV_CAP_BITS { 75 HNAE3_DEV_SUPPORT_FD_B, 76 HNAE3_DEV_SUPPORT_GRO_B, 77 HNAE3_DEV_SUPPORT_FEC_B, 78 HNAE3_DEV_SUPPORT_UDP_GSO_B, 79 HNAE3_DEV_SUPPORT_QB_B, 80 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 81 HNAE3_DEV_SUPPORT_PTP_B, 82 HNAE3_DEV_SUPPORT_INT_QL_B, 83 HNAE3_DEV_SUPPORT_SIMPLE_BD_B, 84 HNAE3_DEV_SUPPORT_TX_PUSH_B, 85 HNAE3_DEV_SUPPORT_PHY_IMP_B, 86 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 87 HNAE3_DEV_SUPPORT_HW_PAD_B, 88 HNAE3_DEV_SUPPORT_STASH_B, 89}; 90 91#define hnae3_dev_fd_supported(hdev) \ 92 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 93 94#define hnae3_dev_gro_supported(hdev) \ 95 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 96 97#define hnae3_dev_fec_supported(hdev) \ 98 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 99 100#define hnae3_dev_udp_gso_supported(hdev) \ 101 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 102 103#define hnae3_dev_qb_supported(hdev) \ 104 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 105 106#define hnae3_dev_fd_forward_tc_supported(hdev) \ 107 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 108 109#define hnae3_dev_ptp_supported(hdev) \ 110 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 111 112#define hnae3_dev_int_ql_supported(hdev) \ 113 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 114 115#define hnae3_dev_simple_bd_supported(hdev) \ 116 test_bit(HNAE3_DEV_SUPPORT_SIMPLE_BD_B, (hdev)->ae_dev->caps) 117 118#define hnae3_dev_tx_push_supported(hdev) \ 119 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 120 121#define hnae3_dev_phy_imp_supported(hdev) \ 122 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 123 124#define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 125 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 126 127#define hnae3_dev_hw_pad_supported(hdev) \ 128 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 129 130#define hnae3_dev_stash_supported(hdev) \ 131 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 132 133#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 134 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 135 136#define ring_ptr_move_fw(ring, p) \ 137 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 138#define ring_ptr_move_bw(ring, p) \ 139 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 140 141enum hns_desc_type { 142 DESC_TYPE_UNKNOWN, 143 DESC_TYPE_SKB, 144 DESC_TYPE_FRAGLIST_SKB, 145 DESC_TYPE_PAGE, 146}; 147 148struct hnae3_handle; 149 150struct hnae3_queue { 151 void __iomem *io_base; 152 struct hnae3_ae_algo *ae_algo; 153 struct hnae3_handle *handle; 154 int tqp_index; /* index in a handle */ 155 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 156 u16 tx_desc_num; /* total number of tx desc */ 157 u16 rx_desc_num; /* total number of rx desc */ 158}; 159 160struct hns3_mac_stats { 161 u64 tx_pause_cnt; 162 u64 rx_pause_cnt; 163}; 164 165/* hnae3 loop mode */ 166enum hnae3_loop { 167 HNAE3_LOOP_APP, 168 HNAE3_LOOP_SERIAL_SERDES, 169 HNAE3_LOOP_PARALLEL_SERDES, 170 HNAE3_LOOP_PHY, 171 HNAE3_LOOP_NONE, 172}; 173 174enum hnae3_client_type { 175 HNAE3_CLIENT_KNIC, 176 HNAE3_CLIENT_ROCE, 177}; 178 179/* mac media type */ 180enum hnae3_media_type { 181 HNAE3_MEDIA_TYPE_UNKNOWN, 182 HNAE3_MEDIA_TYPE_FIBER, 183 HNAE3_MEDIA_TYPE_COPPER, 184 HNAE3_MEDIA_TYPE_BACKPLANE, 185 HNAE3_MEDIA_TYPE_NONE, 186}; 187 188/* must be consistent with definition in firmware */ 189enum hnae3_module_type { 190 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 191 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 192 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 193 HNAE3_MODULE_TYPE_AOC = 0x03, 194 HNAE3_MODULE_TYPE_CR = 0x04, 195 HNAE3_MODULE_TYPE_KR = 0x05, 196 HNAE3_MODULE_TYPE_TP = 0x06, 197}; 198 199enum hnae3_fec_mode { 200 HNAE3_FEC_AUTO = 0, 201 HNAE3_FEC_BASER, 202 HNAE3_FEC_RS, 203 HNAE3_FEC_USER_DEF, 204}; 205 206enum hnae3_reset_notify_type { 207 HNAE3_UP_CLIENT, 208 HNAE3_DOWN_CLIENT, 209 HNAE3_INIT_CLIENT, 210 HNAE3_UNINIT_CLIENT, 211}; 212 213enum hnae3_hw_error_type { 214 HNAE3_PPU_POISON_ERROR, 215 HNAE3_CMDQ_ECC_ERROR, 216 HNAE3_IMP_RD_POISON_ERROR, 217 HNAE3_ROCEE_AXI_RESP_ERROR, 218}; 219 220enum hnae3_reset_type { 221 HNAE3_VF_RESET, 222 HNAE3_VF_FUNC_RESET, 223 HNAE3_VF_PF_FUNC_RESET, 224 HNAE3_VF_FULL_RESET, 225 HNAE3_FLR_RESET, 226 HNAE3_FUNC_RESET, 227 HNAE3_GLOBAL_RESET, 228 HNAE3_IMP_RESET, 229 HNAE3_UNKNOWN_RESET, 230 HNAE3_NONE_RESET, 231 HNAE3_MAX_RESET, 232}; 233 234enum hnae3_port_base_vlan_state { 235 HNAE3_PORT_BASE_VLAN_DISABLE, 236 HNAE3_PORT_BASE_VLAN_ENABLE, 237 HNAE3_PORT_BASE_VLAN_MODIFY, 238 HNAE3_PORT_BASE_VLAN_NOCHANGE, 239}; 240 241struct hnae3_vector_info { 242 u8 __iomem *io_addr; 243 int vector; 244}; 245 246#define HNAE3_RING_TYPE_B 0 247#define HNAE3_RING_TYPE_TX 0 248#define HNAE3_RING_TYPE_RX 1 249#define HNAE3_RING_GL_IDX_S 0 250#define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 251#define HNAE3_RING_GL_RX 0 252#define HNAE3_RING_GL_TX 1 253 254#define HNAE3_FW_VERSION_BYTE3_SHIFT 24 255#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 256#define HNAE3_FW_VERSION_BYTE2_SHIFT 16 257#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 258#define HNAE3_FW_VERSION_BYTE1_SHIFT 8 259#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 260#define HNAE3_FW_VERSION_BYTE0_SHIFT 0 261#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 262 263struct hnae3_ring_chain_node { 264 struct hnae3_ring_chain_node *next; 265 u32 tqp_index; 266 u32 flag; 267 u32 int_gl_idx; 268}; 269 270#define HNAE3_IS_TX_RING(node) \ 271 (((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX) 272 273/* device specification info from firmware */ 274struct hnae3_dev_specs { 275 u32 mac_entry_num; /* number of mac-vlan table entry */ 276 u32 mng_entry_num; /* number of manager table entry */ 277 u32 max_tm_rate; 278 u16 rss_ind_tbl_size; 279 u16 rss_key_size; 280 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 281 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 282}; 283 284struct hnae3_client_ops { 285 int (*init_instance)(struct hnae3_handle *handle); 286 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 287 void (*link_status_change)(struct hnae3_handle *handle, bool state); 288 int (*setup_tc)(struct hnae3_handle *handle, u8 tc); 289 int (*reset_notify)(struct hnae3_handle *handle, 290 enum hnae3_reset_notify_type type); 291 void (*process_hw_error)(struct hnae3_handle *handle, 292 enum hnae3_hw_error_type); 293}; 294 295#define HNAE3_CLIENT_NAME_LENGTH 16 296struct hnae3_client { 297 char name[HNAE3_CLIENT_NAME_LENGTH]; 298 unsigned long state; 299 enum hnae3_client_type type; 300 const struct hnae3_client_ops *ops; 301 struct list_head node; 302}; 303 304#define HNAE3_DEV_CAPS_MAX_NUM 96 305struct hnae3_ae_dev { 306 struct pci_dev *pdev; 307 const struct hnae3_ae_ops *ops; 308 struct list_head node; 309 u32 flag; 310 unsigned long hw_err_reset_req; 311 struct hnae3_dev_specs dev_specs; 312 u32 dev_version; 313 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 314 void *priv; 315}; 316 317/* This struct defines the operation on the handle. 318 * 319 * init_ae_dev(): (mandatory) 320 * Get PF configure from pci_dev and initialize PF hardware 321 * uninit_ae_dev() 322 * Disable PF device and release PF resource 323 * register_client 324 * Register client to ae_dev 325 * unregister_client() 326 * Unregister client from ae_dev 327 * start() 328 * Enable the hardware 329 * stop() 330 * Disable the hardware 331 * start_client() 332 * Inform the hclge that client has been started 333 * stop_client() 334 * Inform the hclge that client has been stopped 335 * get_status() 336 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 337 * non-ok 338 * get_ksettings_an_result() 339 * Get negotiation status,speed and duplex 340 * get_media_type() 341 * Get media type of MAC 342 * check_port_speed() 343 * Check target speed whether is supported 344 * adjust_link() 345 * Adjust link status 346 * set_loopback() 347 * Set loopback 348 * set_promisc_mode 349 * Set promisc mode 350 * request_update_promisc_mode 351 * request to hclge(vf) to update promisc mode 352 * set_mtu() 353 * set mtu 354 * get_pauseparam() 355 * get tx and rx of pause frame use 356 * set_pauseparam() 357 * set tx and rx of pause frame use 358 * set_autoneg() 359 * set auto autonegotiation of pause frame use 360 * get_autoneg() 361 * get auto autonegotiation of pause frame use 362 * restart_autoneg() 363 * restart autonegotiation 364 * halt_autoneg() 365 * halt/resume autonegotiation when autonegotiation on 366 * get_coalesce_usecs() 367 * get usecs to delay a TX interrupt after a packet is sent 368 * get_rx_max_coalesced_frames() 369 * get Maximum number of packets to be sent before a TX interrupt. 370 * set_coalesce_usecs() 371 * set usecs to delay a TX interrupt after a packet is sent 372 * set_coalesce_frames() 373 * set Maximum number of packets to be sent before a TX interrupt. 374 * get_mac_addr() 375 * get mac address 376 * set_mac_addr() 377 * set mac address 378 * add_uc_addr 379 * Add unicast addr to mac table 380 * rm_uc_addr 381 * Remove unicast addr from mac table 382 * set_mc_addr() 383 * Set multicast address 384 * add_mc_addr 385 * Add multicast address to mac table 386 * rm_mc_addr 387 * Remove multicast address from mac table 388 * update_stats() 389 * Update Old network device statistics 390 * get_mac_stats() 391 * get mac pause statistics including tx_cnt and rx_cnt 392 * get_ethtool_stats() 393 * Get ethtool network device statistics 394 * get_strings() 395 * Get a set of strings that describe the requested objects 396 * get_sset_count() 397 * Get number of strings that @get_strings will write 398 * update_led_status() 399 * Update the led status 400 * set_led_id() 401 * Set led id 402 * get_regs() 403 * Get regs dump 404 * get_regs_len() 405 * Get the len of the regs dump 406 * get_rss_key_size() 407 * Get rss key size 408 * get_rss_indir_size() 409 * Get rss indirection table size 410 * get_rss() 411 * Get rss table 412 * set_rss() 413 * Set rss table 414 * get_tc_size() 415 * Get tc size of handle 416 * get_vector() 417 * Get vector number and vector information 418 * put_vector() 419 * Put the vector in hdev 420 * map_ring_to_vector() 421 * Map rings to vector 422 * unmap_ring_from_vector() 423 * Unmap rings from vector 424 * reset_queue() 425 * Reset queue 426 * get_fw_version() 427 * Get firmware version 428 * get_mdix_mode() 429 * Get media typr of phy 430 * enable_vlan_filter() 431 * Enable vlan filter 432 * set_vlan_filter() 433 * Set vlan filter config of Ports 434 * set_vf_vlan_filter() 435 * Set vlan filter config of vf 436 * enable_hw_strip_rxvtag() 437 * Enable/disable hardware strip vlan tag of packets received 438 * set_gro_en 439 * Enable/disable HW GRO 440 * add_arfs_entry 441 * Check the 5-tuples of flow, and create flow director rule 442 * get_vf_config 443 * Get the VF configuration setting by the host 444 * set_vf_link_state 445 * Set VF link status 446 * set_vf_spoofchk 447 * Enable/disable spoof check for specified vf 448 * set_vf_trust 449 * Enable/disable trust for specified vf, if the vf being trusted, then 450 * it can enable promisc mode 451 * set_vf_rate 452 * Set the max tx rate of specified vf. 453 * set_vf_mac 454 * Configure the default MAC for specified VF 455 * get_module_eeprom 456 * Get the optical module eeprom info. 457 */ 458struct hnae3_ae_ops { 459 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 460 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 461 void (*flr_prepare)(struct hnae3_ae_dev *ae_dev); 462 void (*flr_done)(struct hnae3_ae_dev *ae_dev); 463 int (*init_client_instance)(struct hnae3_client *client, 464 struct hnae3_ae_dev *ae_dev); 465 void (*uninit_client_instance)(struct hnae3_client *client, 466 struct hnae3_ae_dev *ae_dev); 467 int (*start)(struct hnae3_handle *handle); 468 void (*stop)(struct hnae3_handle *handle); 469 int (*client_start)(struct hnae3_handle *handle); 470 void (*client_stop)(struct hnae3_handle *handle); 471 int (*get_status)(struct hnae3_handle *handle); 472 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 473 u8 *auto_neg, u32 *speed, u8 *duplex); 474 475 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 476 u8 duplex); 477 478 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 479 u8 *module_type); 480 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 481 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 482 u8 *fec_mode); 483 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 484 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 485 int (*set_loopback)(struct hnae3_handle *handle, 486 enum hnae3_loop loop_mode, bool en); 487 488 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 489 bool en_mc_pmc); 490 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 491 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 492 493 void (*get_pauseparam)(struct hnae3_handle *handle, 494 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 495 int (*set_pauseparam)(struct hnae3_handle *handle, 496 u32 auto_neg, u32 rx_en, u32 tx_en); 497 498 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 499 int (*get_autoneg)(struct hnae3_handle *handle); 500 int (*restart_autoneg)(struct hnae3_handle *handle); 501 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 502 503 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 504 u32 *tx_usecs, u32 *rx_usecs); 505 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 506 u32 *tx_frames, u32 *rx_frames); 507 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 508 int (*set_coalesce_frames)(struct hnae3_handle *handle, 509 u32 coalesce_frames); 510 void (*get_coalesce_range)(struct hnae3_handle *handle, 511 u32 *tx_frames_low, u32 *rx_frames_low, 512 u32 *tx_frames_high, u32 *rx_frames_high, 513 u32 *tx_usecs_low, u32 *rx_usecs_low, 514 u32 *tx_usecs_high, u32 *rx_usecs_high); 515 516 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 517 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 518 bool is_first); 519 int (*do_ioctl)(struct hnae3_handle *handle, 520 struct ifreq *ifr, int cmd); 521 int (*add_uc_addr)(struct hnae3_handle *handle, 522 const unsigned char *addr); 523 int (*rm_uc_addr)(struct hnae3_handle *handle, 524 const unsigned char *addr); 525 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 526 int (*add_mc_addr)(struct hnae3_handle *handle, 527 const unsigned char *addr); 528 int (*rm_mc_addr)(struct hnae3_handle *handle, 529 const unsigned char *addr); 530 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 531 void (*update_stats)(struct hnae3_handle *handle, 532 struct net_device_stats *net_stats); 533 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 534 void (*get_mac_stats)(struct hnae3_handle *handle, 535 struct hns3_mac_stats *mac_stats); 536 void (*get_strings)(struct hnae3_handle *handle, 537 u32 stringset, u8 *data); 538 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 539 540 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 541 void *data); 542 int (*get_regs_len)(struct hnae3_handle *handle); 543 544 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 545 u32 (*get_rss_indir_size)(struct hnae3_handle *handle); 546 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 547 u8 *hfunc); 548 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 549 const u8 *key, const u8 hfunc); 550 int (*set_rss_tuple)(struct hnae3_handle *handle, 551 struct ethtool_rxnfc *cmd); 552 int (*get_rss_tuple)(struct hnae3_handle *handle, 553 struct ethtool_rxnfc *cmd); 554 555 int (*get_tc_size)(struct hnae3_handle *handle); 556 557 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 558 struct hnae3_vector_info *vector_info); 559 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 560 int (*map_ring_to_vector)(struct hnae3_handle *handle, 561 int vector_num, 562 struct hnae3_ring_chain_node *vr_chain); 563 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 564 int vector_num, 565 struct hnae3_ring_chain_node *vr_chain); 566 567 int (*reset_queue)(struct hnae3_handle *handle, u16 queue_id); 568 u32 (*get_fw_version)(struct hnae3_handle *handle); 569 void (*get_mdix_mode)(struct hnae3_handle *handle, 570 u8 *tp_mdix_ctrl, u8 *tp_mdix); 571 572 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 573 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 574 u16 vlan_id, bool is_kill); 575 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 576 u16 vlan, u8 qos, __be16 proto); 577 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 578 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 579 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 580 unsigned long *addr); 581 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 582 enum hnae3_reset_type rst_type); 583 void (*get_channels)(struct hnae3_handle *handle, 584 struct ethtool_channels *ch); 585 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 586 u16 *alloc_tqps, u16 *max_rss_size); 587 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 588 bool rxfh_configured); 589 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 590 u32 *flowctrl_adv); 591 int (*set_led_id)(struct hnae3_handle *handle, 592 enum ethtool_phys_id_state status); 593 void (*get_link_mode)(struct hnae3_handle *handle, 594 unsigned long *supported, 595 unsigned long *advertising); 596 int (*add_fd_entry)(struct hnae3_handle *handle, 597 struct ethtool_rxnfc *cmd); 598 int (*del_fd_entry)(struct hnae3_handle *handle, 599 struct ethtool_rxnfc *cmd); 600 void (*del_all_fd_entries)(struct hnae3_handle *handle, 601 bool clear_list); 602 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 603 struct ethtool_rxnfc *cmd); 604 int (*get_fd_rule_info)(struct hnae3_handle *handle, 605 struct ethtool_rxnfc *cmd); 606 int (*get_fd_all_rules)(struct hnae3_handle *handle, 607 struct ethtool_rxnfc *cmd, u32 *rule_locs); 608 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 609 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 610 u16 flow_id, struct flow_keys *fkeys); 611 int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); 612 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 613 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 614 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 615 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 616 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 617 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 618 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 619 int (*mac_connect_phy)(struct hnae3_handle *handle); 620 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 621 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 622 struct ifla_vf_info *ivf); 623 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 624 int link_state); 625 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 626 bool enable); 627 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 628 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 629 int min_tx_rate, int max_tx_rate, bool force); 630 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 631 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 632 u32 len, u8 *data); 633 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 634}; 635 636struct hnae3_dcb_ops { 637 /* IEEE 802.1Qaz std */ 638 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 639 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 640 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 641 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 642 643 /* DCBX configuration */ 644 u8 (*getdcbx)(struct hnae3_handle *); 645 u8 (*setdcbx)(struct hnae3_handle *, u8); 646 647 int (*setup_tc)(struct hnae3_handle *, u8, u8 *); 648}; 649 650struct hnae3_ae_algo { 651 const struct hnae3_ae_ops *ops; 652 struct list_head node; 653 const struct pci_device_id *pdev_id_table; 654}; 655 656#define HNAE3_INT_NAME_LEN 32 657#define HNAE3_ITR_COUNTDOWN_START 100 658 659struct hnae3_tc_info { 660 u16 tqp_offset; /* TQP offset from base TQP */ 661 u16 tqp_count; /* Total TQPs */ 662 u8 tc; /* TC index */ 663 bool enable; /* If this TC is enable or not */ 664}; 665 666#define HNAE3_MAX_TC 8 667#define HNAE3_MAX_USER_PRIO 8 668struct hnae3_knic_private_info { 669 struct net_device *netdev; /* Set by KNIC client when init instance */ 670 u16 rss_size; /* Allocated RSS queues */ 671 u16 req_rss_size; 672 u16 rx_buf_len; 673 u16 num_tx_desc; 674 u16 num_rx_desc; 675 676 u8 num_tc; /* Total number of enabled TCs */ 677 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 678 struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */ 679 680 u16 num_tqps; /* total number of TQPs in this handle */ 681 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 682 const struct hnae3_dcb_ops *dcb_ops; 683 684 u16 int_rl_setting; 685 enum pkt_hash_types rss_type; 686}; 687 688struct hnae3_roce_private_info { 689 struct net_device *netdev; 690 void __iomem *roce_io_base; 691 int base_vector; 692 int num_vectors; 693 694 /* The below attributes defined for RoCE client, hnae3 gives 695 * initial values to them, and RoCE client can modify and use 696 * them. 697 */ 698 unsigned long reset_state; 699 unsigned long instance_state; 700 unsigned long state; 701}; 702 703#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 704#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 705#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 706#define HNAE3_SUPPORT_VF BIT(3) 707#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 708 709#define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 710#define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 711#define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 712#define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 713#define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 714#define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ 715#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 716#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 717 718struct hnae3_handle { 719 struct hnae3_client *client; 720 struct pci_dev *pdev; 721 void *priv; 722 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 723 u64 flags; /* Indicate the capabilities for this handle */ 724 725 union { 726 struct net_device *netdev; /* first member */ 727 struct hnae3_knic_private_info kinfo; 728 struct hnae3_roce_private_info rinfo; 729 }; 730 731 u32 numa_node_mask; /* for multi-chip support */ 732 733 enum hnae3_port_base_vlan_state port_base_vlan_state; 734 735 u8 netdev_flags; 736 struct dentry *hnae3_dbgfs; 737 738 /* Network interface message level enabled bits */ 739 u32 msg_enable; 740}; 741 742#define hnae3_set_field(origin, mask, shift, val) \ 743 do { \ 744 (origin) &= (~(mask)); \ 745 (origin) |= ((val) << (shift)) & (mask); \ 746 } while (0) 747#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 748 749#define hnae3_set_bit(origin, shift, val) \ 750 hnae3_set_field((origin), (0x1 << (shift)), (shift), (val)) 751#define hnae3_get_bit(origin, shift) \ 752 hnae3_get_field((origin), (0x1 << (shift)), (shift)) 753 754int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 755void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 756 757void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo); 758void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 759void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 760 761void hnae3_unregister_client(struct hnae3_client *client); 762int hnae3_register_client(struct hnae3_client *client); 763 764void hnae3_set_client_init_flag(struct hnae3_client *client, 765 struct hnae3_ae_dev *ae_dev, 766 unsigned int inited); 767#endif 768