1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Google virtual Ethernet (gve) driver 3 * 4 * Copyright (C) 2015-2019 Google, Inc. 5 */ 6 7#ifndef _GVE_H_ 8#define _GVE_H_ 9 10#include <linux/dma-mapping.h> 11#include <linux/netdevice.h> 12#include <linux/pci.h> 13#include <linux/u64_stats_sync.h> 14#include "gve_desc.h" 15 16#ifndef PCI_VENDOR_ID_GOOGLE 17#define PCI_VENDOR_ID_GOOGLE 0x1ae0 18#endif 19 20#define PCI_DEV_ID_GVNIC 0x0042 21 22#define GVE_REGISTER_BAR 0 23#define GVE_DOORBELL_BAR 2 24 25/* Driver can alloc up to 2 segments for the header and 2 for the payload. */ 26#define GVE_TX_MAX_IOVEC 4 27/* 1 for management, 1 for rx, 1 for tx */ 28#define GVE_MIN_MSIX 3 29 30/* Numbers of gve tx/rx stats in stats report. */ 31#define GVE_TX_STATS_REPORT_NUM 6 32#define GVE_RX_STATS_REPORT_NUM 2 33 34/* Interval to schedule a stats report update, 20000ms. */ 35#define GVE_STATS_REPORT_TIMER_PERIOD 20000 36 37/* Numbers of NIC tx/rx stats in stats report. */ 38#define NIC_TX_STATS_REPORT_NUM 0 39#define NIC_RX_STATS_REPORT_NUM 4 40 41/* Each slot in the desc ring has a 1:1 mapping to a slot in the data ring */ 42struct gve_rx_desc_queue { 43 struct gve_rx_desc *desc_ring; /* the descriptor ring */ 44 dma_addr_t bus; /* the bus for the desc_ring */ 45 u8 seqno; /* the next expected seqno for this desc*/ 46}; 47 48/* The page info for a single slot in the RX data queue */ 49struct gve_rx_slot_page_info { 50 struct page *page; 51 void *page_address; 52 u32 page_offset; /* offset to write to in page */ 53}; 54 55/* A list of pages registered with the device during setup and used by a queue 56 * as buffers 57 */ 58struct gve_queue_page_list { 59 u32 id; /* unique id */ 60 u32 num_entries; 61 struct page **pages; /* list of num_entries pages */ 62 dma_addr_t *page_buses; /* the dma addrs of the pages */ 63}; 64 65/* Each slot in the data ring has a 1:1 mapping to a slot in the desc ring */ 66struct gve_rx_data_queue { 67 struct gve_rx_data_slot *data_ring; /* read by NIC */ 68 dma_addr_t data_bus; /* dma mapping of the slots */ 69 struct gve_rx_slot_page_info *page_info; /* page info of the buffers */ 70 struct gve_queue_page_list *qpl; /* qpl assigned to this queue */ 71}; 72 73struct gve_priv; 74 75/* An RX ring that contains a power-of-two sized desc and data ring. */ 76struct gve_rx_ring { 77 struct gve_priv *gve; 78 struct gve_rx_desc_queue desc; 79 struct gve_rx_data_queue data; 80 u64 rbytes; /* free-running bytes received */ 81 u64 rpackets; /* free-running packets received */ 82 u32 cnt; /* free-running total number of completed packets */ 83 u32 fill_cnt; /* free-running total number of descs and buffs posted */ 84 u32 mask; /* masks the cnt and fill_cnt to the size of the ring */ 85 u64 rx_copybreak_pkt; /* free-running count of copybreak packets */ 86 u64 rx_copied_pkt; /* free-running total number of copied packets */ 87 u64 rx_skb_alloc_fail; /* free-running count of skb alloc fails */ 88 u64 rx_buf_alloc_fail; /* free-running count of buffer alloc fails */ 89 u64 rx_desc_err_dropped_pkt; /* free-running count of packets dropped by descriptor error */ 90 u32 q_num; /* queue index */ 91 u32 ntfy_id; /* notification block index */ 92 struct gve_queue_resources *q_resources; /* head and tail pointer idx */ 93 dma_addr_t q_resources_bus; /* dma address for the queue resources */ 94 struct u64_stats_sync statss; /* sync stats for 32bit archs */ 95}; 96 97/* A TX desc ring entry */ 98union gve_tx_desc { 99 struct gve_tx_pkt_desc pkt; /* first desc for a packet */ 100 struct gve_tx_seg_desc seg; /* subsequent descs for a packet */ 101}; 102 103/* Tracks the memory in the fifo occupied by a segment of a packet */ 104struct gve_tx_iovec { 105 u32 iov_offset; /* offset into this segment */ 106 u32 iov_len; /* length */ 107 u32 iov_padding; /* padding associated with this segment */ 108}; 109 110/* Tracks the memory in the fifo occupied by the skb. Mapped 1:1 to a desc 111 * ring entry but only used for a pkt_desc not a seg_desc 112 */ 113struct gve_tx_buffer_state { 114 struct sk_buff *skb; /* skb for this pkt */ 115 struct gve_tx_iovec iov[GVE_TX_MAX_IOVEC]; /* segments of this pkt */ 116}; 117 118/* A TX buffer - each queue has one */ 119struct gve_tx_fifo { 120 void *base; /* address of base of FIFO */ 121 u32 size; /* total size */ 122 atomic_t available; /* how much space is still available */ 123 u32 head; /* offset to write at */ 124 struct gve_queue_page_list *qpl; /* QPL mapped into this FIFO */ 125}; 126 127/* A TX ring that contains a power-of-two sized desc ring and a FIFO buffer */ 128struct gve_tx_ring { 129 /* Cacheline 0 -- Accessed & dirtied during transmit */ 130 struct gve_tx_fifo tx_fifo; 131 u32 req; /* driver tracked head pointer */ 132 u32 done; /* driver tracked tail pointer */ 133 134 /* Cacheline 1 -- Accessed & dirtied during gve_clean_tx_done */ 135 __be32 last_nic_done ____cacheline_aligned; /* NIC tail pointer */ 136 u64 pkt_done; /* free-running - total packets completed */ 137 u64 bytes_done; /* free-running - total bytes completed */ 138 139 /* Cacheline 2 -- Read-mostly fields */ 140 union gve_tx_desc *desc ____cacheline_aligned; 141 struct gve_tx_buffer_state *info; /* Maps 1:1 to a desc */ 142 struct netdev_queue *netdev_txq; 143 struct gve_queue_resources *q_resources; /* head and tail pointer idx */ 144 u32 mask; /* masks req and done down to queue size */ 145 146 /* Slow-path fields */ 147 u32 q_num ____cacheline_aligned; /* queue idx */ 148 u32 stop_queue; /* count of queue stops */ 149 u32 wake_queue; /* count of queue wakes */ 150 u32 queue_timeout; /* count of queue timeouts */ 151 u32 ntfy_id; /* notification block index */ 152 u32 last_kick_msec; /* Last time the queue was kicked */ 153 dma_addr_t bus; /* dma address of the descr ring */ 154 dma_addr_t q_resources_bus; /* dma address of the queue resources */ 155 struct u64_stats_sync statss; /* sync stats for 32bit archs */ 156} ____cacheline_aligned; 157 158/* Wraps the info for one irq including the napi struct and the queues 159 * associated with that irq. 160 */ 161struct gve_notify_block { 162 __be32 irq_db_index; /* idx into Bar2 - set by device, must be 1st */ 163 char name[IFNAMSIZ + 16]; /* name registered with the kernel */ 164 struct napi_struct napi; /* kernel napi struct for this block */ 165 struct gve_priv *priv; 166 struct gve_tx_ring *tx; /* tx rings on this block */ 167 struct gve_rx_ring *rx; /* rx rings on this block */ 168} ____cacheline_aligned; 169 170/* Tracks allowed and current queue settings */ 171struct gve_queue_config { 172 u16 max_queues; 173 u16 num_queues; /* current */ 174}; 175 176/* Tracks the available and used qpl IDs */ 177struct gve_qpl_config { 178 u32 qpl_map_size; /* map memory size */ 179 unsigned long *qpl_id_map; /* bitmap of used qpl ids */ 180}; 181 182struct gve_priv { 183 struct net_device *dev; 184 struct gve_tx_ring *tx; /* array of tx_cfg.num_queues */ 185 struct gve_rx_ring *rx; /* array of rx_cfg.num_queues */ 186 struct gve_queue_page_list *qpls; /* array of num qpls */ 187 struct gve_notify_block *ntfy_blocks; /* array of num_ntfy_blks */ 188 dma_addr_t ntfy_block_bus; 189 struct msix_entry *msix_vectors; /* array of num_ntfy_blks + 1 */ 190 char mgmt_msix_name[IFNAMSIZ + 16]; 191 u32 mgmt_msix_idx; 192 __be32 *counter_array; /* array of num_event_counters */ 193 dma_addr_t counter_array_bus; 194 195 u16 num_event_counters; 196 u16 tx_desc_cnt; /* num desc per ring */ 197 u16 rx_desc_cnt; /* num desc per ring */ 198 u16 tx_pages_per_qpl; /* tx buffer length */ 199 u16 rx_pages_per_qpl; /* rx buffer length */ 200 u64 max_registered_pages; 201 u64 num_registered_pages; /* num pages registered with NIC */ 202 u32 rx_copybreak; /* copy packets smaller than this */ 203 u16 default_num_queues; /* default num queues to set up */ 204 205 struct gve_queue_config tx_cfg; 206 struct gve_queue_config rx_cfg; 207 struct gve_qpl_config qpl_cfg; /* map used QPL ids */ 208 u32 num_ntfy_blks; /* spilt between TX and RX so must be even */ 209 210 struct gve_registers __iomem *reg_bar0; /* see gve_register.h */ 211 __be32 __iomem *db_bar2; /* "array" of doorbells */ 212 u32 msg_enable; /* level for netif* netdev print macros */ 213 struct pci_dev *pdev; 214 215 /* metrics */ 216 u32 tx_timeo_cnt; 217 218 /* Admin queue - see gve_adminq.h*/ 219 union gve_adminq_command *adminq; 220 dma_addr_t adminq_bus_addr; 221 u32 adminq_mask; /* masks prod_cnt to adminq size */ 222 u32 adminq_prod_cnt; /* free-running count of AQ cmds executed */ 223 u32 adminq_cmd_fail; /* free-running count of AQ cmds failed */ 224 u32 adminq_timeouts; /* free-running count of AQ cmds timeouts */ 225 /* free-running count of per AQ cmd executed */ 226 u32 adminq_describe_device_cnt; 227 u32 adminq_cfg_device_resources_cnt; 228 u32 adminq_register_page_list_cnt; 229 u32 adminq_unregister_page_list_cnt; 230 u32 adminq_create_tx_queue_cnt; 231 u32 adminq_create_rx_queue_cnt; 232 u32 adminq_destroy_tx_queue_cnt; 233 u32 adminq_destroy_rx_queue_cnt; 234 u32 adminq_dcfg_device_resources_cnt; 235 u32 adminq_set_driver_parameter_cnt; 236 u32 adminq_report_stats_cnt; 237 u32 adminq_report_link_speed_cnt; 238 239 /* Global stats */ 240 u32 interface_up_cnt; /* count of times interface turned up since last reset */ 241 u32 interface_down_cnt; /* count of times interface turned down since last reset */ 242 u32 reset_cnt; /* count of reset */ 243 u32 page_alloc_fail; /* count of page alloc fails */ 244 u32 dma_mapping_error; /* count of dma mapping errors */ 245 u32 stats_report_trigger_cnt; /* count of device-requested stats-reports since last reset */ 246 struct workqueue_struct *gve_wq; 247 struct work_struct service_task; 248 struct work_struct stats_report_task; 249 unsigned long service_task_flags; 250 unsigned long state_flags; 251 252 struct gve_stats_report *stats_report; 253 u64 stats_report_len; 254 dma_addr_t stats_report_bus; /* dma address for the stats report */ 255 unsigned long ethtool_flags; 256 257 unsigned long stats_report_timer_period; 258 struct timer_list stats_report_timer; 259 260 /* Gvnic device link speed from hypervisor. */ 261 u64 link_speed; 262}; 263 264enum gve_service_task_flags_bit { 265 GVE_PRIV_FLAGS_DO_RESET = 1, 266 GVE_PRIV_FLAGS_RESET_IN_PROGRESS = 2, 267 GVE_PRIV_FLAGS_PROBE_IN_PROGRESS = 3, 268 GVE_PRIV_FLAGS_DO_REPORT_STATS = 4, 269}; 270 271enum gve_state_flags_bit { 272 GVE_PRIV_FLAGS_ADMIN_QUEUE_OK = 1, 273 GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK = 2, 274 GVE_PRIV_FLAGS_DEVICE_RINGS_OK = 3, 275 GVE_PRIV_FLAGS_NAPI_ENABLED = 4, 276}; 277 278enum gve_ethtool_flags_bit { 279 GVE_PRIV_FLAGS_REPORT_STATS = 0, 280}; 281 282static inline bool gve_get_do_reset(struct gve_priv *priv) 283{ 284 return test_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags); 285} 286 287static inline void gve_set_do_reset(struct gve_priv *priv) 288{ 289 set_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags); 290} 291 292static inline void gve_clear_do_reset(struct gve_priv *priv) 293{ 294 clear_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags); 295} 296 297static inline bool gve_get_reset_in_progress(struct gve_priv *priv) 298{ 299 return test_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS, 300 &priv->service_task_flags); 301} 302 303static inline void gve_set_reset_in_progress(struct gve_priv *priv) 304{ 305 set_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS, &priv->service_task_flags); 306} 307 308static inline void gve_clear_reset_in_progress(struct gve_priv *priv) 309{ 310 clear_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS, &priv->service_task_flags); 311} 312 313static inline bool gve_get_probe_in_progress(struct gve_priv *priv) 314{ 315 return test_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS, 316 &priv->service_task_flags); 317} 318 319static inline void gve_set_probe_in_progress(struct gve_priv *priv) 320{ 321 set_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS, &priv->service_task_flags); 322} 323 324static inline void gve_clear_probe_in_progress(struct gve_priv *priv) 325{ 326 clear_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS, &priv->service_task_flags); 327} 328 329static inline bool gve_get_do_report_stats(struct gve_priv *priv) 330{ 331 return test_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS, 332 &priv->service_task_flags); 333} 334 335static inline void gve_set_do_report_stats(struct gve_priv *priv) 336{ 337 set_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS, &priv->service_task_flags); 338} 339 340static inline void gve_clear_do_report_stats(struct gve_priv *priv) 341{ 342 clear_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS, &priv->service_task_flags); 343} 344 345static inline bool gve_get_admin_queue_ok(struct gve_priv *priv) 346{ 347 return test_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags); 348} 349 350static inline void gve_set_admin_queue_ok(struct gve_priv *priv) 351{ 352 set_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags); 353} 354 355static inline void gve_clear_admin_queue_ok(struct gve_priv *priv) 356{ 357 clear_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags); 358} 359 360static inline bool gve_get_device_resources_ok(struct gve_priv *priv) 361{ 362 return test_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags); 363} 364 365static inline void gve_set_device_resources_ok(struct gve_priv *priv) 366{ 367 set_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags); 368} 369 370static inline void gve_clear_device_resources_ok(struct gve_priv *priv) 371{ 372 clear_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags); 373} 374 375static inline bool gve_get_device_rings_ok(struct gve_priv *priv) 376{ 377 return test_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags); 378} 379 380static inline void gve_set_device_rings_ok(struct gve_priv *priv) 381{ 382 set_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags); 383} 384 385static inline void gve_clear_device_rings_ok(struct gve_priv *priv) 386{ 387 clear_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags); 388} 389 390static inline bool gve_get_napi_enabled(struct gve_priv *priv) 391{ 392 return test_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags); 393} 394 395static inline void gve_set_napi_enabled(struct gve_priv *priv) 396{ 397 set_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags); 398} 399 400static inline void gve_clear_napi_enabled(struct gve_priv *priv) 401{ 402 clear_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags); 403} 404 405static inline bool gve_get_report_stats(struct gve_priv *priv) 406{ 407 return test_bit(GVE_PRIV_FLAGS_REPORT_STATS, &priv->ethtool_flags); 408} 409 410static inline void gve_clear_report_stats(struct gve_priv *priv) 411{ 412 clear_bit(GVE_PRIV_FLAGS_REPORT_STATS, &priv->ethtool_flags); 413} 414 415/* Returns the address of the ntfy_blocks irq doorbell 416 */ 417static inline __be32 __iomem *gve_irq_doorbell(struct gve_priv *priv, 418 struct gve_notify_block *block) 419{ 420 return &priv->db_bar2[be32_to_cpu(block->irq_db_index)]; 421} 422 423/* Returns the index into ntfy_blocks of the given tx ring's block 424 */ 425static inline u32 gve_tx_idx_to_ntfy(struct gve_priv *priv, u32 queue_idx) 426{ 427 return queue_idx; 428} 429 430/* Returns the index into ntfy_blocks of the given rx ring's block 431 */ 432static inline u32 gve_rx_idx_to_ntfy(struct gve_priv *priv, u32 queue_idx) 433{ 434 return (priv->num_ntfy_blks / 2) + queue_idx; 435} 436 437/* Returns the number of tx queue page lists 438 */ 439static inline u32 gve_num_tx_qpls(struct gve_priv *priv) 440{ 441 return priv->tx_cfg.num_queues; 442} 443 444/* Returns the number of rx queue page lists 445 */ 446static inline u32 gve_num_rx_qpls(struct gve_priv *priv) 447{ 448 return priv->rx_cfg.num_queues; 449} 450 451/* Returns a pointer to the next available tx qpl in the list of qpls 452 */ 453static inline 454struct gve_queue_page_list *gve_assign_tx_qpl(struct gve_priv *priv) 455{ 456 int id = find_first_zero_bit(priv->qpl_cfg.qpl_id_map, 457 priv->qpl_cfg.qpl_map_size); 458 459 /* we are out of tx qpls */ 460 if (id >= gve_num_tx_qpls(priv)) 461 return NULL; 462 463 set_bit(id, priv->qpl_cfg.qpl_id_map); 464 return &priv->qpls[id]; 465} 466 467/* Returns a pointer to the next available rx qpl in the list of qpls 468 */ 469static inline 470struct gve_queue_page_list *gve_assign_rx_qpl(struct gve_priv *priv) 471{ 472 int id = find_next_zero_bit(priv->qpl_cfg.qpl_id_map, 473 priv->qpl_cfg.qpl_map_size, 474 gve_num_tx_qpls(priv)); 475 476 /* we are out of rx qpls */ 477 if (id == gve_num_tx_qpls(priv) + gve_num_rx_qpls(priv)) 478 return NULL; 479 480 set_bit(id, priv->qpl_cfg.qpl_id_map); 481 return &priv->qpls[id]; 482} 483 484/* Unassigns the qpl with the given id 485 */ 486static inline void gve_unassign_qpl(struct gve_priv *priv, int id) 487{ 488 clear_bit(id, priv->qpl_cfg.qpl_id_map); 489} 490 491/* Returns the correct dma direction for tx and rx qpls 492 */ 493static inline enum dma_data_direction gve_qpl_dma_dir(struct gve_priv *priv, 494 int id) 495{ 496 if (id < gve_num_tx_qpls(priv)) 497 return DMA_TO_DEVICE; 498 else 499 return DMA_FROM_DEVICE; 500} 501 502/* Returns true if the max mtu allows page recycling */ 503static inline bool gve_can_recycle_pages(struct net_device *dev) 504{ 505 /* We can't recycle the pages if we can't fit a packet into half a 506 * page. 507 */ 508 return dev->max_mtu <= PAGE_SIZE / 2; 509} 510 511/* buffers */ 512int gve_alloc_page(struct gve_priv *priv, struct device *dev, 513 struct page **page, dma_addr_t *dma, 514 enum dma_data_direction); 515void gve_free_page(struct device *dev, struct page *page, dma_addr_t dma, 516 enum dma_data_direction); 517/* tx handling */ 518netdev_tx_t gve_tx(struct sk_buff *skb, struct net_device *dev); 519bool gve_tx_poll(struct gve_notify_block *block, int budget); 520int gve_tx_alloc_rings(struct gve_priv *priv); 521void gve_tx_free_rings(struct gve_priv *priv); 522__be32 gve_tx_load_event_counter(struct gve_priv *priv, 523 struct gve_tx_ring *tx); 524/* rx handling */ 525void gve_rx_write_doorbell(struct gve_priv *priv, struct gve_rx_ring *rx); 526bool gve_rx_poll(struct gve_notify_block *block, int budget); 527int gve_rx_alloc_rings(struct gve_priv *priv); 528void gve_rx_free_rings(struct gve_priv *priv); 529bool gve_clean_rx_done(struct gve_rx_ring *rx, int budget, 530 netdev_features_t feat); 531/* Reset */ 532void gve_schedule_reset(struct gve_priv *priv); 533int gve_reset(struct gve_priv *priv, bool attempt_teardown); 534int gve_adjust_queues(struct gve_priv *priv, 535 struct gve_queue_config new_rx_config, 536 struct gve_queue_config new_tx_config); 537/* report stats handling */ 538void gve_handle_report_stats(struct gve_priv *priv); 539/* exported by ethtool.c */ 540extern const struct ethtool_ops gve_ethtool_ops; 541/* needed by ethtool */ 542extern const char gve_version_str[]; 543#endif /* _GVE_H_ */ 544