1/* 2 * Copyright 2008-2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35#include "fman_dtsec.h" 36#include "fman.h" 37 38#include <linux/slab.h> 39#include <linux/bitrev.h> 40#include <linux/io.h> 41#include <linux/delay.h> 42#include <linux/phy.h> 43#include <linux/crc32.h> 44#include <linux/of_mdio.h> 45#include <linux/mii.h> 46 47/* TBI register addresses */ 48#define MII_TBICON 0x11 49 50/* TBICON register bit fields */ 51#define TBICON_SOFT_RESET 0x8000 /* Soft reset */ 52#define TBICON_DISABLE_RX_DIS 0x2000 /* Disable receive disparity */ 53#define TBICON_DISABLE_TX_DIS 0x1000 /* Disable transmit disparity */ 54#define TBICON_AN_SENSE 0x0100 /* Auto-negotiation sense enable */ 55#define TBICON_CLK_SELECT 0x0020 /* Clock select */ 56#define TBICON_MI_MODE 0x0010 /* GMII mode (TBI if not set) */ 57 58#define TBIANA_SGMII 0x4001 59#define TBIANA_1000X 0x01a0 60 61/* Interrupt Mask Register (IMASK) */ 62#define DTSEC_IMASK_BREN 0x80000000 63#define DTSEC_IMASK_RXCEN 0x40000000 64#define DTSEC_IMASK_MSROEN 0x04000000 65#define DTSEC_IMASK_GTSCEN 0x02000000 66#define DTSEC_IMASK_BTEN 0x01000000 67#define DTSEC_IMASK_TXCEN 0x00800000 68#define DTSEC_IMASK_TXEEN 0x00400000 69#define DTSEC_IMASK_LCEN 0x00040000 70#define DTSEC_IMASK_CRLEN 0x00020000 71#define DTSEC_IMASK_XFUNEN 0x00010000 72#define DTSEC_IMASK_ABRTEN 0x00008000 73#define DTSEC_IMASK_IFERREN 0x00004000 74#define DTSEC_IMASK_MAGEN 0x00000800 75#define DTSEC_IMASK_MMRDEN 0x00000400 76#define DTSEC_IMASK_MMWREN 0x00000200 77#define DTSEC_IMASK_GRSCEN 0x00000100 78#define DTSEC_IMASK_TDPEEN 0x00000002 79#define DTSEC_IMASK_RDPEEN 0x00000001 80 81#define DTSEC_EVENTS_MASK \ 82 ((u32)(DTSEC_IMASK_BREN | \ 83 DTSEC_IMASK_RXCEN | \ 84 DTSEC_IMASK_BTEN | \ 85 DTSEC_IMASK_TXCEN | \ 86 DTSEC_IMASK_TXEEN | \ 87 DTSEC_IMASK_ABRTEN | \ 88 DTSEC_IMASK_LCEN | \ 89 DTSEC_IMASK_CRLEN | \ 90 DTSEC_IMASK_XFUNEN | \ 91 DTSEC_IMASK_IFERREN | \ 92 DTSEC_IMASK_MAGEN | \ 93 DTSEC_IMASK_TDPEEN | \ 94 DTSEC_IMASK_RDPEEN)) 95 96/* dtsec timestamp event bits */ 97#define TMR_PEMASK_TSREEN 0x00010000 98#define TMR_PEVENT_TSRE 0x00010000 99 100/* Group address bit indication */ 101#define MAC_GROUP_ADDRESS 0x0000010000000000ULL 102 103/* Defaults */ 104#define DEFAULT_HALFDUP_RETRANSMIT 0xf 105#define DEFAULT_HALFDUP_COLL_WINDOW 0x37 106#define DEFAULT_TX_PAUSE_TIME 0xf000 107#define DEFAULT_RX_PREPEND 0 108#define DEFAULT_PREAMBLE_LEN 7 109#define DEFAULT_TX_PAUSE_TIME_EXTD 0 110#define DEFAULT_NON_BACK_TO_BACK_IPG1 0x40 111#define DEFAULT_NON_BACK_TO_BACK_IPG2 0x60 112#define DEFAULT_MIN_IFG_ENFORCEMENT 0x50 113#define DEFAULT_BACK_TO_BACK_IPG 0x60 114#define DEFAULT_MAXIMUM_FRAME 0x600 115 116/* register related defines (bits, field offsets..) */ 117#define DTSEC_ID2_INT_REDUCED_OFF 0x00010000 118 119#define DTSEC_ECNTRL_GMIIM 0x00000040 120#define DTSEC_ECNTRL_TBIM 0x00000020 121#define DTSEC_ECNTRL_SGMIIM 0x00000002 122#define DTSEC_ECNTRL_RPM 0x00000010 123#define DTSEC_ECNTRL_R100M 0x00000008 124#define DTSEC_ECNTRL_QSGMIIM 0x00000001 125 126#define TCTRL_TTSE 0x00000040 127#define TCTRL_GTS 0x00000020 128 129#define RCTRL_PAL_MASK 0x001f0000 130#define RCTRL_PAL_SHIFT 16 131#define RCTRL_GHTX 0x00000400 132#define RCTRL_RTSE 0x00000040 133#define RCTRL_GRS 0x00000020 134#define RCTRL_MPROM 0x00000008 135#define RCTRL_RSF 0x00000004 136#define RCTRL_UPROM 0x00000001 137 138#define MACCFG1_SOFT_RESET 0x80000000 139#define MACCFG1_RX_FLOW 0x00000020 140#define MACCFG1_TX_FLOW 0x00000010 141#define MACCFG1_TX_EN 0x00000001 142#define MACCFG1_RX_EN 0x00000004 143 144#define MACCFG2_NIBBLE_MODE 0x00000100 145#define MACCFG2_BYTE_MODE 0x00000200 146#define MACCFG2_PAD_CRC_EN 0x00000004 147#define MACCFG2_FULL_DUPLEX 0x00000001 148#define MACCFG2_PREAMBLE_LENGTH_MASK 0x0000f000 149#define MACCFG2_PREAMBLE_LENGTH_SHIFT 12 150 151#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24 152#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16 153#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8 154 155#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000 156#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000 157#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00 158#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F 159 160#define HAFDUP_EXCESS_DEFER 0x00010000 161#define HAFDUP_COLLISION_WINDOW 0x000003ff 162#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12 163#define HAFDUP_RETRANSMISSION_MAX 0x0000f000 164 165#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */ 166 167#define PTV_PTE_MASK 0xffff0000 168#define PTV_PT_MASK 0x0000ffff 169#define PTV_PTE_SHIFT 16 170 171#define MAX_PACKET_ALIGNMENT 31 172#define MAX_INTER_PACKET_GAP 0x7f 173#define MAX_RETRANSMISSION 0x0f 174#define MAX_COLLISION_WINDOW 0x03ff 175 176/* Hash table size (32 bits*8 regs) */ 177#define DTSEC_HASH_TABLE_SIZE 256 178/* Extended Hash table size (32 bits*16 regs) */ 179#define EXTENDED_HASH_TABLE_SIZE 512 180 181/* dTSEC Memory Map registers */ 182struct dtsec_regs { 183 /* dTSEC General Control and Status Registers */ 184 u32 tsec_id; /* 0x000 ETSEC_ID register */ 185 u32 tsec_id2; /* 0x004 ETSEC_ID2 register */ 186 u32 ievent; /* 0x008 Interrupt event register */ 187 u32 imask; /* 0x00C Interrupt mask register */ 188 u32 reserved0010[1]; 189 u32 ecntrl; /* 0x014 E control register */ 190 u32 ptv; /* 0x018 Pause time value register */ 191 u32 tbipa; /* 0x01C TBI PHY address register */ 192 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */ 193 u32 tmr_pevent; /* 0x024 Time-stamp event register */ 194 u32 tmr_pemask; /* 0x028 Timer event mask register */ 195 u32 reserved002c[5]; 196 u32 tctrl; /* 0x040 Transmit control register */ 197 u32 reserved0044[3]; 198 u32 rctrl; /* 0x050 Receive control register */ 199 u32 reserved0054[11]; 200 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */ 201 u32 gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */ 202 u32 reserved00c0[16]; 203 u32 maccfg1; /* 0x100 MAC configuration #1 */ 204 u32 maccfg2; /* 0x104 MAC configuration #2 */ 205 u32 ipgifg; /* 0x108 IPG/IFG */ 206 u32 hafdup; /* 0x10C Half-duplex */ 207 u32 maxfrm; /* 0x110 Maximum frame */ 208 u32 reserved0114[10]; 209 u32 ifstat; /* 0x13C Interface status */ 210 u32 macstnaddr1; /* 0x140 Station Address,part 1 */ 211 u32 macstnaddr2; /* 0x144 Station Address,part 2 */ 212 struct { 213 u32 exact_match1; /* octets 1-4 */ 214 u32 exact_match2; /* octets 5-6 */ 215 } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */ 216 u32 reserved01c0[16]; 217 u32 tr64; /* 0x200 Tx and Rx 64 byte frame counter */ 218 u32 tr127; /* 0x204 Tx and Rx 65 to 127 byte frame counter */ 219 u32 tr255; /* 0x208 Tx and Rx 128 to 255 byte frame counter */ 220 u32 tr511; /* 0x20C Tx and Rx 256 to 511 byte frame counter */ 221 u32 tr1k; /* 0x210 Tx and Rx 512 to 1023 byte frame counter */ 222 u32 trmax; /* 0x214 Tx and Rx 1024 to 1518 byte frame counter */ 223 u32 trmgv; 224 /* 0x218 Tx and Rx 1519 to 1522 byte good VLAN frame count */ 225 u32 rbyt; /* 0x21C receive byte counter */ 226 u32 rpkt; /* 0x220 receive packet counter */ 227 u32 rfcs; /* 0x224 receive FCS error counter */ 228 u32 rmca; /* 0x228 RMCA Rx multicast packet counter */ 229 u32 rbca; /* 0x22C Rx broadcast packet counter */ 230 u32 rxcf; /* 0x230 Rx control frame packet counter */ 231 u32 rxpf; /* 0x234 Rx pause frame packet counter */ 232 u32 rxuo; /* 0x238 Rx unknown OP code counter */ 233 u32 raln; /* 0x23C Rx alignment error counter */ 234 u32 rflr; /* 0x240 Rx frame length error counter */ 235 u32 rcde; /* 0x244 Rx code error counter */ 236 u32 rcse; /* 0x248 Rx carrier sense error counter */ 237 u32 rund; /* 0x24C Rx undersize packet counter */ 238 u32 rovr; /* 0x250 Rx oversize packet counter */ 239 u32 rfrg; /* 0x254 Rx fragments counter */ 240 u32 rjbr; /* 0x258 Rx jabber counter */ 241 u32 rdrp; /* 0x25C Rx drop */ 242 u32 tbyt; /* 0x260 Tx byte counter */ 243 u32 tpkt; /* 0x264 Tx packet counter */ 244 u32 tmca; /* 0x268 Tx multicast packet counter */ 245 u32 tbca; /* 0x26C Tx broadcast packet counter */ 246 u32 txpf; /* 0x270 Tx pause control frame counter */ 247 u32 tdfr; /* 0x274 Tx deferral packet counter */ 248 u32 tedf; /* 0x278 Tx excessive deferral packet counter */ 249 u32 tscl; /* 0x27C Tx single collision packet counter */ 250 u32 tmcl; /* 0x280 Tx multiple collision packet counter */ 251 u32 tlcl; /* 0x284 Tx late collision packet counter */ 252 u32 txcl; /* 0x288 Tx excessive collision packet counter */ 253 u32 tncl; /* 0x28C Tx total collision counter */ 254 u32 reserved0290[1]; 255 u32 tdrp; /* 0x294 Tx drop frame counter */ 256 u32 tjbr; /* 0x298 Tx jabber frame counter */ 257 u32 tfcs; /* 0x29C Tx FCS error counter */ 258 u32 txcf; /* 0x2A0 Tx control frame counter */ 259 u32 tovr; /* 0x2A4 Tx oversize frame counter */ 260 u32 tund; /* 0x2A8 Tx undersize frame counter */ 261 u32 tfrg; /* 0x2AC Tx fragments frame counter */ 262 u32 car1; /* 0x2B0 carry register one register* */ 263 u32 car2; /* 0x2B4 carry register two register* */ 264 u32 cam1; /* 0x2B8 carry register one mask register */ 265 u32 cam2; /* 0x2BC carry register two mask register */ 266 u32 reserved02c0[848]; 267}; 268 269/* struct dtsec_cfg - dTSEC configuration 270 * Transmit half-duplex flow control, under software control for 10/100-Mbps 271 * half-duplex media. If set, back pressure is applied to media by raising 272 * carrier. 273 * halfdup_retransmit: 274 * Number of retransmission attempts following a collision. 275 * If this is exceeded dTSEC aborts transmission due to excessive collisions. 276 * The standard specifies the attempt limit to be 15. 277 * halfdup_coll_window: 278 * The number of bytes of the frame during which collisions may occur. 279 * The default value of 55 corresponds to the frame byte at the end of the 280 * standard 512-bit slot time window. If collisions are detected after this 281 * byte, the late collision event is asserted and transmission of current 282 * frame is aborted. 283 * tx_pad_crc: 284 * Pad and append CRC. If set, the MAC pads all ransmitted short frames and 285 * appends a CRC to every frame regardless of padding requirement. 286 * tx_pause_time: 287 * Transmit pause time value. This pause value is used as part of the pause 288 * frame to be sent when a transmit pause frame is initiated. 289 * If set to 0 this disables transmission of pause frames. 290 * preamble_len: 291 * Length, in bytes, of the preamble field preceding each Ethernet 292 * start-of-frame delimiter byte. The default value of 0x7 should be used in 293 * order to guarantee reliable operation with IEEE 802.3 compliant hardware. 294 * rx_prepend: 295 * Packet alignment padding length. The specified number of bytes (1-31) 296 * of zero padding are inserted before the start of each received frame. 297 * For Ethernet, where optional preamble extraction is enabled, the padding 298 * appears before the preamble, otherwise the padding precedes the 299 * layer 2 header. 300 * 301 * This structure contains basic dTSEC configuration and must be passed to 302 * init() function. A default set of configuration values can be 303 * obtained by calling set_dflts(). 304 */ 305struct dtsec_cfg { 306 u16 halfdup_retransmit; 307 u16 halfdup_coll_window; 308 bool tx_pad_crc; 309 u16 tx_pause_time; 310 bool ptp_tsu_en; 311 bool ptp_exception_en; 312 u32 preamble_len; 313 u32 rx_prepend; 314 u16 tx_pause_time_extd; 315 u16 maximum_frame; 316 u32 non_back_to_back_ipg1; 317 u32 non_back_to_back_ipg2; 318 u32 min_ifg_enforcement; 319 u32 back_to_back_ipg; 320}; 321 322struct fman_mac { 323 /* pointer to dTSEC memory mapped registers */ 324 struct dtsec_regs __iomem *regs; 325 /* MAC address of device */ 326 u64 addr; 327 /* Ethernet physical interface */ 328 phy_interface_t phy_if; 329 u16 max_speed; 330 void *dev_id; /* device cookie used by the exception cbs */ 331 fman_mac_exception_cb *exception_cb; 332 fman_mac_exception_cb *event_cb; 333 /* Number of individual addresses in registers for this station */ 334 u8 num_of_ind_addr_in_regs; 335 /* pointer to driver's global address hash table */ 336 struct eth_hash_t *multicast_addr_hash; 337 /* pointer to driver's individual address hash table */ 338 struct eth_hash_t *unicast_addr_hash; 339 u8 mac_id; 340 u32 exceptions; 341 bool ptp_tsu_enabled; 342 bool en_tsu_err_exception; 343 struct dtsec_cfg *dtsec_drv_param; 344 void *fm; 345 struct fman_rev_info fm_rev_info; 346 bool basex_if; 347 struct phy_device *tbiphy; 348}; 349 350static void set_dflts(struct dtsec_cfg *cfg) 351{ 352 cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT; 353 cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW; 354 cfg->tx_pad_crc = true; 355 cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME; 356 /* PHY address 0 is reserved (DPAA RM) */ 357 cfg->rx_prepend = DEFAULT_RX_PREPEND; 358 cfg->ptp_tsu_en = true; 359 cfg->ptp_exception_en = true; 360 cfg->preamble_len = DEFAULT_PREAMBLE_LEN; 361 cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD; 362 cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1; 363 cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2; 364 cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT; 365 cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG; 366 cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME; 367} 368 369static void set_mac_address(struct dtsec_regs __iomem *regs, u8 *adr) 370{ 371 u32 tmp; 372 373 tmp = (u32)((adr[5] << 24) | 374 (adr[4] << 16) | (adr[3] << 8) | adr[2]); 375 iowrite32be(tmp, ®s->macstnaddr1); 376 377 tmp = (u32)((adr[1] << 24) | (adr[0] << 16)); 378 iowrite32be(tmp, ®s->macstnaddr2); 379} 380 381static int init(struct dtsec_regs __iomem *regs, struct dtsec_cfg *cfg, 382 phy_interface_t iface, u16 iface_speed, u64 addr, 383 u32 exception_mask, u8 tbi_addr) 384{ 385 bool is_rgmii, is_sgmii, is_qsgmii; 386 enet_addr_t eth_addr; 387 u32 tmp; 388 int i; 389 390 /* Soft reset */ 391 iowrite32be(MACCFG1_SOFT_RESET, ®s->maccfg1); 392 iowrite32be(0, ®s->maccfg1); 393 394 /* dtsec_id2 */ 395 tmp = ioread32be(®s->tsec_id2); 396 397 /* check RGMII support */ 398 if (iface == PHY_INTERFACE_MODE_RGMII || 399 iface == PHY_INTERFACE_MODE_RGMII_ID || 400 iface == PHY_INTERFACE_MODE_RGMII_RXID || 401 iface == PHY_INTERFACE_MODE_RGMII_TXID || 402 iface == PHY_INTERFACE_MODE_RMII) 403 if (tmp & DTSEC_ID2_INT_REDUCED_OFF) 404 return -EINVAL; 405 406 if (iface == PHY_INTERFACE_MODE_SGMII || 407 iface == PHY_INTERFACE_MODE_MII) 408 if (tmp & DTSEC_ID2_INT_REDUCED_OFF) 409 return -EINVAL; 410 411 is_rgmii = iface == PHY_INTERFACE_MODE_RGMII || 412 iface == PHY_INTERFACE_MODE_RGMII_ID || 413 iface == PHY_INTERFACE_MODE_RGMII_RXID || 414 iface == PHY_INTERFACE_MODE_RGMII_TXID; 415 is_sgmii = iface == PHY_INTERFACE_MODE_SGMII; 416 is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII; 417 418 tmp = 0; 419 if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII) 420 tmp |= DTSEC_ECNTRL_GMIIM; 421 if (is_sgmii) 422 tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM); 423 if (is_qsgmii) 424 tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM | 425 DTSEC_ECNTRL_QSGMIIM); 426 if (is_rgmii) 427 tmp |= DTSEC_ECNTRL_RPM; 428 if (iface_speed == SPEED_100) 429 tmp |= DTSEC_ECNTRL_R100M; 430 431 iowrite32be(tmp, ®s->ecntrl); 432 433 tmp = 0; 434 435 if (cfg->tx_pause_time) 436 tmp |= cfg->tx_pause_time; 437 if (cfg->tx_pause_time_extd) 438 tmp |= cfg->tx_pause_time_extd << PTV_PTE_SHIFT; 439 iowrite32be(tmp, ®s->ptv); 440 441 tmp = 0; 442 tmp |= (cfg->rx_prepend << RCTRL_PAL_SHIFT) & RCTRL_PAL_MASK; 443 /* Accept short frames */ 444 tmp |= RCTRL_RSF; 445 446 iowrite32be(tmp, ®s->rctrl); 447 448 /* Assign a Phy Address to the TBI (TBIPA). 449 * Done also in cases where TBI is not selected to avoid conflict with 450 * the external PHY's Physical address 451 */ 452 iowrite32be(tbi_addr, ®s->tbipa); 453 454 iowrite32be(0, ®s->tmr_ctrl); 455 456 if (cfg->ptp_tsu_en) { 457 tmp = 0; 458 tmp |= TMR_PEVENT_TSRE; 459 iowrite32be(tmp, ®s->tmr_pevent); 460 461 if (cfg->ptp_exception_en) { 462 tmp = 0; 463 tmp |= TMR_PEMASK_TSREEN; 464 iowrite32be(tmp, ®s->tmr_pemask); 465 } 466 } 467 468 tmp = 0; 469 tmp |= MACCFG1_RX_FLOW; 470 tmp |= MACCFG1_TX_FLOW; 471 iowrite32be(tmp, ®s->maccfg1); 472 473 tmp = 0; 474 475 if (iface_speed < SPEED_1000) 476 tmp |= MACCFG2_NIBBLE_MODE; 477 else if (iface_speed == SPEED_1000) 478 tmp |= MACCFG2_BYTE_MODE; 479 480 tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) & 481 MACCFG2_PREAMBLE_LENGTH_MASK; 482 if (cfg->tx_pad_crc) 483 tmp |= MACCFG2_PAD_CRC_EN; 484 /* Full Duplex */ 485 tmp |= MACCFG2_FULL_DUPLEX; 486 iowrite32be(tmp, ®s->maccfg2); 487 488 tmp = (((cfg->non_back_to_back_ipg1 << 489 IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT) 490 & IPGIFG_NON_BACK_TO_BACK_IPG_1) 491 | ((cfg->non_back_to_back_ipg2 << 492 IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT) 493 & IPGIFG_NON_BACK_TO_BACK_IPG_2) 494 | ((cfg->min_ifg_enforcement << IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT) 495 & IPGIFG_MIN_IFG_ENFORCEMENT) 496 | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG)); 497 iowrite32be(tmp, ®s->ipgifg); 498 499 tmp = 0; 500 tmp |= HAFDUP_EXCESS_DEFER; 501 tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT) 502 & HAFDUP_RETRANSMISSION_MAX); 503 tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW); 504 505 iowrite32be(tmp, ®s->hafdup); 506 507 /* Initialize Maximum frame length */ 508 iowrite32be(cfg->maximum_frame, ®s->maxfrm); 509 510 iowrite32be(0xffffffff, ®s->cam1); 511 iowrite32be(0xffffffff, ®s->cam2); 512 513 iowrite32be(exception_mask, ®s->imask); 514 515 iowrite32be(0xffffffff, ®s->ievent); 516 517 if (addr) { 518 MAKE_ENET_ADDR_FROM_UINT64(addr, eth_addr); 519 set_mac_address(regs, (u8 *)eth_addr); 520 } 521 522 /* HASH */ 523 for (i = 0; i < NUM_OF_HASH_REGS; i++) { 524 /* Initialize IADDRx */ 525 iowrite32be(0, ®s->igaddr[i]); 526 /* Initialize GADDRx */ 527 iowrite32be(0, ®s->gaddr[i]); 528 } 529 530 return 0; 531} 532 533static void set_bucket(struct dtsec_regs __iomem *regs, int bucket, 534 bool enable) 535{ 536 int reg_idx = (bucket >> 5) & 0xf; 537 int bit_idx = bucket & 0x1f; 538 u32 bit_mask = 0x80000000 >> bit_idx; 539 u32 __iomem *reg; 540 541 if (reg_idx > 7) 542 reg = ®s->gaddr[reg_idx - 8]; 543 else 544 reg = ®s->igaddr[reg_idx]; 545 546 if (enable) 547 iowrite32be(ioread32be(reg) | bit_mask, reg); 548 else 549 iowrite32be(ioread32be(reg) & (~bit_mask), reg); 550} 551 552static int check_init_parameters(struct fman_mac *dtsec) 553{ 554 if (dtsec->max_speed >= SPEED_10000) { 555 pr_err("1G MAC driver supports 1G or lower speeds\n"); 556 return -EINVAL; 557 } 558 if ((dtsec->dtsec_drv_param)->rx_prepend > 559 MAX_PACKET_ALIGNMENT) { 560 pr_err("packetAlignmentPadding can't be > than %d\n", 561 MAX_PACKET_ALIGNMENT); 562 return -EINVAL; 563 } 564 if (((dtsec->dtsec_drv_param)->non_back_to_back_ipg1 > 565 MAX_INTER_PACKET_GAP) || 566 ((dtsec->dtsec_drv_param)->non_back_to_back_ipg2 > 567 MAX_INTER_PACKET_GAP) || 568 ((dtsec->dtsec_drv_param)->back_to_back_ipg > 569 MAX_INTER_PACKET_GAP)) { 570 pr_err("Inter packet gap can't be greater than %d\n", 571 MAX_INTER_PACKET_GAP); 572 return -EINVAL; 573 } 574 if ((dtsec->dtsec_drv_param)->halfdup_retransmit > 575 MAX_RETRANSMISSION) { 576 pr_err("maxRetransmission can't be greater than %d\n", 577 MAX_RETRANSMISSION); 578 return -EINVAL; 579 } 580 if ((dtsec->dtsec_drv_param)->halfdup_coll_window > 581 MAX_COLLISION_WINDOW) { 582 pr_err("collisionWindow can't be greater than %d\n", 583 MAX_COLLISION_WINDOW); 584 return -EINVAL; 585 /* If Auto negotiation process is disabled, need to set up the PHY 586 * using the MII Management Interface 587 */ 588 } 589 if (!dtsec->exception_cb) { 590 pr_err("uninitialized exception_cb\n"); 591 return -EINVAL; 592 } 593 if (!dtsec->event_cb) { 594 pr_err("uninitialized event_cb\n"); 595 return -EINVAL; 596 } 597 598 return 0; 599} 600 601static int get_exception_flag(enum fman_mac_exceptions exception) 602{ 603 u32 bit_mask; 604 605 switch (exception) { 606 case FM_MAC_EX_1G_BAB_RX: 607 bit_mask = DTSEC_IMASK_BREN; 608 break; 609 case FM_MAC_EX_1G_RX_CTL: 610 bit_mask = DTSEC_IMASK_RXCEN; 611 break; 612 case FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: 613 bit_mask = DTSEC_IMASK_GTSCEN; 614 break; 615 case FM_MAC_EX_1G_BAB_TX: 616 bit_mask = DTSEC_IMASK_BTEN; 617 break; 618 case FM_MAC_EX_1G_TX_CTL: 619 bit_mask = DTSEC_IMASK_TXCEN; 620 break; 621 case FM_MAC_EX_1G_TX_ERR: 622 bit_mask = DTSEC_IMASK_TXEEN; 623 break; 624 case FM_MAC_EX_1G_LATE_COL: 625 bit_mask = DTSEC_IMASK_LCEN; 626 break; 627 case FM_MAC_EX_1G_COL_RET_LMT: 628 bit_mask = DTSEC_IMASK_CRLEN; 629 break; 630 case FM_MAC_EX_1G_TX_FIFO_UNDRN: 631 bit_mask = DTSEC_IMASK_XFUNEN; 632 break; 633 case FM_MAC_EX_1G_MAG_PCKT: 634 bit_mask = DTSEC_IMASK_MAGEN; 635 break; 636 case FM_MAC_EX_1G_MII_MNG_RD_COMPLET: 637 bit_mask = DTSEC_IMASK_MMRDEN; 638 break; 639 case FM_MAC_EX_1G_MII_MNG_WR_COMPLET: 640 bit_mask = DTSEC_IMASK_MMWREN; 641 break; 642 case FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: 643 bit_mask = DTSEC_IMASK_GRSCEN; 644 break; 645 case FM_MAC_EX_1G_DATA_ERR: 646 bit_mask = DTSEC_IMASK_TDPEEN; 647 break; 648 case FM_MAC_EX_1G_RX_MIB_CNT_OVFL: 649 bit_mask = DTSEC_IMASK_MSROEN; 650 break; 651 default: 652 bit_mask = 0; 653 break; 654 } 655 656 return bit_mask; 657} 658 659static bool is_init_done(struct dtsec_cfg *dtsec_drv_params) 660{ 661 /* Checks if dTSEC driver parameters were initialized */ 662 if (!dtsec_drv_params) 663 return true; 664 665 return false; 666} 667 668static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec) 669{ 670 struct dtsec_regs __iomem *regs = dtsec->regs; 671 672 if (is_init_done(dtsec->dtsec_drv_param)) 673 return 0; 674 675 return (u16)ioread32be(®s->maxfrm); 676} 677 678static void dtsec_isr(void *handle) 679{ 680 struct fman_mac *dtsec = (struct fman_mac *)handle; 681 struct dtsec_regs __iomem *regs = dtsec->regs; 682 u32 event; 683 684 /* do not handle MDIO events */ 685 event = ioread32be(®s->ievent) & 686 (u32)(~(DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN)); 687 688 event &= ioread32be(®s->imask); 689 690 iowrite32be(event, ®s->ievent); 691 692 if (event & DTSEC_IMASK_BREN) 693 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_RX); 694 if (event & DTSEC_IMASK_RXCEN) 695 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_RX_CTL); 696 if (event & DTSEC_IMASK_GTSCEN) 697 dtsec->exception_cb(dtsec->dev_id, 698 FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET); 699 if (event & DTSEC_IMASK_BTEN) 700 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_TX); 701 if (event & DTSEC_IMASK_TXCEN) 702 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_CTL); 703 if (event & DTSEC_IMASK_TXEEN) 704 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_ERR); 705 if (event & DTSEC_IMASK_LCEN) 706 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_LATE_COL); 707 if (event & DTSEC_IMASK_CRLEN) 708 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT); 709 if (event & DTSEC_IMASK_XFUNEN) { 710 /* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */ 711 if (dtsec->fm_rev_info.major == 2) { 712 u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i; 713 /* a. Write 0x00E0_0C00 to DTSEC_ID 714 * This is a read only register 715 * b. Read and save the value of TPKT 716 */ 717 tpkt1 = ioread32be(®s->tpkt); 718 719 /* c. Read the register at dTSEC address offset 0x32C */ 720 tmp_reg1 = ioread32be(®s->reserved02c0[27]); 721 722 /* d. Compare bits [9:15] to bits [25:31] of the 723 * register at address offset 0x32C. 724 */ 725 if ((tmp_reg1 & 0x007F0000) != 726 (tmp_reg1 & 0x0000007F)) { 727 /* If they are not equal, save the value of 728 * this register and wait for at least 729 * MAXFRM*16 ns 730 */ 731 usleep_range((u32)(min 732 (dtsec_get_max_frame_length(dtsec) * 733 16 / 1000, 1)), (u32) 734 (min(dtsec_get_max_frame_length 735 (dtsec) * 16 / 1000, 1) + 1)); 736 } 737 738 /* e. Read and save TPKT again and read the register 739 * at dTSEC address offset 0x32C again 740 */ 741 tpkt2 = ioread32be(®s->tpkt); 742 tmp_reg2 = ioread32be(®s->reserved02c0[27]); 743 744 /* f. Compare the value of TPKT saved in step b to 745 * value read in step e. Also compare bits [9:15] of 746 * the register at offset 0x32C saved in step d to the 747 * value of bits [9:15] saved in step e. If the two 748 * registers values are unchanged, then the transmit 749 * portion of the dTSEC controller is locked up and 750 * the user should proceed to the recover sequence. 751 */ 752 if ((tpkt1 == tpkt2) && ((tmp_reg1 & 0x007F0000) == 753 (tmp_reg2 & 0x007F0000))) { 754 /* recover sequence */ 755 756 /* a.Write a 1 to RCTRL[GRS] */ 757 758 iowrite32be(ioread32be(®s->rctrl) | 759 RCTRL_GRS, ®s->rctrl); 760 761 /* b.Wait until IEVENT[GRSC]=1, or at least 762 * 100 us has elapsed. 763 */ 764 for (i = 0; i < 100; i++) { 765 if (ioread32be(®s->ievent) & 766 DTSEC_IMASK_GRSCEN) 767 break; 768 udelay(1); 769 } 770 if (ioread32be(®s->ievent) & 771 DTSEC_IMASK_GRSCEN) 772 iowrite32be(DTSEC_IMASK_GRSCEN, 773 ®s->ievent); 774 else 775 pr_debug("Rx lockup due to Tx lockup\n"); 776 777 /* c.Write a 1 to bit n of FM_RSTC 778 * (offset 0x0CC of FPM) 779 */ 780 fman_reset_mac(dtsec->fm, dtsec->mac_id); 781 782 /* d.Wait 4 Tx clocks (32 ns) */ 783 udelay(1); 784 785 /* e.Write a 0 to bit n of FM_RSTC. */ 786 /* cleared by FMAN 787 */ 788 } 789 } 790 791 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_FIFO_UNDRN); 792 } 793 if (event & DTSEC_IMASK_MAGEN) 794 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_MAG_PCKT); 795 if (event & DTSEC_IMASK_GRSCEN) 796 dtsec->exception_cb(dtsec->dev_id, 797 FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET); 798 if (event & DTSEC_IMASK_TDPEEN) 799 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_DATA_ERR); 800 if (event & DTSEC_IMASK_RDPEEN) 801 dtsec->exception_cb(dtsec->dev_id, FM_MAC_1G_RX_DATA_ERR); 802 803 /* masked interrupts */ 804 WARN_ON(event & DTSEC_IMASK_ABRTEN); 805 WARN_ON(event & DTSEC_IMASK_IFERREN); 806} 807 808static void dtsec_1588_isr(void *handle) 809{ 810 struct fman_mac *dtsec = (struct fman_mac *)handle; 811 struct dtsec_regs __iomem *regs = dtsec->regs; 812 u32 event; 813 814 if (dtsec->ptp_tsu_enabled) { 815 event = ioread32be(®s->tmr_pevent); 816 event &= ioread32be(®s->tmr_pemask); 817 818 if (event) { 819 iowrite32be(event, ®s->tmr_pevent); 820 WARN_ON(event & TMR_PEVENT_TSRE); 821 dtsec->exception_cb(dtsec->dev_id, 822 FM_MAC_EX_1G_1588_TS_RX_ERR); 823 } 824 } 825} 826 827static void free_init_resources(struct fman_mac *dtsec) 828{ 829 fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, 830 FMAN_INTR_TYPE_ERR); 831 fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, 832 FMAN_INTR_TYPE_NORMAL); 833 834 /* release the driver's group hash table */ 835 free_hash_table(dtsec->multicast_addr_hash); 836 dtsec->multicast_addr_hash = NULL; 837 838 /* release the driver's individual hash table */ 839 free_hash_table(dtsec->unicast_addr_hash); 840 dtsec->unicast_addr_hash = NULL; 841} 842 843int dtsec_cfg_max_frame_len(struct fman_mac *dtsec, u16 new_val) 844{ 845 if (is_init_done(dtsec->dtsec_drv_param)) 846 return -EINVAL; 847 848 dtsec->dtsec_drv_param->maximum_frame = new_val; 849 850 return 0; 851} 852 853int dtsec_cfg_pad_and_crc(struct fman_mac *dtsec, bool new_val) 854{ 855 if (is_init_done(dtsec->dtsec_drv_param)) 856 return -EINVAL; 857 858 dtsec->dtsec_drv_param->tx_pad_crc = new_val; 859 860 return 0; 861} 862 863static void graceful_start(struct fman_mac *dtsec, enum comm_mode mode) 864{ 865 struct dtsec_regs __iomem *regs = dtsec->regs; 866 867 if (mode & COMM_MODE_TX) 868 iowrite32be(ioread32be(®s->tctrl) & 869 ~TCTRL_GTS, ®s->tctrl); 870 if (mode & COMM_MODE_RX) 871 iowrite32be(ioread32be(®s->rctrl) & 872 ~RCTRL_GRS, ®s->rctrl); 873} 874 875static void graceful_stop(struct fman_mac *dtsec, enum comm_mode mode) 876{ 877 struct dtsec_regs __iomem *regs = dtsec->regs; 878 u32 tmp; 879 880 /* Graceful stop - Assert the graceful Rx stop bit */ 881 if (mode & COMM_MODE_RX) { 882 tmp = ioread32be(®s->rctrl) | RCTRL_GRS; 883 iowrite32be(tmp, ®s->rctrl); 884 885 if (dtsec->fm_rev_info.major == 2) { 886 /* Workaround for dTSEC Errata A002 */ 887 usleep_range(100, 200); 888 } else { 889 /* Workaround for dTSEC Errata A004839 */ 890 usleep_range(10, 50); 891 } 892 } 893 894 /* Graceful stop - Assert the graceful Tx stop bit */ 895 if (mode & COMM_MODE_TX) { 896 if (dtsec->fm_rev_info.major == 2) { 897 /* dTSEC Errata A004: Do not use TCTRL[GTS]=1 */ 898 pr_debug("GTS not supported due to DTSEC_A004 Errata.\n"); 899 } else { 900 tmp = ioread32be(®s->tctrl) | TCTRL_GTS; 901 iowrite32be(tmp, ®s->tctrl); 902 903 /* Workaround for dTSEC Errata A0012, A0014 */ 904 usleep_range(10, 50); 905 } 906 } 907} 908 909int dtsec_enable(struct fman_mac *dtsec, enum comm_mode mode) 910{ 911 struct dtsec_regs __iomem *regs = dtsec->regs; 912 u32 tmp; 913 914 if (!is_init_done(dtsec->dtsec_drv_param)) 915 return -EINVAL; 916 917 /* Enable */ 918 tmp = ioread32be(®s->maccfg1); 919 if (mode & COMM_MODE_RX) 920 tmp |= MACCFG1_RX_EN; 921 if (mode & COMM_MODE_TX) 922 tmp |= MACCFG1_TX_EN; 923 924 iowrite32be(tmp, ®s->maccfg1); 925 926 /* Graceful start - clear the graceful Rx/Tx stop bit */ 927 graceful_start(dtsec, mode); 928 929 return 0; 930} 931 932int dtsec_disable(struct fman_mac *dtsec, enum comm_mode mode) 933{ 934 struct dtsec_regs __iomem *regs = dtsec->regs; 935 u32 tmp; 936 937 if (!is_init_done(dtsec->dtsec_drv_param)) 938 return -EINVAL; 939 940 /* Graceful stop - Assert the graceful Rx/Tx stop bit */ 941 graceful_stop(dtsec, mode); 942 943 tmp = ioread32be(®s->maccfg1); 944 if (mode & COMM_MODE_RX) 945 tmp &= ~MACCFG1_RX_EN; 946 if (mode & COMM_MODE_TX) 947 tmp &= ~MACCFG1_TX_EN; 948 949 iowrite32be(tmp, ®s->maccfg1); 950 951 return 0; 952} 953 954int dtsec_set_tx_pause_frames(struct fman_mac *dtsec, 955 u8 __maybe_unused priority, 956 u16 pause_time, u16 __maybe_unused thresh_time) 957{ 958 struct dtsec_regs __iomem *regs = dtsec->regs; 959 enum comm_mode mode = COMM_MODE_NONE; 960 u32 ptv = 0; 961 962 if (!is_init_done(dtsec->dtsec_drv_param)) 963 return -EINVAL; 964 965 if ((ioread32be(®s->rctrl) & RCTRL_GRS) == 0) 966 mode |= COMM_MODE_RX; 967 if ((ioread32be(®s->tctrl) & TCTRL_GTS) == 0) 968 mode |= COMM_MODE_TX; 969 970 graceful_stop(dtsec, mode); 971 972 if (pause_time) { 973 /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */ 974 if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) { 975 pr_warn("pause-time: %d illegal.Should be > 320\n", 976 pause_time); 977 return -EINVAL; 978 } 979 980 ptv = ioread32be(®s->ptv); 981 ptv &= PTV_PTE_MASK; 982 ptv |= pause_time & PTV_PT_MASK; 983 iowrite32be(ptv, ®s->ptv); 984 985 /* trigger the transmission of a flow-control pause frame */ 986 iowrite32be(ioread32be(®s->maccfg1) | MACCFG1_TX_FLOW, 987 ®s->maccfg1); 988 } else 989 iowrite32be(ioread32be(®s->maccfg1) & ~MACCFG1_TX_FLOW, 990 ®s->maccfg1); 991 992 graceful_start(dtsec, mode); 993 994 return 0; 995} 996 997int dtsec_accept_rx_pause_frames(struct fman_mac *dtsec, bool en) 998{ 999 struct dtsec_regs __iomem *regs = dtsec->regs; 1000 enum comm_mode mode = COMM_MODE_NONE; 1001 u32 tmp; 1002 1003 if (!is_init_done(dtsec->dtsec_drv_param)) 1004 return -EINVAL; 1005 1006 if ((ioread32be(®s->rctrl) & RCTRL_GRS) == 0) 1007 mode |= COMM_MODE_RX; 1008 if ((ioread32be(®s->tctrl) & TCTRL_GTS) == 0) 1009 mode |= COMM_MODE_TX; 1010 1011 graceful_stop(dtsec, mode); 1012 1013 tmp = ioread32be(®s->maccfg1); 1014 if (en) 1015 tmp |= MACCFG1_RX_FLOW; 1016 else 1017 tmp &= ~MACCFG1_RX_FLOW; 1018 iowrite32be(tmp, ®s->maccfg1); 1019 1020 graceful_start(dtsec, mode); 1021 1022 return 0; 1023} 1024 1025int dtsec_modify_mac_address(struct fman_mac *dtsec, enet_addr_t *enet_addr) 1026{ 1027 struct dtsec_regs __iomem *regs = dtsec->regs; 1028 enum comm_mode mode = COMM_MODE_NONE; 1029 1030 if (!is_init_done(dtsec->dtsec_drv_param)) 1031 return -EINVAL; 1032 1033 if ((ioread32be(®s->rctrl) & RCTRL_GRS) == 0) 1034 mode |= COMM_MODE_RX; 1035 if ((ioread32be(®s->tctrl) & TCTRL_GTS) == 0) 1036 mode |= COMM_MODE_TX; 1037 1038 graceful_stop(dtsec, mode); 1039 1040 /* Initialize MAC Station Address registers (1 & 2) 1041 * Station address have to be swapped (big endian to little endian 1042 */ 1043 dtsec->addr = ENET_ADDR_TO_UINT64(*enet_addr); 1044 set_mac_address(dtsec->regs, (u8 *)(*enet_addr)); 1045 1046 graceful_start(dtsec, mode); 1047 1048 return 0; 1049} 1050 1051int dtsec_add_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr) 1052{ 1053 struct dtsec_regs __iomem *regs = dtsec->regs; 1054 struct eth_hash_entry *hash_entry; 1055 u64 addr; 1056 s32 bucket; 1057 u32 crc = 0xFFFFFFFF; 1058 bool mcast, ghtx; 1059 1060 if (!is_init_done(dtsec->dtsec_drv_param)) 1061 return -EINVAL; 1062 1063 addr = ENET_ADDR_TO_UINT64(*eth_addr); 1064 1065 ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? true : false); 1066 mcast = (bool)((addr & MAC_GROUP_ADDRESS) ? true : false); 1067 1068 /* Cannot handle unicast mac addr when GHTX is on */ 1069 if (ghtx && !mcast) { 1070 pr_err("Could not compute hash bucket\n"); 1071 return -EINVAL; 1072 } 1073 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 1074 crc = bitrev32(crc); 1075 1076 /* considering the 9 highest order bits in crc H[8:0]: 1077 *if ghtx = 0 H[8:6] (highest order 3 bits) identify the hash register 1078 *and H[5:1] (next 5 bits) identify the hash bit 1079 *if ghts = 1 H[8:5] (highest order 4 bits) identify the hash register 1080 *and H[4:0] (next 5 bits) identify the hash bit. 1081 * 1082 *In bucket index output the low 5 bits identify the hash register 1083 *bit, while the higher 4 bits identify the hash register 1084 */ 1085 1086 if (ghtx) { 1087 bucket = (s32)((crc >> 23) & 0x1ff); 1088 } else { 1089 bucket = (s32)((crc >> 24) & 0xff); 1090 /* if !ghtx and mcast the bit must be set in gaddr instead of 1091 *igaddr. 1092 */ 1093 if (mcast) 1094 bucket += 0x100; 1095 } 1096 1097 set_bucket(dtsec->regs, bucket, true); 1098 1099 /* Create element to be added to the driver hash table */ 1100 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 1101 if (!hash_entry) 1102 return -ENOMEM; 1103 hash_entry->addr = addr; 1104 INIT_LIST_HEAD(&hash_entry->node); 1105 1106 if (addr & MAC_GROUP_ADDRESS) 1107 /* Group Address */ 1108 list_add_tail(&hash_entry->node, 1109 &dtsec->multicast_addr_hash->lsts[bucket]); 1110 else 1111 list_add_tail(&hash_entry->node, 1112 &dtsec->unicast_addr_hash->lsts[bucket]); 1113 1114 return 0; 1115} 1116 1117int dtsec_set_allmulti(struct fman_mac *dtsec, bool enable) 1118{ 1119 u32 tmp; 1120 struct dtsec_regs __iomem *regs = dtsec->regs; 1121 1122 if (!is_init_done(dtsec->dtsec_drv_param)) 1123 return -EINVAL; 1124 1125 tmp = ioread32be(®s->rctrl); 1126 if (enable) 1127 tmp |= RCTRL_MPROM; 1128 else 1129 tmp &= ~RCTRL_MPROM; 1130 1131 iowrite32be(tmp, ®s->rctrl); 1132 1133 return 0; 1134} 1135 1136int dtsec_set_tstamp(struct fman_mac *dtsec, bool enable) 1137{ 1138 struct dtsec_regs __iomem *regs = dtsec->regs; 1139 u32 rctrl, tctrl; 1140 1141 if (!is_init_done(dtsec->dtsec_drv_param)) 1142 return -EINVAL; 1143 1144 rctrl = ioread32be(®s->rctrl); 1145 tctrl = ioread32be(®s->tctrl); 1146 1147 if (enable) { 1148 rctrl |= RCTRL_RTSE; 1149 tctrl |= TCTRL_TTSE; 1150 } else { 1151 rctrl &= ~RCTRL_RTSE; 1152 tctrl &= ~TCTRL_TTSE; 1153 } 1154 1155 iowrite32be(rctrl, ®s->rctrl); 1156 iowrite32be(tctrl, ®s->tctrl); 1157 1158 return 0; 1159} 1160 1161int dtsec_del_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr) 1162{ 1163 struct dtsec_regs __iomem *regs = dtsec->regs; 1164 struct list_head *pos; 1165 struct eth_hash_entry *hash_entry = NULL; 1166 u64 addr; 1167 s32 bucket; 1168 u32 crc = 0xFFFFFFFF; 1169 bool mcast, ghtx; 1170 1171 if (!is_init_done(dtsec->dtsec_drv_param)) 1172 return -EINVAL; 1173 1174 addr = ENET_ADDR_TO_UINT64(*eth_addr); 1175 1176 ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? true : false); 1177 mcast = (bool)((addr & MAC_GROUP_ADDRESS) ? true : false); 1178 1179 /* Cannot handle unicast mac addr when GHTX is on */ 1180 if (ghtx && !mcast) { 1181 pr_err("Could not compute hash bucket\n"); 1182 return -EINVAL; 1183 } 1184 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 1185 crc = bitrev32(crc); 1186 1187 if (ghtx) { 1188 bucket = (s32)((crc >> 23) & 0x1ff); 1189 } else { 1190 bucket = (s32)((crc >> 24) & 0xff); 1191 /* if !ghtx and mcast the bit must be set 1192 * in gaddr instead of igaddr. 1193 */ 1194 if (mcast) 1195 bucket += 0x100; 1196 } 1197 1198 if (addr & MAC_GROUP_ADDRESS) { 1199 /* Group Address */ 1200 list_for_each(pos, 1201 &dtsec->multicast_addr_hash->lsts[bucket]) { 1202 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 1203 if (hash_entry && hash_entry->addr == addr) { 1204 list_del_init(&hash_entry->node); 1205 kfree(hash_entry); 1206 break; 1207 } 1208 } 1209 if (list_empty(&dtsec->multicast_addr_hash->lsts[bucket])) 1210 set_bucket(dtsec->regs, bucket, false); 1211 } else { 1212 /* Individual Address */ 1213 list_for_each(pos, 1214 &dtsec->unicast_addr_hash->lsts[bucket]) { 1215 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 1216 if (hash_entry && hash_entry->addr == addr) { 1217 list_del_init(&hash_entry->node); 1218 kfree(hash_entry); 1219 break; 1220 } 1221 } 1222 if (list_empty(&dtsec->unicast_addr_hash->lsts[bucket])) 1223 set_bucket(dtsec->regs, bucket, false); 1224 } 1225 1226 /* address does not exist */ 1227 WARN_ON(!hash_entry); 1228 1229 return 0; 1230} 1231 1232int dtsec_set_promiscuous(struct fman_mac *dtsec, bool new_val) 1233{ 1234 struct dtsec_regs __iomem *regs = dtsec->regs; 1235 u32 tmp; 1236 1237 if (!is_init_done(dtsec->dtsec_drv_param)) 1238 return -EINVAL; 1239 1240 /* Set unicast promiscuous */ 1241 tmp = ioread32be(®s->rctrl); 1242 if (new_val) 1243 tmp |= RCTRL_UPROM; 1244 else 1245 tmp &= ~RCTRL_UPROM; 1246 1247 iowrite32be(tmp, ®s->rctrl); 1248 1249 /* Set multicast promiscuous */ 1250 tmp = ioread32be(®s->rctrl); 1251 if (new_val) 1252 tmp |= RCTRL_MPROM; 1253 else 1254 tmp &= ~RCTRL_MPROM; 1255 1256 iowrite32be(tmp, ®s->rctrl); 1257 1258 return 0; 1259} 1260 1261int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed) 1262{ 1263 struct dtsec_regs __iomem *regs = dtsec->regs; 1264 enum comm_mode mode = COMM_MODE_NONE; 1265 u32 tmp; 1266 1267 if (!is_init_done(dtsec->dtsec_drv_param)) 1268 return -EINVAL; 1269 1270 if ((ioread32be(®s->rctrl) & RCTRL_GRS) == 0) 1271 mode |= COMM_MODE_RX; 1272 if ((ioread32be(®s->tctrl) & TCTRL_GTS) == 0) 1273 mode |= COMM_MODE_TX; 1274 1275 graceful_stop(dtsec, mode); 1276 1277 tmp = ioread32be(®s->maccfg2); 1278 1279 /* Full Duplex */ 1280 tmp |= MACCFG2_FULL_DUPLEX; 1281 1282 tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE); 1283 if (speed < SPEED_1000) 1284 tmp |= MACCFG2_NIBBLE_MODE; 1285 else if (speed == SPEED_1000) 1286 tmp |= MACCFG2_BYTE_MODE; 1287 iowrite32be(tmp, ®s->maccfg2); 1288 1289 tmp = ioread32be(®s->ecntrl); 1290 if (speed == SPEED_100) 1291 tmp |= DTSEC_ECNTRL_R100M; 1292 else 1293 tmp &= ~DTSEC_ECNTRL_R100M; 1294 iowrite32be(tmp, ®s->ecntrl); 1295 1296 graceful_start(dtsec, mode); 1297 1298 return 0; 1299} 1300 1301int dtsec_restart_autoneg(struct fman_mac *dtsec) 1302{ 1303 u16 tmp_reg16; 1304 1305 if (!is_init_done(dtsec->dtsec_drv_param)) 1306 return -EINVAL; 1307 1308 tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR); 1309 1310 tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000); 1311 tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART | 1312 BMCR_FULLDPLX | BMCR_SPEED1000); 1313 1314 phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16); 1315 1316 return 0; 1317} 1318 1319int dtsec_get_version(struct fman_mac *dtsec, u32 *mac_version) 1320{ 1321 struct dtsec_regs __iomem *regs = dtsec->regs; 1322 1323 if (!is_init_done(dtsec->dtsec_drv_param)) 1324 return -EINVAL; 1325 1326 *mac_version = ioread32be(®s->tsec_id); 1327 1328 return 0; 1329} 1330 1331int dtsec_set_exception(struct fman_mac *dtsec, 1332 enum fman_mac_exceptions exception, bool enable) 1333{ 1334 struct dtsec_regs __iomem *regs = dtsec->regs; 1335 u32 bit_mask = 0; 1336 1337 if (!is_init_done(dtsec->dtsec_drv_param)) 1338 return -EINVAL; 1339 1340 if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) { 1341 bit_mask = get_exception_flag(exception); 1342 if (bit_mask) { 1343 if (enable) 1344 dtsec->exceptions |= bit_mask; 1345 else 1346 dtsec->exceptions &= ~bit_mask; 1347 } else { 1348 pr_err("Undefined exception\n"); 1349 return -EINVAL; 1350 } 1351 if (enable) 1352 iowrite32be(ioread32be(®s->imask) | bit_mask, 1353 ®s->imask); 1354 else 1355 iowrite32be(ioread32be(®s->imask) & ~bit_mask, 1356 ®s->imask); 1357 } else { 1358 if (!dtsec->ptp_tsu_enabled) { 1359 pr_err("Exception valid for 1588 only\n"); 1360 return -EINVAL; 1361 } 1362 switch (exception) { 1363 case FM_MAC_EX_1G_1588_TS_RX_ERR: 1364 if (enable) { 1365 dtsec->en_tsu_err_exception = true; 1366 iowrite32be(ioread32be(®s->tmr_pemask) | 1367 TMR_PEMASK_TSREEN, 1368 ®s->tmr_pemask); 1369 } else { 1370 dtsec->en_tsu_err_exception = false; 1371 iowrite32be(ioread32be(®s->tmr_pemask) & 1372 ~TMR_PEMASK_TSREEN, 1373 ®s->tmr_pemask); 1374 } 1375 break; 1376 default: 1377 pr_err("Undefined exception\n"); 1378 return -EINVAL; 1379 } 1380 } 1381 1382 return 0; 1383} 1384 1385int dtsec_init(struct fman_mac *dtsec) 1386{ 1387 struct dtsec_regs __iomem *regs = dtsec->regs; 1388 struct dtsec_cfg *dtsec_drv_param; 1389 u16 max_frm_ln; 1390 int err; 1391 1392 if (is_init_done(dtsec->dtsec_drv_param)) 1393 return -EINVAL; 1394 1395 if (DEFAULT_RESET_ON_INIT && 1396 (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) { 1397 pr_err("Can't reset MAC!\n"); 1398 return -EINVAL; 1399 } 1400 1401 err = check_init_parameters(dtsec); 1402 if (err) 1403 return err; 1404 1405 dtsec_drv_param = dtsec->dtsec_drv_param; 1406 1407 err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if, 1408 dtsec->max_speed, dtsec->addr, dtsec->exceptions, 1409 dtsec->tbiphy->mdio.addr); 1410 if (err) { 1411 free_init_resources(dtsec); 1412 pr_err("DTSEC version doesn't support this i/f mode\n"); 1413 return err; 1414 } 1415 1416 if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) { 1417 u16 tmp_reg16; 1418 1419 /* Configure the TBI PHY Control Register */ 1420 tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET; 1421 phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16); 1422 1423 tmp_reg16 = TBICON_CLK_SELECT; 1424 phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16); 1425 1426 tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE | 1427 BMCR_FULLDPLX | BMCR_SPEED1000); 1428 phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16); 1429 1430 if (dtsec->basex_if) 1431 tmp_reg16 = TBIANA_1000X; 1432 else 1433 tmp_reg16 = TBIANA_SGMII; 1434 phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16); 1435 1436 tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART | 1437 BMCR_FULLDPLX | BMCR_SPEED1000); 1438 1439 phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16); 1440 } 1441 1442 /* Max Frame Length */ 1443 max_frm_ln = (u16)ioread32be(®s->maxfrm); 1444 err = fman_set_mac_max_frame(dtsec->fm, dtsec->mac_id, max_frm_ln); 1445 if (err) { 1446 pr_err("Setting max frame length failed\n"); 1447 free_init_resources(dtsec); 1448 return -EINVAL; 1449 } 1450 1451 dtsec->multicast_addr_hash = 1452 alloc_hash_table(EXTENDED_HASH_TABLE_SIZE); 1453 if (!dtsec->multicast_addr_hash) { 1454 free_init_resources(dtsec); 1455 pr_err("MC hash table is failed\n"); 1456 return -ENOMEM; 1457 } 1458 1459 dtsec->unicast_addr_hash = alloc_hash_table(DTSEC_HASH_TABLE_SIZE); 1460 if (!dtsec->unicast_addr_hash) { 1461 free_init_resources(dtsec); 1462 pr_err("UC hash table is failed\n"); 1463 return -ENOMEM; 1464 } 1465 1466 /* register err intr handler for dtsec to FPM (err) */ 1467 fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, 1468 FMAN_INTR_TYPE_ERR, dtsec_isr, dtsec); 1469 /* register 1588 intr handler for TMR to FPM (normal) */ 1470 fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, 1471 FMAN_INTR_TYPE_NORMAL, dtsec_1588_isr, dtsec); 1472 1473 kfree(dtsec_drv_param); 1474 dtsec->dtsec_drv_param = NULL; 1475 1476 return 0; 1477} 1478 1479int dtsec_free(struct fman_mac *dtsec) 1480{ 1481 free_init_resources(dtsec); 1482 1483 kfree(dtsec->dtsec_drv_param); 1484 dtsec->dtsec_drv_param = NULL; 1485 kfree(dtsec); 1486 1487 return 0; 1488} 1489 1490struct fman_mac *dtsec_config(struct fman_mac_params *params) 1491{ 1492 struct fman_mac *dtsec; 1493 struct dtsec_cfg *dtsec_drv_param; 1494 void __iomem *base_addr; 1495 1496 base_addr = params->base_addr; 1497 1498 /* allocate memory for the UCC GETH data structure. */ 1499 dtsec = kzalloc(sizeof(*dtsec), GFP_KERNEL); 1500 if (!dtsec) 1501 return NULL; 1502 1503 /* allocate memory for the d_tsec driver parameters data structure. */ 1504 dtsec_drv_param = kzalloc(sizeof(*dtsec_drv_param), GFP_KERNEL); 1505 if (!dtsec_drv_param) 1506 goto err_dtsec; 1507 1508 /* Plant parameter structure pointer */ 1509 dtsec->dtsec_drv_param = dtsec_drv_param; 1510 1511 set_dflts(dtsec_drv_param); 1512 1513 dtsec->regs = base_addr; 1514 dtsec->addr = ENET_ADDR_TO_UINT64(params->addr); 1515 dtsec->max_speed = params->max_speed; 1516 dtsec->phy_if = params->phy_if; 1517 dtsec->mac_id = params->mac_id; 1518 dtsec->exceptions = (DTSEC_IMASK_BREN | 1519 DTSEC_IMASK_RXCEN | 1520 DTSEC_IMASK_BTEN | 1521 DTSEC_IMASK_TXCEN | 1522 DTSEC_IMASK_TXEEN | 1523 DTSEC_IMASK_ABRTEN | 1524 DTSEC_IMASK_LCEN | 1525 DTSEC_IMASK_CRLEN | 1526 DTSEC_IMASK_XFUNEN | 1527 DTSEC_IMASK_IFERREN | 1528 DTSEC_IMASK_MAGEN | 1529 DTSEC_IMASK_TDPEEN | 1530 DTSEC_IMASK_RDPEEN); 1531 dtsec->exception_cb = params->exception_cb; 1532 dtsec->event_cb = params->event_cb; 1533 dtsec->dev_id = params->dev_id; 1534 dtsec->ptp_tsu_enabled = dtsec->dtsec_drv_param->ptp_tsu_en; 1535 dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en; 1536 1537 dtsec->fm = params->fm; 1538 dtsec->basex_if = params->basex_if; 1539 1540 if (!params->internal_phy_node) { 1541 pr_err("TBI PHY node is not available\n"); 1542 goto err_dtsec_drv_param; 1543 } 1544 1545 dtsec->tbiphy = of_phy_find_device(params->internal_phy_node); 1546 if (!dtsec->tbiphy) { 1547 pr_err("of_phy_find_device (TBI PHY) failed\n"); 1548 goto err_dtsec_drv_param; 1549 } 1550 1551 put_device(&dtsec->tbiphy->mdio.dev); 1552 1553 /* Save FMan revision */ 1554 fman_get_revision(dtsec->fm, &dtsec->fm_rev_info); 1555 1556 return dtsec; 1557 1558err_dtsec_drv_param: 1559 kfree(dtsec_drv_param); 1560err_dtsec: 1561 kfree(dtsec); 1562 return NULL; 1563} 1564