1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2/* Copyright 2017-2019 NXP */ 3 4#include <linux/bitops.h> 5 6/* ENETC device IDs */ 7#define ENETC_DEV_ID_PF 0xe100 8#define ENETC_DEV_ID_VF 0xef00 9#define ENETC_DEV_ID_PTP 0xee02 10 11/* ENETC register block BAR */ 12#define ENETC_BAR_REGS 0 13 14/** SI regs, offset: 0h */ 15#define ENETC_SIMR 0 16#define ENETC_SIMR_EN BIT(31) 17#define ENETC_SIMR_RSSE BIT(0) 18#define ENETC_SICTR0 0x18 19#define ENETC_SICTR1 0x1c 20#define ENETC_SIPCAPR0 0x20 21#define ENETC_SIPCAPR0_QBV BIT(4) 22#define ENETC_SIPCAPR0_PSFP BIT(9) 23#define ENETC_SIPCAPR0_RSS BIT(8) 24#define ENETC_SIPCAPR1 0x24 25#define ENETC_SITGTGR 0x30 26#define ENETC_SIRBGCR 0x38 27/* cache attribute registers for transactions initiated by ENETC */ 28#define ENETC_SICAR0 0x40 29#define ENETC_SICAR1 0x44 30#define ENETC_SICAR2 0x48 31/* rd snoop, no alloc 32 * wr snoop, no alloc, partial cache line update for BDs and full cache line 33 * update for data 34 */ 35#define ENETC_SICAR_RD_COHERENT 0x2b2b0000 36#define ENETC_SICAR_WR_COHERENT 0x00006727 37#define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 38 39#define ENETC_SIPMAR0 0x80 40#define ENETC_SIPMAR1 0x84 41 42/* VF-PF Message passing */ 43#define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 44/* msg size encoding: default and max msg value of 1024B encoded as 0 */ 45static inline u32 enetc_vsi_set_msize(u32 size) 46{ 47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 48} 49 50#define ENETC_PSIMSGRR 0x204 51#define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 52#define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 53#define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 54#define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 55 56#define ENETC_VSIMSGSR 0x204 /* RO */ 57#define ENETC_VSIMSGSR_MB BIT(0) 58#define ENETC_VSIMSGSR_MS BIT(1) 59#define ENETC_VSIMSGSNDAR0 0x210 60#define ENETC_VSIMSGSNDAR1 0x214 61 62#define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 63#define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 64 65/* SI statistics */ 66#define ENETC_SIROCT 0x300 67#define ENETC_SIRFRM 0x308 68#define ENETC_SIRUCA 0x310 69#define ENETC_SIRMCA 0x318 70#define ENETC_SITOCT 0x320 71#define ENETC_SITFRM 0x328 72#define ENETC_SITUCA 0x330 73#define ENETC_SITMCA 0x338 74#define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 75 76/* Control BDR regs */ 77#define ENETC_SICBDRMR 0x800 78#define ENETC_SICBDRSR 0x804 /* RO */ 79#define ENETC_SICBDRBAR0 0x810 80#define ENETC_SICBDRBAR1 0x814 81#define ENETC_SICBDRPIR 0x818 82#define ENETC_SICBDRCIR 0x81c 83#define ENETC_SICBDRLENR 0x820 84 85#define ENETC_SICAPR0 0x900 86#define ENETC_SICAPR1 0x904 87 88#define ENETC_PSIIER 0xa00 89#define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 90#define ENETC_PSIIDR 0xa08 91#define ENETC_SITXIDR 0xa18 92#define ENETC_SIRXIDR 0xa28 93#define ENETC_SIMSIVR 0xa30 94 95#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 96#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 97 98#define ENETC_SIUEFDCR 0xe28 99 100#define ENETC_SIRFSCAPR 0x1200 101#define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 102#define ENETC_SIRSSCAPR 0x1600 103#define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 104 105/** SI BDR sub-blocks, n = 0..7 */ 106enum enetc_bdr_type {TX, RX}; 107#define ENETC_BDR_OFF(i) ((i) * 0x200) 108#define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 109/* RX BDR reg offsets */ 110#define ENETC_RBMR 0 111#define ENETC_RBMR_BDS BIT(2) 112#define ENETC_RBMR_VTE BIT(5) 113#define ENETC_RBMR_EN BIT(31) 114#define ENETC_RBSR 0x4 115#define ENETC_RBBSR 0x8 116#define ENETC_RBCIR 0xc 117#define ENETC_RBBAR0 0x10 118#define ENETC_RBBAR1 0x14 119#define ENETC_RBPIR 0x18 120#define ENETC_RBLENR 0x20 121#define ENETC_RBIER 0xa0 122#define ENETC_RBIER_RXTIE BIT(0) 123#define ENETC_RBIDR 0xa4 124#define ENETC_RBICR0 0xa8 125#define ENETC_RBICR0_ICEN BIT(31) 126#define ENETC_RBICR0_ICPT_MASK 0x1ff 127#define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 128#define ENETC_RBICR1 0xac 129 130/* TX BDR reg offsets */ 131#define ENETC_TBMR 0 132#define ENETC_TBSR_BUSY BIT(0) 133#define ENETC_TBMR_VIH BIT(9) 134#define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 135#define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 136#define ENETC_TBMR_EN BIT(31) 137#define ENETC_TBSR 0x4 138#define ENETC_TBBAR0 0x10 139#define ENETC_TBBAR1 0x14 140#define ENETC_TBPIR 0x18 141#define ENETC_TBCIR 0x1c 142#define ENETC_TBCIR_IDX_MASK 0xffff 143#define ENETC_TBLENR 0x20 144#define ENETC_TBIER 0xa0 145#define ENETC_TBIER_TXTIE BIT(0) 146#define ENETC_TBIDR 0xa4 147#define ENETC_TBICR0 0xa8 148#define ENETC_TBICR0_ICEN BIT(31) 149#define ENETC_TBICR0_ICPT_MASK 0xf 150#define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 151#define ENETC_TBICR1 0xac 152 153#define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 154 155/* Port regs, offset: 1_0000h */ 156#define ENETC_PORT_BASE 0x10000 157#define ENETC_PMR 0x0000 158#define ENETC_PMR_EN GENMASK(18, 16) 159#define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 160#define ENETC_PMR_PSPEED_10M 0 161#define ENETC_PMR_PSPEED_100M BIT(8) 162#define ENETC_PMR_PSPEED_1000M BIT(9) 163#define ENETC_PMR_PSPEED_2500M BIT(10) 164#define ENETC_PSR 0x0004 /* RO */ 165#define ENETC_PSIPMR 0x0018 166#define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 167#define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 168#define ENETC_PSIPVMR 0x001c 169#define ENETC_VLAN_PROMISC_MAP_ALL 0x7 170#define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 171#define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 172#define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 173#define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 174#define ENETC_PVCLCTR 0x0208 175#define ENETC_PCVLANR1 0x0210 176#define ENETC_PCVLANR2 0x0214 177#define ENETC_VLAN_TYPE_C BIT(0) 178#define ENETC_VLAN_TYPE_S BIT(1) 179#define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 180#define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 181#define ENETC_PSIVLAN_EN BIT(31) 182#define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 183#define ENETC_PTXMBAR 0x0608 184#define ENETC_PCAPR0 0x0900 185#define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 186#define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 187#define ENETC_PCAPR1 0x0904 188#define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 189#define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 190#define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 191#define ENETC_PSICFGR0_VTE BIT(12) 192#define ENETC_PSICFGR0_SIVIE BIT(14) 193#define ENETC_PSICFGR0_ASE BIT(15) 194#define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 195 196#define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 197#define ENETC_CBSE BIT(31) 198#define ENETC_CBS_BW_MASK GENMASK(6, 0) 199#define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 200#define ENETC_RSSHASH_KEY_SIZE 40 201#define ENETC_PRSSCAPR 0x1404 202#define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 203#define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 204#define ENETC_PSIVLANFMR 0x1700 205#define ENETC_PSIVLANFMR_VS BIT(0) 206#define ENETC_PRFSMR 0x1800 207#define ENETC_PRFSMR_RFSE BIT(31) 208#define ENETC_PRFSCAPR 0x1804 209#define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 210#define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 211#define ENETC_PFPMR 0x1900 212#define ENETC_PFPMR_PMACE BIT(1) 213#define ENETC_PFPMR_MWLM BIT(0) 214#define ENETC_EMDIO_BASE 0x1c00 215#define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 216#define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 217#define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 218#define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 219#define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 220#define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 221#define ENETC_MMCSR 0x1f00 222#define ENETC_MMCSR_ME BIT(16) 223#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 224 225#define ENETC_PM0_CMD_CFG 0x8008 226#define ENETC_PM1_CMD_CFG 0x9008 227#define ENETC_PM0_TX_EN BIT(0) 228#define ENETC_PM0_RX_EN BIT(1) 229#define ENETC_PM0_PROMISC BIT(4) 230#define ENETC_PM0_CMD_XGLP BIT(10) 231#define ENETC_PM0_CMD_TXP BIT(11) 232#define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 233#define ENETC_PM0_CMD_SFD BIT(21) 234#define ENETC_PM0_MAXFRM 0x8014 235#define ENETC_SET_TX_MTU(val) ((val) << 16) 236#define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 237#define ENETC_PM0_RX_FIFO 0x801c 238#define ENETC_PM0_RX_FIFO_VAL 1 239 240#define ENETC_PM_IMDIO_BASE 0x8030 241 242#define ENETC_PM0_IF_MODE 0x8300 243#define ENETC_PM0_IFM_RG BIT(2) 244#define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 245#define ENETC_PM0_IFM_EN_AUTO BIT(15) 246#define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 247#define ENETC_PM0_IFM_SSP_1000 (2 << 13) 248#define ENETC_PM0_IFM_SSP_100 (0 << 13) 249#define ENETC_PM0_IFM_SSP_10 (1 << 13) 250#define ENETC_PM0_IFM_FULL_DPX BIT(12) 251#define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 252#define ENETC_PM0_IFM_IFMODE_XGMII 0 253#define ENETC_PM0_IFM_IFMODE_GMII 2 254#define ENETC_PSIDCAPR 0x1b08 255#define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 256#define ENETC_PSFCAPR 0x1b18 257#define ENETC_PSFCAPR_MSK GENMASK(15, 0) 258#define ENETC_PSGCAPR 0x1b28 259#define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 260#define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 261#define ENETC_PFMCAPR 0x1b38 262#define ENETC_PFMCAPR_MSK GENMASK(15, 0) 263 264/* MAC counters */ 265#define ENETC_PM0_REOCT 0x8100 266#define ENETC_PM0_RALN 0x8110 267#define ENETC_PM0_RXPF 0x8118 268#define ENETC_PM0_RFRM 0x8120 269#define ENETC_PM0_RFCS 0x8128 270#define ENETC_PM0_RVLAN 0x8130 271#define ENETC_PM0_RERR 0x8138 272#define ENETC_PM0_RUCA 0x8140 273#define ENETC_PM0_RMCA 0x8148 274#define ENETC_PM0_RBCA 0x8150 275#define ENETC_PM0_RDRP 0x8158 276#define ENETC_PM0_RPKT 0x8160 277#define ENETC_PM0_RUND 0x8168 278#define ENETC_PM0_R64 0x8170 279#define ENETC_PM0_R127 0x8178 280#define ENETC_PM0_R255 0x8180 281#define ENETC_PM0_R511 0x8188 282#define ENETC_PM0_R1023 0x8190 283#define ENETC_PM0_R1522 0x8198 284#define ENETC_PM0_R1523X 0x81A0 285#define ENETC_PM0_ROVR 0x81A8 286#define ENETC_PM0_RJBR 0x81B0 287#define ENETC_PM0_RFRG 0x81B8 288#define ENETC_PM0_RCNP 0x81C0 289#define ENETC_PM0_RDRNTP 0x81C8 290#define ENETC_PM0_TEOCT 0x8200 291#define ENETC_PM0_TOCT 0x8208 292#define ENETC_PM0_TCRSE 0x8210 293#define ENETC_PM0_TXPF 0x8218 294#define ENETC_PM0_TFRM 0x8220 295#define ENETC_PM0_TFCS 0x8228 296#define ENETC_PM0_TVLAN 0x8230 297#define ENETC_PM0_TERR 0x8238 298#define ENETC_PM0_TUCA 0x8240 299#define ENETC_PM0_TMCA 0x8248 300#define ENETC_PM0_TBCA 0x8250 301#define ENETC_PM0_TPKT 0x8260 302#define ENETC_PM0_TUND 0x8268 303#define ENETC_PM0_T64 0x8270 304#define ENETC_PM0_T127 0x8278 305#define ENETC_PM0_T255 0x8280 306#define ENETC_PM0_T511 0x8288 307#define ENETC_PM0_T1023 0x8290 308#define ENETC_PM0_T1522 0x8298 309#define ENETC_PM0_T1523X 0x82A0 310#define ENETC_PM0_TCNP 0x82C0 311#define ENETC_PM0_TDFR 0x82D0 312#define ENETC_PM0_TMCOL 0x82D8 313#define ENETC_PM0_TSCOL 0x82E0 314#define ENETC_PM0_TLCOL 0x82E8 315#define ENETC_PM0_TECOL 0x82F0 316 317/* Port counters */ 318#define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 319#define ENETC_PBFDSIR 0x0810 320#define ENETC_PFDMSAPR 0x0814 321#define ENETC_UFDMF 0x1680 322#define ENETC_MFDMF 0x1684 323#define ENETC_PUFDVFR 0x1780 324#define ENETC_PMFDVFR 0x1784 325#define ENETC_PBFDVFR 0x1788 326 327/** Global regs, offset: 2_0000h */ 328#define ENETC_GLOBAL_BASE 0x20000 329#define ENETC_G_EIPBRR0 0x0bf8 330#define ENETC_G_EIPBRR1 0x0bfc 331#define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 332#define ENETC_G_EPFBLPR1_XGMII 0x80000000 333 334/* PCI device info */ 335struct enetc_hw { 336 /* SI registers, used by all PCI functions */ 337 void __iomem *reg; 338 /* Port registers, PF only */ 339 void __iomem *port; 340 /* IP global registers, PF only */ 341 void __iomem *global; 342}; 343 344/* ENETC register accessors */ 345 346/* MDIO issue workaround (on LS1028A) - 347 * Due to a hardware issue, an access to MDIO registers 348 * that is concurrent with other ENETC register accesses 349 * may lead to the MDIO access being dropped or corrupted. 350 * To protect the MDIO accesses a readers-writers locking 351 * scheme is used, where the MDIO register accesses are 352 * protected by write locks to insure exclusivity, while 353 * the remaining ENETC registers are accessed under read 354 * locks since they only compete with MDIO accesses. 355 */ 356extern rwlock_t enetc_mdio_lock; 357 358/* use this locking primitive only on the fast datapath to 359 * group together multiple non-MDIO register accesses to 360 * minimize the overhead of the lock 361 */ 362static inline void enetc_lock_mdio(void) 363{ 364 read_lock(&enetc_mdio_lock); 365} 366 367static inline void enetc_unlock_mdio(void) 368{ 369 read_unlock(&enetc_mdio_lock); 370} 371 372/* use these accessors only on the fast datapath under 373 * the enetc_lock_mdio() locking primitive to minimize 374 * the overhead of the lock 375 */ 376static inline u32 enetc_rd_reg_hot(void __iomem *reg) 377{ 378 lockdep_assert_held(&enetc_mdio_lock); 379 380 return ioread32(reg); 381} 382 383static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 384{ 385 lockdep_assert_held(&enetc_mdio_lock); 386 387 iowrite32(val, reg); 388} 389 390/* internal helpers for the MDIO w/a */ 391static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 392{ 393 u32 val; 394 395 enetc_lock_mdio(); 396 val = ioread32(reg); 397 enetc_unlock_mdio(); 398 399 return val; 400} 401 402static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 403{ 404 enetc_lock_mdio(); 405 iowrite32(val, reg); 406 enetc_unlock_mdio(); 407} 408 409static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 410{ 411 unsigned long flags; 412 u32 val; 413 414 write_lock_irqsave(&enetc_mdio_lock, flags); 415 val = ioread32(reg); 416 write_unlock_irqrestore(&enetc_mdio_lock, flags); 417 418 return val; 419} 420 421static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 422{ 423 unsigned long flags; 424 425 write_lock_irqsave(&enetc_mdio_lock, flags); 426 iowrite32(val, reg); 427 write_unlock_irqrestore(&enetc_mdio_lock, flags); 428} 429 430#ifdef ioread64 431static inline u64 _enetc_rd_reg64(void __iomem *reg) 432{ 433 return ioread64(reg); 434} 435#else 436/* using this to read out stats on 32b systems */ 437static inline u64 _enetc_rd_reg64(void __iomem *reg) 438{ 439 u32 low, high, tmp; 440 441 do { 442 high = ioread32(reg + 4); 443 low = ioread32(reg); 444 tmp = ioread32(reg + 4); 445 } while (high != tmp); 446 447 return le64_to_cpu((__le64)high << 32 | low); 448} 449#endif 450 451static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 452{ 453 u64 val; 454 455 enetc_lock_mdio(); 456 val = _enetc_rd_reg64(reg); 457 enetc_unlock_mdio(); 458 459 return val; 460} 461 462/* general register accessors */ 463#define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 464#define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 465#define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 466#define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 467#define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 468#define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 469#define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 470/* port register accessors - PF only */ 471#define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 472#define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 473#define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 474#define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 475 (hw)->port + (off), val) 476/* global register accessors - PF only */ 477#define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 478#define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 479/* BDR register accessors, see ENETC_BDR() */ 480#define enetc_bdr_rd(hw, t, n, off) \ 481 enetc_rd(hw, ENETC_BDR(t, n, off)) 482#define enetc_bdr_wr(hw, t, n, off, val) \ 483 enetc_wr(hw, ENETC_BDR(t, n, off), val) 484#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 485#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 486#define enetc_txbdr_wr(hw, n, off, val) \ 487 enetc_bdr_wr(hw, TX, n, off, val) 488#define enetc_rxbdr_wr(hw, n, off, val) \ 489 enetc_bdr_wr(hw, RX, n, off, val) 490 491/* Buffer Descriptors (BD) */ 492union enetc_tx_bd { 493 struct { 494 __le64 addr; 495 __le16 buf_len; 496 __le16 frm_len; 497 union { 498 struct { 499 __le16 l3_csoff; 500 u8 l4_csoff; 501 u8 flags; 502 }; /* default layout */ 503 __le32 txstart; 504 __le32 lstatus; 505 }; 506 }; 507 struct { 508 __le32 tstamp; 509 __le16 tpid; 510 __le16 vid; 511 u8 reserved[6]; 512 u8 e_flags; 513 u8 flags; 514 } ext; /* Tx BD extension */ 515 struct { 516 __le32 tstamp; 517 u8 reserved[10]; 518 u8 status; 519 u8 flags; 520 } wb; /* writeback descriptor */ 521}; 522 523#define ENETC_TXBD_FLAGS_L4CS BIT(0) 524#define ENETC_TXBD_FLAGS_TSE BIT(1) 525#define ENETC_TXBD_FLAGS_W BIT(2) 526#define ENETC_TXBD_FLAGS_CSUM BIT(3) 527#define ENETC_TXBD_FLAGS_TXSTART BIT(4) 528#define ENETC_TXBD_FLAGS_EX BIT(6) 529#define ENETC_TXBD_FLAGS_F BIT(7) 530#define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 531#define ENETC_TXBD_FLAGS_OFFSET 24 532static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 533{ 534 memset(txbd, 0, sizeof(*txbd)); 535} 536 537/* L3 csum flags */ 538#define ENETC_TXBD_L3_IPCS BIT(7) 539#define ENETC_TXBD_L3_IPV6 BIT(15) 540 541#define ENETC_TXBD_L3_START_MASK GENMASK(6, 0) 542#define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8) 543 544/* Extension flags */ 545#define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 546#define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 547 548static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags) 549{ 550 return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) | 551 (start & ENETC_TXBD_L3_START_MASK)); 552} 553 554/* L4 csum flags */ 555#define ENETC_TXBD_L4_UDP BIT(5) 556#define ENETC_TXBD_L4_TCP BIT(6) 557 558union enetc_rx_bd { 559 struct { 560 __le64 addr; 561 u8 reserved[8]; 562 } w; 563 struct { 564 __le16 inet_csum; 565 __le16 parse_summary; 566 __le32 rss_hash; 567 __le16 buf_len; 568 __le16 vlan_opt; 569 union { 570 struct { 571 __le16 flags; 572 __le16 error; 573 }; 574 __le32 lstatus; 575 }; 576 } r; 577 struct { 578 __le32 tstamp; 579 u8 reserved[12]; 580 } ext; 581}; 582 583#define ENETC_RXBD_LSTATUS_R BIT(30) 584#define ENETC_RXBD_LSTATUS_F BIT(31) 585#define ENETC_RXBD_ERR_MASK 0xff 586#define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 587#define ENETC_RXBD_FLAG_VLAN BIT(9) 588#define ENETC_RXBD_FLAG_TSTMP BIT(10) 589#define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 590 591#define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 592#define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 593#define ENETC_MAX_NUM_VFS 2 594 595#define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 596#define ENETC_CBD_STATUS_MASK 0xf 597 598struct enetc_cmd_rfse { 599 u8 smac_h[6]; 600 u8 smac_m[6]; 601 u8 dmac_h[6]; 602 u8 dmac_m[6]; 603 u32 sip_h[4]; 604 u32 sip_m[4]; 605 u32 dip_h[4]; 606 u32 dip_m[4]; 607 u16 ethtype_h; 608 u16 ethtype_m; 609 u16 ethtype4_h; 610 u16 ethtype4_m; 611 u16 sport_h; 612 u16 sport_m; 613 u16 dport_h; 614 u16 dport_m; 615 u16 vlan_h; 616 u16 vlan_m; 617 u8 proto_h; 618 u8 proto_m; 619 u16 flags; 620 u16 result; 621 u16 mode; 622}; 623 624#define ENETC_RFSE_EN BIT(15) 625#define ENETC_RFSE_MODE_BD 2 626 627static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) 628{ 629 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 630 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 631} 632 633#define ENETC_SI_INT_IDX 0 634/* base index for Rx/Tx interrupts */ 635#define ENETC_BDR_INT_BASE_IDX 1 636 637/* Messaging */ 638 639/* Command completion status */ 640enum enetc_msg_cmd_status { 641 ENETC_MSG_CMD_STATUS_OK, 642 ENETC_MSG_CMD_STATUS_FAIL 643}; 644 645/* VSI-PSI command message types */ 646enum enetc_msg_cmd_type { 647 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 648 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 649 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 650}; 651 652/* VSI-PSI command action types */ 653enum enetc_msg_cmd_action_type { 654 ENETC_MSG_CMD_MNG_ADD = 1, 655 ENETC_MSG_CMD_MNG_REMOVE 656}; 657 658/* PSI-VSI command header format */ 659struct enetc_msg_cmd_header { 660 u16 type; /* command class type */ 661 u16 id; /* denotes the specific required action */ 662}; 663 664/* Common H/W utility functions */ 665 666static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 667 bool en) 668{ 669 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 670 671 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 672 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 673} 674 675static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 676 bool en) 677{ 678 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 679 680 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 681 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 682} 683 684static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 685 int prio) 686{ 687 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 688 689 val &= ~ENETC_TBMR_PRIO_MASK; 690 val |= ENETC_TBMR_SET_PRIO(prio); 691 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 692} 693 694enum bdcr_cmd_class { 695 BDCR_CMD_UNSPEC = 0, 696 BDCR_CMD_MAC_FILTER, 697 BDCR_CMD_VLAN_FILTER, 698 BDCR_CMD_RSS, 699 BDCR_CMD_RFS, 700 BDCR_CMD_PORT_GCL, 701 BDCR_CMD_RECV_CLASSIFIER, 702 BDCR_CMD_STREAM_IDENTIFY, 703 BDCR_CMD_STREAM_FILTER, 704 BDCR_CMD_STREAM_GCL, 705 BDCR_CMD_FLOW_METER, 706 __BDCR_CMD_MAX_LEN, 707 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 708}; 709 710/* class 5, command 0 */ 711struct tgs_gcl_conf { 712 u8 atc; /* init gate value */ 713 u8 res[7]; 714 struct { 715 u8 res1[4]; 716 __le16 acl_len; 717 u8 res2[2]; 718 }; 719}; 720 721/* gate control list entry */ 722struct gce { 723 __le32 period; 724 u8 gate; 725 u8 res[3]; 726}; 727 728/* tgs_gcl_conf address point to this data space */ 729struct tgs_gcl_data { 730 __le32 btl; 731 __le32 bth; 732 __le32 ct; 733 __le32 cte; 734 struct gce entry[]; 735}; 736 737/* class 7, command 0, Stream Identity Entry Configuration */ 738struct streamid_conf { 739 __le32 stream_handle; /* init gate value */ 740 __le32 iports; 741 u8 id_type; 742 u8 oui[3]; 743 u8 res[3]; 744 u8 en; 745}; 746 747#define ENETC_CBDR_SID_VID_MASK 0xfff 748#define ENETC_CBDR_SID_VIDM BIT(12) 749#define ENETC_CBDR_SID_TG_MASK 0xc000 750/* streamid_conf address point to this data space */ 751struct streamid_data { 752 union { 753 u8 dmac[6]; 754 u8 smac[6]; 755 }; 756 u16 vid_vidm_tg; 757}; 758 759#define ENETC_CBDR_SFI_PRI_MASK 0x7 760#define ENETC_CBDR_SFI_PRIM BIT(3) 761#define ENETC_CBDR_SFI_BLOV BIT(4) 762#define ENETC_CBDR_SFI_BLEN BIT(5) 763#define ENETC_CBDR_SFI_MSDUEN BIT(6) 764#define ENETC_CBDR_SFI_FMITEN BIT(7) 765#define ENETC_CBDR_SFI_ENABLE BIT(7) 766/* class 8, command 0, Stream Filter Instance, Short Format */ 767struct sfi_conf { 768 __le32 stream_handle; 769 u8 multi; 770 u8 res[2]; 771 u8 sthm; 772 /* Max Service Data Unit or Flow Meter Instance Table index. 773 * Depending on the value of FLT this represents either Max 774 * Service Data Unit (max frame size) allowed by the filter 775 * entry or is an index into the Flow Meter Instance table 776 * index identifying the policer which will be used to police 777 * it. 778 */ 779 __le16 fm_inst_table_index; 780 __le16 msdu; 781 __le16 sg_inst_table_index; 782 u8 res1[2]; 783 __le32 input_ports; 784 u8 res2[3]; 785 u8 en; 786}; 787 788/* class 8, command 2 stream Filter Instance status query short format 789 * command no need structure define 790 * Stream Filter Instance Query Statistics Response data 791 */ 792struct sfi_counter_data { 793 u32 matchl; 794 u32 matchh; 795 u32 msdu_dropl; 796 u32 msdu_droph; 797 u32 stream_gate_dropl; 798 u32 stream_gate_droph; 799 u32 flow_meter_dropl; 800 u32 flow_meter_droph; 801}; 802 803#define ENETC_CBDR_SGI_OIPV_MASK 0x7 804#define ENETC_CBDR_SGI_OIPV_EN BIT(3) 805#define ENETC_CBDR_SGI_CGTST BIT(6) 806#define ENETC_CBDR_SGI_OGTST BIT(7) 807#define ENETC_CBDR_SGI_CFG_CHG BIT(1) 808#define ENETC_CBDR_SGI_CFG_PND BIT(2) 809#define ENETC_CBDR_SGI_OEX BIT(4) 810#define ENETC_CBDR_SGI_OEXEN BIT(5) 811#define ENETC_CBDR_SGI_IRX BIT(6) 812#define ENETC_CBDR_SGI_IRXEN BIT(7) 813#define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 814#define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 815#define ENETC_CBDR_SGI_EN BIT(7) 816/* class 9, command 0, Stream Gate Instance Table, Short Format 817 * class 9, command 2, Stream Gate Instance Table entry query write back 818 * Short Format 819 */ 820struct sgi_table { 821 u8 res[8]; 822 u8 oipv; 823 u8 res0[2]; 824 u8 ocgtst; 825 u8 res1[7]; 826 u8 gset; 827 u8 oacl_len; 828 u8 res2[2]; 829 u8 en; 830}; 831 832#define ENETC_CBDR_SGI_AIPV_MASK 0x7 833#define ENETC_CBDR_SGI_AIPV_EN BIT(3) 834#define ENETC_CBDR_SGI_AGTST BIT(7) 835 836/* class 9, command 1, Stream Gate Control List, Long Format */ 837struct sgcl_conf { 838 u8 aipv; 839 u8 res[2]; 840 u8 agtst; 841 u8 res1[4]; 842 union { 843 struct { 844 u8 res2[4]; 845 u8 acl_len; 846 u8 res3[3]; 847 }; 848 u8 cct[8]; /* Config change time */ 849 }; 850}; 851 852#define ENETC_CBDR_SGL_IOMEN BIT(0) 853#define ENETC_CBDR_SGL_IPVEN BIT(3) 854#define ENETC_CBDR_SGL_GTST BIT(4) 855#define ENETC_CBDR_SGL_IPV_MASK 0xe 856/* Stream Gate Control List Entry */ 857struct sgce { 858 u32 interval; 859 u8 msdu[3]; 860 u8 multi; 861}; 862 863/* stream control list class 9 , cmd 1 data buffer */ 864struct sgcl_data { 865 u32 btl; 866 u32 bth; 867 u32 ct; 868 u32 cte; 869 struct sgce sgcl[0]; 870}; 871 872#define ENETC_CBDR_FMI_MR BIT(0) 873#define ENETC_CBDR_FMI_MREN BIT(1) 874#define ENETC_CBDR_FMI_DOY BIT(2) 875#define ENETC_CBDR_FMI_CM BIT(3) 876#define ENETC_CBDR_FMI_CF BIT(4) 877#define ENETC_CBDR_FMI_NDOR BIT(5) 878#define ENETC_CBDR_FMI_OALEN BIT(6) 879#define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 880 881/* class 10: command 0/1, Flow Meter Instance Set, short Format */ 882struct fmi_conf { 883 __le32 cir; 884 __le32 cbs; 885 __le32 eir; 886 __le32 ebs; 887 u8 conf; 888 u8 res1; 889 u8 ir_fpp; 890 u8 res2[4]; 891 u8 en; 892}; 893 894struct enetc_cbd { 895 union{ 896 struct sfi_conf sfi_conf; 897 struct sgi_table sgi_table; 898 struct fmi_conf fmi_conf; 899 struct { 900 __le32 addr[2]; 901 union { 902 __le32 opt[4]; 903 struct tgs_gcl_conf gcl_conf; 904 struct streamid_conf sid_set; 905 struct sgcl_conf sgcl_conf; 906 }; 907 }; /* Long format */ 908 __le32 data[6]; 909 }; 910 __le16 index; 911 __le16 length; 912 u8 cmd; 913 u8 cls; 914 u8 _res; 915 u8 status_flags; 916}; 917 918#define ENETC_CLK 400000000ULL 919static inline u32 enetc_cycles_to_usecs(u32 cycles) 920{ 921 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK); 922} 923 924static inline u32 enetc_usecs_to_cycles(u32 usecs) 925{ 926 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL); 927} 928 929/* port time gating control register */ 930#define ENETC_QBV_PTGCR_OFFSET 0x11a00 931#define ENETC_QBV_TGE BIT(31) 932#define ENETC_QBV_TGPE BIT(30) 933 934/* Port time gating capability register */ 935#define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 936#define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) 937 938/* Port time specific departure */ 939#define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 940#define ENETC_TSDE BIT(31) 941 942/* PSFP setting */ 943#define ENETC_PPSFPMR 0x11b00 944#define ENETC_PPSFPMR_PSFPEN BIT(0) 945#define ENETC_PPSFPMR_VS BIT(1) 946#define ENETC_PPSFPMR_PVC BIT(2) 947#define ENETC_PPSFPMR_PVZC BIT(3) 948