1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2/* Copyright 2017-2019 NXP */ 3 4#include <linux/timer.h> 5#include <linux/pci.h> 6#include <linux/netdevice.h> 7#include <linux/etherdevice.h> 8#include <linux/dma-mapping.h> 9#include <linux/skbuff.h> 10#include <linux/ethtool.h> 11#include <linux/if_vlan.h> 12#include <linux/phylink.h> 13#include <linux/dim.h> 14 15#include "enetc_hw.h" 16 17#define ENETC_MAC_MAXFRM_SIZE 9600 18#define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \ 19 (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN)) 20 21struct enetc_tx_swbd { 22 struct sk_buff *skb; 23 dma_addr_t dma; 24 u16 len; 25 u8 is_dma_page:1; 26 u8 check_wb:1; 27 u8 do_tstamp:1; 28}; 29 30#define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE 31#define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ 32#define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ 33#define ENETC_RXB_DMA_SIZE \ 34 (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) 35 36struct enetc_rx_swbd { 37 dma_addr_t dma; 38 struct page *page; 39 u16 page_offset; 40}; 41 42struct enetc_ring_stats { 43 unsigned int packets; 44 unsigned int bytes; 45 unsigned int rx_alloc_errs; 46}; 47 48#define ENETC_RX_RING_DEFAULT_SIZE 512 49#define ENETC_TX_RING_DEFAULT_SIZE 256 50#define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2) 51 52struct enetc_bdr { 53 struct device *dev; /* for DMA mapping */ 54 struct net_device *ndev; 55 void *bd_base; /* points to Rx or Tx BD ring */ 56 union { 57 void __iomem *tpir; 58 void __iomem *rcir; 59 }; 60 u16 index; 61 u16 prio; 62 int bd_count; /* # of BDs */ 63 int next_to_use; 64 int next_to_clean; 65 union { 66 struct enetc_tx_swbd *tx_swbd; 67 struct enetc_rx_swbd *rx_swbd; 68 }; 69 union { 70 void __iomem *tcir; /* Tx */ 71 int next_to_alloc; /* Rx */ 72 }; 73 void __iomem *idr; /* Interrupt Detect Register pointer */ 74 75 struct enetc_ring_stats stats; 76 77 dma_addr_t bd_dma_base; 78 u8 tsd_enable; /* Time specific departure */ 79 bool ext_en; /* enable h/w descriptor extensions */ 80} ____cacheline_aligned_in_smp; 81 82static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i) 83{ 84 if (unlikely(++*i == bdr->bd_count)) 85 *i = 0; 86} 87 88static inline int enetc_bd_unused(struct enetc_bdr *bdr) 89{ 90 if (bdr->next_to_clean > bdr->next_to_use) 91 return bdr->next_to_clean - bdr->next_to_use - 1; 92 93 return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; 94} 95 96/* Control BD ring */ 97#define ENETC_CBDR_DEFAULT_SIZE 64 98struct enetc_cbdr { 99 void *bd_base; /* points to Rx or Tx BD ring */ 100 void __iomem *pir; 101 void __iomem *cir; 102 103 int bd_count; /* # of BDs */ 104 int next_to_use; 105 int next_to_clean; 106 107 dma_addr_t bd_dma_base; 108}; 109 110#define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i])) 111 112static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i) 113{ 114 int hw_idx = i; 115 116#ifdef CONFIG_FSL_ENETC_PTP_CLOCK 117 if (rx_ring->ext_en) 118 hw_idx = 2 * i; 119#endif 120 return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]); 121} 122 123static inline union enetc_rx_bd *enetc_rxbd_next(struct enetc_bdr *rx_ring, 124 union enetc_rx_bd *rxbd, 125 int i) 126{ 127 rxbd++; 128#ifdef CONFIG_FSL_ENETC_PTP_CLOCK 129 if (rx_ring->ext_en) 130 rxbd++; 131#endif 132 if (unlikely(++i == rx_ring->bd_count)) 133 rxbd = rx_ring->bd_base; 134 135 return rxbd; 136} 137 138static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd) 139{ 140 return ++rxbd; 141} 142 143struct enetc_msg_swbd { 144 void *vaddr; 145 dma_addr_t dma; 146 int size; 147}; 148 149#define ENETC_REV1 0x1 150enum enetc_errata { 151 ENETC_ERR_TXCSUM = BIT(0), 152 ENETC_ERR_VLAN_ISOL = BIT(1), 153 ENETC_ERR_UCMCSWP = BIT(2), 154}; 155 156#define ENETC_SI_F_QBV BIT(0) 157#define ENETC_SI_F_PSFP BIT(1) 158 159/* PCI IEP device data */ 160struct enetc_si { 161 struct pci_dev *pdev; 162 struct enetc_hw hw; 163 enum enetc_errata errata; 164 165 struct net_device *ndev; /* back ref. */ 166 167 struct enetc_cbdr cbd_ring; 168 169 int num_rx_rings; /* how many rings are available in the SI */ 170 int num_tx_rings; 171 int num_fs_entries; 172 int num_rss; /* number of RSS buckets */ 173 unsigned short pad; 174 int hw_features; 175}; 176 177#define ENETC_SI_ALIGN 32 178 179static inline void *enetc_si_priv(const struct enetc_si *si) 180{ 181 return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN); 182} 183 184static inline bool enetc_si_is_pf(struct enetc_si *si) 185{ 186 return !!(si->hw.port); 187} 188 189#define ENETC_MAX_NUM_TXQS 8 190#define ENETC_INT_NAME_MAX (IFNAMSIZ + 8) 191 192struct enetc_int_vector { 193 void __iomem *rbier; 194 void __iomem *tbier_base; 195 void __iomem *ricr1; 196 unsigned long tx_rings_map; 197 int count_tx_rings; 198 u32 rx_ictt; 199 u16 comp_cnt; 200 bool rx_dim_en, rx_napi_work; 201 struct napi_struct napi ____cacheline_aligned_in_smp; 202 struct dim rx_dim ____cacheline_aligned_in_smp; 203 char name[ENETC_INT_NAME_MAX]; 204 205 struct enetc_bdr rx_ring; 206 struct enetc_bdr tx_ring[]; 207} ____cacheline_aligned_in_smp; 208 209struct enetc_cls_rule { 210 struct ethtool_rx_flow_spec fs; 211 int used; 212}; 213 214#define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */ 215struct psfp_cap { 216 u32 max_streamid; 217 u32 max_psfp_filter; 218 u32 max_psfp_gate; 219 u32 max_psfp_gatelist; 220 u32 max_psfp_meter; 221}; 222 223/* TODO: more hardware offloads */ 224enum enetc_active_offloads { 225 ENETC_F_RX_TSTAMP = BIT(0), 226 ENETC_F_TX_TSTAMP = BIT(1), 227 ENETC_F_QBV = BIT(2), 228 ENETC_F_QCI = BIT(3), 229}; 230 231/* interrupt coalescing modes */ 232enum enetc_ic_mode { 233 /* one interrupt per frame */ 234 ENETC_IC_NONE = 0, 235 /* activated when int coalescing time is set to a non-0 value */ 236 ENETC_IC_RX_MANUAL = BIT(0), 237 ENETC_IC_TX_MANUAL = BIT(1), 238 /* use dynamic interrupt moderation */ 239 ENETC_IC_RX_ADAPTIVE = BIT(2), 240}; 241 242#define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2) 243#define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2) 244#define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600) 245 246struct enetc_ndev_priv { 247 struct net_device *ndev; 248 struct device *dev; /* dma-mapping device */ 249 struct enetc_si *si; 250 251 int bdr_int_num; /* number of Rx/Tx ring interrupts */ 252 struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT]; 253 u16 num_rx_rings, num_tx_rings; 254 u16 rx_bd_count, tx_bd_count; 255 256 u16 msg_enable; 257 int active_offloads; 258 259 u32 speed; /* store speed for compare update pspeed */ 260 261 struct enetc_bdr *tx_ring[16]; 262 struct enetc_bdr *rx_ring[16]; 263 264 struct enetc_cls_rule *cls_rules; 265 266 struct psfp_cap psfp_cap; 267 268 struct phylink *phylink; 269 int ic_mode; 270 u32 tx_ictt; 271}; 272 273/* Messaging */ 274 275/* VF-PF set primary MAC address message format */ 276struct enetc_msg_cmd_set_primary_mac { 277 struct enetc_msg_cmd_header header; 278 struct sockaddr mac; 279}; 280 281#define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i])) 282 283#define ENETC_CBDR_TIMEOUT 1000 /* usecs */ 284 285/* PTP driver exports */ 286extern int enetc_phc_index; 287 288/* SI common */ 289int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv); 290void enetc_pci_remove(struct pci_dev *pdev); 291int enetc_alloc_msix(struct enetc_ndev_priv *priv); 292void enetc_free_msix(struct enetc_ndev_priv *priv); 293void enetc_get_si_caps(struct enetc_si *si); 294void enetc_init_si_rings_params(struct enetc_ndev_priv *priv); 295int enetc_alloc_si_resources(struct enetc_ndev_priv *priv); 296void enetc_free_si_resources(struct enetc_ndev_priv *priv); 297int enetc_configure_si(struct enetc_ndev_priv *priv); 298 299int enetc_open(struct net_device *ndev); 300int enetc_close(struct net_device *ndev); 301void enetc_start(struct net_device *ndev); 302void enetc_stop(struct net_device *ndev); 303netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev); 304struct net_device_stats *enetc_get_stats(struct net_device *ndev); 305void enetc_set_features(struct net_device *ndev, netdev_features_t features); 306int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd); 307int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type, 308 void *type_data); 309 310/* ethtool */ 311void enetc_set_ethtool_ops(struct net_device *ndev); 312 313/* control buffer descriptor ring (CBDR) */ 314int enetc_alloc_cbdr(struct device *dev, struct enetc_cbdr *cbdr); 315void enetc_free_cbdr(struct device *dev, struct enetc_cbdr *cbdr); 316void enetc_setup_cbdr(struct enetc_hw *hw, struct enetc_cbdr *cbdr); 317void enetc_clear_cbdr(struct enetc_hw *hw); 318int enetc_set_mac_flt_entry(struct enetc_si *si, int index, 319 char *mac_addr, int si_map); 320int enetc_clear_mac_flt_entry(struct enetc_si *si, int index); 321int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, 322 int index); 323void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes); 324int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count); 325int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count); 326int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd); 327 328#ifdef CONFIG_FSL_ENETC_QOS 329int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data); 330void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed); 331int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data); 332int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data); 333int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 334 void *cb_priv); 335int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data); 336int enetc_psfp_init(struct enetc_ndev_priv *priv); 337int enetc_psfp_clean(struct enetc_ndev_priv *priv); 338int enetc_set_psfp(struct net_device *ndev, bool en); 339 340static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv) 341{ 342 struct enetc_hw *hw = &priv->si->hw; 343 u32 reg; 344 345 reg = enetc_port_rd(hw, ENETC_PSIDCAPR); 346 priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK; 347 /* Port stream filter capability */ 348 reg = enetc_port_rd(hw, ENETC_PSFCAPR); 349 priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK; 350 /* Port stream gate capability */ 351 reg = enetc_port_rd(hw, ENETC_PSGCAPR); 352 priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK); 353 priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16; 354 /* Port flow meter capability */ 355 reg = enetc_port_rd(hw, ENETC_PFMCAPR); 356 priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK; 357} 358 359static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 360{ 361 struct enetc_hw *hw = &priv->si->hw; 362 int err; 363 364 enetc_get_max_cap(priv); 365 366 err = enetc_psfp_init(priv); 367 if (err) 368 return err; 369 370 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) | 371 ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS | 372 ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC); 373 374 return 0; 375} 376 377static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 378{ 379 struct enetc_hw *hw = &priv->si->hw; 380 int err; 381 382 err = enetc_psfp_clean(priv); 383 if (err) 384 return err; 385 386 enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) & 387 ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS & 388 ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC); 389 390 memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap)); 391 392 return 0; 393} 394 395#else 396#define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP 397#define enetc_sched_speed_set(priv, speed) (void)0 398#define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP 399#define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP 400#define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP 401#define enetc_setup_tc_block_cb NULL 402 403#define enetc_get_max_cap(p) \ 404 memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap)) 405 406static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 407{ 408 return 0; 409} 410 411static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 412{ 413 return 0; 414} 415 416static inline int enetc_set_psfp(struct net_device *ndev, bool en) 417{ 418 return 0; 419} 420#endif 421