1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* Copyright 2014-2016 Freescale Semiconductor Inc. 3 * Copyright 2016-2020 NXP 4 */ 5#include <linux/init.h> 6#include <linux/module.h> 7#include <linux/platform_device.h> 8#include <linux/etherdevice.h> 9#include <linux/of_net.h> 10#include <linux/interrupt.h> 11#include <linux/msi.h> 12#include <linux/kthread.h> 13#include <linux/iommu.h> 14#include <linux/fsl/mc.h> 15#include <linux/bpf.h> 16#include <linux/bpf_trace.h> 17#include <linux/fsl/ptp_qoriq.h> 18#include <linux/ptp_classify.h> 19#include <net/pkt_cls.h> 20#include <net/sock.h> 21 22#include "dpaa2-eth.h" 23 24/* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files 25 * using trace events only need to #include <trace/events/sched.h> 26 */ 27#define CREATE_TRACE_POINTS 28#include "dpaa2-eth-trace.h" 29 30MODULE_LICENSE("Dual BSD/GPL"); 31MODULE_AUTHOR("Freescale Semiconductor, Inc"); 32MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver"); 33 34struct ptp_qoriq *dpaa2_ptp; 35EXPORT_SYMBOL(dpaa2_ptp); 36 37static void *dpaa2_iova_to_virt(struct iommu_domain *domain, 38 dma_addr_t iova_addr) 39{ 40 phys_addr_t phys_addr; 41 42 phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr; 43 44 return phys_to_virt(phys_addr); 45} 46 47static void dpaa2_eth_validate_rx_csum(struct dpaa2_eth_priv *priv, 48 u32 fd_status, 49 struct sk_buff *skb) 50{ 51 skb_checksum_none_assert(skb); 52 53 /* HW checksum validation is disabled, nothing to do here */ 54 if (!(priv->net_dev->features & NETIF_F_RXCSUM)) 55 return; 56 57 /* Read checksum validation bits */ 58 if (!((fd_status & DPAA2_FAS_L3CV) && 59 (fd_status & DPAA2_FAS_L4CV))) 60 return; 61 62 /* Inform the stack there's no need to compute L3/L4 csum anymore */ 63 skb->ip_summed = CHECKSUM_UNNECESSARY; 64} 65 66/* Free a received FD. 67 * Not to be used for Tx conf FDs or on any other paths. 68 */ 69static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv, 70 const struct dpaa2_fd *fd, 71 void *vaddr) 72{ 73 struct device *dev = priv->net_dev->dev.parent; 74 dma_addr_t addr = dpaa2_fd_get_addr(fd); 75 u8 fd_format = dpaa2_fd_get_format(fd); 76 struct dpaa2_sg_entry *sgt; 77 void *sg_vaddr; 78 int i; 79 80 /* If single buffer frame, just free the data buffer */ 81 if (fd_format == dpaa2_fd_single) 82 goto free_buf; 83 else if (fd_format != dpaa2_fd_sg) 84 /* We don't support any other format */ 85 return; 86 87 /* For S/G frames, we first need to free all SG entries 88 * except the first one, which was taken care of already 89 */ 90 sgt = vaddr + dpaa2_fd_get_offset(fd); 91 for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { 92 addr = dpaa2_sg_get_addr(&sgt[i]); 93 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); 94 dma_unmap_page(dev, addr, priv->rx_buf_size, 95 DMA_BIDIRECTIONAL); 96 97 free_pages((unsigned long)sg_vaddr, 0); 98 if (dpaa2_sg_is_final(&sgt[i])) 99 break; 100 } 101 102free_buf: 103 free_pages((unsigned long)vaddr, 0); 104} 105 106/* Build a linear skb based on a single-buffer frame descriptor */ 107static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_channel *ch, 108 const struct dpaa2_fd *fd, 109 void *fd_vaddr) 110{ 111 struct sk_buff *skb = NULL; 112 u16 fd_offset = dpaa2_fd_get_offset(fd); 113 u32 fd_length = dpaa2_fd_get_len(fd); 114 115 ch->buf_count--; 116 117 skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE); 118 if (unlikely(!skb)) 119 return NULL; 120 121 skb_reserve(skb, fd_offset); 122 skb_put(skb, fd_length); 123 124 return skb; 125} 126 127/* Build a non linear (fragmented) skb based on a S/G table */ 128static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv, 129 struct dpaa2_eth_channel *ch, 130 struct dpaa2_sg_entry *sgt) 131{ 132 struct sk_buff *skb = NULL; 133 struct device *dev = priv->net_dev->dev.parent; 134 void *sg_vaddr; 135 dma_addr_t sg_addr; 136 u16 sg_offset; 137 u32 sg_length; 138 struct page *page, *head_page; 139 int page_offset; 140 int i; 141 142 for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { 143 struct dpaa2_sg_entry *sge = &sgt[i]; 144 145 /* NOTE: We only support SG entries in dpaa2_sg_single format, 146 * but this is the only format we may receive from HW anyway 147 */ 148 149 /* Get the address and length from the S/G entry */ 150 sg_addr = dpaa2_sg_get_addr(sge); 151 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr); 152 dma_unmap_page(dev, sg_addr, priv->rx_buf_size, 153 DMA_BIDIRECTIONAL); 154 155 sg_length = dpaa2_sg_get_len(sge); 156 157 if (i == 0) { 158 /* We build the skb around the first data buffer */ 159 skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE); 160 if (unlikely(!skb)) { 161 /* Free the first SG entry now, since we already 162 * unmapped it and obtained the virtual address 163 */ 164 free_pages((unsigned long)sg_vaddr, 0); 165 166 /* We still need to subtract the buffers used 167 * by this FD from our software counter 168 */ 169 while (!dpaa2_sg_is_final(&sgt[i]) && 170 i < DPAA2_ETH_MAX_SG_ENTRIES) 171 i++; 172 break; 173 } 174 175 sg_offset = dpaa2_sg_get_offset(sge); 176 skb_reserve(skb, sg_offset); 177 skb_put(skb, sg_length); 178 } else { 179 /* Rest of the data buffers are stored as skb frags */ 180 page = virt_to_page(sg_vaddr); 181 head_page = virt_to_head_page(sg_vaddr); 182 183 /* Offset in page (which may be compound). 184 * Data in subsequent SG entries is stored from the 185 * beginning of the buffer, so we don't need to add the 186 * sg_offset. 187 */ 188 page_offset = ((unsigned long)sg_vaddr & 189 (PAGE_SIZE - 1)) + 190 (page_address(page) - page_address(head_page)); 191 192 skb_add_rx_frag(skb, i - 1, head_page, page_offset, 193 sg_length, priv->rx_buf_size); 194 } 195 196 if (dpaa2_sg_is_final(sge)) 197 break; 198 } 199 200 WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT"); 201 202 /* Count all data buffers + SG table buffer */ 203 ch->buf_count -= i + 2; 204 205 return skb; 206} 207 208/* Free buffers acquired from the buffer pool or which were meant to 209 * be released in the pool 210 */ 211static void dpaa2_eth_free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, 212 int count) 213{ 214 struct device *dev = priv->net_dev->dev.parent; 215 void *vaddr; 216 int i; 217 218 for (i = 0; i < count; i++) { 219 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]); 220 dma_unmap_page(dev, buf_array[i], priv->rx_buf_size, 221 DMA_BIDIRECTIONAL); 222 free_pages((unsigned long)vaddr, 0); 223 } 224} 225 226static void dpaa2_eth_xdp_release_buf(struct dpaa2_eth_priv *priv, 227 struct dpaa2_eth_channel *ch, 228 dma_addr_t addr) 229{ 230 int retries = 0; 231 int err; 232 233 ch->xdp.drop_bufs[ch->xdp.drop_cnt++] = addr; 234 if (ch->xdp.drop_cnt < DPAA2_ETH_BUFS_PER_CMD) 235 return; 236 237 while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid, 238 ch->xdp.drop_bufs, 239 ch->xdp.drop_cnt)) == -EBUSY) { 240 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) 241 break; 242 cpu_relax(); 243 } 244 245 if (err) { 246 dpaa2_eth_free_bufs(priv, ch->xdp.drop_bufs, ch->xdp.drop_cnt); 247 ch->buf_count -= ch->xdp.drop_cnt; 248 } 249 250 ch->xdp.drop_cnt = 0; 251} 252 253static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv, 254 struct dpaa2_eth_fq *fq, 255 struct dpaa2_eth_xdp_fds *xdp_fds) 256{ 257 int total_enqueued = 0, retries = 0, enqueued; 258 struct dpaa2_eth_drv_stats *percpu_extras; 259 int num_fds, err, max_retries; 260 struct dpaa2_fd *fds; 261 262 percpu_extras = this_cpu_ptr(priv->percpu_extras); 263 264 /* try to enqueue all the FDs until the max number of retries is hit */ 265 fds = xdp_fds->fds; 266 num_fds = xdp_fds->num; 267 max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES; 268 while (total_enqueued < num_fds && retries < max_retries) { 269 err = priv->enqueue(priv, fq, &fds[total_enqueued], 270 0, num_fds - total_enqueued, &enqueued); 271 if (err == -EBUSY) { 272 percpu_extras->tx_portal_busy += ++retries; 273 continue; 274 } 275 total_enqueued += enqueued; 276 } 277 xdp_fds->num = 0; 278 279 return total_enqueued; 280} 281 282static void dpaa2_eth_xdp_tx_flush(struct dpaa2_eth_priv *priv, 283 struct dpaa2_eth_channel *ch, 284 struct dpaa2_eth_fq *fq) 285{ 286 struct rtnl_link_stats64 *percpu_stats; 287 struct dpaa2_fd *fds; 288 int enqueued, i; 289 290 percpu_stats = this_cpu_ptr(priv->percpu_stats); 291 292 // enqueue the array of XDP_TX frames 293 enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds); 294 295 /* update statistics */ 296 percpu_stats->tx_packets += enqueued; 297 fds = fq->xdp_tx_fds.fds; 298 for (i = 0; i < enqueued; i++) { 299 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]); 300 ch->stats.xdp_tx++; 301 } 302 for (i = enqueued; i < fq->xdp_tx_fds.num; i++) { 303 dpaa2_eth_xdp_release_buf(priv, ch, dpaa2_fd_get_addr(&fds[i])); 304 percpu_stats->tx_errors++; 305 ch->stats.xdp_tx_err++; 306 } 307 fq->xdp_tx_fds.num = 0; 308} 309 310static void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv, 311 struct dpaa2_eth_channel *ch, 312 struct dpaa2_fd *fd, 313 void *buf_start, u16 queue_id) 314{ 315 struct dpaa2_faead *faead; 316 struct dpaa2_fd *dest_fd; 317 struct dpaa2_eth_fq *fq; 318 u32 ctrl, frc; 319 320 /* Mark the egress frame hardware annotation area as valid */ 321 frc = dpaa2_fd_get_frc(fd); 322 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV); 323 dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL); 324 325 /* Instruct hardware to release the FD buffer directly into 326 * the buffer pool once transmission is completed, instead of 327 * sending a Tx confirmation frame to us 328 */ 329 ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV; 330 faead = dpaa2_get_faead(buf_start, false); 331 faead->ctrl = cpu_to_le32(ctrl); 332 faead->conf_fqid = 0; 333 334 fq = &priv->fq[queue_id]; 335 dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++]; 336 memcpy(dest_fd, fd, sizeof(*dest_fd)); 337 338 if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE) 339 return; 340 341 dpaa2_eth_xdp_tx_flush(priv, ch, fq); 342} 343 344static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv, 345 struct dpaa2_eth_channel *ch, 346 struct dpaa2_eth_fq *rx_fq, 347 struct dpaa2_fd *fd, void *vaddr) 348{ 349 dma_addr_t addr = dpaa2_fd_get_addr(fd); 350 struct bpf_prog *xdp_prog; 351 struct xdp_buff xdp; 352 u32 xdp_act = XDP_PASS; 353 int err; 354 355 rcu_read_lock(); 356 357 xdp_prog = READ_ONCE(ch->xdp.prog); 358 if (!xdp_prog) 359 goto out; 360 361 xdp.data = vaddr + dpaa2_fd_get_offset(fd); 362 xdp.data_end = xdp.data + dpaa2_fd_get_len(fd); 363 xdp.data_hard_start = xdp.data - XDP_PACKET_HEADROOM; 364 xdp_set_data_meta_invalid(&xdp); 365 xdp.rxq = &ch->xdp_rxq; 366 367 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE - 368 (dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM); 369 370 xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp); 371 372 /* xdp.data pointer may have changed */ 373 dpaa2_fd_set_offset(fd, xdp.data - vaddr); 374 dpaa2_fd_set_len(fd, xdp.data_end - xdp.data); 375 376 switch (xdp_act) { 377 case XDP_PASS: 378 break; 379 case XDP_TX: 380 dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid); 381 break; 382 default: 383 bpf_warn_invalid_xdp_action(xdp_act); 384 fallthrough; 385 case XDP_ABORTED: 386 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act); 387 fallthrough; 388 case XDP_DROP: 389 dpaa2_eth_xdp_release_buf(priv, ch, addr); 390 ch->stats.xdp_drop++; 391 break; 392 case XDP_REDIRECT: 393 dma_unmap_page(priv->net_dev->dev.parent, addr, 394 priv->rx_buf_size, DMA_BIDIRECTIONAL); 395 ch->buf_count--; 396 397 /* Allow redirect use of full headroom */ 398 xdp.data_hard_start = vaddr; 399 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE; 400 401 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog); 402 if (unlikely(err)) { 403 addr = dma_map_page(priv->net_dev->dev.parent, 404 virt_to_page(vaddr), 0, 405 priv->rx_buf_size, DMA_BIDIRECTIONAL); 406 if (unlikely(dma_mapping_error(priv->net_dev->dev.parent, addr))) { 407 free_pages((unsigned long)vaddr, 0); 408 } else { 409 ch->buf_count++; 410 dpaa2_eth_xdp_release_buf(priv, ch, addr); 411 } 412 ch->stats.xdp_drop++; 413 } else { 414 ch->stats.xdp_redirect++; 415 } 416 break; 417 } 418 419 ch->xdp.res |= xdp_act; 420out: 421 rcu_read_unlock(); 422 return xdp_act; 423} 424 425/* Main Rx frame processing routine */ 426static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, 427 struct dpaa2_eth_channel *ch, 428 const struct dpaa2_fd *fd, 429 struct dpaa2_eth_fq *fq) 430{ 431 dma_addr_t addr = dpaa2_fd_get_addr(fd); 432 u8 fd_format = dpaa2_fd_get_format(fd); 433 void *vaddr; 434 struct sk_buff *skb; 435 struct rtnl_link_stats64 *percpu_stats; 436 struct dpaa2_eth_drv_stats *percpu_extras; 437 struct device *dev = priv->net_dev->dev.parent; 438 struct dpaa2_fas *fas; 439 void *buf_data; 440 u32 status = 0; 441 u32 xdp_act; 442 443 /* Tracing point */ 444 trace_dpaa2_rx_fd(priv->net_dev, fd); 445 446 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); 447 dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size, 448 DMA_BIDIRECTIONAL); 449 450 fas = dpaa2_get_fas(vaddr, false); 451 prefetch(fas); 452 buf_data = vaddr + dpaa2_fd_get_offset(fd); 453 prefetch(buf_data); 454 455 percpu_stats = this_cpu_ptr(priv->percpu_stats); 456 percpu_extras = this_cpu_ptr(priv->percpu_extras); 457 458 if (fd_format == dpaa2_fd_single) { 459 xdp_act = dpaa2_eth_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr); 460 if (xdp_act != XDP_PASS) { 461 percpu_stats->rx_packets++; 462 percpu_stats->rx_bytes += dpaa2_fd_get_len(fd); 463 return; 464 } 465 466 dma_unmap_page(dev, addr, priv->rx_buf_size, 467 DMA_BIDIRECTIONAL); 468 skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr); 469 } else if (fd_format == dpaa2_fd_sg) { 470 WARN_ON(priv->xdp_prog); 471 472 dma_unmap_page(dev, addr, priv->rx_buf_size, 473 DMA_BIDIRECTIONAL); 474 skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data); 475 free_pages((unsigned long)vaddr, 0); 476 percpu_extras->rx_sg_frames++; 477 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd); 478 } else { 479 /* We don't support any other format */ 480 goto err_frame_format; 481 } 482 483 if (unlikely(!skb)) 484 goto err_build_skb; 485 486 prefetch(skb->data); 487 488 /* Get the timestamp value */ 489 if (priv->rx_tstamp) { 490 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 491 __le64 *ts = dpaa2_get_ts(vaddr, false); 492 u64 ns; 493 494 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 495 496 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts); 497 shhwtstamps->hwtstamp = ns_to_ktime(ns); 498 } 499 500 /* Check if we need to validate the L4 csum */ 501 if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) { 502 status = le32_to_cpu(fas->status); 503 dpaa2_eth_validate_rx_csum(priv, status, skb); 504 } 505 506 skb->protocol = eth_type_trans(skb, priv->net_dev); 507 skb_record_rx_queue(skb, fq->flowid); 508 509 percpu_stats->rx_packets++; 510 percpu_stats->rx_bytes += dpaa2_fd_get_len(fd); 511 512 list_add_tail(&skb->list, ch->rx_list); 513 514 return; 515 516err_build_skb: 517 dpaa2_eth_free_rx_fd(priv, fd, vaddr); 518err_frame_format: 519 percpu_stats->rx_dropped++; 520} 521 522/* Processing of Rx frames received on the error FQ 523 * We check and print the error bits and then free the frame 524 */ 525static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv, 526 struct dpaa2_eth_channel *ch, 527 const struct dpaa2_fd *fd, 528 struct dpaa2_eth_fq *fq __always_unused) 529{ 530 struct device *dev = priv->net_dev->dev.parent; 531 dma_addr_t addr = dpaa2_fd_get_addr(fd); 532 u8 fd_format = dpaa2_fd_get_format(fd); 533 struct rtnl_link_stats64 *percpu_stats; 534 struct dpaa2_eth_trap_item *trap_item; 535 struct dpaa2_fapr *fapr; 536 struct sk_buff *skb; 537 void *buf_data; 538 void *vaddr; 539 540 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); 541 dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size, 542 DMA_BIDIRECTIONAL); 543 544 buf_data = vaddr + dpaa2_fd_get_offset(fd); 545 546 if (fd_format == dpaa2_fd_single) { 547 dma_unmap_page(dev, addr, priv->rx_buf_size, 548 DMA_BIDIRECTIONAL); 549 skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr); 550 } else if (fd_format == dpaa2_fd_sg) { 551 dma_unmap_page(dev, addr, priv->rx_buf_size, 552 DMA_BIDIRECTIONAL); 553 skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data); 554 free_pages((unsigned long)vaddr, 0); 555 } else { 556 /* We don't support any other format */ 557 dpaa2_eth_free_rx_fd(priv, fd, vaddr); 558 goto err_frame_format; 559 } 560 561 fapr = dpaa2_get_fapr(vaddr, false); 562 trap_item = dpaa2_eth_dl_get_trap(priv, fapr); 563 if (trap_item) 564 devlink_trap_report(priv->devlink, skb, trap_item->trap_ctx, 565 &priv->devlink_port, NULL); 566 consume_skb(skb); 567 568err_frame_format: 569 percpu_stats = this_cpu_ptr(priv->percpu_stats); 570 percpu_stats->rx_errors++; 571 ch->buf_count--; 572} 573 574/* Consume all frames pull-dequeued into the store. This is the simplest way to 575 * make sure we don't accidentally issue another volatile dequeue which would 576 * overwrite (leak) frames already in the store. 577 * 578 * Observance of NAPI budget is not our concern, leaving that to the caller. 579 */ 580static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch, 581 struct dpaa2_eth_fq **src) 582{ 583 struct dpaa2_eth_priv *priv = ch->priv; 584 struct dpaa2_eth_fq *fq = NULL; 585 struct dpaa2_dq *dq; 586 const struct dpaa2_fd *fd; 587 int cleaned = 0, retries = 0; 588 int is_last; 589 590 do { 591 dq = dpaa2_io_store_next(ch->store, &is_last); 592 if (unlikely(!dq)) { 593 /* If we're here, we *must* have placed a 594 * volatile dequeue comnmand, so keep reading through 595 * the store until we get some sort of valid response 596 * token (either a valid frame or an "empty dequeue") 597 */ 598 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) { 599 netdev_err_once(priv->net_dev, 600 "Unable to read a valid dequeue response\n"); 601 return -ETIMEDOUT; 602 } 603 continue; 604 } 605 606 fd = dpaa2_dq_fd(dq); 607 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq); 608 609 fq->consume(priv, ch, fd, fq); 610 cleaned++; 611 retries = 0; 612 } while (!is_last); 613 614 if (!cleaned) 615 return 0; 616 617 fq->stats.frames += cleaned; 618 ch->stats.frames += cleaned; 619 620 /* A dequeue operation only pulls frames from a single queue 621 * into the store. Return the frame queue as an out param. 622 */ 623 if (src) 624 *src = fq; 625 626 return cleaned; 627} 628 629static int dpaa2_eth_ptp_parse(struct sk_buff *skb, 630 u8 *msgtype, u8 *twostep, u8 *udp, 631 u16 *correction_offset, 632 u16 *origintimestamp_offset) 633{ 634 unsigned int ptp_class; 635 struct ptp_header *hdr; 636 unsigned int type; 637 u8 *base; 638 639 ptp_class = ptp_classify_raw(skb); 640 if (ptp_class == PTP_CLASS_NONE) 641 return -EINVAL; 642 643 hdr = ptp_parse_header(skb, ptp_class); 644 if (!hdr) 645 return -EINVAL; 646 647 *msgtype = ptp_get_msgtype(hdr, ptp_class); 648 *twostep = hdr->flag_field[0] & 0x2; 649 650 type = ptp_class & PTP_CLASS_PMASK; 651 if (type == PTP_CLASS_IPV4 || 652 type == PTP_CLASS_IPV6) 653 *udp = 1; 654 else 655 *udp = 0; 656 657 base = skb_mac_header(skb); 658 *correction_offset = (u8 *)&hdr->correction - base; 659 *origintimestamp_offset = (u8 *)hdr + sizeof(struct ptp_header) - base; 660 661 return 0; 662} 663 664/* Configure the egress frame annotation for timestamp update */ 665static void dpaa2_eth_enable_tx_tstamp(struct dpaa2_eth_priv *priv, 666 struct dpaa2_fd *fd, 667 void *buf_start, 668 struct sk_buff *skb) 669{ 670 struct ptp_tstamp origin_timestamp; 671 struct dpni_single_step_cfg cfg; 672 u8 msgtype, twostep, udp; 673 struct dpaa2_faead *faead; 674 struct dpaa2_fas *fas; 675 struct timespec64 ts; 676 u16 offset1, offset2; 677 u32 ctrl, frc; 678 __le64 *ns; 679 u8 *data; 680 681 /* Mark the egress frame annotation area as valid */ 682 frc = dpaa2_fd_get_frc(fd); 683 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV); 684 685 /* Set hardware annotation size */ 686 ctrl = dpaa2_fd_get_ctrl(fd); 687 dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL); 688 689 /* enable UPD (update prepanded data) bit in FAEAD field of 690 * hardware frame annotation area 691 */ 692 ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD; 693 faead = dpaa2_get_faead(buf_start, true); 694 faead->ctrl = cpu_to_le32(ctrl); 695 696 if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) { 697 if (dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp, 698 &offset1, &offset2) || 699 msgtype != 0 || twostep) { 700 WARN_ONCE(1, "Bad packet for one-step timestamping\n"); 701 return; 702 } 703 704 /* Mark the frame annotation status as valid */ 705 frc = dpaa2_fd_get_frc(fd); 706 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FASV); 707 708 /* Mark the PTP flag for one step timestamping */ 709 fas = dpaa2_get_fas(buf_start, true); 710 fas->status = cpu_to_le32(DPAA2_FAS_PTP); 711 712 dpaa2_ptp->caps.gettime64(&dpaa2_ptp->caps, &ts); 713 ns = dpaa2_get_ts(buf_start, true); 714 *ns = cpu_to_le64(timespec64_to_ns(&ts) / 715 DPAA2_PTP_CLK_PERIOD_NS); 716 717 /* Update current time to PTP message originTimestamp field */ 718 ns_to_ptp_tstamp(&origin_timestamp, le64_to_cpup(ns)); 719 data = skb_mac_header(skb); 720 *(__be16 *)(data + offset2) = htons(origin_timestamp.sec_msb); 721 *(__be32 *)(data + offset2 + 2) = 722 htonl(origin_timestamp.sec_lsb); 723 *(__be32 *)(data + offset2 + 6) = htonl(origin_timestamp.nsec); 724 725 cfg.en = 1; 726 cfg.ch_update = udp; 727 cfg.offset = offset1; 728 cfg.peer_delay = 0; 729 730 if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token, 731 &cfg)) 732 WARN_ONCE(1, "Failed to set single step register"); 733 } 734} 735 736/* Create a frame descriptor based on a fragmented skb */ 737static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv, 738 struct sk_buff *skb, 739 struct dpaa2_fd *fd, 740 void **swa_addr) 741{ 742 struct device *dev = priv->net_dev->dev.parent; 743 void *sgt_buf = NULL; 744 dma_addr_t addr; 745 int nr_frags = skb_shinfo(skb)->nr_frags; 746 struct dpaa2_sg_entry *sgt; 747 int i, err; 748 int sgt_buf_size; 749 struct scatterlist *scl, *crt_scl; 750 int num_sg; 751 int num_dma_bufs; 752 struct dpaa2_eth_swa *swa; 753 754 /* Create and map scatterlist. 755 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have 756 * to go beyond nr_frags+1. 757 * Note: We don't support chained scatterlists 758 */ 759 if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1)) 760 return -EINVAL; 761 762 scl = kmalloc_array(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC); 763 if (unlikely(!scl)) 764 return -ENOMEM; 765 766 sg_init_table(scl, nr_frags + 1); 767 num_sg = skb_to_sgvec(skb, scl, 0, skb->len); 768 if (unlikely(num_sg < 0)) { 769 err = -ENOMEM; 770 goto dma_map_sg_failed; 771 } 772 num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL); 773 if (unlikely(!num_dma_bufs)) { 774 err = -ENOMEM; 775 goto dma_map_sg_failed; 776 } 777 778 /* Prepare the HW SGT structure */ 779 sgt_buf_size = priv->tx_data_offset + 780 sizeof(struct dpaa2_sg_entry) * num_dma_bufs; 781 sgt_buf = napi_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN); 782 if (unlikely(!sgt_buf)) { 783 err = -ENOMEM; 784 goto sgt_buf_alloc_failed; 785 } 786 sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN); 787 memset(sgt_buf, 0, sgt_buf_size); 788 789 sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset); 790 791 /* Fill in the HW SGT structure. 792 * 793 * sgt_buf is zeroed out, so the following fields are implicit 794 * in all sgt entries: 795 * - offset is 0 796 * - format is 'dpaa2_sg_single' 797 */ 798 for_each_sg(scl, crt_scl, num_dma_bufs, i) { 799 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl)); 800 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl)); 801 } 802 dpaa2_sg_set_final(&sgt[i - 1], true); 803 804 /* Store the skb backpointer in the SGT buffer. 805 * Fit the scatterlist and the number of buffers alongside the 806 * skb backpointer in the software annotation area. We'll need 807 * all of them on Tx Conf. 808 */ 809 *swa_addr = (void *)sgt_buf; 810 swa = (struct dpaa2_eth_swa *)sgt_buf; 811 swa->type = DPAA2_ETH_SWA_SG; 812 swa->sg.skb = skb; 813 swa->sg.scl = scl; 814 swa->sg.num_sg = num_sg; 815 swa->sg.sgt_size = sgt_buf_size; 816 817 /* Separately map the SGT buffer */ 818 addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL); 819 if (unlikely(dma_mapping_error(dev, addr))) { 820 err = -ENOMEM; 821 goto dma_map_single_failed; 822 } 823 dpaa2_fd_set_offset(fd, priv->tx_data_offset); 824 dpaa2_fd_set_format(fd, dpaa2_fd_sg); 825 dpaa2_fd_set_addr(fd, addr); 826 dpaa2_fd_set_len(fd, skb->len); 827 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA); 828 829 return 0; 830 831dma_map_single_failed: 832 skb_free_frag(sgt_buf); 833sgt_buf_alloc_failed: 834 dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL); 835dma_map_sg_failed: 836 kfree(scl); 837 return err; 838} 839 840/* Create a SG frame descriptor based on a linear skb. 841 * 842 * This function is used on the Tx path when the skb headroom is not large 843 * enough for the HW requirements, thus instead of realloc-ing the skb we 844 * create a SG frame descriptor with only one entry. 845 */ 846static int dpaa2_eth_build_sg_fd_single_buf(struct dpaa2_eth_priv *priv, 847 struct sk_buff *skb, 848 struct dpaa2_fd *fd, 849 void **swa_addr) 850{ 851 struct device *dev = priv->net_dev->dev.parent; 852 struct dpaa2_eth_sgt_cache *sgt_cache; 853 struct dpaa2_sg_entry *sgt; 854 struct dpaa2_eth_swa *swa; 855 dma_addr_t addr, sgt_addr; 856 void *sgt_buf = NULL; 857 int sgt_buf_size; 858 int err; 859 860 /* Prepare the HW SGT structure */ 861 sgt_cache = this_cpu_ptr(priv->sgt_cache); 862 sgt_buf_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry); 863 864 if (sgt_cache->count == 0) 865 sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN, 866 GFP_ATOMIC); 867 else 868 sgt_buf = sgt_cache->buf[--sgt_cache->count]; 869 if (unlikely(!sgt_buf)) 870 return -ENOMEM; 871 872 sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN); 873 sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset); 874 875 addr = dma_map_single(dev, skb->data, skb->len, DMA_BIDIRECTIONAL); 876 if (unlikely(dma_mapping_error(dev, addr))) { 877 err = -ENOMEM; 878 goto data_map_failed; 879 } 880 881 /* Fill in the HW SGT structure */ 882 dpaa2_sg_set_addr(sgt, addr); 883 dpaa2_sg_set_len(sgt, skb->len); 884 dpaa2_sg_set_final(sgt, true); 885 886 /* Store the skb backpointer in the SGT buffer */ 887 *swa_addr = (void *)sgt_buf; 888 swa = (struct dpaa2_eth_swa *)sgt_buf; 889 swa->type = DPAA2_ETH_SWA_SINGLE; 890 swa->single.skb = skb; 891 swa->single.sgt_size = sgt_buf_size; 892 893 /* Separately map the SGT buffer */ 894 sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL); 895 if (unlikely(dma_mapping_error(dev, sgt_addr))) { 896 err = -ENOMEM; 897 goto sgt_map_failed; 898 } 899 900 dpaa2_fd_set_offset(fd, priv->tx_data_offset); 901 dpaa2_fd_set_format(fd, dpaa2_fd_sg); 902 dpaa2_fd_set_addr(fd, sgt_addr); 903 dpaa2_fd_set_len(fd, skb->len); 904 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA); 905 906 return 0; 907 908sgt_map_failed: 909 dma_unmap_single(dev, addr, skb->len, DMA_BIDIRECTIONAL); 910data_map_failed: 911 if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE) 912 kfree(sgt_buf); 913 else 914 sgt_cache->buf[sgt_cache->count++] = sgt_buf; 915 916 return err; 917} 918 919/* Create a frame descriptor based on a linear skb */ 920static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv, 921 struct sk_buff *skb, 922 struct dpaa2_fd *fd, 923 void **swa_addr) 924{ 925 struct device *dev = priv->net_dev->dev.parent; 926 u8 *buffer_start, *aligned_start; 927 struct dpaa2_eth_swa *swa; 928 dma_addr_t addr; 929 930 buffer_start = skb->data - dpaa2_eth_needed_headroom(skb); 931 aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN, 932 DPAA2_ETH_TX_BUF_ALIGN); 933 if (aligned_start >= skb->head) 934 buffer_start = aligned_start; 935 else 936 return -ENOMEM; 937 938 /* Store a backpointer to the skb at the beginning of the buffer 939 * (in the private data area) such that we can release it 940 * on Tx confirm 941 */ 942 *swa_addr = (void *)buffer_start; 943 swa = (struct dpaa2_eth_swa *)buffer_start; 944 swa->type = DPAA2_ETH_SWA_SINGLE; 945 swa->single.skb = skb; 946 947 addr = dma_map_single(dev, buffer_start, 948 skb_tail_pointer(skb) - buffer_start, 949 DMA_BIDIRECTIONAL); 950 if (unlikely(dma_mapping_error(dev, addr))) 951 return -ENOMEM; 952 953 dpaa2_fd_set_addr(fd, addr); 954 dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start)); 955 dpaa2_fd_set_len(fd, skb->len); 956 dpaa2_fd_set_format(fd, dpaa2_fd_single); 957 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA); 958 959 return 0; 960} 961 962/* FD freeing routine on the Tx path 963 * 964 * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb 965 * back-pointed to is also freed. 966 * This can be called either from dpaa2_eth_tx_conf() or on the error path of 967 * dpaa2_eth_tx(). 968 */ 969static void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv, 970 struct dpaa2_eth_fq *fq, 971 const struct dpaa2_fd *fd, bool in_napi) 972{ 973 struct device *dev = priv->net_dev->dev.parent; 974 dma_addr_t fd_addr, sg_addr; 975 struct sk_buff *skb = NULL; 976 unsigned char *buffer_start; 977 struct dpaa2_eth_swa *swa; 978 u8 fd_format = dpaa2_fd_get_format(fd); 979 u32 fd_len = dpaa2_fd_get_len(fd); 980 981 struct dpaa2_eth_sgt_cache *sgt_cache; 982 struct dpaa2_sg_entry *sgt; 983 984 fd_addr = dpaa2_fd_get_addr(fd); 985 buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr); 986 swa = (struct dpaa2_eth_swa *)buffer_start; 987 988 if (fd_format == dpaa2_fd_single) { 989 if (swa->type == DPAA2_ETH_SWA_SINGLE) { 990 skb = swa->single.skb; 991 /* Accessing the skb buffer is safe before dma unmap, 992 * because we didn't map the actual skb shell. 993 */ 994 dma_unmap_single(dev, fd_addr, 995 skb_tail_pointer(skb) - buffer_start, 996 DMA_BIDIRECTIONAL); 997 } else { 998 WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type"); 999 dma_unmap_single(dev, fd_addr, swa->xdp.dma_size, 1000 DMA_BIDIRECTIONAL); 1001 } 1002 } else if (fd_format == dpaa2_fd_sg) { 1003 if (swa->type == DPAA2_ETH_SWA_SG) { 1004 skb = swa->sg.skb; 1005 1006 /* Unmap the scatterlist */ 1007 dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg, 1008 DMA_BIDIRECTIONAL); 1009 kfree(swa->sg.scl); 1010 1011 /* Unmap the SGT buffer */ 1012 dma_unmap_single(dev, fd_addr, swa->sg.sgt_size, 1013 DMA_BIDIRECTIONAL); 1014 } else { 1015 skb = swa->single.skb; 1016 1017 /* Unmap the SGT Buffer */ 1018 dma_unmap_single(dev, fd_addr, swa->single.sgt_size, 1019 DMA_BIDIRECTIONAL); 1020 1021 sgt = (struct dpaa2_sg_entry *)(buffer_start + 1022 priv->tx_data_offset); 1023 sg_addr = dpaa2_sg_get_addr(sgt); 1024 dma_unmap_single(dev, sg_addr, skb->len, DMA_BIDIRECTIONAL); 1025 } 1026 } else { 1027 netdev_dbg(priv->net_dev, "Invalid FD format\n"); 1028 return; 1029 } 1030 1031 if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) { 1032 fq->dq_frames++; 1033 fq->dq_bytes += fd_len; 1034 } 1035 1036 if (swa->type == DPAA2_ETH_SWA_XDP) { 1037 xdp_return_frame(swa->xdp.xdpf); 1038 return; 1039 } 1040 1041 /* Get the timestamp value */ 1042 if (skb->cb[0] == TX_TSTAMP) { 1043 struct skb_shared_hwtstamps shhwtstamps; 1044 __le64 *ts = dpaa2_get_ts(buffer_start, true); 1045 u64 ns; 1046 1047 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1048 1049 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts); 1050 shhwtstamps.hwtstamp = ns_to_ktime(ns); 1051 skb_tstamp_tx(skb, &shhwtstamps); 1052 } else if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) { 1053 mutex_unlock(&priv->onestep_tstamp_lock); 1054 } 1055 1056 /* Free SGT buffer allocated on tx */ 1057 if (fd_format != dpaa2_fd_single) { 1058 sgt_cache = this_cpu_ptr(priv->sgt_cache); 1059 if (swa->type == DPAA2_ETH_SWA_SG) { 1060 skb_free_frag(buffer_start); 1061 } else { 1062 if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE) 1063 kfree(buffer_start); 1064 else 1065 sgt_cache->buf[sgt_cache->count++] = buffer_start; 1066 } 1067 } 1068 1069 /* Move on with skb release */ 1070 napi_consume_skb(skb, in_napi); 1071} 1072 1073static netdev_tx_t __dpaa2_eth_tx(struct sk_buff *skb, 1074 struct net_device *net_dev) 1075{ 1076 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1077 struct dpaa2_fd fd; 1078 struct rtnl_link_stats64 *percpu_stats; 1079 struct dpaa2_eth_drv_stats *percpu_extras; 1080 struct dpaa2_eth_fq *fq; 1081 struct netdev_queue *nq; 1082 u16 queue_mapping; 1083 unsigned int needed_headroom; 1084 u32 fd_len; 1085 u8 prio = 0; 1086 int err, i; 1087 void *swa; 1088 1089 percpu_stats = this_cpu_ptr(priv->percpu_stats); 1090 percpu_extras = this_cpu_ptr(priv->percpu_extras); 1091 1092 needed_headroom = dpaa2_eth_needed_headroom(skb); 1093 1094 /* We'll be holding a back-reference to the skb until Tx Confirmation; 1095 * we don't want that overwritten by a concurrent Tx with a cloned skb. 1096 */ 1097 skb = skb_unshare(skb, GFP_ATOMIC); 1098 if (unlikely(!skb)) { 1099 /* skb_unshare() has already freed the skb */ 1100 percpu_stats->tx_dropped++; 1101 return NETDEV_TX_OK; 1102 } 1103 1104 /* Setup the FD fields */ 1105 memset(&fd, 0, sizeof(fd)); 1106 1107 if (skb_is_nonlinear(skb)) { 1108 err = dpaa2_eth_build_sg_fd(priv, skb, &fd, &swa); 1109 percpu_extras->tx_sg_frames++; 1110 percpu_extras->tx_sg_bytes += skb->len; 1111 } else if (skb_headroom(skb) < needed_headroom) { 1112 err = dpaa2_eth_build_sg_fd_single_buf(priv, skb, &fd, &swa); 1113 percpu_extras->tx_sg_frames++; 1114 percpu_extras->tx_sg_bytes += skb->len; 1115 percpu_extras->tx_converted_sg_frames++; 1116 percpu_extras->tx_converted_sg_bytes += skb->len; 1117 } else { 1118 err = dpaa2_eth_build_single_fd(priv, skb, &fd, &swa); 1119 } 1120 1121 if (unlikely(err)) { 1122 percpu_stats->tx_dropped++; 1123 goto err_build_fd; 1124 } 1125 1126 if (skb->cb[0]) 1127 dpaa2_eth_enable_tx_tstamp(priv, &fd, swa, skb); 1128 1129 /* Tracing point */ 1130 trace_dpaa2_tx_fd(net_dev, &fd); 1131 1132 /* TxConf FQ selection relies on queue id from the stack. 1133 * In case of a forwarded frame from another DPNI interface, we choose 1134 * a queue affined to the same core that processed the Rx frame 1135 */ 1136 queue_mapping = skb_get_queue_mapping(skb); 1137 1138 if (net_dev->num_tc) { 1139 prio = netdev_txq_to_tc(net_dev, queue_mapping); 1140 /* Hardware interprets priority level 0 as being the highest, 1141 * so we need to do a reverse mapping to the netdev tc index 1142 */ 1143 prio = net_dev->num_tc - prio - 1; 1144 /* We have only one FQ array entry for all Tx hardware queues 1145 * with the same flow id (but different priority levels) 1146 */ 1147 queue_mapping %= dpaa2_eth_queue_count(priv); 1148 } 1149 fq = &priv->fq[queue_mapping]; 1150 1151 fd_len = dpaa2_fd_get_len(&fd); 1152 nq = netdev_get_tx_queue(net_dev, queue_mapping); 1153 netdev_tx_sent_queue(nq, fd_len); 1154 1155 /* Everything that happens after this enqueues might race with 1156 * the Tx confirmation callback for this frame 1157 */ 1158 for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) { 1159 err = priv->enqueue(priv, fq, &fd, prio, 1, NULL); 1160 if (err != -EBUSY) 1161 break; 1162 } 1163 percpu_extras->tx_portal_busy += i; 1164 if (unlikely(err < 0)) { 1165 percpu_stats->tx_errors++; 1166 /* Clean up everything, including freeing the skb */ 1167 dpaa2_eth_free_tx_fd(priv, fq, &fd, false); 1168 netdev_tx_completed_queue(nq, 1, fd_len); 1169 } else { 1170 percpu_stats->tx_packets++; 1171 percpu_stats->tx_bytes += fd_len; 1172 } 1173 1174 return NETDEV_TX_OK; 1175 1176err_build_fd: 1177 dev_kfree_skb(skb); 1178 1179 return NETDEV_TX_OK; 1180} 1181 1182static void dpaa2_eth_tx_onestep_tstamp(struct work_struct *work) 1183{ 1184 struct dpaa2_eth_priv *priv = container_of(work, struct dpaa2_eth_priv, 1185 tx_onestep_tstamp); 1186 struct sk_buff *skb; 1187 1188 while (true) { 1189 skb = skb_dequeue(&priv->tx_skbs); 1190 if (!skb) 1191 return; 1192 1193 /* Lock just before TX one-step timestamping packet, 1194 * and release the lock in dpaa2_eth_free_tx_fd when 1195 * confirm the packet has been sent on hardware, or 1196 * when clean up during transmit failure. 1197 */ 1198 mutex_lock(&priv->onestep_tstamp_lock); 1199 __dpaa2_eth_tx(skb, priv->net_dev); 1200 } 1201} 1202 1203static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) 1204{ 1205 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1206 u8 msgtype, twostep, udp; 1207 u16 offset1, offset2; 1208 1209 /* Utilize skb->cb[0] for timestamping request per skb */ 1210 skb->cb[0] = 0; 1211 1212 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && dpaa2_ptp) { 1213 if (priv->tx_tstamp_type == HWTSTAMP_TX_ON) 1214 skb->cb[0] = TX_TSTAMP; 1215 else if (priv->tx_tstamp_type == HWTSTAMP_TX_ONESTEP_SYNC) 1216 skb->cb[0] = TX_TSTAMP_ONESTEP_SYNC; 1217 } 1218 1219 /* TX for one-step timestamping PTP Sync packet */ 1220 if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) { 1221 if (!dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp, 1222 &offset1, &offset2)) 1223 if (msgtype == 0 && twostep == 0) { 1224 skb_queue_tail(&priv->tx_skbs, skb); 1225 queue_work(priv->dpaa2_ptp_wq, 1226 &priv->tx_onestep_tstamp); 1227 return NETDEV_TX_OK; 1228 } 1229 /* Use two-step timestamping if not one-step timestamping 1230 * PTP Sync packet 1231 */ 1232 skb->cb[0] = TX_TSTAMP; 1233 } 1234 1235 /* TX for other packets */ 1236 return __dpaa2_eth_tx(skb, net_dev); 1237} 1238 1239/* Tx confirmation frame processing routine */ 1240static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, 1241 struct dpaa2_eth_channel *ch __always_unused, 1242 const struct dpaa2_fd *fd, 1243 struct dpaa2_eth_fq *fq) 1244{ 1245 struct rtnl_link_stats64 *percpu_stats; 1246 struct dpaa2_eth_drv_stats *percpu_extras; 1247 u32 fd_len = dpaa2_fd_get_len(fd); 1248 u32 fd_errors; 1249 1250 /* Tracing point */ 1251 trace_dpaa2_tx_conf_fd(priv->net_dev, fd); 1252 1253 percpu_extras = this_cpu_ptr(priv->percpu_extras); 1254 percpu_extras->tx_conf_frames++; 1255 percpu_extras->tx_conf_bytes += fd_len; 1256 1257 /* Check frame errors in the FD field */ 1258 fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK; 1259 dpaa2_eth_free_tx_fd(priv, fq, fd, true); 1260 1261 if (likely(!fd_errors)) 1262 return; 1263 1264 if (net_ratelimit()) 1265 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n", 1266 fd_errors); 1267 1268 percpu_stats = this_cpu_ptr(priv->percpu_stats); 1269 /* Tx-conf logically pertains to the egress path. */ 1270 percpu_stats->tx_errors++; 1271} 1272 1273static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable) 1274{ 1275 int err; 1276 1277 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token, 1278 DPNI_OFF_RX_L3_CSUM, enable); 1279 if (err) { 1280 netdev_err(priv->net_dev, 1281 "dpni_set_offload(RX_L3_CSUM) failed\n"); 1282 return err; 1283 } 1284 1285 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token, 1286 DPNI_OFF_RX_L4_CSUM, enable); 1287 if (err) { 1288 netdev_err(priv->net_dev, 1289 "dpni_set_offload(RX_L4_CSUM) failed\n"); 1290 return err; 1291 } 1292 1293 return 0; 1294} 1295 1296static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable) 1297{ 1298 int err; 1299 1300 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token, 1301 DPNI_OFF_TX_L3_CSUM, enable); 1302 if (err) { 1303 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n"); 1304 return err; 1305 } 1306 1307 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token, 1308 DPNI_OFF_TX_L4_CSUM, enable); 1309 if (err) { 1310 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n"); 1311 return err; 1312 } 1313 1314 return 0; 1315} 1316 1317/* Perform a single release command to add buffers 1318 * to the specified buffer pool 1319 */ 1320static int dpaa2_eth_add_bufs(struct dpaa2_eth_priv *priv, 1321 struct dpaa2_eth_channel *ch, u16 bpid) 1322{ 1323 struct device *dev = priv->net_dev->dev.parent; 1324 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; 1325 struct page *page; 1326 dma_addr_t addr; 1327 int retries = 0; 1328 int i, err; 1329 1330 for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) { 1331 /* Allocate buffer visible to WRIOP + skb shared info + 1332 * alignment padding 1333 */ 1334 /* allocate one page for each Rx buffer. WRIOP sees 1335 * the entire page except for a tailroom reserved for 1336 * skb shared info 1337 */ 1338 page = dev_alloc_pages(0); 1339 if (!page) 1340 goto err_alloc; 1341 1342 addr = dma_map_page(dev, page, 0, priv->rx_buf_size, 1343 DMA_BIDIRECTIONAL); 1344 if (unlikely(dma_mapping_error(dev, addr))) 1345 goto err_map; 1346 1347 buf_array[i] = addr; 1348 1349 /* tracing point */ 1350 trace_dpaa2_eth_buf_seed(priv->net_dev, page_address(page), 1351 DPAA2_ETH_RX_BUF_RAW_SIZE, 1352 addr, priv->rx_buf_size, 1353 bpid); 1354 } 1355 1356release_bufs: 1357 /* In case the portal is busy, retry until successful */ 1358 while ((err = dpaa2_io_service_release(ch->dpio, bpid, 1359 buf_array, i)) == -EBUSY) { 1360 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) 1361 break; 1362 cpu_relax(); 1363 } 1364 1365 /* If release command failed, clean up and bail out; 1366 * not much else we can do about it 1367 */ 1368 if (err) { 1369 dpaa2_eth_free_bufs(priv, buf_array, i); 1370 return 0; 1371 } 1372 1373 return i; 1374 1375err_map: 1376 __free_pages(page, 0); 1377err_alloc: 1378 /* If we managed to allocate at least some buffers, 1379 * release them to hardware 1380 */ 1381 if (i) 1382 goto release_bufs; 1383 1384 return 0; 1385} 1386 1387static int dpaa2_eth_seed_pool(struct dpaa2_eth_priv *priv, u16 bpid) 1388{ 1389 int i, j; 1390 int new_count; 1391 1392 for (j = 0; j < priv->num_channels; j++) { 1393 for (i = 0; i < DPAA2_ETH_NUM_BUFS; 1394 i += DPAA2_ETH_BUFS_PER_CMD) { 1395 new_count = dpaa2_eth_add_bufs(priv, priv->channel[j], bpid); 1396 priv->channel[j]->buf_count += new_count; 1397 1398 if (new_count < DPAA2_ETH_BUFS_PER_CMD) { 1399 return -ENOMEM; 1400 } 1401 } 1402 } 1403 1404 return 0; 1405} 1406 1407/* 1408 * Drain the specified number of buffers from the DPNI's private buffer pool. 1409 * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD 1410 */ 1411static void dpaa2_eth_drain_bufs(struct dpaa2_eth_priv *priv, int count) 1412{ 1413 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; 1414 int retries = 0; 1415 int ret; 1416 1417 do { 1418 ret = dpaa2_io_service_acquire(NULL, priv->bpid, 1419 buf_array, count); 1420 if (ret < 0) { 1421 if (ret == -EBUSY && 1422 retries++ < DPAA2_ETH_SWP_BUSY_RETRIES) 1423 continue; 1424 netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n"); 1425 return; 1426 } 1427 dpaa2_eth_free_bufs(priv, buf_array, ret); 1428 retries = 0; 1429 } while (ret); 1430} 1431 1432static void dpaa2_eth_drain_pool(struct dpaa2_eth_priv *priv) 1433{ 1434 int i; 1435 1436 dpaa2_eth_drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD); 1437 dpaa2_eth_drain_bufs(priv, 1); 1438 1439 for (i = 0; i < priv->num_channels; i++) 1440 priv->channel[i]->buf_count = 0; 1441} 1442 1443/* Function is called from softirq context only, so we don't need to guard 1444 * the access to percpu count 1445 */ 1446static int dpaa2_eth_refill_pool(struct dpaa2_eth_priv *priv, 1447 struct dpaa2_eth_channel *ch, 1448 u16 bpid) 1449{ 1450 int new_count; 1451 1452 if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH)) 1453 return 0; 1454 1455 do { 1456 new_count = dpaa2_eth_add_bufs(priv, ch, bpid); 1457 if (unlikely(!new_count)) { 1458 /* Out of memory; abort for now, we'll try later on */ 1459 break; 1460 } 1461 ch->buf_count += new_count; 1462 } while (ch->buf_count < DPAA2_ETH_NUM_BUFS); 1463 1464 if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS)) 1465 return -ENOMEM; 1466 1467 return 0; 1468} 1469 1470static void dpaa2_eth_sgt_cache_drain(struct dpaa2_eth_priv *priv) 1471{ 1472 struct dpaa2_eth_sgt_cache *sgt_cache; 1473 u16 count; 1474 int k, i; 1475 1476 for_each_possible_cpu(k) { 1477 sgt_cache = per_cpu_ptr(priv->sgt_cache, k); 1478 count = sgt_cache->count; 1479 1480 for (i = 0; i < count; i++) 1481 kfree(sgt_cache->buf[i]); 1482 sgt_cache->count = 0; 1483 } 1484} 1485 1486static int dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch) 1487{ 1488 int err; 1489 int dequeues = -1; 1490 1491 /* Retry while portal is busy */ 1492 do { 1493 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id, 1494 ch->store); 1495 dequeues++; 1496 cpu_relax(); 1497 } while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES); 1498 1499 ch->stats.dequeue_portal_busy += dequeues; 1500 if (unlikely(err)) 1501 ch->stats.pull_err++; 1502 1503 return err; 1504} 1505 1506/* NAPI poll routine 1507 * 1508 * Frames are dequeued from the QMan channel associated with this NAPI context. 1509 * Rx, Tx confirmation and (if configured) Rx error frames all count 1510 * towards the NAPI budget. 1511 */ 1512static int dpaa2_eth_poll(struct napi_struct *napi, int budget) 1513{ 1514 struct dpaa2_eth_channel *ch; 1515 struct dpaa2_eth_priv *priv; 1516 int rx_cleaned = 0, txconf_cleaned = 0; 1517 struct dpaa2_eth_fq *fq, *txc_fq = NULL; 1518 struct netdev_queue *nq; 1519 int store_cleaned, work_done; 1520 struct list_head rx_list; 1521 int retries = 0; 1522 u16 flowid; 1523 int err; 1524 1525 ch = container_of(napi, struct dpaa2_eth_channel, napi); 1526 ch->xdp.res = 0; 1527 priv = ch->priv; 1528 1529 INIT_LIST_HEAD(&rx_list); 1530 ch->rx_list = &rx_list; 1531 1532 do { 1533 err = dpaa2_eth_pull_channel(ch); 1534 if (unlikely(err)) 1535 break; 1536 1537 /* Refill pool if appropriate */ 1538 dpaa2_eth_refill_pool(priv, ch, priv->bpid); 1539 1540 store_cleaned = dpaa2_eth_consume_frames(ch, &fq); 1541 if (store_cleaned <= 0) 1542 break; 1543 if (fq->type == DPAA2_RX_FQ) { 1544 rx_cleaned += store_cleaned; 1545 flowid = fq->flowid; 1546 } else { 1547 txconf_cleaned += store_cleaned; 1548 /* We have a single Tx conf FQ on this channel */ 1549 txc_fq = fq; 1550 } 1551 1552 /* If we either consumed the whole NAPI budget with Rx frames 1553 * or we reached the Tx confirmations threshold, we're done. 1554 */ 1555 if (rx_cleaned >= budget || 1556 txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) { 1557 work_done = budget; 1558 goto out; 1559 } 1560 } while (store_cleaned); 1561 1562 /* We didn't consume the entire budget, so finish napi and 1563 * re-enable data availability notifications 1564 */ 1565 napi_complete_done(napi, rx_cleaned); 1566 do { 1567 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx); 1568 cpu_relax(); 1569 } while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES); 1570 WARN_ONCE(err, "CDAN notifications rearm failed on core %d", 1571 ch->nctx.desired_cpu); 1572 1573 work_done = max(rx_cleaned, 1); 1574 1575out: 1576 netif_receive_skb_list(ch->rx_list); 1577 1578 if (txc_fq && txc_fq->dq_frames) { 1579 nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid); 1580 netdev_tx_completed_queue(nq, txc_fq->dq_frames, 1581 txc_fq->dq_bytes); 1582 txc_fq->dq_frames = 0; 1583 txc_fq->dq_bytes = 0; 1584 } 1585 1586 if (ch->xdp.res & XDP_REDIRECT) 1587 xdp_do_flush_map(); 1588 else if (rx_cleaned && ch->xdp.res & XDP_TX) 1589 dpaa2_eth_xdp_tx_flush(priv, ch, &priv->fq[flowid]); 1590 1591 return work_done; 1592} 1593 1594static void dpaa2_eth_enable_ch_napi(struct dpaa2_eth_priv *priv) 1595{ 1596 struct dpaa2_eth_channel *ch; 1597 int i; 1598 1599 for (i = 0; i < priv->num_channels; i++) { 1600 ch = priv->channel[i]; 1601 napi_enable(&ch->napi); 1602 } 1603} 1604 1605static void dpaa2_eth_disable_ch_napi(struct dpaa2_eth_priv *priv) 1606{ 1607 struct dpaa2_eth_channel *ch; 1608 int i; 1609 1610 for (i = 0; i < priv->num_channels; i++) { 1611 ch = priv->channel[i]; 1612 napi_disable(&ch->napi); 1613 } 1614} 1615 1616void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv, 1617 bool tx_pause, bool pfc) 1618{ 1619 struct dpni_taildrop td = {0}; 1620 struct dpaa2_eth_fq *fq; 1621 int i, err; 1622 1623 /* FQ taildrop: threshold is in bytes, per frame queue. Enabled if 1624 * flow control is disabled (as it might interfere with either the 1625 * buffer pool depletion trigger for pause frames or with the group 1626 * congestion trigger for PFC frames) 1627 */ 1628 td.enable = !tx_pause; 1629 if (priv->rx_fqtd_enabled == td.enable) 1630 goto set_cgtd; 1631 1632 td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH; 1633 td.units = DPNI_CONGESTION_UNIT_BYTES; 1634 1635 for (i = 0; i < priv->num_fqs; i++) { 1636 fq = &priv->fq[i]; 1637 if (fq->type != DPAA2_RX_FQ) 1638 continue; 1639 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token, 1640 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 1641 fq->tc, fq->flowid, &td); 1642 if (err) { 1643 netdev_err(priv->net_dev, 1644 "dpni_set_taildrop(FQ) failed\n"); 1645 return; 1646 } 1647 } 1648 1649 priv->rx_fqtd_enabled = td.enable; 1650 1651set_cgtd: 1652 /* Congestion group taildrop: threshold is in frames, per group 1653 * of FQs belonging to the same traffic class 1654 * Enabled if general Tx pause disabled or if PFCs are enabled 1655 * (congestion group threhsold for PFC generation is lower than the 1656 * CG taildrop threshold, so it won't interfere with it; we also 1657 * want frames in non-PFC enabled traffic classes to be kept in check) 1658 */ 1659 td.enable = !tx_pause || (tx_pause && pfc); 1660 if (priv->rx_cgtd_enabled == td.enable) 1661 return; 1662 1663 td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv); 1664 td.units = DPNI_CONGESTION_UNIT_FRAMES; 1665 for (i = 0; i < dpaa2_eth_tc_count(priv); i++) { 1666 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token, 1667 DPNI_CP_GROUP, DPNI_QUEUE_RX, 1668 i, 0, &td); 1669 if (err) { 1670 netdev_err(priv->net_dev, 1671 "dpni_set_taildrop(CG) failed\n"); 1672 return; 1673 } 1674 } 1675 1676 priv->rx_cgtd_enabled = td.enable; 1677} 1678 1679static int dpaa2_eth_link_state_update(struct dpaa2_eth_priv *priv) 1680{ 1681 struct dpni_link_state state = {0}; 1682 bool tx_pause; 1683 int err; 1684 1685 err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state); 1686 if (unlikely(err)) { 1687 netdev_err(priv->net_dev, 1688 "dpni_get_link_state() failed\n"); 1689 return err; 1690 } 1691 1692 /* If Tx pause frame settings have changed, we need to update 1693 * Rx FQ taildrop configuration as well. We configure taildrop 1694 * only when pause frame generation is disabled. 1695 */ 1696 tx_pause = dpaa2_eth_tx_pause_enabled(state.options); 1697 dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled); 1698 1699 /* When we manage the MAC/PHY using phylink there is no need 1700 * to manually update the netif_carrier. 1701 */ 1702 if (priv->mac) 1703 goto out; 1704 1705 /* Chech link state; speed / duplex changes are not treated yet */ 1706 if (priv->link_state.up == state.up) 1707 goto out; 1708 1709 if (state.up) { 1710 netif_carrier_on(priv->net_dev); 1711 netif_tx_start_all_queues(priv->net_dev); 1712 } else { 1713 netif_tx_stop_all_queues(priv->net_dev); 1714 netif_carrier_off(priv->net_dev); 1715 } 1716 1717 netdev_info(priv->net_dev, "Link Event: state %s\n", 1718 state.up ? "up" : "down"); 1719 1720out: 1721 priv->link_state = state; 1722 1723 return 0; 1724} 1725 1726static int dpaa2_eth_open(struct net_device *net_dev) 1727{ 1728 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1729 int err; 1730 1731 err = dpaa2_eth_seed_pool(priv, priv->bpid); 1732 if (err) { 1733 /* Not much to do; the buffer pool, though not filled up, 1734 * may still contain some buffers which would enable us 1735 * to limp on. 1736 */ 1737 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n", 1738 priv->dpbp_dev->obj_desc.id, priv->bpid); 1739 } 1740 1741 if (!priv->mac) { 1742 /* We'll only start the txqs when the link is actually ready; 1743 * make sure we don't race against the link up notification, 1744 * which may come immediately after dpni_enable(); 1745 */ 1746 netif_tx_stop_all_queues(net_dev); 1747 1748 /* Also, explicitly set carrier off, otherwise 1749 * netif_carrier_ok() will return true and cause 'ip link show' 1750 * to report the LOWER_UP flag, even though the link 1751 * notification wasn't even received. 1752 */ 1753 netif_carrier_off(net_dev); 1754 } 1755 dpaa2_eth_enable_ch_napi(priv); 1756 1757 err = dpni_enable(priv->mc_io, 0, priv->mc_token); 1758 if (err < 0) { 1759 netdev_err(net_dev, "dpni_enable() failed\n"); 1760 goto enable_err; 1761 } 1762 1763 if (priv->mac) 1764 phylink_start(priv->mac->phylink); 1765 1766 return 0; 1767 1768enable_err: 1769 dpaa2_eth_disable_ch_napi(priv); 1770 dpaa2_eth_drain_pool(priv); 1771 return err; 1772} 1773 1774/* Total number of in-flight frames on ingress queues */ 1775static u32 dpaa2_eth_ingress_fq_count(struct dpaa2_eth_priv *priv) 1776{ 1777 struct dpaa2_eth_fq *fq; 1778 u32 fcnt = 0, bcnt = 0, total = 0; 1779 int i, err; 1780 1781 for (i = 0; i < priv->num_fqs; i++) { 1782 fq = &priv->fq[i]; 1783 err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt); 1784 if (err) { 1785 netdev_warn(priv->net_dev, "query_fq_count failed"); 1786 break; 1787 } 1788 total += fcnt; 1789 } 1790 1791 return total; 1792} 1793 1794static void dpaa2_eth_wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv) 1795{ 1796 int retries = 10; 1797 u32 pending; 1798 1799 do { 1800 pending = dpaa2_eth_ingress_fq_count(priv); 1801 if (pending) 1802 msleep(100); 1803 } while (pending && --retries); 1804} 1805 1806#define DPNI_TX_PENDING_VER_MAJOR 7 1807#define DPNI_TX_PENDING_VER_MINOR 13 1808static void dpaa2_eth_wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv) 1809{ 1810 union dpni_statistics stats; 1811 int retries = 10; 1812 int err; 1813 1814 if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR, 1815 DPNI_TX_PENDING_VER_MINOR) < 0) 1816 goto out; 1817 1818 do { 1819 err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6, 1820 &stats); 1821 if (err) 1822 goto out; 1823 if (stats.page_6.tx_pending_frames == 0) 1824 return; 1825 } while (--retries); 1826 1827out: 1828 msleep(500); 1829} 1830 1831static int dpaa2_eth_stop(struct net_device *net_dev) 1832{ 1833 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1834 int dpni_enabled = 0; 1835 int retries = 10; 1836 1837 if (!priv->mac) { 1838 netif_tx_stop_all_queues(net_dev); 1839 netif_carrier_off(net_dev); 1840 } else { 1841 phylink_stop(priv->mac->phylink); 1842 } 1843 1844 /* On dpni_disable(), the MC firmware will: 1845 * - stop MAC Rx and wait for all Rx frames to be enqueued to software 1846 * - cut off WRIOP dequeues from egress FQs and wait until transmission 1847 * of all in flight Tx frames is finished (and corresponding Tx conf 1848 * frames are enqueued back to software) 1849 * 1850 * Before calling dpni_disable(), we wait for all Tx frames to arrive 1851 * on WRIOP. After it finishes, wait until all remaining frames on Rx 1852 * and Tx conf queues are consumed on NAPI poll. 1853 */ 1854 dpaa2_eth_wait_for_egress_fq_empty(priv); 1855 1856 do { 1857 dpni_disable(priv->mc_io, 0, priv->mc_token); 1858 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled); 1859 if (dpni_enabled) 1860 /* Allow the hardware some slack */ 1861 msleep(100); 1862 } while (dpni_enabled && --retries); 1863 if (!retries) { 1864 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n"); 1865 /* Must go on and disable NAPI nonetheless, so we don't crash at 1866 * the next "ifconfig up" 1867 */ 1868 } 1869 1870 dpaa2_eth_wait_for_ingress_fq_empty(priv); 1871 dpaa2_eth_disable_ch_napi(priv); 1872 1873 /* Empty the buffer pool */ 1874 dpaa2_eth_drain_pool(priv); 1875 1876 /* Empty the Scatter-Gather Buffer cache */ 1877 dpaa2_eth_sgt_cache_drain(priv); 1878 1879 return 0; 1880} 1881 1882static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr) 1883{ 1884 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1885 struct device *dev = net_dev->dev.parent; 1886 int err; 1887 1888 err = eth_mac_addr(net_dev, addr); 1889 if (err < 0) { 1890 dev_err(dev, "eth_mac_addr() failed (%d)\n", err); 1891 return err; 1892 } 1893 1894 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token, 1895 net_dev->dev_addr); 1896 if (err) { 1897 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err); 1898 return err; 1899 } 1900 1901 return 0; 1902} 1903 1904/** Fill in counters maintained by the GPP driver. These may be different from 1905 * the hardware counters obtained by ethtool. 1906 */ 1907static void dpaa2_eth_get_stats(struct net_device *net_dev, 1908 struct rtnl_link_stats64 *stats) 1909{ 1910 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1911 struct rtnl_link_stats64 *percpu_stats; 1912 u64 *cpustats; 1913 u64 *netstats = (u64 *)stats; 1914 int i, j; 1915 int num = sizeof(struct rtnl_link_stats64) / sizeof(u64); 1916 1917 for_each_possible_cpu(i) { 1918 percpu_stats = per_cpu_ptr(priv->percpu_stats, i); 1919 cpustats = (u64 *)percpu_stats; 1920 for (j = 0; j < num; j++) 1921 netstats[j] += cpustats[j]; 1922 } 1923} 1924 1925/* Copy mac unicast addresses from @net_dev to @priv. 1926 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. 1927 */ 1928static void dpaa2_eth_add_uc_hw_addr(const struct net_device *net_dev, 1929 struct dpaa2_eth_priv *priv) 1930{ 1931 struct netdev_hw_addr *ha; 1932 int err; 1933 1934 netdev_for_each_uc_addr(ha, net_dev) { 1935 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, 1936 ha->addr); 1937 if (err) 1938 netdev_warn(priv->net_dev, 1939 "Could not add ucast MAC %pM to the filtering table (err %d)\n", 1940 ha->addr, err); 1941 } 1942} 1943 1944/* Copy mac multicast addresses from @net_dev to @priv 1945 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. 1946 */ 1947static void dpaa2_eth_add_mc_hw_addr(const struct net_device *net_dev, 1948 struct dpaa2_eth_priv *priv) 1949{ 1950 struct netdev_hw_addr *ha; 1951 int err; 1952 1953 netdev_for_each_mc_addr(ha, net_dev) { 1954 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, 1955 ha->addr); 1956 if (err) 1957 netdev_warn(priv->net_dev, 1958 "Could not add mcast MAC %pM to the filtering table (err %d)\n", 1959 ha->addr, err); 1960 } 1961} 1962 1963static void dpaa2_eth_set_rx_mode(struct net_device *net_dev) 1964{ 1965 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 1966 int uc_count = netdev_uc_count(net_dev); 1967 int mc_count = netdev_mc_count(net_dev); 1968 u8 max_mac = priv->dpni_attrs.mac_filter_entries; 1969 u32 options = priv->dpni_attrs.options; 1970 u16 mc_token = priv->mc_token; 1971 struct fsl_mc_io *mc_io = priv->mc_io; 1972 int err; 1973 1974 /* Basic sanity checks; these probably indicate a misconfiguration */ 1975 if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0) 1976 netdev_info(net_dev, 1977 "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n", 1978 max_mac); 1979 1980 /* Force promiscuous if the uc or mc counts exceed our capabilities. */ 1981 if (uc_count > max_mac) { 1982 netdev_info(net_dev, 1983 "Unicast addr count reached %d, max allowed is %d; forcing promisc\n", 1984 uc_count, max_mac); 1985 goto force_promisc; 1986 } 1987 if (mc_count + uc_count > max_mac) { 1988 netdev_info(net_dev, 1989 "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n", 1990 uc_count + mc_count, max_mac); 1991 goto force_mc_promisc; 1992 } 1993 1994 /* Adjust promisc settings due to flag combinations */ 1995 if (net_dev->flags & IFF_PROMISC) 1996 goto force_promisc; 1997 if (net_dev->flags & IFF_ALLMULTI) { 1998 /* First, rebuild unicast filtering table. This should be done 1999 * in promisc mode, in order to avoid frame loss while we 2000 * progressively add entries to the table. 2001 * We don't know whether we had been in promisc already, and 2002 * making an MC call to find out is expensive; so set uc promisc 2003 * nonetheless. 2004 */ 2005 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); 2006 if (err) 2007 netdev_warn(net_dev, "Can't set uc promisc\n"); 2008 2009 /* Actual uc table reconstruction. */ 2010 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0); 2011 if (err) 2012 netdev_warn(net_dev, "Can't clear uc filters\n"); 2013 dpaa2_eth_add_uc_hw_addr(net_dev, priv); 2014 2015 /* Finally, clear uc promisc and set mc promisc as requested. */ 2016 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); 2017 if (err) 2018 netdev_warn(net_dev, "Can't clear uc promisc\n"); 2019 goto force_mc_promisc; 2020 } 2021 2022 /* Neither unicast, nor multicast promisc will be on... eventually. 2023 * For now, rebuild mac filtering tables while forcing both of them on. 2024 */ 2025 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); 2026 if (err) 2027 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err); 2028 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); 2029 if (err) 2030 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err); 2031 2032 /* Actual mac filtering tables reconstruction */ 2033 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1); 2034 if (err) 2035 netdev_warn(net_dev, "Can't clear mac filters\n"); 2036 dpaa2_eth_add_mc_hw_addr(net_dev, priv); 2037 dpaa2_eth_add_uc_hw_addr(net_dev, priv); 2038 2039 /* Now we can clear both ucast and mcast promisc, without risking 2040 * to drop legitimate frames anymore. 2041 */ 2042 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); 2043 if (err) 2044 netdev_warn(net_dev, "Can't clear ucast promisc\n"); 2045 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0); 2046 if (err) 2047 netdev_warn(net_dev, "Can't clear mcast promisc\n"); 2048 2049 return; 2050 2051force_promisc: 2052 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); 2053 if (err) 2054 netdev_warn(net_dev, "Can't set ucast promisc\n"); 2055force_mc_promisc: 2056 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); 2057 if (err) 2058 netdev_warn(net_dev, "Can't set mcast promisc\n"); 2059} 2060 2061static int dpaa2_eth_set_features(struct net_device *net_dev, 2062 netdev_features_t features) 2063{ 2064 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 2065 netdev_features_t changed = features ^ net_dev->features; 2066 bool enable; 2067 int err; 2068 2069 if (changed & NETIF_F_RXCSUM) { 2070 enable = !!(features & NETIF_F_RXCSUM); 2071 err = dpaa2_eth_set_rx_csum(priv, enable); 2072 if (err) 2073 return err; 2074 } 2075 2076 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) { 2077 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 2078 err = dpaa2_eth_set_tx_csum(priv, enable); 2079 if (err) 2080 return err; 2081 } 2082 2083 return 0; 2084} 2085 2086static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2087{ 2088 struct dpaa2_eth_priv *priv = netdev_priv(dev); 2089 struct hwtstamp_config config; 2090 2091 if (!dpaa2_ptp) 2092 return -EINVAL; 2093 2094 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 2095 return -EFAULT; 2096 2097 switch (config.tx_type) { 2098 case HWTSTAMP_TX_OFF: 2099 case HWTSTAMP_TX_ON: 2100 case HWTSTAMP_TX_ONESTEP_SYNC: 2101 priv->tx_tstamp_type = config.tx_type; 2102 break; 2103 default: 2104 return -ERANGE; 2105 } 2106 2107 if (config.rx_filter == HWTSTAMP_FILTER_NONE) { 2108 priv->rx_tstamp = false; 2109 } else { 2110 priv->rx_tstamp = true; 2111 /* TS is set for all frame types, not only those requested */ 2112 config.rx_filter = HWTSTAMP_FILTER_ALL; 2113 } 2114 2115 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? 2116 -EFAULT : 0; 2117} 2118 2119static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2120{ 2121 struct dpaa2_eth_priv *priv = netdev_priv(dev); 2122 2123 if (cmd == SIOCSHWTSTAMP) 2124 return dpaa2_eth_ts_ioctl(dev, rq, cmd); 2125 2126 if (priv->mac) 2127 return phylink_mii_ioctl(priv->mac->phylink, rq, cmd); 2128 2129 return -EOPNOTSUPP; 2130} 2131 2132static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu) 2133{ 2134 int mfl, linear_mfl; 2135 2136 mfl = DPAA2_ETH_L2_MAX_FRM(mtu); 2137 linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE - 2138 dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM; 2139 2140 if (mfl > linear_mfl) { 2141 netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n", 2142 linear_mfl - VLAN_ETH_HLEN); 2143 return false; 2144 } 2145 2146 return true; 2147} 2148 2149static int dpaa2_eth_set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp) 2150{ 2151 int mfl, err; 2152 2153 /* We enforce a maximum Rx frame length based on MTU only if we have 2154 * an XDP program attached (in order to avoid Rx S/G frames). 2155 * Otherwise, we accept all incoming frames as long as they are not 2156 * larger than maximum size supported in hardware 2157 */ 2158 if (has_xdp) 2159 mfl = DPAA2_ETH_L2_MAX_FRM(mtu); 2160 else 2161 mfl = DPAA2_ETH_MFL; 2162 2163 err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl); 2164 if (err) { 2165 netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n"); 2166 return err; 2167 } 2168 2169 return 0; 2170} 2171 2172static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu) 2173{ 2174 struct dpaa2_eth_priv *priv = netdev_priv(dev); 2175 int err; 2176 2177 if (!priv->xdp_prog) 2178 goto out; 2179 2180 if (!xdp_mtu_valid(priv, new_mtu)) 2181 return -EINVAL; 2182 2183 err = dpaa2_eth_set_rx_mfl(priv, new_mtu, true); 2184 if (err) 2185 return err; 2186 2187out: 2188 dev->mtu = new_mtu; 2189 return 0; 2190} 2191 2192static int dpaa2_eth_update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp) 2193{ 2194 struct dpni_buffer_layout buf_layout = {0}; 2195 int err; 2196 2197 err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token, 2198 DPNI_QUEUE_RX, &buf_layout); 2199 if (err) { 2200 netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n"); 2201 return err; 2202 } 2203 2204 /* Reserve extra headroom for XDP header size changes */ 2205 buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) + 2206 (has_xdp ? XDP_PACKET_HEADROOM : 0); 2207 buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM; 2208 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, 2209 DPNI_QUEUE_RX, &buf_layout); 2210 if (err) { 2211 netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n"); 2212 return err; 2213 } 2214 2215 return 0; 2216} 2217 2218static int dpaa2_eth_setup_xdp(struct net_device *dev, struct bpf_prog *prog) 2219{ 2220 struct dpaa2_eth_priv *priv = netdev_priv(dev); 2221 struct dpaa2_eth_channel *ch; 2222 struct bpf_prog *old; 2223 bool up, need_update; 2224 int i, err; 2225 2226 if (prog && !xdp_mtu_valid(priv, dev->mtu)) 2227 return -EINVAL; 2228 2229 if (prog) 2230 bpf_prog_add(prog, priv->num_channels); 2231 2232 up = netif_running(dev); 2233 need_update = (!!priv->xdp_prog != !!prog); 2234 2235 if (up) 2236 dpaa2_eth_stop(dev); 2237 2238 /* While in xdp mode, enforce a maximum Rx frame size based on MTU. 2239 * Also, when switching between xdp/non-xdp modes we need to reconfigure 2240 * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop, 2241 * so we are sure no old format buffers will be used from now on. 2242 */ 2243 if (need_update) { 2244 err = dpaa2_eth_set_rx_mfl(priv, dev->mtu, !!prog); 2245 if (err) 2246 goto out_err; 2247 err = dpaa2_eth_update_rx_buffer_headroom(priv, !!prog); 2248 if (err) 2249 goto out_err; 2250 } 2251 2252 old = xchg(&priv->xdp_prog, prog); 2253 if (old) 2254 bpf_prog_put(old); 2255 2256 for (i = 0; i < priv->num_channels; i++) { 2257 ch = priv->channel[i]; 2258 old = xchg(&ch->xdp.prog, prog); 2259 if (old) 2260 bpf_prog_put(old); 2261 } 2262 2263 if (up) { 2264 err = dpaa2_eth_open(dev); 2265 if (err) 2266 return err; 2267 } 2268 2269 return 0; 2270 2271out_err: 2272 if (prog) 2273 bpf_prog_sub(prog, priv->num_channels); 2274 if (up) 2275 dpaa2_eth_open(dev); 2276 2277 return err; 2278} 2279 2280static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2281{ 2282 switch (xdp->command) { 2283 case XDP_SETUP_PROG: 2284 return dpaa2_eth_setup_xdp(dev, xdp->prog); 2285 default: 2286 return -EINVAL; 2287 } 2288 2289 return 0; 2290} 2291 2292static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev, 2293 struct xdp_frame *xdpf, 2294 struct dpaa2_fd *fd) 2295{ 2296 struct device *dev = net_dev->dev.parent; 2297 unsigned int needed_headroom; 2298 struct dpaa2_eth_swa *swa; 2299 void *buffer_start, *aligned_start; 2300 dma_addr_t addr; 2301 2302 /* We require a minimum headroom to be able to transmit the frame. 2303 * Otherwise return an error and let the original net_device handle it 2304 */ 2305 needed_headroom = dpaa2_eth_needed_headroom(NULL); 2306 if (xdpf->headroom < needed_headroom) 2307 return -EINVAL; 2308 2309 /* Setup the FD fields */ 2310 memset(fd, 0, sizeof(*fd)); 2311 2312 /* Align FD address, if possible */ 2313 buffer_start = xdpf->data - needed_headroom; 2314 aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN, 2315 DPAA2_ETH_TX_BUF_ALIGN); 2316 if (aligned_start >= xdpf->data - xdpf->headroom) 2317 buffer_start = aligned_start; 2318 2319 swa = (struct dpaa2_eth_swa *)buffer_start; 2320 /* fill in necessary fields here */ 2321 swa->type = DPAA2_ETH_SWA_XDP; 2322 swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start; 2323 swa->xdp.xdpf = xdpf; 2324 2325 addr = dma_map_single(dev, buffer_start, 2326 swa->xdp.dma_size, 2327 DMA_BIDIRECTIONAL); 2328 if (unlikely(dma_mapping_error(dev, addr))) 2329 return -ENOMEM; 2330 2331 dpaa2_fd_set_addr(fd, addr); 2332 dpaa2_fd_set_offset(fd, xdpf->data - buffer_start); 2333 dpaa2_fd_set_len(fd, xdpf->len); 2334 dpaa2_fd_set_format(fd, dpaa2_fd_single); 2335 dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA); 2336 2337 return 0; 2338} 2339 2340static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n, 2341 struct xdp_frame **frames, u32 flags) 2342{ 2343 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 2344 struct dpaa2_eth_xdp_fds *xdp_redirect_fds; 2345 struct rtnl_link_stats64 *percpu_stats; 2346 struct dpaa2_eth_fq *fq; 2347 struct dpaa2_fd *fds; 2348 int enqueued, i, err; 2349 2350 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2351 return -EINVAL; 2352 2353 if (!netif_running(net_dev)) 2354 return -ENETDOWN; 2355 2356 fq = &priv->fq[smp_processor_id()]; 2357 xdp_redirect_fds = &fq->xdp_redirect_fds; 2358 fds = xdp_redirect_fds->fds; 2359 2360 percpu_stats = this_cpu_ptr(priv->percpu_stats); 2361 2362 /* create a FD for each xdp_frame in the list received */ 2363 for (i = 0; i < n; i++) { 2364 err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]); 2365 if (err) 2366 break; 2367 } 2368 xdp_redirect_fds->num = i; 2369 2370 /* enqueue all the frame descriptors */ 2371 enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds); 2372 2373 /* update statistics */ 2374 percpu_stats->tx_packets += enqueued; 2375 for (i = 0; i < enqueued; i++) 2376 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]); 2377 for (i = enqueued; i < n; i++) 2378 xdp_return_frame_rx_napi(frames[i]); 2379 2380 return enqueued; 2381} 2382 2383static int update_xps(struct dpaa2_eth_priv *priv) 2384{ 2385 struct net_device *net_dev = priv->net_dev; 2386 struct cpumask xps_mask; 2387 struct dpaa2_eth_fq *fq; 2388 int i, num_queues, netdev_queues; 2389 int err = 0; 2390 2391 num_queues = dpaa2_eth_queue_count(priv); 2392 netdev_queues = (net_dev->num_tc ? : 1) * num_queues; 2393 2394 /* The first <num_queues> entries in priv->fq array are Tx/Tx conf 2395 * queues, so only process those 2396 */ 2397 for (i = 0; i < netdev_queues; i++) { 2398 fq = &priv->fq[i % num_queues]; 2399 2400 cpumask_clear(&xps_mask); 2401 cpumask_set_cpu(fq->target_cpu, &xps_mask); 2402 2403 err = netif_set_xps_queue(net_dev, &xps_mask, i); 2404 if (err) { 2405 netdev_warn_once(net_dev, "Error setting XPS queue\n"); 2406 break; 2407 } 2408 } 2409 2410 return err; 2411} 2412 2413static int dpaa2_eth_setup_mqprio(struct net_device *net_dev, 2414 struct tc_mqprio_qopt *mqprio) 2415{ 2416 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 2417 u8 num_tc, num_queues; 2418 int i; 2419 2420 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 2421 num_queues = dpaa2_eth_queue_count(priv); 2422 num_tc = mqprio->num_tc; 2423 2424 if (num_tc == net_dev->num_tc) 2425 return 0; 2426 2427 if (num_tc > dpaa2_eth_tc_count(priv)) { 2428 netdev_err(net_dev, "Max %d traffic classes supported\n", 2429 dpaa2_eth_tc_count(priv)); 2430 return -EOPNOTSUPP; 2431 } 2432 2433 if (!num_tc) { 2434 netdev_reset_tc(net_dev); 2435 netif_set_real_num_tx_queues(net_dev, num_queues); 2436 goto out; 2437 } 2438 2439 netdev_set_num_tc(net_dev, num_tc); 2440 netif_set_real_num_tx_queues(net_dev, num_tc * num_queues); 2441 2442 for (i = 0; i < num_tc; i++) 2443 netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues); 2444 2445out: 2446 update_xps(priv); 2447 2448 return 0; 2449} 2450 2451#define bps_to_mbits(rate) (div_u64((rate), 1000000) * 8) 2452 2453static int dpaa2_eth_setup_tbf(struct net_device *net_dev, struct tc_tbf_qopt_offload *p) 2454{ 2455 struct tc_tbf_qopt_offload_replace_params *cfg = &p->replace_params; 2456 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 2457 struct dpni_tx_shaping_cfg tx_cr_shaper = { 0 }; 2458 struct dpni_tx_shaping_cfg tx_er_shaper = { 0 }; 2459 int err; 2460 2461 if (p->command == TC_TBF_STATS) 2462 return -EOPNOTSUPP; 2463 2464 /* Only per port Tx shaping */ 2465 if (p->parent != TC_H_ROOT) 2466 return -EOPNOTSUPP; 2467 2468 if (p->command == TC_TBF_REPLACE) { 2469 if (cfg->max_size > DPAA2_ETH_MAX_BURST_SIZE) { 2470 netdev_err(net_dev, "burst size cannot be greater than %d\n", 2471 DPAA2_ETH_MAX_BURST_SIZE); 2472 return -EINVAL; 2473 } 2474 2475 tx_cr_shaper.max_burst_size = cfg->max_size; 2476 /* The TBF interface is in bytes/s, whereas DPAA2 expects the 2477 * rate in Mbits/s 2478 */ 2479 tx_cr_shaper.rate_limit = bps_to_mbits(cfg->rate.rate_bytes_ps); 2480 } 2481 2482 err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &tx_cr_shaper, 2483 &tx_er_shaper, 0); 2484 if (err) { 2485 netdev_err(net_dev, "dpni_set_tx_shaping() = %d\n", err); 2486 return err; 2487 } 2488 2489 return 0; 2490} 2491 2492static int dpaa2_eth_setup_tc(struct net_device *net_dev, 2493 enum tc_setup_type type, void *type_data) 2494{ 2495 switch (type) { 2496 case TC_SETUP_QDISC_MQPRIO: 2497 return dpaa2_eth_setup_mqprio(net_dev, type_data); 2498 case TC_SETUP_QDISC_TBF: 2499 return dpaa2_eth_setup_tbf(net_dev, type_data); 2500 default: 2501 return -EOPNOTSUPP; 2502 } 2503} 2504 2505static const struct net_device_ops dpaa2_eth_ops = { 2506 .ndo_open = dpaa2_eth_open, 2507 .ndo_start_xmit = dpaa2_eth_tx, 2508 .ndo_stop = dpaa2_eth_stop, 2509 .ndo_set_mac_address = dpaa2_eth_set_addr, 2510 .ndo_get_stats64 = dpaa2_eth_get_stats, 2511 .ndo_set_rx_mode = dpaa2_eth_set_rx_mode, 2512 .ndo_set_features = dpaa2_eth_set_features, 2513 .ndo_do_ioctl = dpaa2_eth_ioctl, 2514 .ndo_change_mtu = dpaa2_eth_change_mtu, 2515 .ndo_bpf = dpaa2_eth_xdp, 2516 .ndo_xdp_xmit = dpaa2_eth_xdp_xmit, 2517 .ndo_setup_tc = dpaa2_eth_setup_tc, 2518}; 2519 2520static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx) 2521{ 2522 struct dpaa2_eth_channel *ch; 2523 2524 ch = container_of(ctx, struct dpaa2_eth_channel, nctx); 2525 2526 /* Update NAPI statistics */ 2527 ch->stats.cdan++; 2528 2529 napi_schedule(&ch->napi); 2530} 2531 2532/* Allocate and configure a DPCON object */ 2533static struct fsl_mc_device *dpaa2_eth_setup_dpcon(struct dpaa2_eth_priv *priv) 2534{ 2535 struct fsl_mc_device *dpcon; 2536 struct device *dev = priv->net_dev->dev.parent; 2537 int err; 2538 2539 err = fsl_mc_object_allocate(to_fsl_mc_device(dev), 2540 FSL_MC_POOL_DPCON, &dpcon); 2541 if (err) { 2542 if (err == -ENXIO) 2543 err = -EPROBE_DEFER; 2544 else 2545 dev_info(dev, "Not enough DPCONs, will go on as-is\n"); 2546 return ERR_PTR(err); 2547 } 2548 2549 err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle); 2550 if (err) { 2551 dev_err(dev, "dpcon_open() failed\n"); 2552 goto free; 2553 } 2554 2555 err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle); 2556 if (err) { 2557 dev_err(dev, "dpcon_reset() failed\n"); 2558 goto close; 2559 } 2560 2561 err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle); 2562 if (err) { 2563 dev_err(dev, "dpcon_enable() failed\n"); 2564 goto close; 2565 } 2566 2567 return dpcon; 2568 2569close: 2570 dpcon_close(priv->mc_io, 0, dpcon->mc_handle); 2571free: 2572 fsl_mc_object_free(dpcon); 2573 2574 return ERR_PTR(err); 2575} 2576 2577static void dpaa2_eth_free_dpcon(struct dpaa2_eth_priv *priv, 2578 struct fsl_mc_device *dpcon) 2579{ 2580 dpcon_disable(priv->mc_io, 0, dpcon->mc_handle); 2581 dpcon_close(priv->mc_io, 0, dpcon->mc_handle); 2582 fsl_mc_object_free(dpcon); 2583} 2584 2585static struct dpaa2_eth_channel *dpaa2_eth_alloc_channel(struct dpaa2_eth_priv *priv) 2586{ 2587 struct dpaa2_eth_channel *channel; 2588 struct dpcon_attr attr; 2589 struct device *dev = priv->net_dev->dev.parent; 2590 int err; 2591 2592 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 2593 if (!channel) 2594 return NULL; 2595 2596 channel->dpcon = dpaa2_eth_setup_dpcon(priv); 2597 if (IS_ERR(channel->dpcon)) { 2598 err = PTR_ERR(channel->dpcon); 2599 goto err_setup; 2600 } 2601 2602 err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle, 2603 &attr); 2604 if (err) { 2605 dev_err(dev, "dpcon_get_attributes() failed\n"); 2606 goto err_get_attr; 2607 } 2608 2609 channel->dpcon_id = attr.id; 2610 channel->ch_id = attr.qbman_ch_id; 2611 channel->priv = priv; 2612 2613 return channel; 2614 2615err_get_attr: 2616 dpaa2_eth_free_dpcon(priv, channel->dpcon); 2617err_setup: 2618 kfree(channel); 2619 return ERR_PTR(err); 2620} 2621 2622static void dpaa2_eth_free_channel(struct dpaa2_eth_priv *priv, 2623 struct dpaa2_eth_channel *channel) 2624{ 2625 dpaa2_eth_free_dpcon(priv, channel->dpcon); 2626 kfree(channel); 2627} 2628 2629/* DPIO setup: allocate and configure QBMan channels, setup core affinity 2630 * and register data availability notifications 2631 */ 2632static int dpaa2_eth_setup_dpio(struct dpaa2_eth_priv *priv) 2633{ 2634 struct dpaa2_io_notification_ctx *nctx; 2635 struct dpaa2_eth_channel *channel; 2636 struct dpcon_notification_cfg dpcon_notif_cfg; 2637 struct device *dev = priv->net_dev->dev.parent; 2638 int i, err; 2639 2640 /* We want the ability to spread ingress traffic (RX, TX conf) to as 2641 * many cores as possible, so we need one channel for each core 2642 * (unless there's fewer queues than cores, in which case the extra 2643 * channels would be wasted). 2644 * Allocate one channel per core and register it to the core's 2645 * affine DPIO. If not enough channels are available for all cores 2646 * or if some cores don't have an affine DPIO, there will be no 2647 * ingress frame processing on those cores. 2648 */ 2649 cpumask_clear(&priv->dpio_cpumask); 2650 for_each_online_cpu(i) { 2651 /* Try to allocate a channel */ 2652 channel = dpaa2_eth_alloc_channel(priv); 2653 if (IS_ERR_OR_NULL(channel)) { 2654 err = PTR_ERR_OR_ZERO(channel); 2655 if (err != -EPROBE_DEFER) 2656 dev_info(dev, 2657 "No affine channel for cpu %d and above\n", i); 2658 goto err_alloc_ch; 2659 } 2660 2661 priv->channel[priv->num_channels] = channel; 2662 2663 nctx = &channel->nctx; 2664 nctx->is_cdan = 1; 2665 nctx->cb = dpaa2_eth_cdan_cb; 2666 nctx->id = channel->ch_id; 2667 nctx->desired_cpu = i; 2668 2669 /* Register the new context */ 2670 channel->dpio = dpaa2_io_service_select(i); 2671 err = dpaa2_io_service_register(channel->dpio, nctx, dev); 2672 if (err) { 2673 dev_dbg(dev, "No affine DPIO for cpu %d\n", i); 2674 /* If no affine DPIO for this core, there's probably 2675 * none available for next cores either. Signal we want 2676 * to retry later, in case the DPIO devices weren't 2677 * probed yet. 2678 */ 2679 err = -EPROBE_DEFER; 2680 goto err_service_reg; 2681 } 2682 2683 /* Register DPCON notification with MC */ 2684 dpcon_notif_cfg.dpio_id = nctx->dpio_id; 2685 dpcon_notif_cfg.priority = 0; 2686 dpcon_notif_cfg.user_ctx = nctx->qman64; 2687 err = dpcon_set_notification(priv->mc_io, 0, 2688 channel->dpcon->mc_handle, 2689 &dpcon_notif_cfg); 2690 if (err) { 2691 dev_err(dev, "dpcon_set_notification failed()\n"); 2692 goto err_set_cdan; 2693 } 2694 2695 /* If we managed to allocate a channel and also found an affine 2696 * DPIO for this core, add it to the final mask 2697 */ 2698 cpumask_set_cpu(i, &priv->dpio_cpumask); 2699 priv->num_channels++; 2700 2701 /* Stop if we already have enough channels to accommodate all 2702 * RX and TX conf queues 2703 */ 2704 if (priv->num_channels == priv->dpni_attrs.num_queues) 2705 break; 2706 } 2707 2708 return 0; 2709 2710err_set_cdan: 2711 dpaa2_io_service_deregister(channel->dpio, nctx, dev); 2712err_service_reg: 2713 dpaa2_eth_free_channel(priv, channel); 2714err_alloc_ch: 2715 if (err == -EPROBE_DEFER) { 2716 for (i = 0; i < priv->num_channels; i++) { 2717 channel = priv->channel[i]; 2718 nctx = &channel->nctx; 2719 dpaa2_io_service_deregister(channel->dpio, nctx, dev); 2720 dpaa2_eth_free_channel(priv, channel); 2721 } 2722 priv->num_channels = 0; 2723 return err; 2724 } 2725 2726 if (cpumask_empty(&priv->dpio_cpumask)) { 2727 dev_err(dev, "No cpu with an affine DPIO/DPCON\n"); 2728 return -ENODEV; 2729 } 2730 2731 dev_info(dev, "Cores %*pbl available for processing ingress traffic\n", 2732 cpumask_pr_args(&priv->dpio_cpumask)); 2733 2734 return 0; 2735} 2736 2737static void dpaa2_eth_free_dpio(struct dpaa2_eth_priv *priv) 2738{ 2739 struct device *dev = priv->net_dev->dev.parent; 2740 struct dpaa2_eth_channel *ch; 2741 int i; 2742 2743 /* deregister CDAN notifications and free channels */ 2744 for (i = 0; i < priv->num_channels; i++) { 2745 ch = priv->channel[i]; 2746 dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev); 2747 dpaa2_eth_free_channel(priv, ch); 2748 } 2749} 2750 2751static struct dpaa2_eth_channel *dpaa2_eth_get_affine_channel(struct dpaa2_eth_priv *priv, 2752 int cpu) 2753{ 2754 struct device *dev = priv->net_dev->dev.parent; 2755 int i; 2756 2757 for (i = 0; i < priv->num_channels; i++) 2758 if (priv->channel[i]->nctx.desired_cpu == cpu) 2759 return priv->channel[i]; 2760 2761 /* We should never get here. Issue a warning and return 2762 * the first channel, because it's still better than nothing 2763 */ 2764 dev_warn(dev, "No affine channel found for cpu %d\n", cpu); 2765 2766 return priv->channel[0]; 2767} 2768 2769static void dpaa2_eth_set_fq_affinity(struct dpaa2_eth_priv *priv) 2770{ 2771 struct device *dev = priv->net_dev->dev.parent; 2772 struct dpaa2_eth_fq *fq; 2773 int rx_cpu, txc_cpu; 2774 int i; 2775 2776 /* For each FQ, pick one channel/CPU to deliver frames to. 2777 * This may well change at runtime, either through irqbalance or 2778 * through direct user intervention. 2779 */ 2780 rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask); 2781 2782 for (i = 0; i < priv->num_fqs; i++) { 2783 fq = &priv->fq[i]; 2784 switch (fq->type) { 2785 case DPAA2_RX_FQ: 2786 case DPAA2_RX_ERR_FQ: 2787 fq->target_cpu = rx_cpu; 2788 rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask); 2789 if (rx_cpu >= nr_cpu_ids) 2790 rx_cpu = cpumask_first(&priv->dpio_cpumask); 2791 break; 2792 case DPAA2_TX_CONF_FQ: 2793 fq->target_cpu = txc_cpu; 2794 txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask); 2795 if (txc_cpu >= nr_cpu_ids) 2796 txc_cpu = cpumask_first(&priv->dpio_cpumask); 2797 break; 2798 default: 2799 dev_err(dev, "Unknown FQ type: %d\n", fq->type); 2800 } 2801 fq->channel = dpaa2_eth_get_affine_channel(priv, fq->target_cpu); 2802 } 2803 2804 update_xps(priv); 2805} 2806 2807static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv) 2808{ 2809 int i, j; 2810 2811 /* We have one TxConf FQ per Tx flow. 2812 * The number of Tx and Rx queues is the same. 2813 * Tx queues come first in the fq array. 2814 */ 2815 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) { 2816 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ; 2817 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf; 2818 priv->fq[priv->num_fqs++].flowid = (u16)i; 2819 } 2820 2821 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) { 2822 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) { 2823 priv->fq[priv->num_fqs].type = DPAA2_RX_FQ; 2824 priv->fq[priv->num_fqs].consume = dpaa2_eth_rx; 2825 priv->fq[priv->num_fqs].tc = (u8)j; 2826 priv->fq[priv->num_fqs++].flowid = (u16)i; 2827 } 2828 } 2829 2830 /* We have exactly one Rx error queue per DPNI */ 2831 priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ; 2832 priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err; 2833 2834 /* For each FQ, decide on which core to process incoming frames */ 2835 dpaa2_eth_set_fq_affinity(priv); 2836} 2837 2838/* Allocate and configure one buffer pool for each interface */ 2839static int dpaa2_eth_setup_dpbp(struct dpaa2_eth_priv *priv) 2840{ 2841 int err; 2842 struct fsl_mc_device *dpbp_dev; 2843 struct device *dev = priv->net_dev->dev.parent; 2844 struct dpbp_attr dpbp_attrs; 2845 2846 err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP, 2847 &dpbp_dev); 2848 if (err) { 2849 if (err == -ENXIO) 2850 err = -EPROBE_DEFER; 2851 else 2852 dev_err(dev, "DPBP device allocation failed\n"); 2853 return err; 2854 } 2855 2856 priv->dpbp_dev = dpbp_dev; 2857 2858 err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id, 2859 &dpbp_dev->mc_handle); 2860 if (err) { 2861 dev_err(dev, "dpbp_open() failed\n"); 2862 goto err_open; 2863 } 2864 2865 err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle); 2866 if (err) { 2867 dev_err(dev, "dpbp_reset() failed\n"); 2868 goto err_reset; 2869 } 2870 2871 err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle); 2872 if (err) { 2873 dev_err(dev, "dpbp_enable() failed\n"); 2874 goto err_enable; 2875 } 2876 2877 err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle, 2878 &dpbp_attrs); 2879 if (err) { 2880 dev_err(dev, "dpbp_get_attributes() failed\n"); 2881 goto err_get_attr; 2882 } 2883 priv->bpid = dpbp_attrs.bpid; 2884 2885 return 0; 2886 2887err_get_attr: 2888 dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle); 2889err_enable: 2890err_reset: 2891 dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle); 2892err_open: 2893 fsl_mc_object_free(dpbp_dev); 2894 2895 return err; 2896} 2897 2898static void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv) 2899{ 2900 dpaa2_eth_drain_pool(priv); 2901 dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle); 2902 dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle); 2903 fsl_mc_object_free(priv->dpbp_dev); 2904} 2905 2906static int dpaa2_eth_set_buffer_layout(struct dpaa2_eth_priv *priv) 2907{ 2908 struct device *dev = priv->net_dev->dev.parent; 2909 struct dpni_buffer_layout buf_layout = {0}; 2910 u16 rx_buf_align; 2911 int err; 2912 2913 /* We need to check for WRIOP version 1.0.0, but depending on the MC 2914 * version, this number is not always provided correctly on rev1. 2915 * We need to check for both alternatives in this situation. 2916 */ 2917 if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) || 2918 priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0)) 2919 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1; 2920 else 2921 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN; 2922 2923 /* We need to ensure that the buffer size seen by WRIOP is a multiple 2924 * of 64 or 256 bytes depending on the WRIOP version. 2925 */ 2926 priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align); 2927 2928 /* tx buffer */ 2929 buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; 2930 buf_layout.pass_timestamp = true; 2931 buf_layout.pass_frame_status = true; 2932 buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | 2933 DPNI_BUF_LAYOUT_OPT_TIMESTAMP | 2934 DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2935 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, 2936 DPNI_QUEUE_TX, &buf_layout); 2937 if (err) { 2938 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n"); 2939 return err; 2940 } 2941 2942 /* tx-confirm buffer */ 2943 buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP | 2944 DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2945 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, 2946 DPNI_QUEUE_TX_CONFIRM, &buf_layout); 2947 if (err) { 2948 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n"); 2949 return err; 2950 } 2951 2952 /* Now that we've set our tx buffer layout, retrieve the minimum 2953 * required tx data offset. 2954 */ 2955 err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token, 2956 &priv->tx_data_offset); 2957 if (err) { 2958 dev_err(dev, "dpni_get_tx_data_offset() failed\n"); 2959 return err; 2960 } 2961 2962 if ((priv->tx_data_offset % 64) != 0) 2963 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n", 2964 priv->tx_data_offset); 2965 2966 /* rx buffer */ 2967 buf_layout.pass_frame_status = true; 2968 buf_layout.pass_parser_result = true; 2969 buf_layout.data_align = rx_buf_align; 2970 buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv); 2971 buf_layout.private_data_size = 0; 2972 buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | 2973 DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2974 DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | 2975 DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM | 2976 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2977 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, 2978 DPNI_QUEUE_RX, &buf_layout); 2979 if (err) { 2980 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n"); 2981 return err; 2982 } 2983 2984 return 0; 2985} 2986 2987#define DPNI_ENQUEUE_FQID_VER_MAJOR 7 2988#define DPNI_ENQUEUE_FQID_VER_MINOR 9 2989 2990static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv, 2991 struct dpaa2_eth_fq *fq, 2992 struct dpaa2_fd *fd, u8 prio, 2993 u32 num_frames __always_unused, 2994 int *frames_enqueued) 2995{ 2996 int err; 2997 2998 err = dpaa2_io_service_enqueue_qd(fq->channel->dpio, 2999 priv->tx_qdid, prio, 3000 fq->tx_qdbin, fd); 3001 if (!err && frames_enqueued) 3002 *frames_enqueued = 1; 3003 return err; 3004} 3005 3006static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv, 3007 struct dpaa2_eth_fq *fq, 3008 struct dpaa2_fd *fd, 3009 u8 prio, u32 num_frames, 3010 int *frames_enqueued) 3011{ 3012 int err; 3013 3014 err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio, 3015 fq->tx_fqid[prio], 3016 fd, num_frames); 3017 3018 if (err == 0) 3019 return -EBUSY; 3020 3021 if (frames_enqueued) 3022 *frames_enqueued = err; 3023 return 0; 3024} 3025 3026static void dpaa2_eth_set_enqueue_mode(struct dpaa2_eth_priv *priv) 3027{ 3028 if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR, 3029 DPNI_ENQUEUE_FQID_VER_MINOR) < 0) 3030 priv->enqueue = dpaa2_eth_enqueue_qd; 3031 else 3032 priv->enqueue = dpaa2_eth_enqueue_fq_multiple; 3033} 3034 3035static int dpaa2_eth_set_pause(struct dpaa2_eth_priv *priv) 3036{ 3037 struct device *dev = priv->net_dev->dev.parent; 3038 struct dpni_link_cfg link_cfg = {0}; 3039 int err; 3040 3041 /* Get the default link options so we don't override other flags */ 3042 err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg); 3043 if (err) { 3044 dev_err(dev, "dpni_get_link_cfg() failed\n"); 3045 return err; 3046 } 3047 3048 /* By default, enable both Rx and Tx pause frames */ 3049 link_cfg.options |= DPNI_LINK_OPT_PAUSE; 3050 link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 3051 err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg); 3052 if (err) { 3053 dev_err(dev, "dpni_set_link_cfg() failed\n"); 3054 return err; 3055 } 3056 3057 priv->link_state.options = link_cfg.options; 3058 3059 return 0; 3060} 3061 3062static void dpaa2_eth_update_tx_fqids(struct dpaa2_eth_priv *priv) 3063{ 3064 struct dpni_queue_id qid = {0}; 3065 struct dpaa2_eth_fq *fq; 3066 struct dpni_queue queue; 3067 int i, j, err; 3068 3069 /* We only use Tx FQIDs for FQID-based enqueue, so check 3070 * if DPNI version supports it before updating FQIDs 3071 */ 3072 if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR, 3073 DPNI_ENQUEUE_FQID_VER_MINOR) < 0) 3074 return; 3075 3076 for (i = 0; i < priv->num_fqs; i++) { 3077 fq = &priv->fq[i]; 3078 if (fq->type != DPAA2_TX_CONF_FQ) 3079 continue; 3080 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) { 3081 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token, 3082 DPNI_QUEUE_TX, j, fq->flowid, 3083 &queue, &qid); 3084 if (err) 3085 goto out_err; 3086 3087 fq->tx_fqid[j] = qid.fqid; 3088 if (fq->tx_fqid[j] == 0) 3089 goto out_err; 3090 } 3091 } 3092 3093 priv->enqueue = dpaa2_eth_enqueue_fq_multiple; 3094 3095 return; 3096 3097out_err: 3098 netdev_info(priv->net_dev, 3099 "Error reading Tx FQID, fallback to QDID-based enqueue\n"); 3100 priv->enqueue = dpaa2_eth_enqueue_qd; 3101} 3102 3103/* Configure ingress classification based on VLAN PCP */ 3104static int dpaa2_eth_set_vlan_qos(struct dpaa2_eth_priv *priv) 3105{ 3106 struct device *dev = priv->net_dev->dev.parent; 3107 struct dpkg_profile_cfg kg_cfg = {0}; 3108 struct dpni_qos_tbl_cfg qos_cfg = {0}; 3109 struct dpni_rule_cfg key_params; 3110 void *dma_mem, *key, *mask; 3111 u8 key_size = 2; /* VLAN TCI field */ 3112 int i, pcp, err; 3113 3114 /* VLAN-based classification only makes sense if we have multiple 3115 * traffic classes. 3116 * Also, we need to extract just the 3-bit PCP field from the VLAN 3117 * header and we can only do that by using a mask 3118 */ 3119 if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) { 3120 dev_dbg(dev, "VLAN-based QoS classification not supported\n"); 3121 return -EOPNOTSUPP; 3122 } 3123 3124 dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL); 3125 if (!dma_mem) 3126 return -ENOMEM; 3127 3128 kg_cfg.num_extracts = 1; 3129 kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR; 3130 kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN; 3131 kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD; 3132 kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI; 3133 3134 err = dpni_prepare_key_cfg(&kg_cfg, dma_mem); 3135 if (err) { 3136 dev_err(dev, "dpni_prepare_key_cfg failed\n"); 3137 goto out_free_tbl; 3138 } 3139 3140 /* set QoS table */ 3141 qos_cfg.default_tc = 0; 3142 qos_cfg.discard_on_miss = 0; 3143 qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem, 3144 DPAA2_CLASSIFIER_DMA_SIZE, 3145 DMA_TO_DEVICE); 3146 if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) { 3147 dev_err(dev, "QoS table DMA mapping failed\n"); 3148 err = -ENOMEM; 3149 goto out_free_tbl; 3150 } 3151 3152 err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg); 3153 if (err) { 3154 dev_err(dev, "dpni_set_qos_table failed\n"); 3155 goto out_unmap_tbl; 3156 } 3157 3158 /* Add QoS table entries */ 3159 key = kzalloc(key_size * 2, GFP_KERNEL); 3160 if (!key) { 3161 err = -ENOMEM; 3162 goto out_unmap_tbl; 3163 } 3164 mask = key + key_size; 3165 *(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK); 3166 3167 key_params.key_iova = dma_map_single(dev, key, key_size * 2, 3168 DMA_TO_DEVICE); 3169 if (dma_mapping_error(dev, key_params.key_iova)) { 3170 dev_err(dev, "Qos table entry DMA mapping failed\n"); 3171 err = -ENOMEM; 3172 goto out_free_key; 3173 } 3174 3175 key_params.mask_iova = key_params.key_iova + key_size; 3176 key_params.key_size = key_size; 3177 3178 /* We add rules for PCP-based distribution starting with highest 3179 * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic 3180 * classes to accommodate all priority levels, the lowest ones end up 3181 * on TC 0 which was configured as default 3182 */ 3183 for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) { 3184 *(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT); 3185 dma_sync_single_for_device(dev, key_params.key_iova, 3186 key_size * 2, DMA_TO_DEVICE); 3187 3188 err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token, 3189 &key_params, i, i); 3190 if (err) { 3191 dev_err(dev, "dpni_add_qos_entry failed\n"); 3192 dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token); 3193 goto out_unmap_key; 3194 } 3195 } 3196 3197 priv->vlan_cls_enabled = true; 3198 3199 /* Table and key memory is not persistent, clean everything up after 3200 * configuration is finished 3201 */ 3202out_unmap_key: 3203 dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE); 3204out_free_key: 3205 kfree(key); 3206out_unmap_tbl: 3207 dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE, 3208 DMA_TO_DEVICE); 3209out_free_tbl: 3210 kfree(dma_mem); 3211 3212 return err; 3213} 3214 3215/* Configure the DPNI object this interface is associated with */ 3216static int dpaa2_eth_setup_dpni(struct fsl_mc_device *ls_dev) 3217{ 3218 struct device *dev = &ls_dev->dev; 3219 struct dpaa2_eth_priv *priv; 3220 struct net_device *net_dev; 3221 int err; 3222 3223 net_dev = dev_get_drvdata(dev); 3224 priv = netdev_priv(net_dev); 3225 3226 /* get a handle for the DPNI object */ 3227 err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token); 3228 if (err) { 3229 dev_err(dev, "dpni_open() failed\n"); 3230 return err; 3231 } 3232 3233 /* Check if we can work with this DPNI object */ 3234 err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major, 3235 &priv->dpni_ver_minor); 3236 if (err) { 3237 dev_err(dev, "dpni_get_api_version() failed\n"); 3238 goto close; 3239 } 3240 if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) { 3241 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n", 3242 priv->dpni_ver_major, priv->dpni_ver_minor, 3243 DPNI_VER_MAJOR, DPNI_VER_MINOR); 3244 err = -ENOTSUPP; 3245 goto close; 3246 } 3247 3248 ls_dev->mc_io = priv->mc_io; 3249 ls_dev->mc_handle = priv->mc_token; 3250 3251 err = dpni_reset(priv->mc_io, 0, priv->mc_token); 3252 if (err) { 3253 dev_err(dev, "dpni_reset() failed\n"); 3254 goto close; 3255 } 3256 3257 err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token, 3258 &priv->dpni_attrs); 3259 if (err) { 3260 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err); 3261 goto close; 3262 } 3263 3264 err = dpaa2_eth_set_buffer_layout(priv); 3265 if (err) 3266 goto close; 3267 3268 dpaa2_eth_set_enqueue_mode(priv); 3269 3270 /* Enable pause frame support */ 3271 if (dpaa2_eth_has_pause_support(priv)) { 3272 err = dpaa2_eth_set_pause(priv); 3273 if (err) 3274 goto close; 3275 } 3276 3277 err = dpaa2_eth_set_vlan_qos(priv); 3278 if (err && err != -EOPNOTSUPP) 3279 goto close; 3280 3281 priv->cls_rules = devm_kcalloc(dev, dpaa2_eth_fs_count(priv), 3282 sizeof(struct dpaa2_eth_cls_rule), 3283 GFP_KERNEL); 3284 if (!priv->cls_rules) { 3285 err = -ENOMEM; 3286 goto close; 3287 } 3288 3289 return 0; 3290 3291close: 3292 dpni_close(priv->mc_io, 0, priv->mc_token); 3293 3294 return err; 3295} 3296 3297static void dpaa2_eth_free_dpni(struct dpaa2_eth_priv *priv) 3298{ 3299 int err; 3300 3301 err = dpni_reset(priv->mc_io, 0, priv->mc_token); 3302 if (err) 3303 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n", 3304 err); 3305 3306 dpni_close(priv->mc_io, 0, priv->mc_token); 3307} 3308 3309static int dpaa2_eth_setup_rx_flow(struct dpaa2_eth_priv *priv, 3310 struct dpaa2_eth_fq *fq) 3311{ 3312 struct device *dev = priv->net_dev->dev.parent; 3313 struct dpni_queue queue; 3314 struct dpni_queue_id qid; 3315 int err; 3316 3317 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token, 3318 DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid); 3319 if (err) { 3320 dev_err(dev, "dpni_get_queue(RX) failed\n"); 3321 return err; 3322 } 3323 3324 fq->fqid = qid.fqid; 3325 3326 queue.destination.id = fq->channel->dpcon_id; 3327 queue.destination.type = DPNI_DEST_DPCON; 3328 queue.destination.priority = 1; 3329 queue.user_context = (u64)(uintptr_t)fq; 3330 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token, 3331 DPNI_QUEUE_RX, fq->tc, fq->flowid, 3332 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST, 3333 &queue); 3334 if (err) { 3335 dev_err(dev, "dpni_set_queue(RX) failed\n"); 3336 return err; 3337 } 3338 3339 /* xdp_rxq setup */ 3340 /* only once for each channel */ 3341 if (fq->tc > 0) 3342 return 0; 3343 3344 err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev, 3345 fq->flowid); 3346 if (err) { 3347 dev_err(dev, "xdp_rxq_info_reg failed\n"); 3348 return err; 3349 } 3350 3351 err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq, 3352 MEM_TYPE_PAGE_ORDER0, NULL); 3353 if (err) { 3354 dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n"); 3355 return err; 3356 } 3357 3358 return 0; 3359} 3360 3361static int dpaa2_eth_setup_tx_flow(struct dpaa2_eth_priv *priv, 3362 struct dpaa2_eth_fq *fq) 3363{ 3364 struct device *dev = priv->net_dev->dev.parent; 3365 struct dpni_queue queue; 3366 struct dpni_queue_id qid; 3367 int i, err; 3368 3369 for (i = 0; i < dpaa2_eth_tc_count(priv); i++) { 3370 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token, 3371 DPNI_QUEUE_TX, i, fq->flowid, 3372 &queue, &qid); 3373 if (err) { 3374 dev_err(dev, "dpni_get_queue(TX) failed\n"); 3375 return err; 3376 } 3377 fq->tx_fqid[i] = qid.fqid; 3378 } 3379 3380 /* All Tx queues belonging to the same flowid have the same qdbin */ 3381 fq->tx_qdbin = qid.qdbin; 3382 3383 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token, 3384 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid, 3385 &queue, &qid); 3386 if (err) { 3387 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n"); 3388 return err; 3389 } 3390 3391 fq->fqid = qid.fqid; 3392 3393 queue.destination.id = fq->channel->dpcon_id; 3394 queue.destination.type = DPNI_DEST_DPCON; 3395 queue.destination.priority = 0; 3396 queue.user_context = (u64)(uintptr_t)fq; 3397 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token, 3398 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid, 3399 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST, 3400 &queue); 3401 if (err) { 3402 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n"); 3403 return err; 3404 } 3405 3406 return 0; 3407} 3408 3409static int setup_rx_err_flow(struct dpaa2_eth_priv *priv, 3410 struct dpaa2_eth_fq *fq) 3411{ 3412 struct device *dev = priv->net_dev->dev.parent; 3413 struct dpni_queue q = { { 0 } }; 3414 struct dpni_queue_id qid; 3415 u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST; 3416 int err; 3417 3418 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token, 3419 DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid); 3420 if (err) { 3421 dev_err(dev, "dpni_get_queue() failed (%d)\n", err); 3422 return err; 3423 } 3424 3425 fq->fqid = qid.fqid; 3426 3427 q.destination.id = fq->channel->dpcon_id; 3428 q.destination.type = DPNI_DEST_DPCON; 3429 q.destination.priority = 1; 3430 q.user_context = (u64)(uintptr_t)fq; 3431 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token, 3432 DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q); 3433 if (err) { 3434 dev_err(dev, "dpni_set_queue() failed (%d)\n", err); 3435 return err; 3436 } 3437 3438 return 0; 3439} 3440 3441/* Supported header fields for Rx hash distribution key */ 3442static const struct dpaa2_eth_dist_fields dist_fields[] = { 3443 { 3444 /* L2 header */ 3445 .rxnfc_field = RXH_L2DA, 3446 .cls_prot = NET_PROT_ETH, 3447 .cls_field = NH_FLD_ETH_DA, 3448 .id = DPAA2_ETH_DIST_ETHDST, 3449 .size = 6, 3450 }, { 3451 .cls_prot = NET_PROT_ETH, 3452 .cls_field = NH_FLD_ETH_SA, 3453 .id = DPAA2_ETH_DIST_ETHSRC, 3454 .size = 6, 3455 }, { 3456 /* This is the last ethertype field parsed: 3457 * depending on frame format, it can be the MAC ethertype 3458 * or the VLAN etype. 3459 */ 3460 .cls_prot = NET_PROT_ETH, 3461 .cls_field = NH_FLD_ETH_TYPE, 3462 .id = DPAA2_ETH_DIST_ETHTYPE, 3463 .size = 2, 3464 }, { 3465 /* VLAN header */ 3466 .rxnfc_field = RXH_VLAN, 3467 .cls_prot = NET_PROT_VLAN, 3468 .cls_field = NH_FLD_VLAN_TCI, 3469 .id = DPAA2_ETH_DIST_VLAN, 3470 .size = 2, 3471 }, { 3472 /* IP header */ 3473 .rxnfc_field = RXH_IP_SRC, 3474 .cls_prot = NET_PROT_IP, 3475 .cls_field = NH_FLD_IP_SRC, 3476 .id = DPAA2_ETH_DIST_IPSRC, 3477 .size = 4, 3478 }, { 3479 .rxnfc_field = RXH_IP_DST, 3480 .cls_prot = NET_PROT_IP, 3481 .cls_field = NH_FLD_IP_DST, 3482 .id = DPAA2_ETH_DIST_IPDST, 3483 .size = 4, 3484 }, { 3485 .rxnfc_field = RXH_L3_PROTO, 3486 .cls_prot = NET_PROT_IP, 3487 .cls_field = NH_FLD_IP_PROTO, 3488 .id = DPAA2_ETH_DIST_IPPROTO, 3489 .size = 1, 3490 }, { 3491 /* Using UDP ports, this is functionally equivalent to raw 3492 * byte pairs from L4 header. 3493 */ 3494 .rxnfc_field = RXH_L4_B_0_1, 3495 .cls_prot = NET_PROT_UDP, 3496 .cls_field = NH_FLD_UDP_PORT_SRC, 3497 .id = DPAA2_ETH_DIST_L4SRC, 3498 .size = 2, 3499 }, { 3500 .rxnfc_field = RXH_L4_B_2_3, 3501 .cls_prot = NET_PROT_UDP, 3502 .cls_field = NH_FLD_UDP_PORT_DST, 3503 .id = DPAA2_ETH_DIST_L4DST, 3504 .size = 2, 3505 }, 3506}; 3507 3508/* Configure the Rx hash key using the legacy API */ 3509static int dpaa2_eth_config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key) 3510{ 3511 struct device *dev = priv->net_dev->dev.parent; 3512 struct dpni_rx_tc_dist_cfg dist_cfg; 3513 int i, err = 0; 3514 3515 memset(&dist_cfg, 0, sizeof(dist_cfg)); 3516 3517 dist_cfg.key_cfg_iova = key; 3518 dist_cfg.dist_size = dpaa2_eth_queue_count(priv); 3519 dist_cfg.dist_mode = DPNI_DIST_MODE_HASH; 3520 3521 for (i = 0; i < dpaa2_eth_tc_count(priv); i++) { 3522 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 3523 i, &dist_cfg); 3524 if (err) { 3525 dev_err(dev, "dpni_set_rx_tc_dist failed\n"); 3526 break; 3527 } 3528 } 3529 3530 return err; 3531} 3532 3533/* Configure the Rx hash key using the new API */ 3534static int dpaa2_eth_config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key) 3535{ 3536 struct device *dev = priv->net_dev->dev.parent; 3537 struct dpni_rx_dist_cfg dist_cfg; 3538 int i, err = 0; 3539 3540 memset(&dist_cfg, 0, sizeof(dist_cfg)); 3541 3542 dist_cfg.key_cfg_iova = key; 3543 dist_cfg.dist_size = dpaa2_eth_queue_count(priv); 3544 dist_cfg.enable = 1; 3545 3546 for (i = 0; i < dpaa2_eth_tc_count(priv); i++) { 3547 dist_cfg.tc = i; 3548 err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token, 3549 &dist_cfg); 3550 if (err) { 3551 dev_err(dev, "dpni_set_rx_hash_dist failed\n"); 3552 break; 3553 } 3554 3555 /* If the flow steering / hashing key is shared between all 3556 * traffic classes, install it just once 3557 */ 3558 if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS) 3559 break; 3560 } 3561 3562 return err; 3563} 3564 3565/* Configure the Rx flow classification key */ 3566static int dpaa2_eth_config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key) 3567{ 3568 struct device *dev = priv->net_dev->dev.parent; 3569 struct dpni_rx_dist_cfg dist_cfg; 3570 int i, err = 0; 3571 3572 memset(&dist_cfg, 0, sizeof(dist_cfg)); 3573 3574 dist_cfg.key_cfg_iova = key; 3575 dist_cfg.dist_size = dpaa2_eth_queue_count(priv); 3576 dist_cfg.enable = 1; 3577 3578 for (i = 0; i < dpaa2_eth_tc_count(priv); i++) { 3579 dist_cfg.tc = i; 3580 err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token, 3581 &dist_cfg); 3582 if (err) { 3583 dev_err(dev, "dpni_set_rx_fs_dist failed\n"); 3584 break; 3585 } 3586 3587 /* If the flow steering / hashing key is shared between all 3588 * traffic classes, install it just once 3589 */ 3590 if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS) 3591 break; 3592 } 3593 3594 return err; 3595} 3596 3597/* Size of the Rx flow classification key */ 3598int dpaa2_eth_cls_key_size(u64 fields) 3599{ 3600 int i, size = 0; 3601 3602 for (i = 0; i < ARRAY_SIZE(dist_fields); i++) { 3603 if (!(fields & dist_fields[i].id)) 3604 continue; 3605 size += dist_fields[i].size; 3606 } 3607 3608 return size; 3609} 3610 3611/* Offset of header field in Rx classification key */ 3612int dpaa2_eth_cls_fld_off(int prot, int field) 3613{ 3614 int i, off = 0; 3615 3616 for (i = 0; i < ARRAY_SIZE(dist_fields); i++) { 3617 if (dist_fields[i].cls_prot == prot && 3618 dist_fields[i].cls_field == field) 3619 return off; 3620 off += dist_fields[i].size; 3621 } 3622 3623 WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n"); 3624 return 0; 3625} 3626 3627/* Prune unused fields from the classification rule. 3628 * Used when masking is not supported 3629 */ 3630void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields) 3631{ 3632 int off = 0, new_off = 0; 3633 int i, size; 3634 3635 for (i = 0; i < ARRAY_SIZE(dist_fields); i++) { 3636 size = dist_fields[i].size; 3637 if (dist_fields[i].id & fields) { 3638 memcpy(key_mem + new_off, key_mem + off, size); 3639 new_off += size; 3640 } 3641 off += size; 3642 } 3643} 3644 3645/* Set Rx distribution (hash or flow classification) key 3646 * flags is a combination of RXH_ bits 3647 */ 3648static int dpaa2_eth_set_dist_key(struct net_device *net_dev, 3649 enum dpaa2_eth_rx_dist type, u64 flags) 3650{ 3651 struct device *dev = net_dev->dev.parent; 3652 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 3653 struct dpkg_profile_cfg cls_cfg; 3654 u32 rx_hash_fields = 0; 3655 dma_addr_t key_iova; 3656 u8 *dma_mem; 3657 int i; 3658 int err = 0; 3659 3660 memset(&cls_cfg, 0, sizeof(cls_cfg)); 3661 3662 for (i = 0; i < ARRAY_SIZE(dist_fields); i++) { 3663 struct dpkg_extract *key = 3664 &cls_cfg.extracts[cls_cfg.num_extracts]; 3665 3666 /* For both Rx hashing and classification keys 3667 * we set only the selected fields. 3668 */ 3669 if (!(flags & dist_fields[i].id)) 3670 continue; 3671 if (type == DPAA2_ETH_RX_DIST_HASH) 3672 rx_hash_fields |= dist_fields[i].rxnfc_field; 3673 3674 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) { 3675 dev_err(dev, "error adding key extraction rule, too many rules?\n"); 3676 return -E2BIG; 3677 } 3678 3679 key->type = DPKG_EXTRACT_FROM_HDR; 3680 key->extract.from_hdr.prot = dist_fields[i].cls_prot; 3681 key->extract.from_hdr.type = DPKG_FULL_FIELD; 3682 key->extract.from_hdr.field = dist_fields[i].cls_field; 3683 cls_cfg.num_extracts++; 3684 } 3685 3686 dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL); 3687 if (!dma_mem) 3688 return -ENOMEM; 3689 3690 err = dpni_prepare_key_cfg(&cls_cfg, dma_mem); 3691 if (err) { 3692 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err); 3693 goto free_key; 3694 } 3695 3696 /* Prepare for setting the rx dist */ 3697 key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE, 3698 DMA_TO_DEVICE); 3699 if (dma_mapping_error(dev, key_iova)) { 3700 dev_err(dev, "DMA mapping failed\n"); 3701 err = -ENOMEM; 3702 goto free_key; 3703 } 3704 3705 if (type == DPAA2_ETH_RX_DIST_HASH) { 3706 if (dpaa2_eth_has_legacy_dist(priv)) 3707 err = dpaa2_eth_config_legacy_hash_key(priv, key_iova); 3708 else 3709 err = dpaa2_eth_config_hash_key(priv, key_iova); 3710 } else { 3711 err = dpaa2_eth_config_cls_key(priv, key_iova); 3712 } 3713 3714 dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE, 3715 DMA_TO_DEVICE); 3716 if (!err && type == DPAA2_ETH_RX_DIST_HASH) 3717 priv->rx_hash_fields = rx_hash_fields; 3718 3719free_key: 3720 kfree(dma_mem); 3721 return err; 3722} 3723 3724int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) 3725{ 3726 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 3727 u64 key = 0; 3728 int i; 3729 3730 if (!dpaa2_eth_hash_enabled(priv)) 3731 return -EOPNOTSUPP; 3732 3733 for (i = 0; i < ARRAY_SIZE(dist_fields); i++) 3734 if (dist_fields[i].rxnfc_field & flags) 3735 key |= dist_fields[i].id; 3736 3737 return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key); 3738} 3739 3740int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags) 3741{ 3742 return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags); 3743} 3744 3745static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv) 3746{ 3747 struct device *dev = priv->net_dev->dev.parent; 3748 int err; 3749 3750 /* Check if we actually support Rx flow classification */ 3751 if (dpaa2_eth_has_legacy_dist(priv)) { 3752 dev_dbg(dev, "Rx cls not supported by current MC version\n"); 3753 return -EOPNOTSUPP; 3754 } 3755 3756 if (!dpaa2_eth_fs_enabled(priv)) { 3757 dev_dbg(dev, "Rx cls disabled in DPNI options\n"); 3758 return -EOPNOTSUPP; 3759 } 3760 3761 if (!dpaa2_eth_hash_enabled(priv)) { 3762 dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n"); 3763 return -EOPNOTSUPP; 3764 } 3765 3766 /* If there is no support for masking in the classification table, 3767 * we don't set a default key, as it will depend on the rules 3768 * added by the user at runtime. 3769 */ 3770 if (!dpaa2_eth_fs_mask_enabled(priv)) 3771 goto out; 3772 3773 err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL); 3774 if (err) 3775 return err; 3776 3777out: 3778 priv->rx_cls_enabled = 1; 3779 3780 return 0; 3781} 3782 3783/* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs, 3784 * frame queues and channels 3785 */ 3786static int dpaa2_eth_bind_dpni(struct dpaa2_eth_priv *priv) 3787{ 3788 struct net_device *net_dev = priv->net_dev; 3789 struct device *dev = net_dev->dev.parent; 3790 struct dpni_pools_cfg pools_params; 3791 struct dpni_error_cfg err_cfg; 3792 int err = 0; 3793 int i; 3794 3795 pools_params.num_dpbp = 1; 3796 pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id; 3797 pools_params.pools[0].backup_pool = 0; 3798 pools_params.pools[0].buffer_size = priv->rx_buf_size; 3799 err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params); 3800 if (err) { 3801 dev_err(dev, "dpni_set_pools() failed\n"); 3802 return err; 3803 } 3804 3805 /* have the interface implicitly distribute traffic based on 3806 * the default hash key 3807 */ 3808 err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT); 3809 if (err && err != -EOPNOTSUPP) 3810 dev_err(dev, "Failed to configure hashing\n"); 3811 3812 /* Configure the flow classification key; it includes all 3813 * supported header fields and cannot be modified at runtime 3814 */ 3815 err = dpaa2_eth_set_default_cls(priv); 3816 if (err && err != -EOPNOTSUPP) 3817 dev_err(dev, "Failed to configure Rx classification key\n"); 3818 3819 /* Configure handling of error frames */ 3820 err_cfg.errors = DPAA2_FAS_RX_ERR_MASK; 3821 err_cfg.set_frame_annotation = 1; 3822 err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD; 3823 err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token, 3824 &err_cfg); 3825 if (err) { 3826 dev_err(dev, "dpni_set_errors_behavior failed\n"); 3827 return err; 3828 } 3829 3830 /* Configure Rx and Tx conf queues to generate CDANs */ 3831 for (i = 0; i < priv->num_fqs; i++) { 3832 switch (priv->fq[i].type) { 3833 case DPAA2_RX_FQ: 3834 err = dpaa2_eth_setup_rx_flow(priv, &priv->fq[i]); 3835 break; 3836 case DPAA2_TX_CONF_FQ: 3837 err = dpaa2_eth_setup_tx_flow(priv, &priv->fq[i]); 3838 break; 3839 case DPAA2_RX_ERR_FQ: 3840 err = setup_rx_err_flow(priv, &priv->fq[i]); 3841 break; 3842 default: 3843 dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type); 3844 return -EINVAL; 3845 } 3846 if (err) 3847 return err; 3848 } 3849 3850 err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token, 3851 DPNI_QUEUE_TX, &priv->tx_qdid); 3852 if (err) { 3853 dev_err(dev, "dpni_get_qdid() failed\n"); 3854 return err; 3855 } 3856 3857 return 0; 3858} 3859 3860/* Allocate rings for storing incoming frame descriptors */ 3861static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv) 3862{ 3863 struct net_device *net_dev = priv->net_dev; 3864 struct device *dev = net_dev->dev.parent; 3865 int i; 3866 3867 for (i = 0; i < priv->num_channels; i++) { 3868 priv->channel[i]->store = 3869 dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev); 3870 if (!priv->channel[i]->store) { 3871 netdev_err(net_dev, "dpaa2_io_store_create() failed\n"); 3872 goto err_ring; 3873 } 3874 } 3875 3876 return 0; 3877 3878err_ring: 3879 for (i = 0; i < priv->num_channels; i++) { 3880 if (!priv->channel[i]->store) 3881 break; 3882 dpaa2_io_store_destroy(priv->channel[i]->store); 3883 } 3884 3885 return -ENOMEM; 3886} 3887 3888static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv) 3889{ 3890 int i; 3891 3892 for (i = 0; i < priv->num_channels; i++) 3893 dpaa2_io_store_destroy(priv->channel[i]->store); 3894} 3895 3896static int dpaa2_eth_set_mac_addr(struct dpaa2_eth_priv *priv) 3897{ 3898 struct net_device *net_dev = priv->net_dev; 3899 struct device *dev = net_dev->dev.parent; 3900 u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN]; 3901 int err; 3902 3903 /* Get firmware address, if any */ 3904 err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr); 3905 if (err) { 3906 dev_err(dev, "dpni_get_port_mac_addr() failed\n"); 3907 return err; 3908 } 3909 3910 /* Get DPNI attributes address, if any */ 3911 err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token, 3912 dpni_mac_addr); 3913 if (err) { 3914 dev_err(dev, "dpni_get_primary_mac_addr() failed\n"); 3915 return err; 3916 } 3917 3918 /* First check if firmware has any address configured by bootloader */ 3919 if (!is_zero_ether_addr(mac_addr)) { 3920 /* If the DPMAC addr != DPNI addr, update it */ 3921 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) { 3922 err = dpni_set_primary_mac_addr(priv->mc_io, 0, 3923 priv->mc_token, 3924 mac_addr); 3925 if (err) { 3926 dev_err(dev, "dpni_set_primary_mac_addr() failed\n"); 3927 return err; 3928 } 3929 } 3930 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); 3931 } else if (is_zero_ether_addr(dpni_mac_addr)) { 3932 /* No MAC address configured, fill in net_dev->dev_addr 3933 * with a random one 3934 */ 3935 eth_hw_addr_random(net_dev); 3936 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n"); 3937 3938 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token, 3939 net_dev->dev_addr); 3940 if (err) { 3941 dev_err(dev, "dpni_set_primary_mac_addr() failed\n"); 3942 return err; 3943 } 3944 3945 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all 3946 * practical purposes, this will be our "permanent" mac address, 3947 * at least until the next reboot. This move will also permit 3948 * register_netdevice() to properly fill up net_dev->perm_addr. 3949 */ 3950 net_dev->addr_assign_type = NET_ADDR_PERM; 3951 } else { 3952 /* NET_ADDR_PERM is default, all we have to do is 3953 * fill in the device addr. 3954 */ 3955 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len); 3956 } 3957 3958 return 0; 3959} 3960 3961static int dpaa2_eth_netdev_init(struct net_device *net_dev) 3962{ 3963 struct device *dev = net_dev->dev.parent; 3964 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 3965 u32 options = priv->dpni_attrs.options; 3966 u64 supported = 0, not_supported = 0; 3967 u8 bcast_addr[ETH_ALEN]; 3968 u8 num_queues; 3969 int err; 3970 3971 net_dev->netdev_ops = &dpaa2_eth_ops; 3972 net_dev->ethtool_ops = &dpaa2_ethtool_ops; 3973 3974 err = dpaa2_eth_set_mac_addr(priv); 3975 if (err) 3976 return err; 3977 3978 /* Explicitly add the broadcast address to the MAC filtering table */ 3979 eth_broadcast_addr(bcast_addr); 3980 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr); 3981 if (err) { 3982 dev_err(dev, "dpni_add_mac_addr() failed\n"); 3983 return err; 3984 } 3985 3986 /* Set MTU upper limit; lower limit is 68B (default value) */ 3987 net_dev->max_mtu = DPAA2_ETH_MAX_MTU; 3988 err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, 3989 DPAA2_ETH_MFL); 3990 if (err) { 3991 dev_err(dev, "dpni_set_max_frame_length() failed\n"); 3992 return err; 3993 } 3994 3995 /* Set actual number of queues in the net device */ 3996 num_queues = dpaa2_eth_queue_count(priv); 3997 err = netif_set_real_num_tx_queues(net_dev, num_queues); 3998 if (err) { 3999 dev_err(dev, "netif_set_real_num_tx_queues() failed\n"); 4000 return err; 4001 } 4002 err = netif_set_real_num_rx_queues(net_dev, num_queues); 4003 if (err) { 4004 dev_err(dev, "netif_set_real_num_rx_queues() failed\n"); 4005 return err; 4006 } 4007 4008 /* Capabilities listing */ 4009 supported |= IFF_LIVE_ADDR_CHANGE; 4010 4011 if (options & DPNI_OPT_NO_MAC_FILTER) 4012 not_supported |= IFF_UNICAST_FLT; 4013 else 4014 supported |= IFF_UNICAST_FLT; 4015 4016 net_dev->priv_flags |= supported; 4017 net_dev->priv_flags &= ~not_supported; 4018 4019 /* Features */ 4020 net_dev->features = NETIF_F_RXCSUM | 4021 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4022 NETIF_F_SG | NETIF_F_HIGHDMA | 4023 NETIF_F_LLTX | NETIF_F_HW_TC; 4024 net_dev->hw_features = net_dev->features; 4025 4026 return 0; 4027} 4028 4029static int dpaa2_eth_poll_link_state(void *arg) 4030{ 4031 struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg; 4032 int err; 4033 4034 while (!kthread_should_stop()) { 4035 err = dpaa2_eth_link_state_update(priv); 4036 if (unlikely(err)) 4037 return err; 4038 4039 msleep(DPAA2_ETH_LINK_STATE_REFRESH); 4040 } 4041 4042 return 0; 4043} 4044 4045static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv) 4046{ 4047 struct fsl_mc_device *dpni_dev, *dpmac_dev; 4048 struct dpaa2_mac *mac; 4049 int err; 4050 4051 dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent); 4052 dpmac_dev = fsl_mc_get_endpoint(dpni_dev); 4053 if (IS_ERR_OR_NULL(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type) 4054 return 0; 4055 4056 if (dpaa2_mac_is_type_fixed(dpmac_dev, priv->mc_io)) 4057 return 0; 4058 4059 mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL); 4060 if (!mac) 4061 return -ENOMEM; 4062 4063 mac->mc_dev = dpmac_dev; 4064 mac->mc_io = priv->mc_io; 4065 mac->net_dev = priv->net_dev; 4066 4067 err = dpaa2_mac_connect(mac); 4068 if (err) { 4069 netdev_err(priv->net_dev, "Error connecting to the MAC endpoint\n"); 4070 kfree(mac); 4071 return err; 4072 } 4073 priv->mac = mac; 4074 4075 return 0; 4076} 4077 4078static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv) 4079{ 4080 if (!priv->mac) 4081 return; 4082 4083 dpaa2_mac_disconnect(priv->mac); 4084 kfree(priv->mac); 4085 priv->mac = NULL; 4086} 4087 4088static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) 4089{ 4090 u32 status = ~0; 4091 struct device *dev = (struct device *)arg; 4092 struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev); 4093 struct net_device *net_dev = dev_get_drvdata(dev); 4094 struct dpaa2_eth_priv *priv = netdev_priv(net_dev); 4095 int err; 4096 4097 err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, 4098 DPNI_IRQ_INDEX, &status); 4099 if (unlikely(err)) { 4100 netdev_err(net_dev, "Can't get irq status (err %d)\n", err); 4101 return IRQ_HANDLED; 4102 } 4103 4104 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) 4105 dpaa2_eth_link_state_update(netdev_priv(net_dev)); 4106 4107 if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) { 4108 dpaa2_eth_set_mac_addr(netdev_priv(net_dev)); 4109 dpaa2_eth_update_tx_fqids(priv); 4110 4111 rtnl_lock(); 4112 if (priv->mac) 4113 dpaa2_eth_disconnect_mac(priv); 4114 else 4115 dpaa2_eth_connect_mac(priv); 4116 rtnl_unlock(); 4117 } 4118 4119 return IRQ_HANDLED; 4120} 4121 4122static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev) 4123{ 4124 int err = 0; 4125 struct fsl_mc_device_irq *irq; 4126 4127 err = fsl_mc_allocate_irqs(ls_dev); 4128 if (err) { 4129 dev_err(&ls_dev->dev, "MC irqs allocation failed\n"); 4130 return err; 4131 } 4132 4133 irq = ls_dev->irqs[0]; 4134 err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq, 4135 NULL, dpni_irq0_handler_thread, 4136 IRQF_NO_SUSPEND | IRQF_ONESHOT, 4137 dev_name(&ls_dev->dev), &ls_dev->dev); 4138 if (err < 0) { 4139 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err); 4140 goto free_mc_irq; 4141 } 4142 4143 err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle, 4144 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED | 4145 DPNI_IRQ_EVENT_ENDPOINT_CHANGED); 4146 if (err < 0) { 4147 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err); 4148 goto free_irq; 4149 } 4150 4151 err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle, 4152 DPNI_IRQ_INDEX, 1); 4153 if (err < 0) { 4154 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err); 4155 goto free_irq; 4156 } 4157 4158 return 0; 4159 4160free_irq: 4161 devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev); 4162free_mc_irq: 4163 fsl_mc_free_irqs(ls_dev); 4164 4165 return err; 4166} 4167 4168static void dpaa2_eth_add_ch_napi(struct dpaa2_eth_priv *priv) 4169{ 4170 int i; 4171 struct dpaa2_eth_channel *ch; 4172 4173 for (i = 0; i < priv->num_channels; i++) { 4174 ch = priv->channel[i]; 4175 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */ 4176 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll, 4177 NAPI_POLL_WEIGHT); 4178 } 4179} 4180 4181static void dpaa2_eth_del_ch_napi(struct dpaa2_eth_priv *priv) 4182{ 4183 int i; 4184 struct dpaa2_eth_channel *ch; 4185 4186 for (i = 0; i < priv->num_channels; i++) { 4187 ch = priv->channel[i]; 4188 netif_napi_del(&ch->napi); 4189 } 4190} 4191 4192static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev) 4193{ 4194 struct device *dev; 4195 struct net_device *net_dev = NULL; 4196 struct dpaa2_eth_priv *priv = NULL; 4197 int err = 0; 4198 4199 dev = &dpni_dev->dev; 4200 4201 /* Net device */ 4202 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES); 4203 if (!net_dev) { 4204 dev_err(dev, "alloc_etherdev_mq() failed\n"); 4205 return -ENOMEM; 4206 } 4207 4208 SET_NETDEV_DEV(net_dev, dev); 4209 dev_set_drvdata(dev, net_dev); 4210 4211 priv = netdev_priv(net_dev); 4212 priv->net_dev = net_dev; 4213 4214 priv->iommu_domain = iommu_get_domain_for_dev(dev); 4215 4216 priv->tx_tstamp_type = HWTSTAMP_TX_OFF; 4217 priv->rx_tstamp = false; 4218 4219 priv->dpaa2_ptp_wq = alloc_workqueue("dpaa2_ptp_wq", 0, 0); 4220 if (!priv->dpaa2_ptp_wq) { 4221 err = -ENOMEM; 4222 goto err_wq_alloc; 4223 } 4224 4225 INIT_WORK(&priv->tx_onestep_tstamp, dpaa2_eth_tx_onestep_tstamp); 4226 mutex_init(&priv->onestep_tstamp_lock); 4227 skb_queue_head_init(&priv->tx_skbs); 4228 4229 /* Obtain a MC portal */ 4230 err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, 4231 &priv->mc_io); 4232 if (err) { 4233 if (err == -ENXIO) 4234 err = -EPROBE_DEFER; 4235 else 4236 dev_err(dev, "MC portal allocation failed\n"); 4237 goto err_portal_alloc; 4238 } 4239 4240 /* MC objects initialization and configuration */ 4241 err = dpaa2_eth_setup_dpni(dpni_dev); 4242 if (err) 4243 goto err_dpni_setup; 4244 4245 err = dpaa2_eth_setup_dpio(priv); 4246 if (err) 4247 goto err_dpio_setup; 4248 4249 dpaa2_eth_setup_fqs(priv); 4250 4251 err = dpaa2_eth_setup_dpbp(priv); 4252 if (err) 4253 goto err_dpbp_setup; 4254 4255 err = dpaa2_eth_bind_dpni(priv); 4256 if (err) 4257 goto err_bind; 4258 4259 /* Add a NAPI context for each channel */ 4260 dpaa2_eth_add_ch_napi(priv); 4261 4262 /* Percpu statistics */ 4263 priv->percpu_stats = alloc_percpu(*priv->percpu_stats); 4264 if (!priv->percpu_stats) { 4265 dev_err(dev, "alloc_percpu(percpu_stats) failed\n"); 4266 err = -ENOMEM; 4267 goto err_alloc_percpu_stats; 4268 } 4269 priv->percpu_extras = alloc_percpu(*priv->percpu_extras); 4270 if (!priv->percpu_extras) { 4271 dev_err(dev, "alloc_percpu(percpu_extras) failed\n"); 4272 err = -ENOMEM; 4273 goto err_alloc_percpu_extras; 4274 } 4275 4276 priv->sgt_cache = alloc_percpu(*priv->sgt_cache); 4277 if (!priv->sgt_cache) { 4278 dev_err(dev, "alloc_percpu(sgt_cache) failed\n"); 4279 err = -ENOMEM; 4280 goto err_alloc_sgt_cache; 4281 } 4282 4283 err = dpaa2_eth_netdev_init(net_dev); 4284 if (err) 4285 goto err_netdev_init; 4286 4287 /* Configure checksum offload based on current interface flags */ 4288 err = dpaa2_eth_set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM)); 4289 if (err) 4290 goto err_csum; 4291 4292 err = dpaa2_eth_set_tx_csum(priv, 4293 !!(net_dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))); 4294 if (err) 4295 goto err_csum; 4296 4297 err = dpaa2_eth_alloc_rings(priv); 4298 if (err) 4299 goto err_alloc_rings; 4300 4301#ifdef CONFIG_FSL_DPAA2_ETH_DCB 4302 if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) { 4303 priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE; 4304 net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops; 4305 } else { 4306 dev_dbg(dev, "PFC not supported\n"); 4307 } 4308#endif 4309 4310 err = dpaa2_eth_setup_irqs(dpni_dev); 4311 if (err) { 4312 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n"); 4313 priv->poll_thread = kthread_run(dpaa2_eth_poll_link_state, priv, 4314 "%s_poll_link", net_dev->name); 4315 if (IS_ERR(priv->poll_thread)) { 4316 dev_err(dev, "Error starting polling thread\n"); 4317 goto err_poll_thread; 4318 } 4319 priv->do_link_poll = true; 4320 } 4321 4322 err = dpaa2_eth_connect_mac(priv); 4323 if (err) 4324 goto err_connect_mac; 4325 4326 err = dpaa2_eth_dl_register(priv); 4327 if (err) 4328 goto err_dl_register; 4329 4330 err = dpaa2_eth_dl_traps_register(priv); 4331 if (err) 4332 goto err_dl_trap_register; 4333 4334 err = dpaa2_eth_dl_port_add(priv); 4335 if (err) 4336 goto err_dl_port_add; 4337 4338 net_dev->needed_headroom = DPAA2_ETH_SWA_SIZE + DPAA2_ETH_TX_BUF_ALIGN; 4339 4340 err = register_netdev(net_dev); 4341 if (err < 0) { 4342 dev_err(dev, "register_netdev() failed\n"); 4343 goto err_netdev_reg; 4344 } 4345 4346#ifdef CONFIG_DEBUG_FS 4347 dpaa2_dbg_add(priv); 4348#endif 4349 4350 dev_info(dev, "Probed interface %s\n", net_dev->name); 4351 return 0; 4352 4353err_netdev_reg: 4354 dpaa2_eth_dl_port_del(priv); 4355err_dl_port_add: 4356 dpaa2_eth_dl_traps_unregister(priv); 4357err_dl_trap_register: 4358 dpaa2_eth_dl_unregister(priv); 4359err_dl_register: 4360 dpaa2_eth_disconnect_mac(priv); 4361err_connect_mac: 4362 if (priv->do_link_poll) 4363 kthread_stop(priv->poll_thread); 4364 else 4365 fsl_mc_free_irqs(dpni_dev); 4366err_poll_thread: 4367 dpaa2_eth_free_rings(priv); 4368err_alloc_rings: 4369err_csum: 4370err_netdev_init: 4371 free_percpu(priv->sgt_cache); 4372err_alloc_sgt_cache: 4373 free_percpu(priv->percpu_extras); 4374err_alloc_percpu_extras: 4375 free_percpu(priv->percpu_stats); 4376err_alloc_percpu_stats: 4377 dpaa2_eth_del_ch_napi(priv); 4378err_bind: 4379 dpaa2_eth_free_dpbp(priv); 4380err_dpbp_setup: 4381 dpaa2_eth_free_dpio(priv); 4382err_dpio_setup: 4383 dpaa2_eth_free_dpni(priv); 4384err_dpni_setup: 4385 fsl_mc_portal_free(priv->mc_io); 4386err_portal_alloc: 4387 destroy_workqueue(priv->dpaa2_ptp_wq); 4388err_wq_alloc: 4389 dev_set_drvdata(dev, NULL); 4390 free_netdev(net_dev); 4391 4392 return err; 4393} 4394 4395static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) 4396{ 4397 struct device *dev; 4398 struct net_device *net_dev; 4399 struct dpaa2_eth_priv *priv; 4400 4401 dev = &ls_dev->dev; 4402 net_dev = dev_get_drvdata(dev); 4403 priv = netdev_priv(net_dev); 4404 4405#ifdef CONFIG_DEBUG_FS 4406 dpaa2_dbg_remove(priv); 4407#endif 4408 rtnl_lock(); 4409 dpaa2_eth_disconnect_mac(priv); 4410 rtnl_unlock(); 4411 4412 unregister_netdev(net_dev); 4413 4414 dpaa2_eth_dl_port_del(priv); 4415 dpaa2_eth_dl_traps_unregister(priv); 4416 dpaa2_eth_dl_unregister(priv); 4417 4418 if (priv->do_link_poll) 4419 kthread_stop(priv->poll_thread); 4420 else 4421 fsl_mc_free_irqs(ls_dev); 4422 4423 dpaa2_eth_free_rings(priv); 4424 free_percpu(priv->sgt_cache); 4425 free_percpu(priv->percpu_stats); 4426 free_percpu(priv->percpu_extras); 4427 4428 dpaa2_eth_del_ch_napi(priv); 4429 dpaa2_eth_free_dpbp(priv); 4430 dpaa2_eth_free_dpio(priv); 4431 dpaa2_eth_free_dpni(priv); 4432 4433 fsl_mc_portal_free(priv->mc_io); 4434 4435 destroy_workqueue(priv->dpaa2_ptp_wq); 4436 4437 dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name); 4438 4439 free_netdev(net_dev); 4440 4441 return 0; 4442} 4443 4444static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = { 4445 { 4446 .vendor = FSL_MC_VENDOR_FREESCALE, 4447 .obj_type = "dpni", 4448 }, 4449 { .vendor = 0x0 } 4450}; 4451MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table); 4452 4453static struct fsl_mc_driver dpaa2_eth_driver = { 4454 .driver = { 4455 .name = KBUILD_MODNAME, 4456 .owner = THIS_MODULE, 4457 }, 4458 .probe = dpaa2_eth_probe, 4459 .remove = dpaa2_eth_remove, 4460 .match_id_table = dpaa2_eth_match_id_table 4461}; 4462 4463static int __init dpaa2_eth_driver_init(void) 4464{ 4465 int err; 4466 4467 dpaa2_eth_dbg_init(); 4468 err = fsl_mc_driver_register(&dpaa2_eth_driver); 4469 if (err) { 4470 dpaa2_eth_dbg_exit(); 4471 return err; 4472 } 4473 4474 return 0; 4475} 4476 4477static void __exit dpaa2_eth_driver_exit(void) 4478{ 4479 dpaa2_eth_dbg_exit(); 4480 fsl_mc_driver_unregister(&dpaa2_eth_driver); 4481} 4482 4483module_init(dpaa2_eth_driver_init); 4484module_exit(dpaa2_eth_driver_exit); 4485