1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef _T4FW_INTERFACE_H_ 36#define _T4FW_INTERFACE_H_ 37 38enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77}; 78 79#define FW_T4VF_SGE_BASE_ADDR 0x0000 80#define FW_T4VF_MPS_BASE_ADDR 0x0100 81#define FW_T4VF_PL_BASE_ADDR 0x0200 82#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83#define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_ETH_TX_EO_WR = 0x1c, 91 FW_OFLD_CONNECTION_WR = 0x2f, 92 FW_FLOWC_WR = 0x0a, 93 FW_OFLD_TX_DATA_WR = 0x0b, 94 FW_CMD_WR = 0x10, 95 FW_ETH_TX_PKT_VM_WR = 0x11, 96 FW_RI_RES_WR = 0x0c, 97 FW_RI_INIT_WR = 0x0d, 98 FW_RI_RDMA_WRITE_WR = 0x14, 99 FW_RI_SEND_WR = 0x15, 100 FW_RI_RDMA_READ_WR = 0x16, 101 FW_RI_RECV_WR = 0x17, 102 FW_RI_BIND_MW_WR = 0x18, 103 FW_RI_FR_NSMR_WR = 0x19, 104 FW_RI_FR_NSMR_TPTE_WR = 0x20, 105 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 106 FW_RI_INV_LSTAG_WR = 0x1a, 107 FW_ISCSI_TX_DATA_WR = 0x45, 108 FW_PTP_TX_PKT_WR = 0x46, 109 FW_TLSTX_DATA_WR = 0x68, 110 FW_CRYPTO_LOOKASIDE_WR = 0X6d, 111 FW_LASTC2E_WR = 0x70, 112 FW_FILTER2_WR = 0x77 113}; 114 115struct fw_wr_hdr { 116 __be32 hi; 117 __be32 lo; 118}; 119 120/* work request opcode (hi) */ 121#define FW_WR_OP_S 24 122#define FW_WR_OP_M 0xff 123#define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 124#define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 125 126/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 127#define FW_WR_ATOMIC_S 23 128#define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 129 130/* flush flag (hi) - firmware flushes flushable work request buffered 131 * in the flow context. 132 */ 133#define FW_WR_FLUSH_S 22 134#define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 135 136/* completion flag (hi) - firmware generates a cpl_fw6_ack */ 137#define FW_WR_COMPL_S 21 138#define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 139#define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 140 141/* work request immediate data length (hi) */ 142#define FW_WR_IMMDLEN_S 0 143#define FW_WR_IMMDLEN_M 0xff 144#define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 145 146/* egress queue status update to associated ingress queue entry (lo) */ 147#define FW_WR_EQUIQ_S 31 148#define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 149#define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 150 151/* egress queue status update to egress queue status entry (lo) */ 152#define FW_WR_EQUEQ_S 30 153#define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 154#define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 155 156/* flow context identifier (lo) */ 157#define FW_WR_FLOWID_S 8 158#define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 159 160/* length in units of 16-bytes (lo) */ 161#define FW_WR_LEN16_S 0 162#define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 163 164#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 165#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 166 167/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 168enum fw_filter_wr_cookie { 169 FW_FILTER_WR_SUCCESS, 170 FW_FILTER_WR_FLT_ADDED, 171 FW_FILTER_WR_FLT_DELETED, 172 FW_FILTER_WR_SMT_TBL_FULL, 173 FW_FILTER_WR_EINVAL, 174}; 175 176struct fw_filter_wr { 177 __be32 op_pkd; 178 __be32 len16_pkd; 179 __be64 r3; 180 __be32 tid_to_iq; 181 __be32 del_filter_to_l2tix; 182 __be16 ethtype; 183 __be16 ethtypem; 184 __u8 frag_to_ovlan_vldm; 185 __u8 smac_sel; 186 __be16 rx_chan_rx_rpl_iq; 187 __be32 maci_to_matchtypem; 188 __u8 ptcl; 189 __u8 ptclm; 190 __u8 ttyp; 191 __u8 ttypm; 192 __be16 ivlan; 193 __be16 ivlanm; 194 __be16 ovlan; 195 __be16 ovlanm; 196 __u8 lip[16]; 197 __u8 lipm[16]; 198 __u8 fip[16]; 199 __u8 fipm[16]; 200 __be16 lp; 201 __be16 lpm; 202 __be16 fp; 203 __be16 fpm; 204 __be16 r7; 205 __u8 sma[6]; 206}; 207 208struct fw_filter2_wr { 209 __be32 op_pkd; 210 __be32 len16_pkd; 211 __be64 r3; 212 __be32 tid_to_iq; 213 __be32 del_filter_to_l2tix; 214 __be16 ethtype; 215 __be16 ethtypem; 216 __u8 frag_to_ovlan_vldm; 217 __u8 smac_sel; 218 __be16 rx_chan_rx_rpl_iq; 219 __be32 maci_to_matchtypem; 220 __u8 ptcl; 221 __u8 ptclm; 222 __u8 ttyp; 223 __u8 ttypm; 224 __be16 ivlan; 225 __be16 ivlanm; 226 __be16 ovlan; 227 __be16 ovlanm; 228 __u8 lip[16]; 229 __u8 lipm[16]; 230 __u8 fip[16]; 231 __u8 fipm[16]; 232 __be16 lp; 233 __be16 lpm; 234 __be16 fp; 235 __be16 fpm; 236 __be16 r7; 237 __u8 sma[6]; 238 __be16 r8; 239 __u8 filter_type_swapmac; 240 __u8 natmode_to_ulp_type; 241 __be16 newlport; 242 __be16 newfport; 243 __u8 newlip[16]; 244 __u8 newfip[16]; 245 __be32 natseqcheck; 246 __be32 r9; 247 __be64 r10; 248 __be64 r11; 249 __be64 r12; 250 __be64 r13; 251}; 252 253#define FW_FILTER_WR_TID_S 12 254#define FW_FILTER_WR_TID_M 0xfffff 255#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 256#define FW_FILTER_WR_TID_G(x) \ 257 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 258 259#define FW_FILTER_WR_RQTYPE_S 11 260#define FW_FILTER_WR_RQTYPE_M 0x1 261#define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 262#define FW_FILTER_WR_RQTYPE_G(x) \ 263 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 264#define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 265 266#define FW_FILTER_WR_NOREPLY_S 10 267#define FW_FILTER_WR_NOREPLY_M 0x1 268#define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 269#define FW_FILTER_WR_NOREPLY_G(x) \ 270 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 271#define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 272 273#define FW_FILTER_WR_IQ_S 0 274#define FW_FILTER_WR_IQ_M 0x3ff 275#define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 276#define FW_FILTER_WR_IQ_G(x) \ 277 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 278 279#define FW_FILTER_WR_DEL_FILTER_S 31 280#define FW_FILTER_WR_DEL_FILTER_M 0x1 281#define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 282#define FW_FILTER_WR_DEL_FILTER_G(x) \ 283 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 284#define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 285 286#define FW_FILTER_WR_RPTTID_S 25 287#define FW_FILTER_WR_RPTTID_M 0x1 288#define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 289#define FW_FILTER_WR_RPTTID_G(x) \ 290 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 291#define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 292 293#define FW_FILTER_WR_DROP_S 24 294#define FW_FILTER_WR_DROP_M 0x1 295#define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 296#define FW_FILTER_WR_DROP_G(x) \ 297 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 298#define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 299 300#define FW_FILTER_WR_DIRSTEER_S 23 301#define FW_FILTER_WR_DIRSTEER_M 0x1 302#define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 303#define FW_FILTER_WR_DIRSTEER_G(x) \ 304 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 305#define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 306 307#define FW_FILTER_WR_MASKHASH_S 22 308#define FW_FILTER_WR_MASKHASH_M 0x1 309#define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 310#define FW_FILTER_WR_MASKHASH_G(x) \ 311 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 312#define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 313 314#define FW_FILTER_WR_DIRSTEERHASH_S 21 315#define FW_FILTER_WR_DIRSTEERHASH_M 0x1 316#define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 317#define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 318 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 319#define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 320 321#define FW_FILTER_WR_LPBK_S 20 322#define FW_FILTER_WR_LPBK_M 0x1 323#define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 324#define FW_FILTER_WR_LPBK_G(x) \ 325 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 326#define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 327 328#define FW_FILTER_WR_DMAC_S 19 329#define FW_FILTER_WR_DMAC_M 0x1 330#define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 331#define FW_FILTER_WR_DMAC_G(x) \ 332 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 333#define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 334 335#define FW_FILTER_WR_SMAC_S 18 336#define FW_FILTER_WR_SMAC_M 0x1 337#define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 338#define FW_FILTER_WR_SMAC_G(x) \ 339 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 340#define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 341 342#define FW_FILTER_WR_INSVLAN_S 17 343#define FW_FILTER_WR_INSVLAN_M 0x1 344#define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 345#define FW_FILTER_WR_INSVLAN_G(x) \ 346 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 347#define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 348 349#define FW_FILTER_WR_RMVLAN_S 16 350#define FW_FILTER_WR_RMVLAN_M 0x1 351#define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 352#define FW_FILTER_WR_RMVLAN_G(x) \ 353 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 354#define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 355 356#define FW_FILTER_WR_HITCNTS_S 15 357#define FW_FILTER_WR_HITCNTS_M 0x1 358#define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 359#define FW_FILTER_WR_HITCNTS_G(x) \ 360 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 361#define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 362 363#define FW_FILTER_WR_TXCHAN_S 13 364#define FW_FILTER_WR_TXCHAN_M 0x3 365#define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 366#define FW_FILTER_WR_TXCHAN_G(x) \ 367 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 368 369#define FW_FILTER_WR_PRIO_S 12 370#define FW_FILTER_WR_PRIO_M 0x1 371#define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 372#define FW_FILTER_WR_PRIO_G(x) \ 373 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 374#define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 375 376#define FW_FILTER_WR_L2TIX_S 0 377#define FW_FILTER_WR_L2TIX_M 0xfff 378#define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 379#define FW_FILTER_WR_L2TIX_G(x) \ 380 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 381 382#define FW_FILTER_WR_FRAG_S 7 383#define FW_FILTER_WR_FRAG_M 0x1 384#define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 385#define FW_FILTER_WR_FRAG_G(x) \ 386 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 387#define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 388 389#define FW_FILTER_WR_FRAGM_S 6 390#define FW_FILTER_WR_FRAGM_M 0x1 391#define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 392#define FW_FILTER_WR_FRAGM_G(x) \ 393 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 394#define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 395 396#define FW_FILTER_WR_IVLAN_VLD_S 5 397#define FW_FILTER_WR_IVLAN_VLD_M 0x1 398#define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 399#define FW_FILTER_WR_IVLAN_VLD_G(x) \ 400 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 401#define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 402 403#define FW_FILTER_WR_OVLAN_VLD_S 4 404#define FW_FILTER_WR_OVLAN_VLD_M 0x1 405#define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 406#define FW_FILTER_WR_OVLAN_VLD_G(x) \ 407 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 408#define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 409 410#define FW_FILTER_WR_IVLAN_VLDM_S 3 411#define FW_FILTER_WR_IVLAN_VLDM_M 0x1 412#define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 413#define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 414 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 415#define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 416 417#define FW_FILTER_WR_OVLAN_VLDM_S 2 418#define FW_FILTER_WR_OVLAN_VLDM_M 0x1 419#define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 420#define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 421 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 422#define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 423 424#define FW_FILTER_WR_RX_CHAN_S 15 425#define FW_FILTER_WR_RX_CHAN_M 0x1 426#define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 427#define FW_FILTER_WR_RX_CHAN_G(x) \ 428 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 429#define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 430 431#define FW_FILTER_WR_RX_RPL_IQ_S 0 432#define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 433#define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 434#define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 435 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 436 437#define FW_FILTER2_WR_FILTER_TYPE_S 1 438#define FW_FILTER2_WR_FILTER_TYPE_M 0x1 439#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S) 440#define FW_FILTER2_WR_FILTER_TYPE_G(x) \ 441 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M) 442#define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U) 443 444#define FW_FILTER2_WR_NATMODE_S 5 445#define FW_FILTER2_WR_NATMODE_M 0x7 446#define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S) 447#define FW_FILTER2_WR_NATMODE_G(x) \ 448 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M) 449 450#define FW_FILTER2_WR_NATFLAGCHECK_S 4 451#define FW_FILTER2_WR_NATFLAGCHECK_M 0x1 452#define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S) 453#define FW_FILTER2_WR_NATFLAGCHECK_G(x) \ 454 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M) 455#define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U) 456 457#define FW_FILTER2_WR_ULP_TYPE_S 0 458#define FW_FILTER2_WR_ULP_TYPE_M 0xf 459#define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S) 460#define FW_FILTER2_WR_ULP_TYPE_G(x) \ 461 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M) 462 463#define FW_FILTER_WR_MACI_S 23 464#define FW_FILTER_WR_MACI_M 0x1ff 465#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 466#define FW_FILTER_WR_MACI_G(x) \ 467 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 468 469#define FW_FILTER_WR_MACIM_S 14 470#define FW_FILTER_WR_MACIM_M 0x1ff 471#define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 472#define FW_FILTER_WR_MACIM_G(x) \ 473 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 474 475#define FW_FILTER_WR_FCOE_S 13 476#define FW_FILTER_WR_FCOE_M 0x1 477#define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 478#define FW_FILTER_WR_FCOE_G(x) \ 479 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 480#define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 481 482#define FW_FILTER_WR_FCOEM_S 12 483#define FW_FILTER_WR_FCOEM_M 0x1 484#define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 485#define FW_FILTER_WR_FCOEM_G(x) \ 486 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 487#define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 488 489#define FW_FILTER_WR_PORT_S 9 490#define FW_FILTER_WR_PORT_M 0x7 491#define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 492#define FW_FILTER_WR_PORT_G(x) \ 493 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 494 495#define FW_FILTER_WR_PORTM_S 6 496#define FW_FILTER_WR_PORTM_M 0x7 497#define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 498#define FW_FILTER_WR_PORTM_G(x) \ 499 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 500 501#define FW_FILTER_WR_MATCHTYPE_S 3 502#define FW_FILTER_WR_MATCHTYPE_M 0x7 503#define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 504#define FW_FILTER_WR_MATCHTYPE_G(x) \ 505 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 506 507#define FW_FILTER_WR_MATCHTYPEM_S 0 508#define FW_FILTER_WR_MATCHTYPEM_M 0x7 509#define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 510#define FW_FILTER_WR_MATCHTYPEM_G(x) \ 511 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 512 513struct fw_ulptx_wr { 514 __be32 op_to_compl; 515 __be32 flowid_len16; 516 u64 cookie; 517}; 518 519#define FW_ULPTX_WR_DATA_S 28 520#define FW_ULPTX_WR_DATA_M 0x1 521#define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S) 522#define FW_ULPTX_WR_DATA_G(x) \ 523 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M) 524#define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U) 525 526struct fw_tp_wr { 527 __be32 op_to_immdlen; 528 __be32 flowid_len16; 529 u64 cookie; 530}; 531 532struct fw_eth_tx_pkt_wr { 533 __be32 op_immdlen; 534 __be32 equiq_to_len16; 535 __be64 r3; 536}; 537 538enum fw_eth_tx_eo_type { 539 FW_ETH_TX_EO_TYPE_UDPSEG = 0, 540 FW_ETH_TX_EO_TYPE_TCPSEG, 541}; 542 543struct fw_eth_tx_eo_wr { 544 __be32 op_immdlen; 545 __be32 equiq_to_len16; 546 __be64 r3; 547 union fw_eth_tx_eo { 548 struct fw_eth_tx_eo_udpseg { 549 __u8 type; 550 __u8 ethlen; 551 __be16 iplen; 552 __u8 udplen; 553 __u8 rtplen; 554 __be16 r4; 555 __be16 mss; 556 __be16 schedpktsize; 557 __be32 plen; 558 } udpseg; 559 struct fw_eth_tx_eo_tcpseg { 560 __u8 type; 561 __u8 ethlen; 562 __be16 iplen; 563 __u8 tcplen; 564 __u8 tsclk_tsoff; 565 __be16 r4; 566 __be16 mss; 567 __be16 r5; 568 __be32 plen; 569 } tcpseg; 570 } u; 571}; 572 573#define FW_ETH_TX_EO_WR_IMMDLEN_S 0 574#define FW_ETH_TX_EO_WR_IMMDLEN_M 0x1ff 575#define FW_ETH_TX_EO_WR_IMMDLEN_V(x) ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S) 576#define FW_ETH_TX_EO_WR_IMMDLEN_G(x) \ 577 (((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M) 578 579struct fw_ofld_connection_wr { 580 __be32 op_compl; 581 __be32 len16_pkd; 582 __u64 cookie; 583 __be64 r2; 584 __be64 r3; 585 struct fw_ofld_connection_le { 586 __be32 version_cpl; 587 __be32 filter; 588 __be32 r1; 589 __be16 lport; 590 __be16 pport; 591 union fw_ofld_connection_leip { 592 struct fw_ofld_connection_le_ipv4 { 593 __be32 pip; 594 __be32 lip; 595 __be64 r0; 596 __be64 r1; 597 __be64 r2; 598 } ipv4; 599 struct fw_ofld_connection_le_ipv6 { 600 __be64 pip_hi; 601 __be64 pip_lo; 602 __be64 lip_hi; 603 __be64 lip_lo; 604 } ipv6; 605 } u; 606 } le; 607 struct fw_ofld_connection_tcb { 608 __be32 t_state_to_astid; 609 __be16 cplrxdataack_cplpassacceptrpl; 610 __be16 rcv_adv; 611 __be32 rcv_nxt; 612 __be32 tx_max; 613 __be64 opt0; 614 __be32 opt2; 615 __be32 r1; 616 __be64 r2; 617 __be64 r3; 618 } tcb; 619}; 620 621#define FW_OFLD_CONNECTION_WR_VERSION_S 31 622#define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 623#define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 624 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 625#define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 626 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 627 FW_OFLD_CONNECTION_WR_VERSION_M) 628#define FW_OFLD_CONNECTION_WR_VERSION_F \ 629 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 630 631#define FW_OFLD_CONNECTION_WR_CPL_S 30 632#define FW_OFLD_CONNECTION_WR_CPL_M 0x1 633#define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 634#define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 635 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 636#define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 637 638#define FW_OFLD_CONNECTION_WR_T_STATE_S 28 639#define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 640#define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 641 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 642#define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 643 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 644 FW_OFLD_CONNECTION_WR_T_STATE_M) 645 646#define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 647#define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 648#define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 649 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 650#define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 651 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 652 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 653 654#define FW_OFLD_CONNECTION_WR_ASTID_S 0 655#define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 656#define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 657 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 658#define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 659 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 660 661#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 662#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 663#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 664 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 665#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 666 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 667 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 668#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 669 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 670 671#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 672#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 673#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 674 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 675#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 676 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 677 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 678#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 679 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 680 681enum fw_flowc_mnem_tcpstate { 682 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 683 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 684 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 685 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 686 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 687 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 688 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 689 * will resend FIN - equiv ESTAB 690 */ 691 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 692 * will resend FIN but have 693 * received FIN 694 */ 695 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 696 * will resend FIN but have 697 * received FIN 698 */ 699 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 700 * waiting for FIN 701 */ 702 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 703}; 704 705enum fw_flowc_mnem_eostate { 706 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 707 /* graceful close, after sending outstanding payload */ 708 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, 709}; 710 711enum fw_flowc_mnem { 712 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 713 FW_FLOWC_MNEM_CH, 714 FW_FLOWC_MNEM_PORT, 715 FW_FLOWC_MNEM_IQID, 716 FW_FLOWC_MNEM_SNDNXT, 717 FW_FLOWC_MNEM_RCVNXT, 718 FW_FLOWC_MNEM_SNDBUF, 719 FW_FLOWC_MNEM_MSS, 720 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 721 FW_FLOWC_MNEM_TCPSTATE, 722 FW_FLOWC_MNEM_EOSTATE, 723 FW_FLOWC_MNEM_SCHEDCLASS, 724 FW_FLOWC_MNEM_DCBPRIO, 725 FW_FLOWC_MNEM_SND_SCALE, 726 FW_FLOWC_MNEM_RCV_SCALE, 727 FW_FLOWC_MNEM_ULD_MODE, 728 FW_FLOWC_MNEM_MAX, 729}; 730 731struct fw_flowc_mnemval { 732 u8 mnemonic; 733 u8 r4[3]; 734 __be32 val; 735}; 736 737struct fw_flowc_wr { 738 __be32 op_to_nparams; 739 __be32 flowid_len16; 740 struct fw_flowc_mnemval mnemval[]; 741}; 742 743#define FW_FLOWC_WR_NPARAMS_S 0 744#define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 745 746struct fw_ofld_tx_data_wr { 747 __be32 op_to_immdlen; 748 __be32 flowid_len16; 749 __be32 plen; 750 __be32 tunnel_to_proxy; 751}; 752 753#define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30 754#define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S) 755#define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U) 756 757#define FW_OFLD_TX_DATA_WR_SHOVE_S 29 758#define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 759#define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 760 761#define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 762#define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 763 764#define FW_OFLD_TX_DATA_WR_SAVE_S 18 765#define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 766 767#define FW_OFLD_TX_DATA_WR_FLUSH_S 17 768#define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 769#define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 770 771#define FW_OFLD_TX_DATA_WR_URGENT_S 16 772#define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 773 774#define FW_OFLD_TX_DATA_WR_MORE_S 15 775#define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 776 777#define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 778#define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 779 780#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 781#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 782 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 783 784struct fw_cmd_wr { 785 __be32 op_dma; 786 __be32 len16_pkd; 787 __be64 cookie_daddr; 788}; 789 790#define FW_CMD_WR_DMA_S 17 791#define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 792 793struct fw_eth_tx_pkt_vm_wr { 794 __be32 op_immdlen; 795 __be32 equiq_to_len16; 796 __be32 r3[2]; 797 u8 ethmacdst[6]; 798 u8 ethmacsrc[6]; 799 __be16 ethtype; 800 __be16 vlantci; 801}; 802 803#define FW_CMD_MAX_TIMEOUT 10000 804 805/* 806 * If a host driver does a HELLO and discovers that there's already a MASTER 807 * selected, we may have to wait for that MASTER to finish issuing RESET, 808 * configuration and INITIALIZE commands. Also, there's a possibility that 809 * our own HELLO may get lost if it happens right as the MASTER is issuign a 810 * RESET command, so we need to be willing to make a few retries of our HELLO. 811 */ 812#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 813#define FW_CMD_HELLO_RETRIES 3 814 815 816enum fw_cmd_opcodes { 817 FW_LDST_CMD = 0x01, 818 FW_RESET_CMD = 0x03, 819 FW_HELLO_CMD = 0x04, 820 FW_BYE_CMD = 0x05, 821 FW_INITIALIZE_CMD = 0x06, 822 FW_CAPS_CONFIG_CMD = 0x07, 823 FW_PARAMS_CMD = 0x08, 824 FW_PFVF_CMD = 0x09, 825 FW_IQ_CMD = 0x10, 826 FW_EQ_MNGT_CMD = 0x11, 827 FW_EQ_ETH_CMD = 0x12, 828 FW_EQ_CTRL_CMD = 0x13, 829 FW_EQ_OFLD_CMD = 0x21, 830 FW_VI_CMD = 0x14, 831 FW_VI_MAC_CMD = 0x15, 832 FW_VI_RXMODE_CMD = 0x16, 833 FW_VI_ENABLE_CMD = 0x17, 834 FW_ACL_MAC_CMD = 0x18, 835 FW_ACL_VLAN_CMD = 0x19, 836 FW_VI_STATS_CMD = 0x1a, 837 FW_PORT_CMD = 0x1b, 838 FW_PORT_STATS_CMD = 0x1c, 839 FW_PORT_LB_STATS_CMD = 0x1d, 840 FW_PORT_TRACE_CMD = 0x1e, 841 FW_PORT_TRACE_MMAP_CMD = 0x1f, 842 FW_RSS_IND_TBL_CMD = 0x20, 843 FW_RSS_GLB_CONFIG_CMD = 0x22, 844 FW_RSS_VI_CONFIG_CMD = 0x23, 845 FW_SCHED_CMD = 0x24, 846 FW_DEVLOG_CMD = 0x25, 847 FW_CLIP_CMD = 0x28, 848 FW_PTP_CMD = 0x3e, 849 FW_HMA_CMD = 0x3f, 850 FW_LASTC2E_CMD = 0x40, 851 FW_ERROR_CMD = 0x80, 852 FW_DEBUG_CMD = 0x81, 853}; 854 855enum fw_cmd_cap { 856 FW_CMD_CAP_PF = 0x01, 857 FW_CMD_CAP_DMAQ = 0x02, 858 FW_CMD_CAP_PORT = 0x04, 859 FW_CMD_CAP_PORTPROMISC = 0x08, 860 FW_CMD_CAP_PORTSTATS = 0x10, 861 FW_CMD_CAP_VF = 0x80, 862}; 863 864/* 865 * Generic command header flit0 866 */ 867struct fw_cmd_hdr { 868 __be32 hi; 869 __be32 lo; 870}; 871 872#define FW_CMD_OP_S 24 873#define FW_CMD_OP_M 0xff 874#define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 875#define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 876 877#define FW_CMD_REQUEST_S 23 878#define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 879#define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 880 881#define FW_CMD_READ_S 22 882#define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 883#define FW_CMD_READ_F FW_CMD_READ_V(1U) 884 885#define FW_CMD_WRITE_S 21 886#define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 887#define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 888 889#define FW_CMD_EXEC_S 20 890#define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 891#define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 892 893#define FW_CMD_RAMASK_S 20 894#define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 895 896#define FW_CMD_RETVAL_S 8 897#define FW_CMD_RETVAL_M 0xff 898#define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 899#define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 900 901#define FW_CMD_LEN16_S 0 902#define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 903 904#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 905 906enum fw_ldst_addrspc { 907 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 908 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 909 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 910 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 911 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 912 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 913 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 914 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 915 FW_LDST_ADDRSPC_MDIO = 0x0018, 916 FW_LDST_ADDRSPC_MPS = 0x0020, 917 FW_LDST_ADDRSPC_FUNC = 0x0028, 918 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 919 FW_LDST_ADDRSPC_I2C = 0x0038, 920}; 921 922enum fw_ldst_mps_fid { 923 FW_LDST_MPS_ATRB, 924 FW_LDST_MPS_RPLC 925}; 926 927enum fw_ldst_func_access_ctl { 928 FW_LDST_FUNC_ACC_CTL_VIID, 929 FW_LDST_FUNC_ACC_CTL_FID 930}; 931 932enum fw_ldst_func_mod_index { 933 FW_LDST_FUNC_MPS 934}; 935 936struct fw_ldst_cmd { 937 __be32 op_to_addrspace; 938 __be32 cycles_to_len16; 939 union fw_ldst { 940 struct fw_ldst_addrval { 941 __be32 addr; 942 __be32 val; 943 } addrval; 944 struct fw_ldst_idctxt { 945 __be32 physid; 946 __be32 msg_ctxtflush; 947 __be32 ctxt_data7; 948 __be32 ctxt_data6; 949 __be32 ctxt_data5; 950 __be32 ctxt_data4; 951 __be32 ctxt_data3; 952 __be32 ctxt_data2; 953 __be32 ctxt_data1; 954 __be32 ctxt_data0; 955 } idctxt; 956 struct fw_ldst_mdio { 957 __be16 paddr_mmd; 958 __be16 raddr; 959 __be16 vctl; 960 __be16 rval; 961 } mdio; 962 struct fw_ldst_cim_rq { 963 u8 req_first64[8]; 964 u8 req_second64[8]; 965 u8 resp_first64[8]; 966 u8 resp_second64[8]; 967 __be32 r3[2]; 968 } cim_rq; 969 union fw_ldst_mps { 970 struct fw_ldst_mps_rplc { 971 __be16 fid_idx; 972 __be16 rplcpf_pkd; 973 __be32 rplc255_224; 974 __be32 rplc223_192; 975 __be32 rplc191_160; 976 __be32 rplc159_128; 977 __be32 rplc127_96; 978 __be32 rplc95_64; 979 __be32 rplc63_32; 980 __be32 rplc31_0; 981 } rplc; 982 struct fw_ldst_mps_atrb { 983 __be16 fid_mpsid; 984 __be16 r2[3]; 985 __be32 r3[2]; 986 __be32 r4; 987 __be32 atrb; 988 __be16 vlan[16]; 989 } atrb; 990 } mps; 991 struct fw_ldst_func { 992 u8 access_ctl; 993 u8 mod_index; 994 __be16 ctl_id; 995 __be32 offset; 996 __be64 data0; 997 __be64 data1; 998 } func; 999 struct fw_ldst_pcie { 1000 u8 ctrl_to_fn; 1001 u8 bnum; 1002 u8 r; 1003 u8 ext_r; 1004 u8 select_naccess; 1005 u8 pcie_fn; 1006 __be16 nset_pkd; 1007 __be32 data[12]; 1008 } pcie; 1009 struct fw_ldst_i2c_deprecated { 1010 u8 pid_pkd; 1011 u8 base; 1012 u8 boffset; 1013 u8 data; 1014 __be32 r9; 1015 } i2c_deprecated; 1016 struct fw_ldst_i2c { 1017 u8 pid; 1018 u8 did; 1019 u8 boffset; 1020 u8 blen; 1021 __be32 r9; 1022 __u8 data[48]; 1023 } i2c; 1024 struct fw_ldst_le { 1025 __be32 index; 1026 __be32 r9; 1027 u8 val[33]; 1028 u8 r11[7]; 1029 } le; 1030 } u; 1031}; 1032 1033#define FW_LDST_CMD_ADDRSPACE_S 0 1034#define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 1035 1036#define FW_LDST_CMD_MSG_S 31 1037#define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 1038 1039#define FW_LDST_CMD_CTXTFLUSH_S 30 1040#define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 1041#define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 1042 1043#define FW_LDST_CMD_PADDR_S 8 1044#define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 1045 1046#define FW_LDST_CMD_MMD_S 0 1047#define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 1048 1049#define FW_LDST_CMD_FID_S 15 1050#define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 1051 1052#define FW_LDST_CMD_IDX_S 0 1053#define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 1054 1055#define FW_LDST_CMD_RPLCPF_S 0 1056#define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 1057 1058#define FW_LDST_CMD_LC_S 4 1059#define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 1060#define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 1061 1062#define FW_LDST_CMD_FN_S 0 1063#define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 1064 1065#define FW_LDST_CMD_NACCESS_S 0 1066#define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 1067 1068struct fw_reset_cmd { 1069 __be32 op_to_write; 1070 __be32 retval_len16; 1071 __be32 val; 1072 __be32 halt_pkd; 1073}; 1074 1075#define FW_RESET_CMD_HALT_S 31 1076#define FW_RESET_CMD_HALT_M 0x1 1077#define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 1078#define FW_RESET_CMD_HALT_G(x) \ 1079 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 1080#define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 1081 1082enum fw_hellow_cmd { 1083 fw_hello_cmd_stage_os = 0x0 1084}; 1085 1086struct fw_hello_cmd { 1087 __be32 op_to_write; 1088 __be32 retval_len16; 1089 __be32 err_to_clearinit; 1090 __be32 fwrev; 1091}; 1092 1093#define FW_HELLO_CMD_ERR_S 31 1094#define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 1095#define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 1096 1097#define FW_HELLO_CMD_INIT_S 30 1098#define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 1099#define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 1100 1101#define FW_HELLO_CMD_MASTERDIS_S 29 1102#define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 1103 1104#define FW_HELLO_CMD_MASTERFORCE_S 28 1105#define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 1106 1107#define FW_HELLO_CMD_MBMASTER_S 24 1108#define FW_HELLO_CMD_MBMASTER_M 0xfU 1109#define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 1110#define FW_HELLO_CMD_MBMASTER_G(x) \ 1111 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 1112 1113#define FW_HELLO_CMD_MBASYNCNOTINT_S 23 1114#define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 1115 1116#define FW_HELLO_CMD_MBASYNCNOT_S 20 1117#define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 1118 1119#define FW_HELLO_CMD_STAGE_S 17 1120#define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 1121 1122#define FW_HELLO_CMD_CLEARINIT_S 16 1123#define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 1124#define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 1125 1126struct fw_bye_cmd { 1127 __be32 op_to_write; 1128 __be32 retval_len16; 1129 __be64 r3; 1130}; 1131 1132struct fw_initialize_cmd { 1133 __be32 op_to_write; 1134 __be32 retval_len16; 1135 __be64 r3; 1136}; 1137 1138enum fw_caps_config_hm { 1139 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 1140 FW_CAPS_CONFIG_HM_PL = 0x00000002, 1141 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 1142 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 1143 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 1144 FW_CAPS_CONFIG_HM_TP = 0x00000020, 1145 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 1146 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 1147 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 1148 FW_CAPS_CONFIG_HM_MC = 0x00000200, 1149 FW_CAPS_CONFIG_HM_LE = 0x00000400, 1150 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 1151 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 1152 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 1153 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 1154 FW_CAPS_CONFIG_HM_MI = 0x00008000, 1155 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 1156 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 1157 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 1158 FW_CAPS_CONFIG_HM_MA = 0x00080000, 1159 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 1160 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1161 FW_CAPS_CONFIG_HM_UART = 0x00400000, 1162 FW_CAPS_CONFIG_HM_SF = 0x00800000, 1163}; 1164 1165enum fw_caps_config_nbm { 1166 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1167 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1168}; 1169 1170enum fw_caps_config_link { 1171 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1172 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1173 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1174}; 1175 1176enum fw_caps_config_switch { 1177 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1178 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1179}; 1180 1181enum fw_caps_config_nic { 1182 FW_CAPS_CONFIG_NIC = 0x00000001, 1183 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1184 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 1185 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 1186}; 1187 1188enum fw_caps_config_ofld { 1189 FW_CAPS_CONFIG_OFLD = 0x00000001, 1190}; 1191 1192enum fw_caps_config_rdma { 1193 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1194 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1195}; 1196 1197enum fw_caps_config_iscsi { 1198 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1199 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1200 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1201 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1202}; 1203 1204enum fw_caps_config_crypto { 1205 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 1206 FW_CAPS_CONFIG_TLS_INLINE = 0x00000002, 1207 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 1208 FW_CAPS_CONFIG_TLS_HW = 0x00000008, 1209}; 1210 1211enum fw_caps_config_fcoe { 1212 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1213 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1214 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1215}; 1216 1217enum fw_memtype_cf { 1218 FW_MEMTYPE_CF_EDC0 = 0x0, 1219 FW_MEMTYPE_CF_EDC1 = 0x1, 1220 FW_MEMTYPE_CF_EXTMEM = 0x2, 1221 FW_MEMTYPE_CF_FLASH = 0x4, 1222 FW_MEMTYPE_CF_INTERNAL = 0x5, 1223 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1224 FW_MEMTYPE_CF_HMA = 0x7, 1225}; 1226 1227struct fw_caps_config_cmd { 1228 __be32 op_to_write; 1229 __be32 cfvalid_to_len16; 1230 __be32 r2; 1231 __be32 hwmbitmap; 1232 __be16 nbmcaps; 1233 __be16 linkcaps; 1234 __be16 switchcaps; 1235 __be16 r3; 1236 __be16 niccaps; 1237 __be16 ofldcaps; 1238 __be16 rdmacaps; 1239 __be16 cryptocaps; 1240 __be16 iscsicaps; 1241 __be16 fcoecaps; 1242 __be32 cfcsum; 1243 __be32 finiver; 1244 __be32 finicsum; 1245}; 1246 1247#define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1248#define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1249#define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1250 1251#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1252#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1253 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1254 1255#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1256#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1257 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1258 1259/* 1260 * params command mnemonics 1261 */ 1262enum fw_params_mnem { 1263 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1264 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1265 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1266 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1267 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1268 FW_PARAMS_MNEM_LAST 1269}; 1270 1271/* 1272 * device parameters 1273 */ 1274 1275#define FW_PARAMS_PARAM_FILTER_MODE_S 16 1276#define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff 1277#define FW_PARAMS_PARAM_FILTER_MODE_V(x) \ 1278 ((x) << FW_PARAMS_PARAM_FILTER_MODE_S) 1279#define FW_PARAMS_PARAM_FILTER_MODE_G(x) \ 1280 (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \ 1281 FW_PARAMS_PARAM_FILTER_MODE_M) 1282 1283#define FW_PARAMS_PARAM_FILTER_MASK_S 0 1284#define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff 1285#define FW_PARAMS_PARAM_FILTER_MASK_V(x) \ 1286 ((x) << FW_PARAMS_PARAM_FILTER_MASK_S) 1287#define FW_PARAMS_PARAM_FILTER_MASK_G(x) \ 1288 (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \ 1289 FW_PARAMS_PARAM_FILTER_MASK_M) 1290 1291enum fw_params_param_dev { 1292 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1293 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1294 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1295 * allocated by the device's 1296 * Lookup Engine 1297 */ 1298 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1299 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1300 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1301 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1302 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1303 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1304 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1305 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1306 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1307 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1308 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1309 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1310 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1311 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1312 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1313 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1314 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1315 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1316 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1317 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 1318 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 1319 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 1320 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 1321 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 1322 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 1323 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 1324 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 1325 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 1326 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 1327 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 1328 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 1329 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 1330 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 1331 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 1332 FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31, 1333}; 1334 1335/* 1336 * physical and virtual function parameters 1337 */ 1338enum fw_params_param_pfvf { 1339 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1340 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1341 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1342 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1343 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1344 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1345 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1346 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1347 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1348 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1349 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1350 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1351 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1352 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1353 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1354 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1355 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1356 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1357 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1358 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1359 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1360 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1361 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1362 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1363 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1364 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 1365 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 1366 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1367 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1368 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1369 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1370 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1371 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1372 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1373 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1374 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1375 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1376 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1377 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1378 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 1379 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1380 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 1381 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 1382 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 1383 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 1384 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 1385 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 1386 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 1387 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 1388 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1389 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 1390 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 1391 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 1392}; 1393 1394/* Virtual link state as seen by the specified VF */ 1395enum vf_link_states { 1396 FW_VF_LINK_STATE_AUTO = 0x00, 1397 FW_VF_LINK_STATE_ENABLE = 0x01, 1398 FW_VF_LINK_STATE_DISABLE = 0x02, 1399}; 1400 1401/* 1402 * dma queue parameters 1403 */ 1404enum fw_params_param_dmaq { 1405 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1406 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1407 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1408 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1409 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1410 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1411 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 1412 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1413}; 1414 1415enum fw_params_param_dev_ktls_hw { 1416 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00, 1417 FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01, 1418 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE = 0x01, 1419}; 1420 1421enum fw_params_param_dev_phyfw { 1422 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1423 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1424}; 1425 1426enum fw_params_param_dev_diag { 1427 FW_PARAM_DEV_DIAG_TMP = 0x00, 1428 FW_PARAM_DEV_DIAG_VDD = 0x01, 1429 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 1430}; 1431 1432enum fw_params_param_dev_filter { 1433 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 1434 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 1435}; 1436 1437enum fw_params_param_dev_fwcache { 1438 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1439 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1440}; 1441 1442#define FW_PARAMS_MNEM_S 24 1443#define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1444 1445#define FW_PARAMS_PARAM_X_S 16 1446#define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1447 1448#define FW_PARAMS_PARAM_Y_S 8 1449#define FW_PARAMS_PARAM_Y_M 0xffU 1450#define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1451#define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1452 FW_PARAMS_PARAM_Y_M) 1453 1454#define FW_PARAMS_PARAM_Z_S 0 1455#define FW_PARAMS_PARAM_Z_M 0xffu 1456#define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1457#define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1458 FW_PARAMS_PARAM_Z_M) 1459 1460#define FW_PARAMS_PARAM_XYZ_S 0 1461#define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1462 1463#define FW_PARAMS_PARAM_YZ_S 0 1464#define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1465 1466struct fw_params_cmd { 1467 __be32 op_to_vfn; 1468 __be32 retval_len16; 1469 struct fw_params_param { 1470 __be32 mnem; 1471 __be32 val; 1472 } param[7]; 1473}; 1474 1475#define FW_PARAMS_CMD_PFN_S 8 1476#define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1477 1478#define FW_PARAMS_CMD_VFN_S 0 1479#define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1480 1481struct fw_pfvf_cmd { 1482 __be32 op_to_vfn; 1483 __be32 retval_len16; 1484 __be32 niqflint_niq; 1485 __be32 type_to_neq; 1486 __be32 tc_to_nexactf; 1487 __be32 r_caps_to_nethctrl; 1488 __be16 nricq; 1489 __be16 nriqp; 1490 __be32 r4; 1491}; 1492 1493#define FW_PFVF_CMD_PFN_S 8 1494#define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1495 1496#define FW_PFVF_CMD_VFN_S 0 1497#define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1498 1499#define FW_PFVF_CMD_NIQFLINT_S 20 1500#define FW_PFVF_CMD_NIQFLINT_M 0xfff 1501#define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1502#define FW_PFVF_CMD_NIQFLINT_G(x) \ 1503 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1504 1505#define FW_PFVF_CMD_NIQ_S 0 1506#define FW_PFVF_CMD_NIQ_M 0xfffff 1507#define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1508#define FW_PFVF_CMD_NIQ_G(x) \ 1509 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1510 1511#define FW_PFVF_CMD_TYPE_S 31 1512#define FW_PFVF_CMD_TYPE_M 0x1 1513#define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1514#define FW_PFVF_CMD_TYPE_G(x) \ 1515 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1516#define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1517 1518#define FW_PFVF_CMD_CMASK_S 24 1519#define FW_PFVF_CMD_CMASK_M 0xf 1520#define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1521#define FW_PFVF_CMD_CMASK_G(x) \ 1522 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1523 1524#define FW_PFVF_CMD_PMASK_S 20 1525#define FW_PFVF_CMD_PMASK_M 0xf 1526#define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1527#define FW_PFVF_CMD_PMASK_G(x) \ 1528 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1529 1530#define FW_PFVF_CMD_NEQ_S 0 1531#define FW_PFVF_CMD_NEQ_M 0xfffff 1532#define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1533#define FW_PFVF_CMD_NEQ_G(x) \ 1534 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1535 1536#define FW_PFVF_CMD_TC_S 24 1537#define FW_PFVF_CMD_TC_M 0xff 1538#define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1539#define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1540 1541#define FW_PFVF_CMD_NVI_S 16 1542#define FW_PFVF_CMD_NVI_M 0xff 1543#define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1544#define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1545 1546#define FW_PFVF_CMD_NEXACTF_S 0 1547#define FW_PFVF_CMD_NEXACTF_M 0xffff 1548#define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1549#define FW_PFVF_CMD_NEXACTF_G(x) \ 1550 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1551 1552#define FW_PFVF_CMD_R_CAPS_S 24 1553#define FW_PFVF_CMD_R_CAPS_M 0xff 1554#define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1555#define FW_PFVF_CMD_R_CAPS_G(x) \ 1556 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1557 1558#define FW_PFVF_CMD_WX_CAPS_S 16 1559#define FW_PFVF_CMD_WX_CAPS_M 0xff 1560#define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1561#define FW_PFVF_CMD_WX_CAPS_G(x) \ 1562 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1563 1564#define FW_PFVF_CMD_NETHCTRL_S 0 1565#define FW_PFVF_CMD_NETHCTRL_M 0xffff 1566#define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1567#define FW_PFVF_CMD_NETHCTRL_G(x) \ 1568 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1569 1570enum fw_iq_type { 1571 FW_IQ_TYPE_FL_INT_CAP, 1572 FW_IQ_TYPE_NO_FL_INT_CAP 1573}; 1574 1575enum fw_iq_iqtype { 1576 FW_IQ_IQTYPE_OTHER, 1577 FW_IQ_IQTYPE_NIC, 1578 FW_IQ_IQTYPE_OFLD, 1579}; 1580 1581struct fw_iq_cmd { 1582 __be32 op_to_vfn; 1583 __be32 alloc_to_len16; 1584 __be16 physiqid; 1585 __be16 iqid; 1586 __be16 fl0id; 1587 __be16 fl1id; 1588 __be32 type_to_iqandstindex; 1589 __be16 iqdroprss_to_iqesize; 1590 __be16 iqsize; 1591 __be64 iqaddr; 1592 __be32 iqns_to_fl0congen; 1593 __be16 fl0dcaen_to_fl0cidxfthresh; 1594 __be16 fl0size; 1595 __be64 fl0addr; 1596 __be32 fl1cngchmap_to_fl1congen; 1597 __be16 fl1dcaen_to_fl1cidxfthresh; 1598 __be16 fl1size; 1599 __be64 fl1addr; 1600}; 1601 1602#define FW_IQ_CMD_PFN_S 8 1603#define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1604 1605#define FW_IQ_CMD_VFN_S 0 1606#define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1607 1608#define FW_IQ_CMD_ALLOC_S 31 1609#define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1610#define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1611 1612#define FW_IQ_CMD_FREE_S 30 1613#define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1614#define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1615 1616#define FW_IQ_CMD_MODIFY_S 29 1617#define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1618#define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1619 1620#define FW_IQ_CMD_IQSTART_S 28 1621#define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1622#define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1623 1624#define FW_IQ_CMD_IQSTOP_S 27 1625#define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1626#define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1627 1628#define FW_IQ_CMD_TYPE_S 29 1629#define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1630 1631#define FW_IQ_CMD_IQASYNCH_S 28 1632#define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1633 1634#define FW_IQ_CMD_VIID_S 16 1635#define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1636 1637#define FW_IQ_CMD_IQANDST_S 15 1638#define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1639 1640#define FW_IQ_CMD_IQANUS_S 14 1641#define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1642 1643#define FW_IQ_CMD_IQANUD_S 12 1644#define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1645 1646#define FW_IQ_CMD_IQANDSTINDEX_S 0 1647#define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1648 1649#define FW_IQ_CMD_IQDROPRSS_S 15 1650#define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1651#define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1652 1653#define FW_IQ_CMD_IQGTSMODE_S 14 1654#define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1655#define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1656 1657#define FW_IQ_CMD_IQPCIECH_S 12 1658#define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1659 1660#define FW_IQ_CMD_IQDCAEN_S 11 1661#define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1662 1663#define FW_IQ_CMD_IQDCACPU_S 6 1664#define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1665 1666#define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1667#define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1668 1669#define FW_IQ_CMD_IQO_S 3 1670#define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1671#define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1672 1673#define FW_IQ_CMD_IQCPRIO_S 2 1674#define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1675 1676#define FW_IQ_CMD_IQESIZE_S 0 1677#define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1678 1679#define FW_IQ_CMD_IQNS_S 31 1680#define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1681 1682#define FW_IQ_CMD_IQRO_S 30 1683#define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1684 1685#define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1686#define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1687 1688#define FW_IQ_CMD_IQFLINTCONGEN_S 27 1689#define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1690#define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1691 1692#define FW_IQ_CMD_IQFLINTISCSIC_S 26 1693#define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1694 1695#define FW_IQ_CMD_IQTYPE_S 24 1696#define FW_IQ_CMD_IQTYPE_M 0x3 1697#define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S) 1698#define FW_IQ_CMD_IQTYPE_G(x) \ 1699 (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M) 1700 1701#define FW_IQ_CMD_FL0CNGCHMAP_S 20 1702#define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1703 1704#define FW_IQ_CMD_FL0CACHELOCK_S 15 1705#define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1706 1707#define FW_IQ_CMD_FL0DBP_S 14 1708#define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1709 1710#define FW_IQ_CMD_FL0DATANS_S 13 1711#define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1712 1713#define FW_IQ_CMD_FL0DATARO_S 12 1714#define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1715#define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1716 1717#define FW_IQ_CMD_FL0CONGCIF_S 11 1718#define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1719#define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1720 1721#define FW_IQ_CMD_FL0ONCHIP_S 10 1722#define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1723 1724#define FW_IQ_CMD_FL0STATUSPGNS_S 9 1725#define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1726 1727#define FW_IQ_CMD_FL0STATUSPGRO_S 8 1728#define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1729 1730#define FW_IQ_CMD_FL0FETCHNS_S 7 1731#define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1732 1733#define FW_IQ_CMD_FL0FETCHRO_S 6 1734#define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1735#define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1736 1737#define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1738#define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1739 1740#define FW_IQ_CMD_FL0CPRIO_S 3 1741#define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1742 1743#define FW_IQ_CMD_FL0PADEN_S 2 1744#define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1745#define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1746 1747#define FW_IQ_CMD_FL0PACKEN_S 1 1748#define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1749#define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1750 1751#define FW_IQ_CMD_FL0CONGEN_S 0 1752#define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1753#define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1754 1755#define FW_IQ_CMD_FL0DCAEN_S 15 1756#define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1757 1758#define FW_IQ_CMD_FL0DCACPU_S 10 1759#define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1760 1761#define FW_IQ_CMD_FL0FBMIN_S 7 1762#define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1763 1764#define FW_IQ_CMD_FL0FBMAX_S 4 1765#define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1766 1767#define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1768#define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1769#define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1770 1771#define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1772#define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1773 1774#define FW_IQ_CMD_FL1CNGCHMAP_S 20 1775#define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1776 1777#define FW_IQ_CMD_FL1CACHELOCK_S 15 1778#define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1779 1780#define FW_IQ_CMD_FL1DBP_S 14 1781#define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1782 1783#define FW_IQ_CMD_FL1DATANS_S 13 1784#define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1785 1786#define FW_IQ_CMD_FL1DATARO_S 12 1787#define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1788 1789#define FW_IQ_CMD_FL1CONGCIF_S 11 1790#define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1791 1792#define FW_IQ_CMD_FL1ONCHIP_S 10 1793#define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1794 1795#define FW_IQ_CMD_FL1STATUSPGNS_S 9 1796#define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1797 1798#define FW_IQ_CMD_FL1STATUSPGRO_S 8 1799#define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1800 1801#define FW_IQ_CMD_FL1FETCHNS_S 7 1802#define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1803 1804#define FW_IQ_CMD_FL1FETCHRO_S 6 1805#define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1806 1807#define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1808#define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1809 1810#define FW_IQ_CMD_FL1CPRIO_S 3 1811#define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1812 1813#define FW_IQ_CMD_FL1PADEN_S 2 1814#define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1815#define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1816 1817#define FW_IQ_CMD_FL1PACKEN_S 1 1818#define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1819#define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1820 1821#define FW_IQ_CMD_FL1CONGEN_S 0 1822#define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1823#define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1824 1825#define FW_IQ_CMD_FL1DCAEN_S 15 1826#define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1827 1828#define FW_IQ_CMD_FL1DCACPU_S 10 1829#define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1830 1831#define FW_IQ_CMD_FL1FBMIN_S 7 1832#define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1833 1834#define FW_IQ_CMD_FL1FBMAX_S 4 1835#define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1836 1837#define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1838#define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1839#define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1840 1841#define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1842#define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1843 1844struct fw_eq_eth_cmd { 1845 __be32 op_to_vfn; 1846 __be32 alloc_to_len16; 1847 __be32 eqid_pkd; 1848 __be32 physeqid_pkd; 1849 __be32 fetchszm_to_iqid; 1850 __be32 dcaen_to_eqsize; 1851 __be64 eqaddr; 1852 __be32 autoequiqe_to_viid; 1853 __be32 timeren_timerix; 1854 __be64 r9; 1855}; 1856 1857#define FW_EQ_ETH_CMD_PFN_S 8 1858#define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1859 1860#define FW_EQ_ETH_CMD_VFN_S 0 1861#define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1862 1863#define FW_EQ_ETH_CMD_ALLOC_S 31 1864#define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1865#define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1866 1867#define FW_EQ_ETH_CMD_FREE_S 30 1868#define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1869#define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1870 1871#define FW_EQ_ETH_CMD_MODIFY_S 29 1872#define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1873#define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1874 1875#define FW_EQ_ETH_CMD_EQSTART_S 28 1876#define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1877#define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1878 1879#define FW_EQ_ETH_CMD_EQSTOP_S 27 1880#define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1881#define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1882 1883#define FW_EQ_ETH_CMD_EQID_S 0 1884#define FW_EQ_ETH_CMD_EQID_M 0xfffff 1885#define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1886#define FW_EQ_ETH_CMD_EQID_G(x) \ 1887 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1888 1889#define FW_EQ_ETH_CMD_PHYSEQID_S 0 1890#define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1891#define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1892#define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1893 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1894 1895#define FW_EQ_ETH_CMD_FETCHSZM_S 26 1896#define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1897#define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1898 1899#define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1900#define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1901 1902#define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1903#define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1904 1905#define FW_EQ_ETH_CMD_FETCHNS_S 23 1906#define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1907 1908#define FW_EQ_ETH_CMD_FETCHRO_S 22 1909#define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1910#define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1911 1912#define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1913#define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1914 1915#define FW_EQ_ETH_CMD_CPRIO_S 19 1916#define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1917 1918#define FW_EQ_ETH_CMD_ONCHIP_S 18 1919#define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1920 1921#define FW_EQ_ETH_CMD_PCIECHN_S 16 1922#define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1923 1924#define FW_EQ_ETH_CMD_IQID_S 0 1925#define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1926 1927#define FW_EQ_ETH_CMD_DCAEN_S 31 1928#define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1929 1930#define FW_EQ_ETH_CMD_DCACPU_S 26 1931#define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1932 1933#define FW_EQ_ETH_CMD_FBMIN_S 23 1934#define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1935 1936#define FW_EQ_ETH_CMD_FBMAX_S 20 1937#define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1938 1939#define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1940#define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1941 1942#define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1943#define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1944 1945#define FW_EQ_ETH_CMD_EQSIZE_S 0 1946#define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1947 1948#define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31 1949#define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S) 1950#define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U) 1951 1952#define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1953#define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1954#define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1955 1956#define FW_EQ_ETH_CMD_VIID_S 16 1957#define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1958 1959#define FW_EQ_ETH_CMD_TIMEREN_S 3 1960#define FW_EQ_ETH_CMD_TIMEREN_M 0x1 1961#define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S) 1962#define FW_EQ_ETH_CMD_TIMEREN_G(x) \ 1963 (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M) 1964#define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U) 1965 1966#define FW_EQ_ETH_CMD_TIMERIX_S 0 1967#define FW_EQ_ETH_CMD_TIMERIX_M 0x7 1968#define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S) 1969#define FW_EQ_ETH_CMD_TIMERIX_G(x) \ 1970 (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M) 1971 1972struct fw_eq_ctrl_cmd { 1973 __be32 op_to_vfn; 1974 __be32 alloc_to_len16; 1975 __be32 cmpliqid_eqid; 1976 __be32 physeqid_pkd; 1977 __be32 fetchszm_to_iqid; 1978 __be32 dcaen_to_eqsize; 1979 __be64 eqaddr; 1980}; 1981 1982#define FW_EQ_CTRL_CMD_PFN_S 8 1983#define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1984 1985#define FW_EQ_CTRL_CMD_VFN_S 0 1986#define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1987 1988#define FW_EQ_CTRL_CMD_ALLOC_S 31 1989#define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1990#define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1991 1992#define FW_EQ_CTRL_CMD_FREE_S 30 1993#define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1994#define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1995 1996#define FW_EQ_CTRL_CMD_MODIFY_S 29 1997#define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1998#define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1999 2000#define FW_EQ_CTRL_CMD_EQSTART_S 28 2001#define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 2002#define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 2003 2004#define FW_EQ_CTRL_CMD_EQSTOP_S 27 2005#define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 2006#define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 2007 2008#define FW_EQ_CTRL_CMD_CMPLIQID_S 20 2009#define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 2010 2011#define FW_EQ_CTRL_CMD_EQID_S 0 2012#define FW_EQ_CTRL_CMD_EQID_M 0xfffff 2013#define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 2014#define FW_EQ_CTRL_CMD_EQID_G(x) \ 2015 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 2016 2017#define FW_EQ_CTRL_CMD_PHYSEQID_S 0 2018#define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 2019#define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 2020 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 2021 2022#define FW_EQ_CTRL_CMD_FETCHSZM_S 26 2023#define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 2024#define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 2025 2026#define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 2027#define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 2028#define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 2029 2030#define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 2031#define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 2032#define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 2033 2034#define FW_EQ_CTRL_CMD_FETCHNS_S 23 2035#define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 2036#define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 2037 2038#define FW_EQ_CTRL_CMD_FETCHRO_S 22 2039#define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 2040#define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 2041 2042#define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 2043#define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 2044 2045#define FW_EQ_CTRL_CMD_CPRIO_S 19 2046#define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 2047 2048#define FW_EQ_CTRL_CMD_ONCHIP_S 18 2049#define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 2050 2051#define FW_EQ_CTRL_CMD_PCIECHN_S 16 2052#define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 2053 2054#define FW_EQ_CTRL_CMD_IQID_S 0 2055#define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 2056 2057#define FW_EQ_CTRL_CMD_DCAEN_S 31 2058#define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 2059 2060#define FW_EQ_CTRL_CMD_DCACPU_S 26 2061#define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 2062 2063#define FW_EQ_CTRL_CMD_FBMIN_S 23 2064#define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 2065 2066#define FW_EQ_CTRL_CMD_FBMAX_S 20 2067#define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 2068 2069#define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 2070#define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 2071 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 2072 2073#define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 2074#define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 2075 2076#define FW_EQ_CTRL_CMD_EQSIZE_S 0 2077#define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 2078 2079struct fw_eq_ofld_cmd { 2080 __be32 op_to_vfn; 2081 __be32 alloc_to_len16; 2082 __be32 eqid_pkd; 2083 __be32 physeqid_pkd; 2084 __be32 fetchszm_to_iqid; 2085 __be32 dcaen_to_eqsize; 2086 __be64 eqaddr; 2087}; 2088 2089#define FW_EQ_OFLD_CMD_PFN_S 8 2090#define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 2091 2092#define FW_EQ_OFLD_CMD_VFN_S 0 2093#define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 2094 2095#define FW_EQ_OFLD_CMD_ALLOC_S 31 2096#define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 2097#define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 2098 2099#define FW_EQ_OFLD_CMD_FREE_S 30 2100#define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 2101#define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 2102 2103#define FW_EQ_OFLD_CMD_MODIFY_S 29 2104#define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 2105#define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 2106 2107#define FW_EQ_OFLD_CMD_EQSTART_S 28 2108#define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 2109#define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 2110 2111#define FW_EQ_OFLD_CMD_EQSTOP_S 27 2112#define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 2113#define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 2114 2115#define FW_EQ_OFLD_CMD_EQID_S 0 2116#define FW_EQ_OFLD_CMD_EQID_M 0xfffff 2117#define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 2118#define FW_EQ_OFLD_CMD_EQID_G(x) \ 2119 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 2120 2121#define FW_EQ_OFLD_CMD_PHYSEQID_S 0 2122#define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 2123#define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 2124 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 2125 2126#define FW_EQ_OFLD_CMD_FETCHSZM_S 26 2127#define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 2128 2129#define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 2130#define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 2131 2132#define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 2133#define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 2134 2135#define FW_EQ_OFLD_CMD_FETCHNS_S 23 2136#define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 2137 2138#define FW_EQ_OFLD_CMD_FETCHRO_S 22 2139#define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 2140#define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 2141 2142#define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 2143#define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 2144 2145#define FW_EQ_OFLD_CMD_CPRIO_S 19 2146#define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 2147 2148#define FW_EQ_OFLD_CMD_ONCHIP_S 18 2149#define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 2150 2151#define FW_EQ_OFLD_CMD_PCIECHN_S 16 2152#define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 2153 2154#define FW_EQ_OFLD_CMD_IQID_S 0 2155#define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 2156 2157#define FW_EQ_OFLD_CMD_DCAEN_S 31 2158#define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 2159 2160#define FW_EQ_OFLD_CMD_DCACPU_S 26 2161#define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 2162 2163#define FW_EQ_OFLD_CMD_FBMIN_S 23 2164#define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 2165 2166#define FW_EQ_OFLD_CMD_FBMAX_S 20 2167#define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 2168 2169#define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 2170#define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 2171 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 2172 2173#define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 2174#define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 2175 2176#define FW_EQ_OFLD_CMD_EQSIZE_S 0 2177#define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 2178 2179/* 2180 * Macros for VIID parsing: 2181 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 2182 */ 2183 2184#define FW_VIID_PFN_S 8 2185#define FW_VIID_PFN_M 0x7 2186#define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 2187 2188#define FW_VIID_VIVLD_S 7 2189#define FW_VIID_VIVLD_M 0x1 2190#define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 2191 2192#define FW_VIID_VIN_S 0 2193#define FW_VIID_VIN_M 0x7F 2194#define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 2195 2196struct fw_vi_cmd { 2197 __be32 op_to_vfn; 2198 __be32 alloc_to_len16; 2199 __be16 type_viid; 2200 u8 mac[6]; 2201 u8 portid_pkd; 2202 u8 nmac; 2203 u8 nmac0[6]; 2204 __be16 rsssize_pkd; 2205 u8 nmac1[6]; 2206 __be16 idsiiq_pkd; 2207 u8 nmac2[6]; 2208 __be16 idseiq_pkd; 2209 u8 nmac3[6]; 2210 __be64 r9; 2211 __be64 r10; 2212}; 2213 2214#define FW_VI_CMD_PFN_S 8 2215#define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 2216 2217#define FW_VI_CMD_VFN_S 0 2218#define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 2219 2220#define FW_VI_CMD_ALLOC_S 31 2221#define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 2222#define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 2223 2224#define FW_VI_CMD_FREE_S 30 2225#define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 2226#define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 2227 2228#define FW_VI_CMD_VFVLD_S 24 2229#define FW_VI_CMD_VFVLD_M 0x1 2230#define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S) 2231#define FW_VI_CMD_VFVLD_G(x) \ 2232 (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M) 2233#define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1U) 2234 2235#define FW_VI_CMD_VIN_S 16 2236#define FW_VI_CMD_VIN_M 0xff 2237#define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S) 2238#define FW_VI_CMD_VIN_G(x) \ 2239 (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M) 2240 2241#define FW_VI_CMD_VIID_S 0 2242#define FW_VI_CMD_VIID_M 0xfff 2243#define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 2244#define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 2245 2246#define FW_VI_CMD_PORTID_S 4 2247#define FW_VI_CMD_PORTID_M 0xf 2248#define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 2249#define FW_VI_CMD_PORTID_G(x) \ 2250 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 2251 2252#define FW_VI_CMD_RSSSIZE_S 0 2253#define FW_VI_CMD_RSSSIZE_M 0x7ff 2254#define FW_VI_CMD_RSSSIZE_G(x) \ 2255 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 2256 2257/* Special VI_MAC command index ids */ 2258#define FW_VI_MAC_ADD_MAC 0x3FF 2259#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 2260#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 2261#define FW_VI_MAC_ID_BASED_FREE 0x3FC 2262#define FW_CLS_TCAM_NUM_ENTRIES 336 2263 2264enum fw_vi_mac_smac { 2265 FW_VI_MAC_MPS_TCAM_ENTRY, 2266 FW_VI_MAC_MPS_TCAM_ONLY, 2267 FW_VI_MAC_SMT_ONLY, 2268 FW_VI_MAC_SMT_AND_MPSTCAM 2269}; 2270 2271enum fw_vi_mac_result { 2272 FW_VI_MAC_R_SUCCESS, 2273 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 2274 FW_VI_MAC_R_SMAC_FAIL, 2275 FW_VI_MAC_R_F_ACL_CHECK 2276}; 2277 2278enum fw_vi_mac_entry_types { 2279 FW_VI_MAC_TYPE_EXACTMAC, 2280 FW_VI_MAC_TYPE_HASHVEC, 2281 FW_VI_MAC_TYPE_RAW, 2282 FW_VI_MAC_TYPE_EXACTMAC_VNI, 2283}; 2284 2285struct fw_vi_mac_cmd { 2286 __be32 op_to_viid; 2287 __be32 freemacs_to_len16; 2288 union fw_vi_mac { 2289 struct fw_vi_mac_exact { 2290 __be16 valid_to_idx; 2291 u8 macaddr[6]; 2292 } exact[7]; 2293 struct fw_vi_mac_hash { 2294 __be64 hashvec; 2295 } hash; 2296 struct fw_vi_mac_raw { 2297 __be32 raw_idx_pkd; 2298 __be32 data0_pkd; 2299 __be32 data1[2]; 2300 __be64 data0m_pkd; 2301 __be32 data1m[2]; 2302 } raw; 2303 struct fw_vi_mac_vni { 2304 __be16 valid_to_idx; 2305 __u8 macaddr[6]; 2306 __be16 r7; 2307 __u8 macaddr_mask[6]; 2308 __be32 lookup_type_to_vni; 2309 __be32 vni_mask_pkd; 2310 } exact_vni[2]; 2311 } u; 2312}; 2313 2314#define FW_VI_MAC_CMD_SMTID_S 12 2315#define FW_VI_MAC_CMD_SMTID_M 0xff 2316#define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S) 2317#define FW_VI_MAC_CMD_SMTID_G(x) \ 2318 (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M) 2319 2320#define FW_VI_MAC_CMD_VIID_S 0 2321#define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 2322 2323#define FW_VI_MAC_CMD_FREEMACS_S 31 2324#define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2325 2326#define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 2327#define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7 2328#define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S) 2329#define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \ 2330 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M) 2331 2332#define FW_VI_MAC_CMD_HASHVECEN_S 23 2333#define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2334#define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2335 2336#define FW_VI_MAC_CMD_HASHUNIEN_S 22 2337#define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2338 2339#define FW_VI_MAC_CMD_VALID_S 15 2340#define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2341#define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2342 2343#define FW_VI_MAC_CMD_PRIO_S 12 2344#define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2345 2346#define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2347#define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2348#define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2349#define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2350 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2351 2352#define FW_VI_MAC_CMD_IDX_S 0 2353#define FW_VI_MAC_CMD_IDX_M 0x3ff 2354#define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2355#define FW_VI_MAC_CMD_IDX_G(x) \ 2356 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2357 2358#define FW_VI_MAC_CMD_RAW_IDX_S 16 2359#define FW_VI_MAC_CMD_RAW_IDX_M 0xffff 2360#define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S) 2361#define FW_VI_MAC_CMD_RAW_IDX_G(x) \ 2362 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M) 2363 2364#define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31 2365#define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0x1 2366#define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S) 2367#define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \ 2368 (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M) 2369#define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U) 2370 2371#define FW_VI_MAC_CMD_DIP_HIT_S 30 2372#define FW_VI_MAC_CMD_DIP_HIT_M 0x1 2373#define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S) 2374#define FW_VI_MAC_CMD_DIP_HIT_G(x) \ 2375 (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M) 2376#define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1U) 2377 2378#define FW_VI_MAC_CMD_VNI_S 0 2379#define FW_VI_MAC_CMD_VNI_M 0xffffff 2380#define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S) 2381#define FW_VI_MAC_CMD_VNI_G(x) \ 2382 (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M) 2383 2384#define FW_VI_MAC_CMD_VNI_MASK_S 0 2385#define FW_VI_MAC_CMD_VNI_MASK_M 0xffffff 2386#define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S) 2387#define FW_VI_MAC_CMD_VNI_MASK_G(x) \ 2388 (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M) 2389 2390#define FW_RXMODE_MTU_NO_CHG 65535 2391 2392struct fw_vi_rxmode_cmd { 2393 __be32 op_to_viid; 2394 __be32 retval_len16; 2395 __be32 mtu_to_vlanexen; 2396 __be32 r4_lo; 2397}; 2398 2399#define FW_VI_RXMODE_CMD_VIID_S 0 2400#define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2401 2402#define FW_VI_RXMODE_CMD_MTU_S 16 2403#define FW_VI_RXMODE_CMD_MTU_M 0xffff 2404#define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2405 2406#define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2407#define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2408#define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2409 2410#define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2411#define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2412#define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2413 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2414 2415#define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2416#define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2417#define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2418 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2419 2420#define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2421#define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2422#define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2423 2424struct fw_vi_enable_cmd { 2425 __be32 op_to_viid; 2426 __be32 ien_to_len16; 2427 __be16 blinkdur; 2428 __be16 r3; 2429 __be32 r4; 2430}; 2431 2432#define FW_VI_ENABLE_CMD_VIID_S 0 2433#define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2434 2435#define FW_VI_ENABLE_CMD_IEN_S 31 2436#define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2437 2438#define FW_VI_ENABLE_CMD_EEN_S 30 2439#define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2440 2441#define FW_VI_ENABLE_CMD_LED_S 29 2442#define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2443#define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2444 2445#define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2446#define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2447 2448/* VI VF stats offset definitions */ 2449#define VI_VF_NUM_STATS 16 2450enum fw_vi_stats_vf_index { 2451 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2452 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2453 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2454 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2455 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2456 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2457 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2458 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2459 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2460 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2461 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2462 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2463 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2464 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2465 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2466 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2467}; 2468 2469/* VI PF stats offset definitions */ 2470#define VI_PF_NUM_STATS 17 2471enum fw_vi_stats_pf_index { 2472 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2473 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2474 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2475 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2476 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2477 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2478 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2479 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2480 FW_VI_PF_STAT_RX_BYTES_IX, 2481 FW_VI_PF_STAT_RX_FRAMES_IX, 2482 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2483 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2484 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2485 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2486 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2487 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2488 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2489}; 2490 2491struct fw_vi_stats_cmd { 2492 __be32 op_to_viid; 2493 __be32 retval_len16; 2494 union fw_vi_stats { 2495 struct fw_vi_stats_ctl { 2496 __be16 nstats_ix; 2497 __be16 r6; 2498 __be32 r7; 2499 __be64 stat0; 2500 __be64 stat1; 2501 __be64 stat2; 2502 __be64 stat3; 2503 __be64 stat4; 2504 __be64 stat5; 2505 } ctl; 2506 struct fw_vi_stats_pf { 2507 __be64 tx_bcast_bytes; 2508 __be64 tx_bcast_frames; 2509 __be64 tx_mcast_bytes; 2510 __be64 tx_mcast_frames; 2511 __be64 tx_ucast_bytes; 2512 __be64 tx_ucast_frames; 2513 __be64 tx_offload_bytes; 2514 __be64 tx_offload_frames; 2515 __be64 rx_pf_bytes; 2516 __be64 rx_pf_frames; 2517 __be64 rx_bcast_bytes; 2518 __be64 rx_bcast_frames; 2519 __be64 rx_mcast_bytes; 2520 __be64 rx_mcast_frames; 2521 __be64 rx_ucast_bytes; 2522 __be64 rx_ucast_frames; 2523 __be64 rx_err_frames; 2524 } pf; 2525 struct fw_vi_stats_vf { 2526 __be64 tx_bcast_bytes; 2527 __be64 tx_bcast_frames; 2528 __be64 tx_mcast_bytes; 2529 __be64 tx_mcast_frames; 2530 __be64 tx_ucast_bytes; 2531 __be64 tx_ucast_frames; 2532 __be64 tx_drop_frames; 2533 __be64 tx_offload_bytes; 2534 __be64 tx_offload_frames; 2535 __be64 rx_bcast_bytes; 2536 __be64 rx_bcast_frames; 2537 __be64 rx_mcast_bytes; 2538 __be64 rx_mcast_frames; 2539 __be64 rx_ucast_bytes; 2540 __be64 rx_ucast_frames; 2541 __be64 rx_err_frames; 2542 } vf; 2543 } u; 2544}; 2545 2546#define FW_VI_STATS_CMD_VIID_S 0 2547#define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2548 2549#define FW_VI_STATS_CMD_NSTATS_S 12 2550#define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2551 2552#define FW_VI_STATS_CMD_IX_S 0 2553#define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2554 2555struct fw_acl_mac_cmd { 2556 __be32 op_to_vfn; 2557 __be32 en_to_len16; 2558 u8 nmac; 2559 u8 r3[7]; 2560 __be16 r4; 2561 u8 macaddr0[6]; 2562 __be16 r5; 2563 u8 macaddr1[6]; 2564 __be16 r6; 2565 u8 macaddr2[6]; 2566 __be16 r7; 2567 u8 macaddr3[6]; 2568}; 2569 2570#define FW_ACL_MAC_CMD_PFN_S 8 2571#define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2572 2573#define FW_ACL_MAC_CMD_VFN_S 0 2574#define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2575 2576#define FW_ACL_MAC_CMD_EN_S 31 2577#define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2578 2579struct fw_acl_vlan_cmd { 2580 __be32 op_to_vfn; 2581 __be32 en_to_len16; 2582 u8 nvlan; 2583 u8 dropnovlan_fm; 2584 u8 r3_lo[6]; 2585 __be16 vlanid[16]; 2586}; 2587 2588#define FW_ACL_VLAN_CMD_PFN_S 8 2589#define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2590 2591#define FW_ACL_VLAN_CMD_VFN_S 0 2592#define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2593 2594#define FW_ACL_VLAN_CMD_EN_S 31 2595#define FW_ACL_VLAN_CMD_EN_M 0x1 2596#define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2597#define FW_ACL_VLAN_CMD_EN_G(x) \ 2598 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M) 2599#define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U) 2600 2601#define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2602#define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2603#define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U) 2604 2605#define FW_ACL_VLAN_CMD_FM_S 6 2606#define FW_ACL_VLAN_CMD_FM_M 0x1 2607#define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2608#define FW_ACL_VLAN_CMD_FM_G(x) \ 2609 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M) 2610#define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U) 2611 2612/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2613enum fw_port_cap { 2614 FW_PORT_CAP_SPEED_100M = 0x0001, 2615 FW_PORT_CAP_SPEED_1G = 0x0002, 2616 FW_PORT_CAP_SPEED_25G = 0x0004, 2617 FW_PORT_CAP_SPEED_10G = 0x0008, 2618 FW_PORT_CAP_SPEED_40G = 0x0010, 2619 FW_PORT_CAP_SPEED_100G = 0x0020, 2620 FW_PORT_CAP_FC_RX = 0x0040, 2621 FW_PORT_CAP_FC_TX = 0x0080, 2622 FW_PORT_CAP_ANEG = 0x0100, 2623 FW_PORT_CAP_MDIAUTO = 0x0200, 2624 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 2625 FW_PORT_CAP_FEC_RS = 0x0800, 2626 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 2627 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 2628 FW_PORT_CAP_802_3_PAUSE = 0x4000, 2629 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2630}; 2631 2632#define FW_PORT_CAP_SPEED_S 0 2633#define FW_PORT_CAP_SPEED_M 0x3f 2634#define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 2635#define FW_PORT_CAP_SPEED_G(x) \ 2636 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 2637 2638enum fw_port_mdi { 2639 FW_PORT_CAP_MDI_UNCHANGED, 2640 FW_PORT_CAP_MDI_AUTO, 2641 FW_PORT_CAP_MDI_F_STRAIGHT, 2642 FW_PORT_CAP_MDI_F_CROSSOVER 2643}; 2644 2645#define FW_PORT_CAP_MDI_S 9 2646#define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2647 2648/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2649#define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2650#define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2651#define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2652#define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2653#define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2654#define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2655#define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2656#define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2657#define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2658#define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2659#define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2660#define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2661#define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2662#define FW_PORT_CAP32_FC_RX 0x00010000UL 2663#define FW_PORT_CAP32_FC_TX 0x00020000UL 2664#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2665#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2666#define FW_PORT_CAP32_ANEG 0x00100000UL 2667#define FW_PORT_CAP32_MDIAUTO 0x00200000UL 2668#define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 2669#define FW_PORT_CAP32_FEC_RS 0x00800000UL 2670#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2671#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2672#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2673#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2674#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 2675#define FW_PORT_CAP32_RESERVED2 0xe0000000UL 2676 2677#define FW_PORT_CAP32_SPEED_S 0 2678#define FW_PORT_CAP32_SPEED_M 0xfff 2679#define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2680#define FW_PORT_CAP32_SPEED_G(x) \ 2681 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2682 2683#define FW_PORT_CAP32_FC_S 16 2684#define FW_PORT_CAP32_FC_M 0x3 2685#define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2686#define FW_PORT_CAP32_FC_G(x) \ 2687 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2688 2689#define FW_PORT_CAP32_802_3_S 18 2690#define FW_PORT_CAP32_802_3_M 0x3 2691#define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2692#define FW_PORT_CAP32_802_3_G(x) \ 2693 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2694 2695#define FW_PORT_CAP32_ANEG_S 20 2696#define FW_PORT_CAP32_ANEG_M 0x1 2697#define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2698#define FW_PORT_CAP32_ANEG_G(x) \ 2699 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2700 2701enum fw_port_mdi32 { 2702 FW_PORT_CAP32_MDI_UNCHANGED, 2703 FW_PORT_CAP32_MDI_AUTO, 2704 FW_PORT_CAP32_MDI_F_STRAIGHT, 2705 FW_PORT_CAP32_MDI_F_CROSSOVER 2706}; 2707 2708#define FW_PORT_CAP32_MDI_S 21 2709#define FW_PORT_CAP32_MDI_M 3 2710#define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2711#define FW_PORT_CAP32_MDI_G(x) \ 2712 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2713 2714#define FW_PORT_CAP32_FEC_S 23 2715#define FW_PORT_CAP32_FEC_M 0x1f 2716#define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2717#define FW_PORT_CAP32_FEC_G(x) \ 2718 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2719 2720/* macros to isolate various 32-bit Port Capabilities sub-fields */ 2721#define CAP32_SPEED(__cap32) \ 2722 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2723 2724#define CAP32_FEC(__cap32) \ 2725 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2726 2727enum fw_port_action { 2728 FW_PORT_ACTION_L1_CFG = 0x0001, 2729 FW_PORT_ACTION_L2_CFG = 0x0002, 2730 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2731 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2732 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2733 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2734 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2735 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2736 FW_PORT_ACTION_L1_CFG32 = 0x0009, 2737 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2738 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2739 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2740 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2741 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2742 FW_PORT_ACTION_L1_LPBK = 0x0021, 2743 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2744 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2745 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2746 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2747 FW_PORT_ACTION_PHY_RESET = 0x0040, 2748 FW_PORT_ACTION_PMA_RESET = 0x0041, 2749 FW_PORT_ACTION_PCS_RESET = 0x0042, 2750 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2751 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2752 FW_PORT_ACTION_AN_RESET = 0x0045 2753}; 2754 2755enum fw_port_l2cfg_ctlbf { 2756 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2757 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2758 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2759 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2760 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2761 FW_PORT_L2_CTLBF_TXIPG = 0x20 2762}; 2763 2764enum fw_port_dcb_versions { 2765 FW_PORT_DCB_VER_UNKNOWN, 2766 FW_PORT_DCB_VER_CEE1D0, 2767 FW_PORT_DCB_VER_CEE1D01, 2768 FW_PORT_DCB_VER_IEEE, 2769 FW_PORT_DCB_VER_AUTO = 7 2770}; 2771 2772enum fw_port_dcb_cfg { 2773 FW_PORT_DCB_CFG_PG = 0x01, 2774 FW_PORT_DCB_CFG_PFC = 0x02, 2775 FW_PORT_DCB_CFG_APPL = 0x04 2776}; 2777 2778enum fw_port_dcb_cfg_rc { 2779 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2780 FW_PORT_DCB_CFG_ERROR = 0x1 2781}; 2782 2783enum fw_port_dcb_type { 2784 FW_PORT_DCB_TYPE_PGID = 0x00, 2785 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2786 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2787 FW_PORT_DCB_TYPE_PFC = 0x03, 2788 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2789 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2790}; 2791 2792enum fw_port_dcb_feature_state { 2793 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2794 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2795 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2796 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2797}; 2798 2799struct fw_port_cmd { 2800 __be32 op_to_portid; 2801 __be32 action_to_len16; 2802 union fw_port { 2803 struct fw_port_l1cfg { 2804 __be32 rcap; 2805 __be32 r; 2806 } l1cfg; 2807 struct fw_port_l2cfg { 2808 __u8 ctlbf; 2809 __u8 ovlan3_to_ivlan0; 2810 __be16 ivlantype; 2811 __be16 txipg_force_pinfo; 2812 __be16 mtu; 2813 __be16 ovlan0mask; 2814 __be16 ovlan0type; 2815 __be16 ovlan1mask; 2816 __be16 ovlan1type; 2817 __be16 ovlan2mask; 2818 __be16 ovlan2type; 2819 __be16 ovlan3mask; 2820 __be16 ovlan3type; 2821 } l2cfg; 2822 struct fw_port_info { 2823 __be32 lstatus_to_modtype; 2824 __be16 pcap; 2825 __be16 acap; 2826 __be16 mtu; 2827 __u8 cbllen; 2828 __u8 auxlinfo; 2829 __u8 dcbxdis_pkd; 2830 __u8 r8_lo; 2831 __be16 lpacap; 2832 __be64 r9; 2833 } info; 2834 struct fw_port_diags { 2835 __u8 diagop; 2836 __u8 r[3]; 2837 __be32 diagval; 2838 } diags; 2839 union fw_port_dcb { 2840 struct fw_port_dcb_pgid { 2841 __u8 type; 2842 __u8 apply_pkd; 2843 __u8 r10_lo[2]; 2844 __be32 pgid; 2845 __be64 r11; 2846 } pgid; 2847 struct fw_port_dcb_pgrate { 2848 __u8 type; 2849 __u8 apply_pkd; 2850 __u8 r10_lo[5]; 2851 __u8 num_tcs_supported; 2852 __u8 pgrate[8]; 2853 __u8 tsa[8]; 2854 } pgrate; 2855 struct fw_port_dcb_priorate { 2856 __u8 type; 2857 __u8 apply_pkd; 2858 __u8 r10_lo[6]; 2859 __u8 strict_priorate[8]; 2860 } priorate; 2861 struct fw_port_dcb_pfc { 2862 __u8 type; 2863 __u8 pfcen; 2864 __u8 r10[5]; 2865 __u8 max_pfc_tcs; 2866 __be64 r11; 2867 } pfc; 2868 struct fw_port_app_priority { 2869 __u8 type; 2870 __u8 r10[2]; 2871 __u8 idx; 2872 __u8 user_prio_map; 2873 __u8 sel_field; 2874 __be16 protocolid; 2875 __be64 r12; 2876 } app_priority; 2877 struct fw_port_dcb_control { 2878 __u8 type; 2879 __u8 all_syncd_pkd; 2880 __be16 dcb_version_to_app_state; 2881 __be32 r11; 2882 __be64 r12; 2883 } control; 2884 } dcb; 2885 struct fw_port_l1cfg32 { 2886 __be32 rcap32; 2887 __be32 r; 2888 } l1cfg32; 2889 struct fw_port_info32 { 2890 __be32 lstatus32_to_cbllen32; 2891 __be32 auxlinfo32_mtu32; 2892 __be32 linkattr32; 2893 __be32 pcaps32; 2894 __be32 acaps32; 2895 __be32 lpacaps32; 2896 } info32; 2897 } u; 2898}; 2899 2900#define FW_PORT_CMD_READ_S 22 2901#define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2902#define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2903 2904#define FW_PORT_CMD_PORTID_S 0 2905#define FW_PORT_CMD_PORTID_M 0xf 2906#define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2907#define FW_PORT_CMD_PORTID_G(x) \ 2908 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2909 2910#define FW_PORT_CMD_ACTION_S 16 2911#define FW_PORT_CMD_ACTION_M 0xffff 2912#define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2913#define FW_PORT_CMD_ACTION_G(x) \ 2914 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2915 2916#define FW_PORT_CMD_OVLAN3_S 7 2917#define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2918 2919#define FW_PORT_CMD_OVLAN2_S 6 2920#define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2921 2922#define FW_PORT_CMD_OVLAN1_S 5 2923#define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2924 2925#define FW_PORT_CMD_OVLAN0_S 4 2926#define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2927 2928#define FW_PORT_CMD_IVLAN0_S 3 2929#define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2930 2931#define FW_PORT_CMD_TXIPG_S 3 2932#define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2933 2934#define FW_PORT_CMD_LSTATUS_S 31 2935#define FW_PORT_CMD_LSTATUS_M 0x1 2936#define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2937#define FW_PORT_CMD_LSTATUS_G(x) \ 2938 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2939#define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2940 2941#define FW_PORT_CMD_LSPEED_S 24 2942#define FW_PORT_CMD_LSPEED_M 0x3f 2943#define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2944#define FW_PORT_CMD_LSPEED_G(x) \ 2945 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2946 2947#define FW_PORT_CMD_TXPAUSE_S 23 2948#define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2949#define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2950 2951#define FW_PORT_CMD_RXPAUSE_S 22 2952#define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2953#define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2954 2955#define FW_PORT_CMD_MDIOCAP_S 21 2956#define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2957#define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2958 2959#define FW_PORT_CMD_MDIOADDR_S 16 2960#define FW_PORT_CMD_MDIOADDR_M 0x1f 2961#define FW_PORT_CMD_MDIOADDR_G(x) \ 2962 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2963 2964#define FW_PORT_CMD_LPTXPAUSE_S 15 2965#define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2966#define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2967 2968#define FW_PORT_CMD_LPRXPAUSE_S 14 2969#define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2970#define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2971 2972#define FW_PORT_CMD_PTYPE_S 8 2973#define FW_PORT_CMD_PTYPE_M 0x1f 2974#define FW_PORT_CMD_PTYPE_G(x) \ 2975 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2976 2977#define FW_PORT_CMD_LINKDNRC_S 5 2978#define FW_PORT_CMD_LINKDNRC_M 0x7 2979#define FW_PORT_CMD_LINKDNRC_G(x) \ 2980 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2981 2982#define FW_PORT_CMD_MODTYPE_S 0 2983#define FW_PORT_CMD_MODTYPE_M 0x1f 2984#define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2985#define FW_PORT_CMD_MODTYPE_G(x) \ 2986 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2987 2988#define FW_PORT_CMD_DCBXDIS_S 7 2989#define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2990#define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2991 2992#define FW_PORT_CMD_APPLY_S 7 2993#define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2994#define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2995 2996#define FW_PORT_CMD_ALL_SYNCD_S 7 2997#define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2998#define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2999 3000#define FW_PORT_CMD_DCB_VERSION_S 12 3001#define FW_PORT_CMD_DCB_VERSION_M 0x7 3002#define FW_PORT_CMD_DCB_VERSION_G(x) \ 3003 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 3004 3005#define FW_PORT_CMD_LSTATUS32_S 31 3006#define FW_PORT_CMD_LSTATUS32_M 0x1 3007#define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 3008#define FW_PORT_CMD_LSTATUS32_G(x) \ 3009 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 3010#define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 3011 3012#define FW_PORT_CMD_LINKDNRC32_S 28 3013#define FW_PORT_CMD_LINKDNRC32_M 0x7 3014#define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 3015#define FW_PORT_CMD_LINKDNRC32_G(x) \ 3016 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 3017 3018#define FW_PORT_CMD_DCBXDIS32_S 27 3019#define FW_PORT_CMD_DCBXDIS32_M 0x1 3020#define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 3021#define FW_PORT_CMD_DCBXDIS32_G(x) \ 3022 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 3023#define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 3024 3025#define FW_PORT_CMD_MDIOCAP32_S 26 3026#define FW_PORT_CMD_MDIOCAP32_M 0x1 3027#define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 3028#define FW_PORT_CMD_MDIOCAP32_G(x) \ 3029 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 3030#define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 3031 3032#define FW_PORT_CMD_MDIOADDR32_S 21 3033#define FW_PORT_CMD_MDIOADDR32_M 0x1f 3034#define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 3035#define FW_PORT_CMD_MDIOADDR32_G(x) \ 3036 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 3037 3038#define FW_PORT_CMD_PORTTYPE32_S 13 3039#define FW_PORT_CMD_PORTTYPE32_M 0xff 3040#define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 3041#define FW_PORT_CMD_PORTTYPE32_G(x) \ 3042 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 3043 3044#define FW_PORT_CMD_MODTYPE32_S 8 3045#define FW_PORT_CMD_MODTYPE32_M 0x1f 3046#define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 3047#define FW_PORT_CMD_MODTYPE32_G(x) \ 3048 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 3049 3050#define FW_PORT_CMD_CBLLEN32_S 0 3051#define FW_PORT_CMD_CBLLEN32_M 0xff 3052#define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 3053#define FW_PORT_CMD_CBLLEN32_G(x) \ 3054 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 3055 3056#define FW_PORT_CMD_AUXLINFO32_S 24 3057#define FW_PORT_CMD_AUXLINFO32_M 0xff 3058#define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 3059#define FW_PORT_CMD_AUXLINFO32_G(x) \ 3060 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 3061 3062#define FW_PORT_AUXLINFO32_KX4_S 2 3063#define FW_PORT_AUXLINFO32_KX4_M 0x1 3064#define FW_PORT_AUXLINFO32_KX4_V(x) \ 3065 ((x) << FW_PORT_AUXLINFO32_KX4_S) 3066#define FW_PORT_AUXLINFO32_KX4_G(x) \ 3067 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 3068#define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 3069 3070#define FW_PORT_AUXLINFO32_KR_S 1 3071#define FW_PORT_AUXLINFO32_KR_M 0x1 3072#define FW_PORT_AUXLINFO32_KR_V(x) \ 3073 ((x) << FW_PORT_AUXLINFO32_KR_S) 3074#define FW_PORT_AUXLINFO32_KR_G(x) \ 3075 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 3076#define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 3077 3078#define FW_PORT_CMD_MTU32_S 0 3079#define FW_PORT_CMD_MTU32_M 0xffff 3080#define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 3081#define FW_PORT_CMD_MTU32_G(x) \ 3082 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 3083 3084enum fw_port_type { 3085 FW_PORT_TYPE_FIBER_XFI, 3086 FW_PORT_TYPE_FIBER_XAUI, 3087 FW_PORT_TYPE_BT_SGMII, 3088 FW_PORT_TYPE_BT_XFI, 3089 FW_PORT_TYPE_BT_XAUI, 3090 FW_PORT_TYPE_KX4, 3091 FW_PORT_TYPE_CX4, 3092 FW_PORT_TYPE_KX, 3093 FW_PORT_TYPE_KR, 3094 FW_PORT_TYPE_SFP, 3095 FW_PORT_TYPE_BP_AP, 3096 FW_PORT_TYPE_BP4_AP, 3097 FW_PORT_TYPE_QSFP_10G, 3098 FW_PORT_TYPE_QSA, 3099 FW_PORT_TYPE_QSFP, 3100 FW_PORT_TYPE_BP40_BA, 3101 FW_PORT_TYPE_KR4_100G, 3102 FW_PORT_TYPE_CR4_QSFP, 3103 FW_PORT_TYPE_CR_QSFP, 3104 FW_PORT_TYPE_CR2_QSFP, 3105 FW_PORT_TYPE_SFP28, 3106 FW_PORT_TYPE_KR_SFP28, 3107 FW_PORT_TYPE_KR_XLAUI, 3108 3109 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 3110}; 3111 3112enum fw_port_module_type { 3113 FW_PORT_MOD_TYPE_NA, 3114 FW_PORT_MOD_TYPE_LR, 3115 FW_PORT_MOD_TYPE_SR, 3116 FW_PORT_MOD_TYPE_ER, 3117 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 3118 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 3119 FW_PORT_MOD_TYPE_LRM, 3120 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 3121 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 3122 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 3123 3124 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 3125}; 3126 3127enum fw_port_mod_sub_type { 3128 FW_PORT_MOD_SUB_TYPE_NA, 3129 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 3130 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 3131 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 3132 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 3133 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 3134 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 3135 3136 /* The following will never been in the VPD. They are TWINAX cable 3137 * lengths decoded from SFP+ module i2c PROMs. These should 3138 * almost certainly go somewhere else ... 3139 */ 3140 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 3141 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 3142 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 3143 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 3144}; 3145 3146enum fw_port_stats_tx_index { 3147 FW_STAT_TX_PORT_BYTES_IX = 0, 3148 FW_STAT_TX_PORT_FRAMES_IX, 3149 FW_STAT_TX_PORT_BCAST_IX, 3150 FW_STAT_TX_PORT_MCAST_IX, 3151 FW_STAT_TX_PORT_UCAST_IX, 3152 FW_STAT_TX_PORT_ERROR_IX, 3153 FW_STAT_TX_PORT_64B_IX, 3154 FW_STAT_TX_PORT_65B_127B_IX, 3155 FW_STAT_TX_PORT_128B_255B_IX, 3156 FW_STAT_TX_PORT_256B_511B_IX, 3157 FW_STAT_TX_PORT_512B_1023B_IX, 3158 FW_STAT_TX_PORT_1024B_1518B_IX, 3159 FW_STAT_TX_PORT_1519B_MAX_IX, 3160 FW_STAT_TX_PORT_DROP_IX, 3161 FW_STAT_TX_PORT_PAUSE_IX, 3162 FW_STAT_TX_PORT_PPP0_IX, 3163 FW_STAT_TX_PORT_PPP1_IX, 3164 FW_STAT_TX_PORT_PPP2_IX, 3165 FW_STAT_TX_PORT_PPP3_IX, 3166 FW_STAT_TX_PORT_PPP4_IX, 3167 FW_STAT_TX_PORT_PPP5_IX, 3168 FW_STAT_TX_PORT_PPP6_IX, 3169 FW_STAT_TX_PORT_PPP7_IX, 3170 FW_NUM_PORT_TX_STATS 3171}; 3172 3173enum fw_port_stat_rx_index { 3174 FW_STAT_RX_PORT_BYTES_IX = 0, 3175 FW_STAT_RX_PORT_FRAMES_IX, 3176 FW_STAT_RX_PORT_BCAST_IX, 3177 FW_STAT_RX_PORT_MCAST_IX, 3178 FW_STAT_RX_PORT_UCAST_IX, 3179 FW_STAT_RX_PORT_MTU_ERROR_IX, 3180 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 3181 FW_STAT_RX_PORT_CRC_ERROR_IX, 3182 FW_STAT_RX_PORT_LEN_ERROR_IX, 3183 FW_STAT_RX_PORT_SYM_ERROR_IX, 3184 FW_STAT_RX_PORT_64B_IX, 3185 FW_STAT_RX_PORT_65B_127B_IX, 3186 FW_STAT_RX_PORT_128B_255B_IX, 3187 FW_STAT_RX_PORT_256B_511B_IX, 3188 FW_STAT_RX_PORT_512B_1023B_IX, 3189 FW_STAT_RX_PORT_1024B_1518B_IX, 3190 FW_STAT_RX_PORT_1519B_MAX_IX, 3191 FW_STAT_RX_PORT_PAUSE_IX, 3192 FW_STAT_RX_PORT_PPP0_IX, 3193 FW_STAT_RX_PORT_PPP1_IX, 3194 FW_STAT_RX_PORT_PPP2_IX, 3195 FW_STAT_RX_PORT_PPP3_IX, 3196 FW_STAT_RX_PORT_PPP4_IX, 3197 FW_STAT_RX_PORT_PPP5_IX, 3198 FW_STAT_RX_PORT_PPP6_IX, 3199 FW_STAT_RX_PORT_PPP7_IX, 3200 FW_STAT_RX_PORT_LESS_64B_IX, 3201 FW_STAT_RX_PORT_MAC_ERROR_IX, 3202 FW_NUM_PORT_RX_STATS 3203}; 3204 3205/* port stats */ 3206#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 3207 3208struct fw_port_stats_cmd { 3209 __be32 op_to_portid; 3210 __be32 retval_len16; 3211 union fw_port_stats { 3212 struct fw_port_stats_ctl { 3213 u8 nstats_bg_bm; 3214 u8 tx_ix; 3215 __be16 r6; 3216 __be32 r7; 3217 __be64 stat0; 3218 __be64 stat1; 3219 __be64 stat2; 3220 __be64 stat3; 3221 __be64 stat4; 3222 __be64 stat5; 3223 } ctl; 3224 struct fw_port_stats_all { 3225 __be64 tx_bytes; 3226 __be64 tx_frames; 3227 __be64 tx_bcast; 3228 __be64 tx_mcast; 3229 __be64 tx_ucast; 3230 __be64 tx_error; 3231 __be64 tx_64b; 3232 __be64 tx_65b_127b; 3233 __be64 tx_128b_255b; 3234 __be64 tx_256b_511b; 3235 __be64 tx_512b_1023b; 3236 __be64 tx_1024b_1518b; 3237 __be64 tx_1519b_max; 3238 __be64 tx_drop; 3239 __be64 tx_pause; 3240 __be64 tx_ppp0; 3241 __be64 tx_ppp1; 3242 __be64 tx_ppp2; 3243 __be64 tx_ppp3; 3244 __be64 tx_ppp4; 3245 __be64 tx_ppp5; 3246 __be64 tx_ppp6; 3247 __be64 tx_ppp7; 3248 __be64 rx_bytes; 3249 __be64 rx_frames; 3250 __be64 rx_bcast; 3251 __be64 rx_mcast; 3252 __be64 rx_ucast; 3253 __be64 rx_mtu_error; 3254 __be64 rx_mtu_crc_error; 3255 __be64 rx_crc_error; 3256 __be64 rx_len_error; 3257 __be64 rx_sym_error; 3258 __be64 rx_64b; 3259 __be64 rx_65b_127b; 3260 __be64 rx_128b_255b; 3261 __be64 rx_256b_511b; 3262 __be64 rx_512b_1023b; 3263 __be64 rx_1024b_1518b; 3264 __be64 rx_1519b_max; 3265 __be64 rx_pause; 3266 __be64 rx_ppp0; 3267 __be64 rx_ppp1; 3268 __be64 rx_ppp2; 3269 __be64 rx_ppp3; 3270 __be64 rx_ppp4; 3271 __be64 rx_ppp5; 3272 __be64 rx_ppp6; 3273 __be64 rx_ppp7; 3274 __be64 rx_less_64b; 3275 __be64 rx_bg_drop; 3276 __be64 rx_bg_trunc; 3277 } all; 3278 } u; 3279}; 3280 3281/* port loopback stats */ 3282#define FW_NUM_LB_STATS 16 3283enum fw_port_lb_stats_index { 3284 FW_STAT_LB_PORT_BYTES_IX, 3285 FW_STAT_LB_PORT_FRAMES_IX, 3286 FW_STAT_LB_PORT_BCAST_IX, 3287 FW_STAT_LB_PORT_MCAST_IX, 3288 FW_STAT_LB_PORT_UCAST_IX, 3289 FW_STAT_LB_PORT_ERROR_IX, 3290 FW_STAT_LB_PORT_64B_IX, 3291 FW_STAT_LB_PORT_65B_127B_IX, 3292 FW_STAT_LB_PORT_128B_255B_IX, 3293 FW_STAT_LB_PORT_256B_511B_IX, 3294 FW_STAT_LB_PORT_512B_1023B_IX, 3295 FW_STAT_LB_PORT_1024B_1518B_IX, 3296 FW_STAT_LB_PORT_1519B_MAX_IX, 3297 FW_STAT_LB_PORT_DROP_FRAMES_IX 3298}; 3299 3300struct fw_port_lb_stats_cmd { 3301 __be32 op_to_lbport; 3302 __be32 retval_len16; 3303 union fw_port_lb_stats { 3304 struct fw_port_lb_stats_ctl { 3305 u8 nstats_bg_bm; 3306 u8 ix_pkd; 3307 __be16 r6; 3308 __be32 r7; 3309 __be64 stat0; 3310 __be64 stat1; 3311 __be64 stat2; 3312 __be64 stat3; 3313 __be64 stat4; 3314 __be64 stat5; 3315 } ctl; 3316 struct fw_port_lb_stats_all { 3317 __be64 tx_bytes; 3318 __be64 tx_frames; 3319 __be64 tx_bcast; 3320 __be64 tx_mcast; 3321 __be64 tx_ucast; 3322 __be64 tx_error; 3323 __be64 tx_64b; 3324 __be64 tx_65b_127b; 3325 __be64 tx_128b_255b; 3326 __be64 tx_256b_511b; 3327 __be64 tx_512b_1023b; 3328 __be64 tx_1024b_1518b; 3329 __be64 tx_1519b_max; 3330 __be64 rx_lb_drop; 3331 __be64 rx_lb_trunc; 3332 } all; 3333 } u; 3334}; 3335 3336enum fw_ptp_subop { 3337 /* none */ 3338 FW_PTP_SC_INIT_TIMER = 0x00, 3339 FW_PTP_SC_TX_TYPE = 0x01, 3340 /* init */ 3341 FW_PTP_SC_RXTIME_STAMP = 0x08, 3342 FW_PTP_SC_RDRX_TYPE = 0x09, 3343 /* ts */ 3344 FW_PTP_SC_ADJ_FREQ = 0x10, 3345 FW_PTP_SC_ADJ_TIME = 0x11, 3346 FW_PTP_SC_ADJ_FTIME = 0x12, 3347 FW_PTP_SC_WALL_CLOCK = 0x13, 3348 FW_PTP_SC_GET_TIME = 0x14, 3349 FW_PTP_SC_SET_TIME = 0x15, 3350}; 3351 3352struct fw_ptp_cmd { 3353 __be32 op_to_portid; 3354 __be32 retval_len16; 3355 union fw_ptp { 3356 struct fw_ptp_sc { 3357 __u8 sc; 3358 __u8 r3[7]; 3359 } scmd; 3360 struct fw_ptp_init { 3361 __u8 sc; 3362 __u8 txchan; 3363 __be16 absid; 3364 __be16 mode; 3365 __be16 r3; 3366 } init; 3367 struct fw_ptp_ts { 3368 __u8 sc; 3369 __u8 sign; 3370 __be16 r3; 3371 __be32 ppb; 3372 __be64 tm; 3373 } ts; 3374 } u; 3375 __be64 r3; 3376}; 3377 3378#define FW_PTP_CMD_PORTID_S 0 3379#define FW_PTP_CMD_PORTID_M 0xf 3380#define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3381#define FW_PTP_CMD_PORTID_G(x) \ 3382 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3383 3384struct fw_rss_ind_tbl_cmd { 3385 __be32 op_to_viid; 3386 __be32 retval_len16; 3387 __be16 niqid; 3388 __be16 startidx; 3389 __be32 r3; 3390 __be32 iq0_to_iq2; 3391 __be32 iq3_to_iq5; 3392 __be32 iq6_to_iq8; 3393 __be32 iq9_to_iq11; 3394 __be32 iq12_to_iq14; 3395 __be32 iq15_to_iq17; 3396 __be32 iq18_to_iq20; 3397 __be32 iq21_to_iq23; 3398 __be32 iq24_to_iq26; 3399 __be32 iq27_to_iq29; 3400 __be32 iq30_iq31; 3401 __be32 r15_lo; 3402}; 3403 3404#define FW_RSS_IND_TBL_CMD_VIID_S 0 3405#define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3406 3407#define FW_RSS_IND_TBL_CMD_IQ0_S 20 3408#define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3409 3410#define FW_RSS_IND_TBL_CMD_IQ1_S 10 3411#define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3412 3413#define FW_RSS_IND_TBL_CMD_IQ2_S 0 3414#define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3415 3416struct fw_rss_glb_config_cmd { 3417 __be32 op_to_write; 3418 __be32 retval_len16; 3419 union fw_rss_glb_config { 3420 struct fw_rss_glb_config_manual { 3421 __be32 mode_pkd; 3422 __be32 r3; 3423 __be64 r4; 3424 __be64 r5; 3425 } manual; 3426 struct fw_rss_glb_config_basicvirtual { 3427 __be32 mode_pkd; 3428 __be32 synmapen_to_hashtoeplitz; 3429 __be64 r8; 3430 __be64 r9; 3431 } basicvirtual; 3432 } u; 3433}; 3434 3435#define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3436#define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3437#define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3438#define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3439 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3440 3441#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3442#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3443 3444#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3445#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3446 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3447#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3448 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3449 3450#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3451#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3452 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3453#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3454 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3455 3456#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3457#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3458 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3459#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3460 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3461 3462#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3463#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3464 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3465#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3466 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3467 3468#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3469#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3470 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3471#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3472 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3473 3474#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3475#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3476 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3477#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3478 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3479 3480#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3481#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3482 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3483#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3484 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3485 3486#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3487#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3488 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3489#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3490 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3491 3492#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3493#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3494 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3495#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3496 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3497 3498struct fw_rss_vi_config_cmd { 3499 __be32 op_to_viid; 3500#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3501 __be32 retval_len16; 3502 union fw_rss_vi_config { 3503 struct fw_rss_vi_config_manual { 3504 __be64 r3; 3505 __be64 r4; 3506 __be64 r5; 3507 } manual; 3508 struct fw_rss_vi_config_basicvirtual { 3509 __be32 r6; 3510 __be32 defaultq_to_udpen; 3511 __be64 r9; 3512 __be64 r10; 3513 } basicvirtual; 3514 } u; 3515}; 3516 3517#define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3518#define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3519 3520#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3521#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3522#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3523 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3524#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3525 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3526 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3527 3528#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3529#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3530 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3531#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3532 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3533 3534#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3535#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3536 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3537#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3538 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3539 3540#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3541#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3542 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3543#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3544 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3545 3546#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3547#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3548 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3549#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3550 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3551 3552#define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3553#define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3554#define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3555 3556enum fw_sched_sc { 3557 FW_SCHED_SC_PARAMS = 1, 3558}; 3559 3560struct fw_sched_cmd { 3561 __be32 op_to_write; 3562 __be32 retval_len16; 3563 union fw_sched { 3564 struct fw_sched_config { 3565 __u8 sc; 3566 __u8 type; 3567 __u8 minmaxen; 3568 __u8 r3[5]; 3569 __u8 nclasses[4]; 3570 __be32 r4; 3571 } config; 3572 struct fw_sched_params { 3573 __u8 sc; 3574 __u8 type; 3575 __u8 level; 3576 __u8 mode; 3577 __u8 unit; 3578 __u8 rate; 3579 __u8 ch; 3580 __u8 cl; 3581 __be32 min; 3582 __be32 max; 3583 __be16 weight; 3584 __be16 pktsize; 3585 __be16 burstsize; 3586 __be16 r4; 3587 } params; 3588 } u; 3589}; 3590 3591struct fw_clip_cmd { 3592 __be32 op_to_write; 3593 __be32 alloc_to_len16; 3594 __be64 ip_hi; 3595 __be64 ip_lo; 3596 __be32 r4[2]; 3597}; 3598 3599#define FW_CLIP_CMD_ALLOC_S 31 3600#define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3601#define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 3602 3603#define FW_CLIP_CMD_FREE_S 30 3604#define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3605#define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 3606 3607enum fw_error_type { 3608 FW_ERROR_TYPE_EXCEPTION = 0x0, 3609 FW_ERROR_TYPE_HWMODULE = 0x1, 3610 FW_ERROR_TYPE_WR = 0x2, 3611 FW_ERROR_TYPE_ACL = 0x3, 3612}; 3613 3614struct fw_error_cmd { 3615 __be32 op_to_type; 3616 __be32 len16_pkd; 3617 union fw_error { 3618 struct fw_error_exception { 3619 __be32 info[6]; 3620 } exception; 3621 struct fw_error_hwmodule { 3622 __be32 regaddr; 3623 __be32 regval; 3624 } hwmodule; 3625 struct fw_error_wr { 3626 __be16 cidx; 3627 __be16 pfn_vfn; 3628 __be32 eqid; 3629 u8 wrhdr[16]; 3630 } wr; 3631 struct fw_error_acl { 3632 __be16 cidx; 3633 __be16 pfn_vfn; 3634 __be32 eqid; 3635 __be16 mv_pkd; 3636 u8 val[6]; 3637 __be64 r4; 3638 } acl; 3639 } u; 3640}; 3641 3642struct fw_debug_cmd { 3643 __be32 op_type; 3644 __be32 len16_pkd; 3645 union fw_debug { 3646 struct fw_debug_assert { 3647 __be32 fcid; 3648 __be32 line; 3649 __be32 x; 3650 __be32 y; 3651 u8 filename_0_7[8]; 3652 u8 filename_8_15[8]; 3653 __be64 r3; 3654 } assert; 3655 struct fw_debug_prt { 3656 __be16 dprtstridx; 3657 __be16 r3[3]; 3658 __be32 dprtstrparam0; 3659 __be32 dprtstrparam1; 3660 __be32 dprtstrparam2; 3661 __be32 dprtstrparam3; 3662 } prt; 3663 } u; 3664}; 3665 3666#define FW_DEBUG_CMD_TYPE_S 0 3667#define FW_DEBUG_CMD_TYPE_M 0xff 3668#define FW_DEBUG_CMD_TYPE_G(x) \ 3669 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3670 3671struct fw_hma_cmd { 3672 __be32 op_pkd; 3673 __be32 retval_len16; 3674 __be32 mode_to_pcie_params; 3675 __be32 naddr_size; 3676 __be32 addr_size_pkd; 3677 __be32 r6; 3678 __be64 phy_address[5]; 3679}; 3680 3681#define FW_HMA_CMD_MODE_S 31 3682#define FW_HMA_CMD_MODE_M 0x1 3683#define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S) 3684#define FW_HMA_CMD_MODE_G(x) \ 3685 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M) 3686#define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U) 3687 3688#define FW_HMA_CMD_SOC_S 30 3689#define FW_HMA_CMD_SOC_M 0x1 3690#define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S) 3691#define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M) 3692#define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U) 3693 3694#define FW_HMA_CMD_EOC_S 29 3695#define FW_HMA_CMD_EOC_M 0x1 3696#define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S) 3697#define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M) 3698#define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U) 3699 3700#define FW_HMA_CMD_PCIE_PARAMS_S 0 3701#define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff 3702#define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S) 3703#define FW_HMA_CMD_PCIE_PARAMS_G(x) \ 3704 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M) 3705 3706#define FW_HMA_CMD_NADDR_S 12 3707#define FW_HMA_CMD_NADDR_M 0x3f 3708#define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S) 3709#define FW_HMA_CMD_NADDR_G(x) \ 3710 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M) 3711 3712#define FW_HMA_CMD_SIZE_S 0 3713#define FW_HMA_CMD_SIZE_M 0xfff 3714#define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S) 3715#define FW_HMA_CMD_SIZE_G(x) \ 3716 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M) 3717 3718#define FW_HMA_CMD_ADDR_SIZE_S 11 3719#define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff 3720#define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S) 3721#define FW_HMA_CMD_ADDR_SIZE_G(x) \ 3722 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M) 3723 3724enum pcie_fw_eval { 3725 PCIE_FW_EVAL_CRASH = 0, 3726}; 3727 3728#define PCIE_FW_ERR_S 31 3729#define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3730#define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3731 3732#define PCIE_FW_INIT_S 30 3733#define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3734#define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3735 3736#define PCIE_FW_HALT_S 29 3737#define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3738#define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3739 3740#define PCIE_FW_EVAL_S 24 3741#define PCIE_FW_EVAL_M 0x7 3742#define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3743 3744#define PCIE_FW_MASTER_VLD_S 15 3745#define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3746#define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3747 3748#define PCIE_FW_MASTER_S 12 3749#define PCIE_FW_MASTER_M 0x7 3750#define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3751#define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3752 3753struct fw_hdr { 3754 u8 ver; 3755 u8 chip; /* terminator chip type */ 3756 __be16 len512; /* bin length in units of 512-bytes */ 3757 __be32 fw_ver; /* firmware version */ 3758 __be32 tp_microcode_ver; 3759 u8 intfver_nic; 3760 u8 intfver_vnic; 3761 u8 intfver_ofld; 3762 u8 intfver_ri; 3763 u8 intfver_iscsipdu; 3764 u8 intfver_iscsi; 3765 u8 intfver_fcoepdu; 3766 u8 intfver_fcoe; 3767 __u32 reserved2; 3768 __u32 reserved3; 3769 __u32 reserved4; 3770 __be32 flags; 3771 __be32 reserved6[23]; 3772}; 3773 3774enum fw_hdr_chip { 3775 FW_HDR_CHIP_T4, 3776 FW_HDR_CHIP_T5, 3777 FW_HDR_CHIP_T6 3778}; 3779 3780#define FW_HDR_FW_VER_MAJOR_S 24 3781#define FW_HDR_FW_VER_MAJOR_M 0xff 3782#define FW_HDR_FW_VER_MAJOR_V(x) \ 3783 ((x) << FW_HDR_FW_VER_MAJOR_S) 3784#define FW_HDR_FW_VER_MAJOR_G(x) \ 3785 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3786 3787#define FW_HDR_FW_VER_MINOR_S 16 3788#define FW_HDR_FW_VER_MINOR_M 0xff 3789#define FW_HDR_FW_VER_MINOR_V(x) \ 3790 ((x) << FW_HDR_FW_VER_MINOR_S) 3791#define FW_HDR_FW_VER_MINOR_G(x) \ 3792 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3793 3794#define FW_HDR_FW_VER_MICRO_S 8 3795#define FW_HDR_FW_VER_MICRO_M 0xff 3796#define FW_HDR_FW_VER_MICRO_V(x) \ 3797 ((x) << FW_HDR_FW_VER_MICRO_S) 3798#define FW_HDR_FW_VER_MICRO_G(x) \ 3799 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3800 3801#define FW_HDR_FW_VER_BUILD_S 0 3802#define FW_HDR_FW_VER_BUILD_M 0xff 3803#define FW_HDR_FW_VER_BUILD_V(x) \ 3804 ((x) << FW_HDR_FW_VER_BUILD_S) 3805#define FW_HDR_FW_VER_BUILD_G(x) \ 3806 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3807 3808enum fw_hdr_intfver { 3809 FW_HDR_INTFVER_NIC = 0x00, 3810 FW_HDR_INTFVER_VNIC = 0x00, 3811 FW_HDR_INTFVER_OFLD = 0x00, 3812 FW_HDR_INTFVER_RI = 0x00, 3813 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3814 FW_HDR_INTFVER_ISCSI = 0x00, 3815 FW_HDR_INTFVER_FCOEPDU = 0x00, 3816 FW_HDR_INTFVER_FCOE = 0x00, 3817}; 3818 3819enum fw_hdr_flags { 3820 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3821}; 3822 3823/* length of the formatting string */ 3824#define FW_DEVLOG_FMT_LEN 192 3825 3826/* maximum number of the formatting string parameters */ 3827#define FW_DEVLOG_FMT_PARAMS_NUM 8 3828 3829/* priority levels */ 3830enum fw_devlog_level { 3831 FW_DEVLOG_LEVEL_EMERG = 0x0, 3832 FW_DEVLOG_LEVEL_CRIT = 0x1, 3833 FW_DEVLOG_LEVEL_ERR = 0x2, 3834 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3835 FW_DEVLOG_LEVEL_INFO = 0x4, 3836 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3837 FW_DEVLOG_LEVEL_MAX = 0x5, 3838}; 3839 3840/* facilities that may send a log message */ 3841enum fw_devlog_facility { 3842 FW_DEVLOG_FACILITY_CORE = 0x00, 3843 FW_DEVLOG_FACILITY_CF = 0x01, 3844 FW_DEVLOG_FACILITY_SCHED = 0x02, 3845 FW_DEVLOG_FACILITY_TIMER = 0x04, 3846 FW_DEVLOG_FACILITY_RES = 0x06, 3847 FW_DEVLOG_FACILITY_HW = 0x08, 3848 FW_DEVLOG_FACILITY_FLR = 0x10, 3849 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3850 FW_DEVLOG_FACILITY_PHY = 0x14, 3851 FW_DEVLOG_FACILITY_MAC = 0x16, 3852 FW_DEVLOG_FACILITY_PORT = 0x18, 3853 FW_DEVLOG_FACILITY_VI = 0x1A, 3854 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3855 FW_DEVLOG_FACILITY_ACL = 0x1E, 3856 FW_DEVLOG_FACILITY_TM = 0x20, 3857 FW_DEVLOG_FACILITY_QFC = 0x22, 3858 FW_DEVLOG_FACILITY_DCB = 0x24, 3859 FW_DEVLOG_FACILITY_ETH = 0x26, 3860 FW_DEVLOG_FACILITY_OFLD = 0x28, 3861 FW_DEVLOG_FACILITY_RI = 0x2A, 3862 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3863 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3864 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3865 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3866 FW_DEVLOG_FACILITY_CHNET = 0x34, 3867 FW_DEVLOG_FACILITY_MAX = 0x34, 3868}; 3869 3870/* log message format */ 3871struct fw_devlog_e { 3872 __be64 timestamp; 3873 __be32 seqno; 3874 __be16 reserved1; 3875 __u8 level; 3876 __u8 facility; 3877 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3878 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3879 __be32 reserved3[4]; 3880}; 3881 3882struct fw_devlog_cmd { 3883 __be32 op_to_write; 3884 __be32 retval_len16; 3885 __u8 level; 3886 __u8 r2[7]; 3887 __be32 memtype_devlog_memaddr16_devlog; 3888 __be32 memsize_devlog; 3889 __be32 r3[2]; 3890}; 3891 3892#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3893#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3894#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3895 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3896 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3897 3898#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3899#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3900#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3901 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3902 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3903 3904/* P C I E F W P F 7 R E G I S T E R */ 3905 3906/* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3907 * access the "devlog" which needing to contact firmware. The encoding is 3908 * mostly the same as that returned by the DEVLOG command except for the size 3909 * which is encoded as the number of entries in multiples-1 of 128 here rather 3910 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3911 * and 15 means 2048. This of course in turn constrains the allowed values 3912 * for the devlog size ... 3913 */ 3914#define PCIE_FW_PF_DEVLOG 7 3915 3916#define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3917#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3918#define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3919 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3920#define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3921 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3922 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3923 3924#define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3925#define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3926#define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3927#define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3928 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3929 3930#define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3931#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3932#define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3933#define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3934 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3935 3936#define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3937 3938struct fw_crypto_lookaside_wr { 3939 __be32 op_to_cctx_size; 3940 __be32 len16_pkd; 3941 __be32 session_id; 3942 __be32 rx_chid_to_rx_q_id; 3943 __be32 key_addr; 3944 __be32 pld_size_hash_size; 3945 __be64 cookie; 3946}; 3947 3948#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3949#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3950#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3951 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3952#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3953 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3954 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3955 3956#define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3957#define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3958#define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3959 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3960#define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3961 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3962 FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3963#define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3964 3965#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3966#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3967#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3968 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3969#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3970 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3971 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3972 3973#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3974#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3975#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3976 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3977#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3978 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3979 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3980 3981#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3982#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3983#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3984 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3985#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3986 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3987 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3988 3989#define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3990#define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3991#define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3992 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3993#define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3994 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3995 FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3996 3997#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3998#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3999#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 4000 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 4001#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 4002 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 4003 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 4004 4005#define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 4006#define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 4007#define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 4008 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 4009#define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 4010 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 4011 4012#define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 4013#define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 4014#define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 4015 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 4016#define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 4017 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 4018 FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 4019 4020#define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 4021#define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 4022#define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 4023 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 4024#define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 4025 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 4026 4027#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 4028#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 4029#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 4030 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 4031#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 4032 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 4033 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 4034 4035#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 4036#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 4037#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 4038 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 4039#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 4040 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 4041 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 4042 4043#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 4044#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 4045#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 4046 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 4047#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 4048 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 4049 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 4050 4051#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 4052#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 4053#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 4054 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 4055#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 4056 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 4057 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 4058 4059#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 4060#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 4061#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 4062 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 4063#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 4064 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 4065 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 4066 4067struct fw_tlstx_data_wr { 4068 __be32 op_to_immdlen; 4069 __be32 flowid_len16; 4070 __be32 plen; 4071 __be32 lsodisable_to_flags; 4072 __be32 r5; 4073 __be32 ctxloc_to_exp; 4074 __be16 mfs; 4075 __be16 adjustedplen_pkd; 4076 __be16 expinplenmax_pkd; 4077 u8 pdusinplenmax_pkd; 4078 u8 r10; 4079}; 4080 4081#define FW_TLSTX_DATA_WR_OPCODE_S 24 4082#define FW_TLSTX_DATA_WR_OPCODE_M 0xff 4083#define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S) 4084#define FW_TLSTX_DATA_WR_OPCODE_G(x) \ 4085 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M) 4086 4087#define FW_TLSTX_DATA_WR_COMPL_S 21 4088#define FW_TLSTX_DATA_WR_COMPL_M 0x1 4089#define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S) 4090#define FW_TLSTX_DATA_WR_COMPL_G(x) \ 4091 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M) 4092#define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U) 4093 4094#define FW_TLSTX_DATA_WR_IMMDLEN_S 0 4095#define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff 4096#define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S) 4097#define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \ 4098 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M) 4099 4100#define FW_TLSTX_DATA_WR_FLOWID_S 8 4101#define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff 4102#define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S) 4103#define FW_TLSTX_DATA_WR_FLOWID_G(x) \ 4104 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M) 4105 4106#define FW_TLSTX_DATA_WR_LEN16_S 0 4107#define FW_TLSTX_DATA_WR_LEN16_M 0xff 4108#define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S) 4109#define FW_TLSTX_DATA_WR_LEN16_G(x) \ 4110 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M) 4111 4112#define FW_TLSTX_DATA_WR_LSODISABLE_S 31 4113#define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1 4114#define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \ 4115 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S) 4116#define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \ 4117 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M) 4118#define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U) 4119 4120#define FW_TLSTX_DATA_WR_ALIGNPLD_S 30 4121#define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1 4122#define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S) 4123#define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \ 4124 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M) 4125#define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U) 4126 4127#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29 4128#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1 4129#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \ 4130 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) 4131#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \ 4132 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \ 4133 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M) 4134#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U) 4135 4136#define FW_TLSTX_DATA_WR_FLAGS_S 0 4137#define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff 4138#define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S) 4139#define FW_TLSTX_DATA_WR_FLAGS_G(x) \ 4140 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M) 4141 4142#define FW_TLSTX_DATA_WR_CTXLOC_S 30 4143#define FW_TLSTX_DATA_WR_CTXLOC_M 0x3 4144#define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S) 4145#define FW_TLSTX_DATA_WR_CTXLOC_G(x) \ 4146 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M) 4147 4148#define FW_TLSTX_DATA_WR_IVDSGL_S 29 4149#define FW_TLSTX_DATA_WR_IVDSGL_M 0x1 4150#define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S) 4151#define FW_TLSTX_DATA_WR_IVDSGL_G(x) \ 4152 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M) 4153#define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U) 4154 4155#define FW_TLSTX_DATA_WR_KEYSIZE_S 24 4156#define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f 4157#define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S) 4158#define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \ 4159 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M) 4160 4161#define FW_TLSTX_DATA_WR_NUMIVS_S 14 4162#define FW_TLSTX_DATA_WR_NUMIVS_M 0xff 4163#define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S) 4164#define FW_TLSTX_DATA_WR_NUMIVS_G(x) \ 4165 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M) 4166 4167#define FW_TLSTX_DATA_WR_EXP_S 0 4168#define FW_TLSTX_DATA_WR_EXP_M 0x3fff 4169#define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S) 4170#define FW_TLSTX_DATA_WR_EXP_G(x) \ 4171 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M) 4172 4173#define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1 4174#define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \ 4175 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S) 4176 4177#define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4 4178#define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \ 4179 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S) 4180 4181#define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2 4182#define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \ 4183 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S) 4184 4185#endif /* _T4FW_INTERFACE_H_ */ 4186