1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37#include <linux/bitmap.h> 38#include <linux/crc32.h> 39#include <linux/ctype.h> 40#include <linux/debugfs.h> 41#include <linux/err.h> 42#include <linux/etherdevice.h> 43#include <linux/firmware.h> 44#include <linux/if.h> 45#include <linux/if_vlan.h> 46#include <linux/init.h> 47#include <linux/log2.h> 48#include <linux/mdio.h> 49#include <linux/module.h> 50#include <linux/moduleparam.h> 51#include <linux/mutex.h> 52#include <linux/netdevice.h> 53#include <linux/pci.h> 54#include <linux/aer.h> 55#include <linux/rtnetlink.h> 56#include <linux/sched.h> 57#include <linux/seq_file.h> 58#include <linux/sockios.h> 59#include <linux/vmalloc.h> 60#include <linux/workqueue.h> 61#include <net/neighbour.h> 62#include <net/netevent.h> 63#include <net/addrconf.h> 64#include <net/bonding.h> 65#include <linux/uaccess.h> 66#include <linux/crash_dump.h> 67#include <net/udp_tunnel.h> 68#include <net/xfrm.h> 69#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 70#include <net/tls.h> 71#endif 72 73#include "cxgb4.h" 74#include "cxgb4_filter.h" 75#include "t4_regs.h" 76#include "t4_values.h" 77#include "t4_msg.h" 78#include "t4fw_api.h" 79#include "t4fw_version.h" 80#include "cxgb4_dcb.h" 81#include "srq.h" 82#include "cxgb4_debugfs.h" 83#include "clip_tbl.h" 84#include "l2t.h" 85#include "smt.h" 86#include "sched.h" 87#include "cxgb4_tc_u32.h" 88#include "cxgb4_tc_flower.h" 89#include "cxgb4_tc_mqprio.h" 90#include "cxgb4_tc_matchall.h" 91#include "cxgb4_ptp.h" 92#include "cxgb4_cudbg.h" 93 94char cxgb4_driver_name[] = KBUILD_MODNAME; 95 96#define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 97 98#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 99 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 100 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 101 102/* Macros needed to support the PCI Device ID Table ... 103 */ 104#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 105 static const struct pci_device_id cxgb4_pci_tbl[] = { 106#define CXGB4_UNIFIED_PF 0x4 107 108#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF 109 110/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 111 * called for both. 112 */ 113#define CH_PCI_DEVICE_ID_FUNCTION2 0x0 114 115#define CH_PCI_ID_TABLE_ENTRY(devid) \ 116 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF} 117 118#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 119 { 0, } \ 120 } 121 122#include "t4_pci_id_tbl.h" 123 124#define FW4_FNAME "cxgb4/t4fw.bin" 125#define FW5_FNAME "cxgb4/t5fw.bin" 126#define FW6_FNAME "cxgb4/t6fw.bin" 127#define FW4_CFNAME "cxgb4/t4-config.txt" 128#define FW5_CFNAME "cxgb4/t5-config.txt" 129#define FW6_CFNAME "cxgb4/t6-config.txt" 130#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 131#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 132#define PHY_AQ1202_DEVICEID 0x4409 133#define PHY_BCM84834_DEVICEID 0x4486 134 135MODULE_DESCRIPTION(DRV_DESC); 136MODULE_AUTHOR("Chelsio Communications"); 137MODULE_LICENSE("Dual BSD/GPL"); 138MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 139MODULE_FIRMWARE(FW4_FNAME); 140MODULE_FIRMWARE(FW5_FNAME); 141MODULE_FIRMWARE(FW6_FNAME); 142 143/* 144 * The driver uses the best interrupt scheme available on a platform in the 145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 146 * of these schemes the driver may consider as follows: 147 * 148 * msi = 2: choose from among all three options 149 * msi = 1: only consider MSI and INTx interrupts 150 * msi = 0: force INTx interrupts 151 */ 152static int msi = 2; 153 154module_param(msi, int, 0644); 155MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 156 157/* 158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 159 * offset by 2 bytes in order to have the IP headers line up on 4-byte 160 * boundaries. This is a requirement for many architectures which will throw 161 * a machine check fault if an attempt is made to access one of the 4-byte IP 162 * header fields on a non-4-byte boundary. And it's a major performance issue 163 * even on some architectures which allow it like some implementations of the 164 * x86 ISA. However, some architectures don't mind this and for some very 165 * edge-case performance sensitive applications (like forwarding large volumes 166 * of small packets), setting this DMA offset to 0 will decrease the number of 167 * PCI-E Bus transfers enough to measurably affect performance. 168 */ 169static int rx_dma_offset = 2; 170 171/* TX Queue select used to determine what algorithm to use for selecting TX 172 * queue. Select between the kernel provided function (select_queue=0) or user 173 * cxgb_select_queue function (select_queue=1) 174 * 175 * Default: select_queue=0 176 */ 177static int select_queue; 178module_param(select_queue, int, 0644); 179MODULE_PARM_DESC(select_queue, 180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 181 182static struct dentry *cxgb4_debugfs_root; 183 184LIST_HEAD(adapter_list); 185DEFINE_MUTEX(uld_mutex); 186LIST_HEAD(uld_list); 187 188static int cfg_queues(struct adapter *adap); 189 190static void link_report(struct net_device *dev) 191{ 192 if (!netif_carrier_ok(dev)) 193 netdev_info(dev, "link down\n"); 194 else { 195 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 196 197 const char *s; 198 const struct port_info *p = netdev_priv(dev); 199 200 switch (p->link_cfg.speed) { 201 case 100: 202 s = "100Mbps"; 203 break; 204 case 1000: 205 s = "1Gbps"; 206 break; 207 case 10000: 208 s = "10Gbps"; 209 break; 210 case 25000: 211 s = "25Gbps"; 212 break; 213 case 40000: 214 s = "40Gbps"; 215 break; 216 case 50000: 217 s = "50Gbps"; 218 break; 219 case 100000: 220 s = "100Gbps"; 221 break; 222 default: 223 pr_info("%s: unsupported speed: %d\n", 224 dev->name, p->link_cfg.speed); 225 return; 226 } 227 228 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 229 fc[p->link_cfg.fc]); 230 } 231} 232 233#ifdef CONFIG_CHELSIO_T4_DCB 234/* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 235static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 236{ 237 struct port_info *pi = netdev_priv(dev); 238 struct adapter *adap = pi->adapter; 239 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 240 int i; 241 242 /* We use a simple mapping of Port TX Queue Index to DCB 243 * Priority when we're enabling DCB. 244 */ 245 for (i = 0; i < pi->nqsets; i++, txq++) { 246 u32 name, value; 247 int err; 248 249 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 250 FW_PARAMS_PARAM_X_V( 251 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 252 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 253 value = enable ? i : 0xffffffff; 254 255 /* Since we can be called while atomic (from "interrupt 256 * level") we need to issue the Set Parameters Commannd 257 * without sleeping (timeout < 0). 258 */ 259 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 260 &name, &value, 261 -FW_CMD_MAX_TIMEOUT); 262 263 if (err) 264 dev_err(adap->pdev_dev, 265 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 266 enable ? "set" : "unset", pi->port_id, i, -err); 267 else 268 txq->dcb_prio = enable ? value : 0; 269 } 270} 271 272int cxgb4_dcb_enabled(const struct net_device *dev) 273{ 274 struct port_info *pi = netdev_priv(dev); 275 276 if (!pi->dcb.enabled) 277 return 0; 278 279 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 280 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 281} 282#endif /* CONFIG_CHELSIO_T4_DCB */ 283 284void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 285{ 286 struct net_device *dev = adapter->port[port_id]; 287 288 /* Skip changes from disabled ports. */ 289 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 290 if (link_stat) 291 netif_carrier_on(dev); 292 else { 293#ifdef CONFIG_CHELSIO_T4_DCB 294 if (cxgb4_dcb_enabled(dev)) { 295 cxgb4_dcb_reset(dev); 296 dcb_tx_queue_prio_enable(dev, false); 297 } 298#endif /* CONFIG_CHELSIO_T4_DCB */ 299 netif_carrier_off(dev); 300 } 301 302 link_report(dev); 303 } 304} 305 306void t4_os_portmod_changed(struct adapter *adap, int port_id) 307{ 308 static const char *mod_str[] = { 309 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 310 }; 311 312 struct net_device *dev = adap->port[port_id]; 313 struct port_info *pi = netdev_priv(dev); 314 315 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 316 netdev_info(dev, "port module unplugged\n"); 317 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 318 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 319 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 320 netdev_info(dev, "%s: unsupported port module inserted\n", 321 dev->name); 322 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 323 netdev_info(dev, "%s: unknown port module inserted\n", 324 dev->name); 325 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 326 netdev_info(dev, "%s: transceiver module error\n", dev->name); 327 else 328 netdev_info(dev, "%s: unknown module type %d inserted\n", 329 dev->name, pi->mod_type); 330 331 /* If the interface is running, then we'll need any "sticky" Link 332 * Parameters redone with a new Transceiver Module. 333 */ 334 pi->link_cfg.redo_l1cfg = netif_running(dev); 335} 336 337int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 338module_param(dbfifo_int_thresh, int, 0644); 339MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 340 341/* 342 * usecs to sleep while draining the dbfifo 343 */ 344static int dbfifo_drain_delay = 1000; 345module_param(dbfifo_drain_delay, int, 0644); 346MODULE_PARM_DESC(dbfifo_drain_delay, 347 "usecs to sleep while draining the dbfifo"); 348 349static inline int cxgb4_set_addr_hash(struct port_info *pi) 350{ 351 struct adapter *adap = pi->adapter; 352 u64 vec = 0; 353 bool ucast = false; 354 struct hash_mac_addr *entry; 355 356 /* Calculate the hash vector for the updated list and program it */ 357 list_for_each_entry(entry, &adap->mac_hlist, list) { 358 ucast |= is_unicast_ether_addr(entry->addr); 359 vec |= (1ULL << hash_mac_addr(entry->addr)); 360 } 361 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 362 vec, false); 363} 364 365static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 366{ 367 struct port_info *pi = netdev_priv(netdev); 368 struct adapter *adap = pi->adapter; 369 int ret; 370 u64 mhash = 0; 371 u64 uhash = 0; 372 /* idx stores the index of allocated filters, 373 * its size should be modified based on the number of 374 * MAC addresses that we allocate filters for 375 */ 376 377 u16 idx[1] = {}; 378 bool free = false; 379 bool ucast = is_unicast_ether_addr(mac_addr); 380 const u8 *maclist[1] = {mac_addr}; 381 struct hash_mac_addr *new_entry; 382 383 ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist, 384 idx, ucast ? &uhash : &mhash, false); 385 if (ret < 0) 386 goto out; 387 /* if hash != 0, then add the addr to hash addr list 388 * so on the end we will calculate the hash for the 389 * list and program it 390 */ 391 if (uhash || mhash) { 392 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 393 if (!new_entry) 394 return -ENOMEM; 395 ether_addr_copy(new_entry->addr, mac_addr); 396 list_add_tail(&new_entry->list, &adap->mac_hlist); 397 ret = cxgb4_set_addr_hash(pi); 398 } 399out: 400 return ret < 0 ? ret : 0; 401} 402 403static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 404{ 405 struct port_info *pi = netdev_priv(netdev); 406 struct adapter *adap = pi->adapter; 407 int ret; 408 const u8 *maclist[1] = {mac_addr}; 409 struct hash_mac_addr *entry, *tmp; 410 411 /* If the MAC address to be removed is in the hash addr 412 * list, delete it from the list and update hash vector 413 */ 414 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 415 if (ether_addr_equal(entry->addr, mac_addr)) { 416 list_del(&entry->list); 417 kfree(entry); 418 return cxgb4_set_addr_hash(pi); 419 } 420 } 421 422 ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false); 423 return ret < 0 ? -EINVAL : 0; 424} 425 426/* 427 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 428 * If @mtu is -1 it is left unchanged. 429 */ 430static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 431{ 432 struct port_info *pi = netdev_priv(dev); 433 struct adapter *adapter = pi->adapter; 434 435 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 436 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 437 438 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, pi->viid_mirror, 439 mtu, (dev->flags & IFF_PROMISC) ? 1 : 0, 440 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 441 sleep_ok); 442} 443 444/** 445 * cxgb4_change_mac - Update match filter for a MAC address. 446 * @pi: the port_info 447 * @viid: the VI id 448 * @tcam_idx: TCAM index of existing filter for old value of MAC address, 449 * or -1 450 * @addr: the new MAC address value 451 * @persist: whether a new MAC allocation should be persistent 452 * @smt_idx: the destination to store the new SMT index. 453 * 454 * Modifies an MPS filter and sets it to the new MAC address if 455 * @tcam_idx >= 0, or adds the MAC address to a new filter if 456 * @tcam_idx < 0. In the latter case the address is added persistently 457 * if @persist is %true. 458 * Addresses are programmed to hash region, if tcam runs out of entries. 459 * 460 */ 461int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 462 int *tcam_idx, const u8 *addr, bool persist, 463 u8 *smt_idx) 464{ 465 struct adapter *adapter = pi->adapter; 466 struct hash_mac_addr *entry, *new_entry; 467 int ret; 468 469 ret = t4_change_mac(adapter, adapter->mbox, viid, 470 *tcam_idx, addr, persist, smt_idx); 471 /* We ran out of TCAM entries. try programming hash region. */ 472 if (ret == -ENOMEM) { 473 /* If the MAC address to be updated is in the hash addr 474 * list, update it from the list 475 */ 476 list_for_each_entry(entry, &adapter->mac_hlist, list) { 477 if (entry->iface_mac) { 478 ether_addr_copy(entry->addr, addr); 479 goto set_hash; 480 } 481 } 482 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL); 483 if (!new_entry) 484 return -ENOMEM; 485 ether_addr_copy(new_entry->addr, addr); 486 new_entry->iface_mac = true; 487 list_add_tail(&new_entry->list, &adapter->mac_hlist); 488set_hash: 489 ret = cxgb4_set_addr_hash(pi); 490 } else if (ret >= 0) { 491 *tcam_idx = ret; 492 ret = 0; 493 } 494 495 return ret; 496} 497 498/* 499 * link_start - enable a port 500 * @dev: the port to enable 501 * 502 * Performs the MAC and PHY actions needed to enable a port. 503 */ 504static int link_start(struct net_device *dev) 505{ 506 struct port_info *pi = netdev_priv(dev); 507 unsigned int mb = pi->adapter->mbox; 508 int ret; 509 510 /* 511 * We do not set address filters and promiscuity here, the stack does 512 * that step explicitly. 513 */ 514 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, pi->viid_mirror, 515 dev->mtu, -1, -1, -1, 516 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 517 if (ret == 0) 518 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt, 519 dev->dev_addr, true, &pi->smt_idx); 520 if (ret == 0) 521 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 522 &pi->link_cfg); 523 if (ret == 0) { 524 local_bh_disable(); 525 ret = t4_enable_pi_params(pi->adapter, mb, pi, true, 526 true, CXGB4_DCB_ENABLED); 527 local_bh_enable(); 528 } 529 530 return ret; 531} 532 533#ifdef CONFIG_CHELSIO_T4_DCB 534/* Handle a Data Center Bridging update message from the firmware. */ 535static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 536{ 537 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 538 struct net_device *dev = adap->port[adap->chan_map[port]]; 539 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 540 int new_dcb_enabled; 541 542 cxgb4_dcb_handle_fw_update(adap, pcmd); 543 new_dcb_enabled = cxgb4_dcb_enabled(dev); 544 545 /* If the DCB has become enabled or disabled on the port then we're 546 * going to need to set up/tear down DCB Priority parameters for the 547 * TX Queues associated with the port. 548 */ 549 if (new_dcb_enabled != old_dcb_enabled) 550 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 551} 552#endif /* CONFIG_CHELSIO_T4_DCB */ 553 554/* Response queue handler for the FW event queue. 555 */ 556static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 557 const struct pkt_gl *gl) 558{ 559 u8 opcode = ((const struct rss_header *)rsp)->opcode; 560 561 rsp++; /* skip RSS header */ 562 563 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 564 */ 565 if (unlikely(opcode == CPL_FW4_MSG && 566 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 567 rsp++; 568 opcode = ((const struct rss_header *)rsp)->opcode; 569 rsp++; 570 if (opcode != CPL_SGE_EGR_UPDATE) { 571 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 572 , opcode); 573 goto out; 574 } 575 } 576 577 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 578 const struct cpl_sge_egr_update *p = (void *)rsp; 579 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 580 struct sge_txq *txq; 581 582 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 583 txq->restarts++; 584 if (txq->q_type == CXGB4_TXQ_ETH) { 585 struct sge_eth_txq *eq; 586 587 eq = container_of(txq, struct sge_eth_txq, q); 588 t4_sge_eth_txq_egress_update(q->adap, eq, -1); 589 } else { 590 struct sge_uld_txq *oq; 591 592 oq = container_of(txq, struct sge_uld_txq, q); 593 tasklet_schedule(&oq->qresume_tsk); 594 } 595 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 596 const struct cpl_fw6_msg *p = (void *)rsp; 597 598#ifdef CONFIG_CHELSIO_T4_DCB 599 const struct fw_port_cmd *pcmd = (const void *)p->data; 600 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 601 unsigned int action = 602 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 603 604 if (cmd == FW_PORT_CMD && 605 (action == FW_PORT_ACTION_GET_PORT_INFO || 606 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 607 int port = FW_PORT_CMD_PORTID_G( 608 be32_to_cpu(pcmd->op_to_portid)); 609 struct net_device *dev; 610 int dcbxdis, state_input; 611 612 dev = q->adap->port[q->adap->chan_map[port]]; 613 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 614 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F) 615 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32) 616 & FW_PORT_CMD_DCBXDIS32_F)); 617 state_input = (dcbxdis 618 ? CXGB4_DCB_INPUT_FW_DISABLED 619 : CXGB4_DCB_INPUT_FW_ENABLED); 620 621 cxgb4_dcb_state_fsm(dev, state_input); 622 } 623 624 if (cmd == FW_PORT_CMD && 625 action == FW_PORT_ACTION_L2_DCB_CFG) 626 dcb_rpl(q->adap, pcmd); 627 else 628#endif 629 if (p->type == 0) 630 t4_handle_fw_rpl(q->adap, p->data); 631 } else if (opcode == CPL_L2T_WRITE_RPL) { 632 const struct cpl_l2t_write_rpl *p = (void *)rsp; 633 634 do_l2t_write_rpl(q->adap, p); 635 } else if (opcode == CPL_SMT_WRITE_RPL) { 636 const struct cpl_smt_write_rpl *p = (void *)rsp; 637 638 do_smt_write_rpl(q->adap, p); 639 } else if (opcode == CPL_SET_TCB_RPL) { 640 const struct cpl_set_tcb_rpl *p = (void *)rsp; 641 642 filter_rpl(q->adap, p); 643 } else if (opcode == CPL_ACT_OPEN_RPL) { 644 const struct cpl_act_open_rpl *p = (void *)rsp; 645 646 hash_filter_rpl(q->adap, p); 647 } else if (opcode == CPL_ABORT_RPL_RSS) { 648 const struct cpl_abort_rpl_rss *p = (void *)rsp; 649 650 hash_del_filter_rpl(q->adap, p); 651 } else if (opcode == CPL_SRQ_TABLE_RPL) { 652 const struct cpl_srq_table_rpl *p = (void *)rsp; 653 654 do_srq_table_rpl(q->adap, p); 655 } else 656 dev_err(q->adap->pdev_dev, 657 "unexpected CPL %#x on FW event queue\n", opcode); 658out: 659 return 0; 660} 661 662static void disable_msi(struct adapter *adapter) 663{ 664 if (adapter->flags & CXGB4_USING_MSIX) { 665 pci_disable_msix(adapter->pdev); 666 adapter->flags &= ~CXGB4_USING_MSIX; 667 } else if (adapter->flags & CXGB4_USING_MSI) { 668 pci_disable_msi(adapter->pdev); 669 adapter->flags &= ~CXGB4_USING_MSI; 670 } 671} 672 673/* 674 * Interrupt handler for non-data events used with MSI-X. 675 */ 676static irqreturn_t t4_nondata_intr(int irq, void *cookie) 677{ 678 struct adapter *adap = cookie; 679 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 680 681 if (v & PFSW_F) { 682 adap->swintr = 1; 683 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 684 } 685 if (adap->flags & CXGB4_MASTER_PF) 686 t4_slow_intr_handler(adap); 687 return IRQ_HANDLED; 688} 689 690int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 691 cpumask_var_t *aff_mask, int idx) 692{ 693 int rv; 694 695 if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) { 696 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n"); 697 return -ENOMEM; 698 } 699 700 cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)), 701 *aff_mask); 702 703 rv = irq_set_affinity_hint(vec, *aff_mask); 704 if (rv) 705 dev_warn(adap->pdev_dev, 706 "irq_set_affinity_hint %u failed %d\n", 707 vec, rv); 708 709 return 0; 710} 711 712void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask) 713{ 714 irq_set_affinity_hint(vec, NULL); 715 free_cpumask_var(aff_mask); 716} 717 718static int request_msix_queue_irqs(struct adapter *adap) 719{ 720 struct sge *s = &adap->sge; 721 struct msix_info *minfo; 722 int err, ethqidx; 723 724 if (s->fwevtq_msix_idx < 0) 725 return -ENOMEM; 726 727 err = request_irq(adap->msix_info[s->fwevtq_msix_idx].vec, 728 t4_sge_intr_msix, 0, 729 adap->msix_info[s->fwevtq_msix_idx].desc, 730 &s->fw_evtq); 731 if (err) 732 return err; 733 734 for_each_ethrxq(s, ethqidx) { 735 minfo = s->ethrxq[ethqidx].msix; 736 err = request_irq(minfo->vec, 737 t4_sge_intr_msix, 0, 738 minfo->desc, 739 &s->ethrxq[ethqidx].rspq); 740 if (err) 741 goto unwind; 742 743 cxgb4_set_msix_aff(adap, minfo->vec, 744 &minfo->aff_mask, ethqidx); 745 } 746 return 0; 747 748unwind: 749 while (--ethqidx >= 0) { 750 minfo = s->ethrxq[ethqidx].msix; 751 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 752 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq); 753 } 754 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq); 755 return err; 756} 757 758static void free_msix_queue_irqs(struct adapter *adap) 759{ 760 struct sge *s = &adap->sge; 761 struct msix_info *minfo; 762 int i; 763 764 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq); 765 for_each_ethrxq(s, i) { 766 minfo = s->ethrxq[i].msix; 767 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 768 free_irq(minfo->vec, &s->ethrxq[i].rspq); 769 } 770} 771 772static int setup_ppod_edram(struct adapter *adap) 773{ 774 unsigned int param, val; 775 int ret; 776 777 /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check 778 * if firmware supports ppod edram feature or not. If firmware 779 * returns 1, then driver can enable this feature by sending 780 * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to 781 * enable ppod edram feature. 782 */ 783 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 784 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM)); 785 786 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 787 if (ret < 0) { 788 dev_warn(adap->pdev_dev, 789 "querying PPOD_EDRAM support failed: %d\n", 790 ret); 791 return -1; 792 } 793 794 if (val != 1) 795 return -1; 796 797 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 798 if (ret < 0) { 799 dev_err(adap->pdev_dev, 800 "setting PPOD_EDRAM failed: %d\n", ret); 801 return -1; 802 } 803 return 0; 804} 805 806static void adap_config_hpfilter(struct adapter *adapter) 807{ 808 u32 param, val = 0; 809 int ret; 810 811 /* Enable HP filter region. Older fw will fail this request and 812 * it is fine. 813 */ 814 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 815 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 816 1, ¶m, &val); 817 818 /* An error means FW doesn't know about HP filter support, 819 * it's not a problem, don't return an error. 820 */ 821 if (ret < 0) 822 dev_err(adapter->pdev_dev, 823 "HP filter region isn't supported by FW\n"); 824} 825 826static int cxgb4_config_rss(const struct port_info *pi, u16 *rss, 827 u16 rss_size, u16 viid) 828{ 829 struct adapter *adap = pi->adapter; 830 int ret; 831 832 ret = t4_config_rss_range(adap, adap->mbox, viid, 0, rss_size, rss, 833 rss_size); 834 if (ret) 835 return ret; 836 837 /* If Tunnel All Lookup isn't specified in the global RSS 838 * Configuration, then we need to specify a default Ingress 839 * Queue for any ingress packets which aren't hashed. We'll 840 * use our first ingress queue ... 841 */ 842 return t4_config_vi_rss(adap, adap->mbox, viid, 843 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 844 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 845 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 846 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 847 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 848 rss[0]); 849} 850 851/** 852 * cxgb4_write_rss - write the RSS table for a given port 853 * @pi: the port 854 * @queues: array of queue indices for RSS 855 * 856 * Sets up the portion of the HW RSS table for the port's VI to distribute 857 * packets to the Rx queues in @queues. 858 * Should never be called before setting up sge eth rx queues 859 */ 860int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 861{ 862 struct adapter *adapter = pi->adapter; 863 const struct sge_eth_rxq *rxq; 864 int i, err; 865 u16 *rss; 866 867 rxq = &adapter->sge.ethrxq[pi->first_qset]; 868 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL); 869 if (!rss) 870 return -ENOMEM; 871 872 /* map the queue indices to queue ids */ 873 for (i = 0; i < pi->rss_size; i++, queues++) 874 rss[i] = rxq[*queues].rspq.abs_id; 875 876 err = cxgb4_config_rss(pi, rss, pi->rss_size, pi->viid); 877 kfree(rss); 878 return err; 879} 880 881/** 882 * setup_rss - configure RSS 883 * @adap: the adapter 884 * 885 * Sets up RSS for each port. 886 */ 887static int setup_rss(struct adapter *adap) 888{ 889 int i, j, err; 890 891 for_each_port(adap, i) { 892 const struct port_info *pi = adap2pinfo(adap, i); 893 894 /* Fill default values with equal distribution */ 895 for (j = 0; j < pi->rss_size; j++) 896 pi->rss[j] = j % pi->nqsets; 897 898 err = cxgb4_write_rss(pi, pi->rss); 899 if (err) 900 return err; 901 } 902 return 0; 903} 904 905/* 906 * Return the channel of the ingress queue with the given qid. 907 */ 908static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 909{ 910 qid -= p->ingr_start; 911 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 912} 913 914void cxgb4_quiesce_rx(struct sge_rspq *q) 915{ 916 if (q->handler) 917 napi_disable(&q->napi); 918} 919 920/* 921 * Wait until all NAPI handlers are descheduled. 922 */ 923static void quiesce_rx(struct adapter *adap) 924{ 925 int i; 926 927 for (i = 0; i < adap->sge.ingr_sz; i++) { 928 struct sge_rspq *q = adap->sge.ingr_map[i]; 929 930 if (!q) 931 continue; 932 933 cxgb4_quiesce_rx(q); 934 } 935} 936 937/* Disable interrupt and napi handler */ 938static void disable_interrupts(struct adapter *adap) 939{ 940 struct sge *s = &adap->sge; 941 942 if (adap->flags & CXGB4_FULL_INIT_DONE) { 943 t4_intr_disable(adap); 944 if (adap->flags & CXGB4_USING_MSIX) { 945 free_msix_queue_irqs(adap); 946 free_irq(adap->msix_info[s->nd_msix_idx].vec, 947 adap); 948 } else { 949 free_irq(adap->pdev->irq, adap); 950 } 951 quiesce_rx(adap); 952 } 953} 954 955void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q) 956{ 957 if (q->handler) 958 napi_enable(&q->napi); 959 960 /* 0-increment GTS to start the timer and enable interrupts */ 961 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 962 SEINTARM_V(q->intr_params) | 963 INGRESSQID_V(q->cntxt_id)); 964} 965 966/* 967 * Enable NAPI scheduling and interrupt generation for all Rx queues. 968 */ 969static void enable_rx(struct adapter *adap) 970{ 971 int i; 972 973 for (i = 0; i < adap->sge.ingr_sz; i++) { 974 struct sge_rspq *q = adap->sge.ingr_map[i]; 975 976 if (!q) 977 continue; 978 979 cxgb4_enable_rx(adap, q); 980 } 981} 982 983static int setup_non_data_intr(struct adapter *adap) 984{ 985 int msix; 986 987 adap->sge.nd_msix_idx = -1; 988 if (!(adap->flags & CXGB4_USING_MSIX)) 989 return 0; 990 991 /* Request MSI-X vector for non-data interrupt */ 992 msix = cxgb4_get_msix_idx_from_bmap(adap); 993 if (msix < 0) 994 return -ENOMEM; 995 996 snprintf(adap->msix_info[msix].desc, 997 sizeof(adap->msix_info[msix].desc), 998 "%s", adap->port[0]->name); 999 1000 adap->sge.nd_msix_idx = msix; 1001 return 0; 1002} 1003 1004static int setup_fw_sge_queues(struct adapter *adap) 1005{ 1006 struct sge *s = &adap->sge; 1007 int msix, err = 0; 1008 1009 bitmap_zero(s->starving_fl, s->egr_sz); 1010 bitmap_zero(s->txq_maperr, s->egr_sz); 1011 1012 if (adap->flags & CXGB4_USING_MSIX) { 1013 s->fwevtq_msix_idx = -1; 1014 msix = cxgb4_get_msix_idx_from_bmap(adap); 1015 if (msix < 0) 1016 return -ENOMEM; 1017 1018 snprintf(adap->msix_info[msix].desc, 1019 sizeof(adap->msix_info[msix].desc), 1020 "%s-FWeventq", adap->port[0]->name); 1021 } else { 1022 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 1023 NULL, NULL, NULL, -1); 1024 if (err) 1025 return err; 1026 msix = -((int)s->intrq.abs_id + 1); 1027 } 1028 1029 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 1030 msix, NULL, fwevtq_handler, NULL, -1); 1031 if (err && msix >= 0) 1032 cxgb4_free_msix_idx_in_bmap(adap, msix); 1033 1034 s->fwevtq_msix_idx = msix; 1035 return err; 1036} 1037 1038/** 1039 * setup_sge_queues - configure SGE Tx/Rx/response queues 1040 * @adap: the adapter 1041 * 1042 * Determines how many sets of SGE queues to use and initializes them. 1043 * We support multiple queue sets per port if we have MSI-X, otherwise 1044 * just one queue set per port. 1045 */ 1046static int setup_sge_queues(struct adapter *adap) 1047{ 1048 struct sge_uld_rxq_info *rxq_info = NULL; 1049 struct sge *s = &adap->sge; 1050 unsigned int cmplqid = 0; 1051 int err, i, j, msix = 0; 1052 1053 if (is_uld(adap)) 1054 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 1055 1056 if (!(adap->flags & CXGB4_USING_MSIX)) 1057 msix = -((int)s->intrq.abs_id + 1); 1058 1059 for_each_port(adap, i) { 1060 struct net_device *dev = adap->port[i]; 1061 struct port_info *pi = netdev_priv(dev); 1062 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 1063 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 1064 1065 for (j = 0; j < pi->nqsets; j++, q++) { 1066 if (msix >= 0) { 1067 msix = cxgb4_get_msix_idx_from_bmap(adap); 1068 if (msix < 0) { 1069 err = msix; 1070 goto freeout; 1071 } 1072 1073 snprintf(adap->msix_info[msix].desc, 1074 sizeof(adap->msix_info[msix].desc), 1075 "%s-Rx%d", dev->name, j); 1076 q->msix = &adap->msix_info[msix]; 1077 } 1078 1079 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 1080 msix, &q->fl, 1081 t4_ethrx_handler, 1082 NULL, 1083 t4_get_tp_ch_map(adap, 1084 pi->tx_chan)); 1085 if (err) 1086 goto freeout; 1087 q->rspq.idx = j; 1088 memset(&q->stats, 0, sizeof(q->stats)); 1089 } 1090 1091 q = &s->ethrxq[pi->first_qset]; 1092 for (j = 0; j < pi->nqsets; j++, t++, q++) { 1093 err = t4_sge_alloc_eth_txq(adap, t, dev, 1094 netdev_get_tx_queue(dev, j), 1095 q->rspq.cntxt_id, 1096 !!(adap->flags & CXGB4_SGE_DBQ_TIMER)); 1097 if (err) 1098 goto freeout; 1099 } 1100 } 1101 1102 for_each_port(adap, i) { 1103 /* Note that cmplqid below is 0 if we don't 1104 * have RDMA queues, and that's the right value. 1105 */ 1106 if (rxq_info) 1107 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 1108 1109 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 1110 s->fw_evtq.cntxt_id, cmplqid); 1111 if (err) 1112 goto freeout; 1113 } 1114 1115 if (!is_t4(adap->params.chip)) { 1116 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 1117 netdev_get_tx_queue(adap->port[0], 0) 1118 , s->fw_evtq.cntxt_id, false); 1119 if (err) 1120 goto freeout; 1121 } 1122 1123 t4_write_reg(adap, is_t4(adap->params.chip) ? 1124 MPS_TRC_RSS_CONTROL_A : 1125 MPS_T5_TRC_RSS_CONTROL_A, 1126 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 1127 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 1128 return 0; 1129freeout: 1130 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err); 1131 t4_free_sge_resources(adap); 1132 return err; 1133} 1134 1135static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 1136 struct net_device *sb_dev) 1137{ 1138 int txq; 1139 1140#ifdef CONFIG_CHELSIO_T4_DCB 1141 /* If a Data Center Bridging has been successfully negotiated on this 1142 * link then we'll use the skb's priority to map it to a TX Queue. 1143 * The skb's priority is determined via the VLAN Tag Priority Code 1144 * Point field. 1145 */ 1146 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 1147 u16 vlan_tci; 1148 int err; 1149 1150 err = vlan_get_tag(skb, &vlan_tci); 1151 if (unlikely(err)) { 1152 if (net_ratelimit()) 1153 netdev_warn(dev, 1154 "TX Packet without VLAN Tag on DCB Link\n"); 1155 txq = 0; 1156 } else { 1157 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 1158#ifdef CONFIG_CHELSIO_T4_FCOE 1159 if (skb->protocol == htons(ETH_P_FCOE)) 1160 txq = skb->priority & 0x7; 1161#endif /* CONFIG_CHELSIO_T4_FCOE */ 1162 } 1163 return txq; 1164 } 1165#endif /* CONFIG_CHELSIO_T4_DCB */ 1166 1167 if (dev->num_tc) { 1168 struct port_info *pi = netdev2pinfo(dev); 1169 u8 ver, proto; 1170 1171 ver = ip_hdr(skb)->version; 1172 proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr : 1173 ip_hdr(skb)->protocol; 1174 1175 /* Send unsupported traffic pattern to normal NIC queues. */ 1176 txq = netdev_pick_tx(dev, skb, sb_dev); 1177 if (xfrm_offload(skb) || is_ptp_enabled(skb, dev) || 1178 skb->encapsulation || 1179 cxgb4_is_ktls_skb(skb) || 1180 (proto != IPPROTO_TCP && proto != IPPROTO_UDP)) 1181 txq = txq % pi->nqsets; 1182 1183 return txq; 1184 } 1185 1186 if (select_queue) { 1187 txq = (skb_rx_queue_recorded(skb) 1188 ? skb_get_rx_queue(skb) 1189 : smp_processor_id()); 1190 1191 while (unlikely(txq >= dev->real_num_tx_queues)) 1192 txq -= dev->real_num_tx_queues; 1193 1194 return txq; 1195 } 1196 1197 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 1198} 1199 1200static int closest_timer(const struct sge *s, int time) 1201{ 1202 int i, delta, match = 0, min_delta = INT_MAX; 1203 1204 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 1205 delta = time - s->timer_val[i]; 1206 if (delta < 0) 1207 delta = -delta; 1208 if (delta < min_delta) { 1209 min_delta = delta; 1210 match = i; 1211 } 1212 } 1213 return match; 1214} 1215 1216static int closest_thres(const struct sge *s, int thres) 1217{ 1218 int i, delta, match = 0, min_delta = INT_MAX; 1219 1220 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 1221 delta = thres - s->counter_val[i]; 1222 if (delta < 0) 1223 delta = -delta; 1224 if (delta < min_delta) { 1225 min_delta = delta; 1226 match = i; 1227 } 1228 } 1229 return match; 1230} 1231 1232/** 1233 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1234 * @q: the Rx queue 1235 * @us: the hold-off time in us, or 0 to disable timer 1236 * @cnt: the hold-off packet count, or 0 to disable counter 1237 * 1238 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1239 * one of the two needs to be enabled for the queue to generate interrupts. 1240 */ 1241int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1242 unsigned int us, unsigned int cnt) 1243{ 1244 struct adapter *adap = q->adap; 1245 1246 if ((us | cnt) == 0) 1247 cnt = 1; 1248 1249 if (cnt) { 1250 int err; 1251 u32 v, new_idx; 1252 1253 new_idx = closest_thres(&adap->sge, cnt); 1254 if (q->desc && q->pktcnt_idx != new_idx) { 1255 /* the queue has already been created, update it */ 1256 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1257 FW_PARAMS_PARAM_X_V( 1258 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1259 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1260 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1261 &v, &new_idx); 1262 if (err) 1263 return err; 1264 } 1265 q->pktcnt_idx = new_idx; 1266 } 1267 1268 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1269 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1270 return 0; 1271} 1272 1273static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1274{ 1275 netdev_features_t changed = dev->features ^ features; 1276 const struct port_info *pi = netdev_priv(dev); 1277 int err; 1278 1279 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1280 return 0; 1281 1282 err = t4_set_rxmode(pi->adapter, pi->adapter->mbox, pi->viid, 1283 pi->viid_mirror, -1, -1, -1, -1, 1284 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1285 if (unlikely(err)) 1286 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1287 return err; 1288} 1289 1290static int setup_debugfs(struct adapter *adap) 1291{ 1292 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1293 return -1; 1294 1295#ifdef CONFIG_DEBUG_FS 1296 t4_setup_debugfs(adap); 1297#endif 1298 return 0; 1299} 1300 1301static void cxgb4_port_mirror_free_rxq(struct adapter *adap, 1302 struct sge_eth_rxq *mirror_rxq) 1303{ 1304 if ((adap->flags & CXGB4_FULL_INIT_DONE) && 1305 !(adap->flags & CXGB4_SHUTTING_DOWN)) 1306 cxgb4_quiesce_rx(&mirror_rxq->rspq); 1307 1308 if (adap->flags & CXGB4_USING_MSIX) { 1309 cxgb4_clear_msix_aff(mirror_rxq->msix->vec, 1310 mirror_rxq->msix->aff_mask); 1311 free_irq(mirror_rxq->msix->vec, &mirror_rxq->rspq); 1312 cxgb4_free_msix_idx_in_bmap(adap, mirror_rxq->msix->idx); 1313 } 1314 1315 free_rspq_fl(adap, &mirror_rxq->rspq, &mirror_rxq->fl); 1316} 1317 1318static int cxgb4_port_mirror_alloc_queues(struct net_device *dev) 1319{ 1320 struct port_info *pi = netdev2pinfo(dev); 1321 struct adapter *adap = netdev2adap(dev); 1322 struct sge_eth_rxq *mirror_rxq; 1323 struct sge *s = &adap->sge; 1324 int ret = 0, msix = 0; 1325 u16 i, rxqid; 1326 u16 *rss; 1327 1328 if (!pi->vi_mirror_count) 1329 return 0; 1330 1331 if (s->mirror_rxq[pi->port_id]) 1332 return 0; 1333 1334 mirror_rxq = kcalloc(pi->nmirrorqsets, sizeof(*mirror_rxq), GFP_KERNEL); 1335 if (!mirror_rxq) 1336 return -ENOMEM; 1337 1338 s->mirror_rxq[pi->port_id] = mirror_rxq; 1339 1340 if (!(adap->flags & CXGB4_USING_MSIX)) 1341 msix = -((int)adap->sge.intrq.abs_id + 1); 1342 1343 for (i = 0, rxqid = 0; i < pi->nmirrorqsets; i++, rxqid++) { 1344 mirror_rxq = &s->mirror_rxq[pi->port_id][i]; 1345 1346 /* Allocate Mirror Rxqs */ 1347 if (msix >= 0) { 1348 msix = cxgb4_get_msix_idx_from_bmap(adap); 1349 if (msix < 0) { 1350 ret = msix; 1351 goto out_free_queues; 1352 } 1353 1354 mirror_rxq->msix = &adap->msix_info[msix]; 1355 snprintf(mirror_rxq->msix->desc, 1356 sizeof(mirror_rxq->msix->desc), 1357 "%s-mirrorrxq%d", dev->name, i); 1358 } 1359 1360 init_rspq(adap, &mirror_rxq->rspq, 1361 CXGB4_MIRROR_RXQ_DEFAULT_INTR_USEC, 1362 CXGB4_MIRROR_RXQ_DEFAULT_PKT_CNT, 1363 CXGB4_MIRROR_RXQ_DEFAULT_DESC_NUM, 1364 CXGB4_MIRROR_RXQ_DEFAULT_DESC_SIZE); 1365 1366 mirror_rxq->fl.size = CXGB4_MIRROR_FLQ_DEFAULT_DESC_NUM; 1367 1368 ret = t4_sge_alloc_rxq(adap, &mirror_rxq->rspq, false, 1369 dev, msix, &mirror_rxq->fl, 1370 t4_ethrx_handler, NULL, 0); 1371 if (ret) 1372 goto out_free_msix_idx; 1373 1374 /* Setup MSI-X vectors for Mirror Rxqs */ 1375 if (adap->flags & CXGB4_USING_MSIX) { 1376 ret = request_irq(mirror_rxq->msix->vec, 1377 t4_sge_intr_msix, 0, 1378 mirror_rxq->msix->desc, 1379 &mirror_rxq->rspq); 1380 if (ret) 1381 goto out_free_rxq; 1382 1383 cxgb4_set_msix_aff(adap, mirror_rxq->msix->vec, 1384 &mirror_rxq->msix->aff_mask, i); 1385 } 1386 1387 /* Start NAPI for Mirror Rxqs */ 1388 cxgb4_enable_rx(adap, &mirror_rxq->rspq); 1389 } 1390 1391 /* Setup RSS for Mirror Rxqs */ 1392 rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 1393 if (!rss) { 1394 ret = -ENOMEM; 1395 goto out_free_queues; 1396 } 1397 1398 mirror_rxq = &s->mirror_rxq[pi->port_id][0]; 1399 for (i = 0; i < pi->rss_size; i++) 1400 rss[i] = mirror_rxq[i % pi->nmirrorqsets].rspq.abs_id; 1401 1402 ret = cxgb4_config_rss(pi, rss, pi->rss_size, pi->viid_mirror); 1403 kfree(rss); 1404 if (ret) 1405 goto out_free_queues; 1406 1407 return 0; 1408 1409out_free_rxq: 1410 free_rspq_fl(adap, &mirror_rxq->rspq, &mirror_rxq->fl); 1411 1412out_free_msix_idx: 1413 cxgb4_free_msix_idx_in_bmap(adap, mirror_rxq->msix->idx); 1414 1415out_free_queues: 1416 while (rxqid-- > 0) 1417 cxgb4_port_mirror_free_rxq(adap, 1418 &s->mirror_rxq[pi->port_id][rxqid]); 1419 1420 kfree(s->mirror_rxq[pi->port_id]); 1421 s->mirror_rxq[pi->port_id] = NULL; 1422 return ret; 1423} 1424 1425static void cxgb4_port_mirror_free_queues(struct net_device *dev) 1426{ 1427 struct port_info *pi = netdev2pinfo(dev); 1428 struct adapter *adap = netdev2adap(dev); 1429 struct sge *s = &adap->sge; 1430 u16 i; 1431 1432 if (!pi->vi_mirror_count) 1433 return; 1434 1435 if (!s->mirror_rxq[pi->port_id]) 1436 return; 1437 1438 for (i = 0; i < pi->nmirrorqsets; i++) 1439 cxgb4_port_mirror_free_rxq(adap, 1440 &s->mirror_rxq[pi->port_id][i]); 1441 1442 kfree(s->mirror_rxq[pi->port_id]); 1443 s->mirror_rxq[pi->port_id] = NULL; 1444} 1445 1446static int cxgb4_port_mirror_start(struct net_device *dev) 1447{ 1448 struct port_info *pi = netdev2pinfo(dev); 1449 struct adapter *adap = netdev2adap(dev); 1450 int ret, idx = -1; 1451 1452 if (!pi->vi_mirror_count) 1453 return 0; 1454 1455 /* Mirror VIs can be created dynamically after stack had 1456 * already setup Rx modes like MTU, promisc, allmulti, etc. 1457 * on main VI. So, parse what the stack had setup on the 1458 * main VI and update the same on the mirror VI. 1459 */ 1460 ret = t4_set_rxmode(adap, adap->mbox, pi->viid, pi->viid_mirror, 1461 dev->mtu, (dev->flags & IFF_PROMISC) ? 1 : 0, 1462 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, 1463 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 1464 if (ret) { 1465 dev_err(adap->pdev_dev, 1466 "Failed start up Rx mode for Mirror VI 0x%x, ret: %d\n", 1467 pi->viid_mirror, ret); 1468 return ret; 1469 } 1470 1471 /* Enable replication bit for the device's MAC address 1472 * in MPS TCAM, so that the packets for the main VI are 1473 * replicated to mirror VI. 1474 */ 1475 ret = cxgb4_update_mac_filt(pi, pi->viid_mirror, &idx, 1476 dev->dev_addr, true, NULL); 1477 if (ret) { 1478 dev_err(adap->pdev_dev, 1479 "Failed updating MAC filter for Mirror VI 0x%x, ret: %d\n", 1480 pi->viid_mirror, ret); 1481 return ret; 1482 } 1483 1484 /* Enabling a Virtual Interface can result in an interrupt 1485 * during the processing of the VI Enable command and, in some 1486 * paths, result in an attempt to issue another command in the 1487 * interrupt context. Thus, we disable interrupts during the 1488 * course of the VI Enable command ... 1489 */ 1490 local_bh_disable(); 1491 ret = t4_enable_vi_params(adap, adap->mbox, pi->viid_mirror, true, true, 1492 false); 1493 local_bh_enable(); 1494 if (ret) 1495 dev_err(adap->pdev_dev, 1496 "Failed starting Mirror VI 0x%x, ret: %d\n", 1497 pi->viid_mirror, ret); 1498 1499 return ret; 1500} 1501 1502static void cxgb4_port_mirror_stop(struct net_device *dev) 1503{ 1504 struct port_info *pi = netdev2pinfo(dev); 1505 struct adapter *adap = netdev2adap(dev); 1506 1507 if (!pi->vi_mirror_count) 1508 return; 1509 1510 t4_enable_vi_params(adap, adap->mbox, pi->viid_mirror, false, false, 1511 false); 1512} 1513 1514int cxgb4_port_mirror_alloc(struct net_device *dev) 1515{ 1516 struct port_info *pi = netdev2pinfo(dev); 1517 struct adapter *adap = netdev2adap(dev); 1518 int ret = 0; 1519 1520 if (!pi->nmirrorqsets) 1521 return -EOPNOTSUPP; 1522 1523 mutex_lock(&pi->vi_mirror_mutex); 1524 if (pi->viid_mirror) { 1525 pi->vi_mirror_count++; 1526 goto out_unlock; 1527 } 1528 1529 ret = t4_init_port_mirror(pi, adap->mbox, pi->port_id, adap->pf, 0, 1530 &pi->viid_mirror); 1531 if (ret) 1532 goto out_unlock; 1533 1534 pi->vi_mirror_count = 1; 1535 1536 if (adap->flags & CXGB4_FULL_INIT_DONE) { 1537 ret = cxgb4_port_mirror_alloc_queues(dev); 1538 if (ret) 1539 goto out_free_vi; 1540 1541 ret = cxgb4_port_mirror_start(dev); 1542 if (ret) 1543 goto out_free_queues; 1544 } 1545 1546 mutex_unlock(&pi->vi_mirror_mutex); 1547 return 0; 1548 1549out_free_queues: 1550 cxgb4_port_mirror_free_queues(dev); 1551 1552out_free_vi: 1553 pi->vi_mirror_count = 0; 1554 t4_free_vi(adap, adap->mbox, adap->pf, 0, pi->viid_mirror); 1555 pi->viid_mirror = 0; 1556 1557out_unlock: 1558 mutex_unlock(&pi->vi_mirror_mutex); 1559 return ret; 1560} 1561 1562void cxgb4_port_mirror_free(struct net_device *dev) 1563{ 1564 struct port_info *pi = netdev2pinfo(dev); 1565 struct adapter *adap = netdev2adap(dev); 1566 1567 mutex_lock(&pi->vi_mirror_mutex); 1568 if (!pi->viid_mirror) 1569 goto out_unlock; 1570 1571 if (pi->vi_mirror_count > 1) { 1572 pi->vi_mirror_count--; 1573 goto out_unlock; 1574 } 1575 1576 cxgb4_port_mirror_stop(dev); 1577 cxgb4_port_mirror_free_queues(dev); 1578 1579 pi->vi_mirror_count = 0; 1580 t4_free_vi(adap, adap->mbox, adap->pf, 0, pi->viid_mirror); 1581 pi->viid_mirror = 0; 1582 1583out_unlock: 1584 mutex_unlock(&pi->vi_mirror_mutex); 1585} 1586 1587/* 1588 * upper-layer driver support 1589 */ 1590 1591/* 1592 * Allocate an active-open TID and set it to the supplied value. 1593 */ 1594int cxgb4_alloc_atid(struct tid_info *t, void *data) 1595{ 1596 int atid = -1; 1597 1598 spin_lock_bh(&t->atid_lock); 1599 if (t->afree) { 1600 union aopen_entry *p = t->afree; 1601 1602 atid = (p - t->atid_tab) + t->atid_base; 1603 t->afree = p->next; 1604 p->data = data; 1605 t->atids_in_use++; 1606 } 1607 spin_unlock_bh(&t->atid_lock); 1608 return atid; 1609} 1610EXPORT_SYMBOL(cxgb4_alloc_atid); 1611 1612/* 1613 * Release an active-open TID. 1614 */ 1615void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1616{ 1617 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1618 1619 spin_lock_bh(&t->atid_lock); 1620 p->next = t->afree; 1621 t->afree = p; 1622 t->atids_in_use--; 1623 spin_unlock_bh(&t->atid_lock); 1624} 1625EXPORT_SYMBOL(cxgb4_free_atid); 1626 1627/* 1628 * Allocate a server TID and set it to the supplied value. 1629 */ 1630int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1631{ 1632 int stid; 1633 1634 spin_lock_bh(&t->stid_lock); 1635 if (family == PF_INET) { 1636 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1637 if (stid < t->nstids) 1638 __set_bit(stid, t->stid_bmap); 1639 else 1640 stid = -1; 1641 } else { 1642 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1643 if (stid < 0) 1644 stid = -1; 1645 } 1646 if (stid >= 0) { 1647 t->stid_tab[stid].data = data; 1648 stid += t->stid_base; 1649 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1650 * This is equivalent to 4 TIDs. With CLIP enabled it 1651 * needs 2 TIDs. 1652 */ 1653 if (family == PF_INET6) { 1654 t->stids_in_use += 2; 1655 t->v6_stids_in_use += 2; 1656 } else { 1657 t->stids_in_use++; 1658 } 1659 } 1660 spin_unlock_bh(&t->stid_lock); 1661 return stid; 1662} 1663EXPORT_SYMBOL(cxgb4_alloc_stid); 1664 1665/* Allocate a server filter TID and set it to the supplied value. 1666 */ 1667int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1668{ 1669 int stid; 1670 1671 spin_lock_bh(&t->stid_lock); 1672 if (family == PF_INET) { 1673 stid = find_next_zero_bit(t->stid_bmap, 1674 t->nstids + t->nsftids, t->nstids); 1675 if (stid < (t->nstids + t->nsftids)) 1676 __set_bit(stid, t->stid_bmap); 1677 else 1678 stid = -1; 1679 } else { 1680 stid = -1; 1681 } 1682 if (stid >= 0) { 1683 t->stid_tab[stid].data = data; 1684 stid -= t->nstids; 1685 stid += t->sftid_base; 1686 t->sftids_in_use++; 1687 } 1688 spin_unlock_bh(&t->stid_lock); 1689 return stid; 1690} 1691EXPORT_SYMBOL(cxgb4_alloc_sftid); 1692 1693/* Release a server TID. 1694 */ 1695void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1696{ 1697 /* Is it a server filter TID? */ 1698 if (t->nsftids && (stid >= t->sftid_base)) { 1699 stid -= t->sftid_base; 1700 stid += t->nstids; 1701 } else { 1702 stid -= t->stid_base; 1703 } 1704 1705 spin_lock_bh(&t->stid_lock); 1706 if (family == PF_INET) 1707 __clear_bit(stid, t->stid_bmap); 1708 else 1709 bitmap_release_region(t->stid_bmap, stid, 1); 1710 t->stid_tab[stid].data = NULL; 1711 if (stid < t->nstids) { 1712 if (family == PF_INET6) { 1713 t->stids_in_use -= 2; 1714 t->v6_stids_in_use -= 2; 1715 } else { 1716 t->stids_in_use--; 1717 } 1718 } else { 1719 t->sftids_in_use--; 1720 } 1721 1722 spin_unlock_bh(&t->stid_lock); 1723} 1724EXPORT_SYMBOL(cxgb4_free_stid); 1725 1726/* 1727 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1728 */ 1729static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1730 unsigned int tid) 1731{ 1732 struct cpl_tid_release *req; 1733 1734 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1735 req = __skb_put(skb, sizeof(*req)); 1736 INIT_TP_WR(req, tid); 1737 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1738} 1739 1740/* 1741 * Queue a TID release request and if necessary schedule a work queue to 1742 * process it. 1743 */ 1744static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1745 unsigned int tid) 1746{ 1747 struct adapter *adap = container_of(t, struct adapter, tids); 1748 void **p = &t->tid_tab[tid - t->tid_base]; 1749 1750 spin_lock_bh(&adap->tid_release_lock); 1751 *p = adap->tid_release_head; 1752 /* Low 2 bits encode the Tx channel number */ 1753 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1754 if (!adap->tid_release_task_busy) { 1755 adap->tid_release_task_busy = true; 1756 queue_work(adap->workq, &adap->tid_release_task); 1757 } 1758 spin_unlock_bh(&adap->tid_release_lock); 1759} 1760 1761/* 1762 * Process the list of pending TID release requests. 1763 */ 1764static void process_tid_release_list(struct work_struct *work) 1765{ 1766 struct sk_buff *skb; 1767 struct adapter *adap; 1768 1769 adap = container_of(work, struct adapter, tid_release_task); 1770 1771 spin_lock_bh(&adap->tid_release_lock); 1772 while (adap->tid_release_head) { 1773 void **p = adap->tid_release_head; 1774 unsigned int chan = (uintptr_t)p & 3; 1775 p = (void *)p - chan; 1776 1777 adap->tid_release_head = *p; 1778 *p = NULL; 1779 spin_unlock_bh(&adap->tid_release_lock); 1780 1781 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1782 GFP_KERNEL))) 1783 schedule_timeout_uninterruptible(1); 1784 1785 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1786 t4_ofld_send(adap, skb); 1787 spin_lock_bh(&adap->tid_release_lock); 1788 } 1789 adap->tid_release_task_busy = false; 1790 spin_unlock_bh(&adap->tid_release_lock); 1791} 1792 1793/* 1794 * Release a TID and inform HW. If we are unable to allocate the release 1795 * message we defer to a work queue. 1796 */ 1797void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1798 unsigned short family) 1799{ 1800 struct adapter *adap = container_of(t, struct adapter, tids); 1801 struct sk_buff *skb; 1802 1803 WARN_ON(tid_out_of_range(&adap->tids, tid)); 1804 1805 if (t->tid_tab[tid - adap->tids.tid_base]) { 1806 t->tid_tab[tid - adap->tids.tid_base] = NULL; 1807 atomic_dec(&t->conns_in_use); 1808 if (t->hash_base && (tid >= t->hash_base)) { 1809 if (family == AF_INET6) 1810 atomic_sub(2, &t->hash_tids_in_use); 1811 else 1812 atomic_dec(&t->hash_tids_in_use); 1813 } else { 1814 if (family == AF_INET6) 1815 atomic_sub(2, &t->tids_in_use); 1816 else 1817 atomic_dec(&t->tids_in_use); 1818 } 1819 } 1820 1821 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1822 if (likely(skb)) { 1823 mk_tid_release(skb, chan, tid); 1824 t4_ofld_send(adap, skb); 1825 } else 1826 cxgb4_queue_tid_release(t, chan, tid); 1827} 1828EXPORT_SYMBOL(cxgb4_remove_tid); 1829 1830/* 1831 * Allocate and initialize the TID tables. Returns 0 on success. 1832 */ 1833static int tid_init(struct tid_info *t) 1834{ 1835 struct adapter *adap = container_of(t, struct adapter, tids); 1836 unsigned int max_ftids = t->nftids + t->nsftids; 1837 unsigned int natids = t->natids; 1838 unsigned int hpftid_bmap_size; 1839 unsigned int eotid_bmap_size; 1840 unsigned int stid_bmap_size; 1841 unsigned int ftid_bmap_size; 1842 size_t size; 1843 1844 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1845 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1846 hpftid_bmap_size = BITS_TO_LONGS(t->nhpftids); 1847 eotid_bmap_size = BITS_TO_LONGS(t->neotids); 1848 size = t->ntids * sizeof(*t->tid_tab) + 1849 natids * sizeof(*t->atid_tab) + 1850 t->nstids * sizeof(*t->stid_tab) + 1851 t->nsftids * sizeof(*t->stid_tab) + 1852 stid_bmap_size * sizeof(long) + 1853 t->nhpftids * sizeof(*t->hpftid_tab) + 1854 hpftid_bmap_size * sizeof(long) + 1855 max_ftids * sizeof(*t->ftid_tab) + 1856 ftid_bmap_size * sizeof(long) + 1857 t->neotids * sizeof(*t->eotid_tab) + 1858 eotid_bmap_size * sizeof(long); 1859 1860 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1861 if (!t->tid_tab) 1862 return -ENOMEM; 1863 1864 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1865 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1866 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1867 t->hpftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1868 t->hpftid_bmap = (unsigned long *)&t->hpftid_tab[t->nhpftids]; 1869 t->ftid_tab = (struct filter_entry *)&t->hpftid_bmap[hpftid_bmap_size]; 1870 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1871 t->eotid_tab = (struct eotid_entry *)&t->ftid_bmap[ftid_bmap_size]; 1872 t->eotid_bmap = (unsigned long *)&t->eotid_tab[t->neotids]; 1873 spin_lock_init(&t->stid_lock); 1874 spin_lock_init(&t->atid_lock); 1875 spin_lock_init(&t->ftid_lock); 1876 1877 t->stids_in_use = 0; 1878 t->v6_stids_in_use = 0; 1879 t->sftids_in_use = 0; 1880 t->afree = NULL; 1881 t->atids_in_use = 0; 1882 atomic_set(&t->tids_in_use, 0); 1883 atomic_set(&t->conns_in_use, 0); 1884 atomic_set(&t->hash_tids_in_use, 0); 1885 atomic_set(&t->eotids_in_use, 0); 1886 1887 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1888 if (natids) { 1889 while (--natids) 1890 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1891 t->afree = t->atid_tab; 1892 } 1893 1894 if (is_offload(adap)) { 1895 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1896 /* Reserve stid 0 for T4/T5 adapters */ 1897 if (!t->stid_base && 1898 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1899 __set_bit(0, t->stid_bmap); 1900 1901 if (t->neotids) 1902 bitmap_zero(t->eotid_bmap, t->neotids); 1903 } 1904 1905 if (t->nhpftids) 1906 bitmap_zero(t->hpftid_bmap, t->nhpftids); 1907 bitmap_zero(t->ftid_bmap, t->nftids); 1908 return 0; 1909} 1910 1911/** 1912 * cxgb4_create_server - create an IP server 1913 * @dev: the device 1914 * @stid: the server TID 1915 * @sip: local IP address to bind server to 1916 * @sport: the server's TCP port 1917 * @vlan: the VLAN header information 1918 * @queue: queue to direct messages from this server to 1919 * 1920 * Create an IP server for the given port and address. 1921 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1922 */ 1923int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1924 __be32 sip, __be16 sport, __be16 vlan, 1925 unsigned int queue) 1926{ 1927 unsigned int chan; 1928 struct sk_buff *skb; 1929 struct adapter *adap; 1930 struct cpl_pass_open_req *req; 1931 int ret; 1932 1933 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1934 if (!skb) 1935 return -ENOMEM; 1936 1937 adap = netdev2adap(dev); 1938 req = __skb_put(skb, sizeof(*req)); 1939 INIT_TP_WR(req, 0); 1940 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1941 req->local_port = sport; 1942 req->peer_port = htons(0); 1943 req->local_ip = sip; 1944 req->peer_ip = htonl(0); 1945 chan = rxq_to_chan(&adap->sge, queue); 1946 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1947 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1948 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1949 ret = t4_mgmt_tx(adap, skb); 1950 return net_xmit_eval(ret); 1951} 1952EXPORT_SYMBOL(cxgb4_create_server); 1953 1954/* cxgb4_create_server6 - create an IPv6 server 1955 * @dev: the device 1956 * @stid: the server TID 1957 * @sip: local IPv6 address to bind server to 1958 * @sport: the server's TCP port 1959 * @queue: queue to direct messages from this server to 1960 * 1961 * Create an IPv6 server for the given port and address. 1962 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1963 */ 1964int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1965 const struct in6_addr *sip, __be16 sport, 1966 unsigned int queue) 1967{ 1968 unsigned int chan; 1969 struct sk_buff *skb; 1970 struct adapter *adap; 1971 struct cpl_pass_open_req6 *req; 1972 int ret; 1973 1974 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1975 if (!skb) 1976 return -ENOMEM; 1977 1978 adap = netdev2adap(dev); 1979 req = __skb_put(skb, sizeof(*req)); 1980 INIT_TP_WR(req, 0); 1981 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1982 req->local_port = sport; 1983 req->peer_port = htons(0); 1984 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1985 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1986 req->peer_ip_hi = cpu_to_be64(0); 1987 req->peer_ip_lo = cpu_to_be64(0); 1988 chan = rxq_to_chan(&adap->sge, queue); 1989 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1990 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1991 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1992 ret = t4_mgmt_tx(adap, skb); 1993 return net_xmit_eval(ret); 1994} 1995EXPORT_SYMBOL(cxgb4_create_server6); 1996 1997int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1998 unsigned int queue, bool ipv6) 1999{ 2000 struct sk_buff *skb; 2001 struct adapter *adap; 2002 struct cpl_close_listsvr_req *req; 2003 int ret; 2004 2005 adap = netdev2adap(dev); 2006 2007 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 2008 if (!skb) 2009 return -ENOMEM; 2010 2011 req = __skb_put(skb, sizeof(*req)); 2012 INIT_TP_WR(req, 0); 2013 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 2014 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 2015 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 2016 ret = t4_mgmt_tx(adap, skb); 2017 return net_xmit_eval(ret); 2018} 2019EXPORT_SYMBOL(cxgb4_remove_server); 2020 2021/** 2022 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 2023 * @mtus: the HW MTU table 2024 * @mtu: the target MTU 2025 * @idx: index of selected entry in the MTU table 2026 * 2027 * Returns the index and the value in the HW MTU table that is closest to 2028 * but does not exceed @mtu, unless @mtu is smaller than any value in the 2029 * table, in which case that smallest available value is selected. 2030 */ 2031unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 2032 unsigned int *idx) 2033{ 2034 unsigned int i = 0; 2035 2036 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 2037 ++i; 2038 if (idx) 2039 *idx = i; 2040 return mtus[i]; 2041} 2042EXPORT_SYMBOL(cxgb4_best_mtu); 2043 2044/** 2045 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 2046 * @mtus: the HW MTU table 2047 * @header_size: Header Size 2048 * @data_size_max: maximum Data Segment Size 2049 * @data_size_align: desired Data Segment Size Alignment (2^N) 2050 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 2051 * 2052 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 2053 * MTU Table based solely on a Maximum MTU parameter, we break that 2054 * parameter up into a Header Size and Maximum Data Segment Size, and 2055 * provide a desired Data Segment Size Alignment. If we find an MTU in 2056 * the Hardware MTU Table which will result in a Data Segment Size with 2057 * the requested alignment _and_ that MTU isn't "too far" from the 2058 * closest MTU, then we'll return that rather than the closest MTU. 2059 */ 2060unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 2061 unsigned short header_size, 2062 unsigned short data_size_max, 2063 unsigned short data_size_align, 2064 unsigned int *mtu_idxp) 2065{ 2066 unsigned short max_mtu = header_size + data_size_max; 2067 unsigned short data_size_align_mask = data_size_align - 1; 2068 int mtu_idx, aligned_mtu_idx; 2069 2070 /* Scan the MTU Table till we find an MTU which is larger than our 2071 * Maximum MTU or we reach the end of the table. Along the way, 2072 * record the last MTU found, if any, which will result in a Data 2073 * Segment Length matching the requested alignment. 2074 */ 2075 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 2076 unsigned short data_size = mtus[mtu_idx] - header_size; 2077 2078 /* If this MTU minus the Header Size would result in a 2079 * Data Segment Size of the desired alignment, remember it. 2080 */ 2081 if ((data_size & data_size_align_mask) == 0) 2082 aligned_mtu_idx = mtu_idx; 2083 2084 /* If we're not at the end of the Hardware MTU Table and the 2085 * next element is larger than our Maximum MTU, drop out of 2086 * the loop. 2087 */ 2088 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 2089 break; 2090 } 2091 2092 /* If we fell out of the loop because we ran to the end of the table, 2093 * then we just have to use the last [largest] entry. 2094 */ 2095 if (mtu_idx == NMTUS) 2096 mtu_idx--; 2097 2098 /* If we found an MTU which resulted in the requested Data Segment 2099 * Length alignment and that's "not far" from the largest MTU which is 2100 * less than or equal to the maximum MTU, then use that. 2101 */ 2102 if (aligned_mtu_idx >= 0 && 2103 mtu_idx - aligned_mtu_idx <= 1) 2104 mtu_idx = aligned_mtu_idx; 2105 2106 /* If the caller has passed in an MTU Index pointer, pass the 2107 * MTU Index back. Return the MTU value. 2108 */ 2109 if (mtu_idxp) 2110 *mtu_idxp = mtu_idx; 2111 return mtus[mtu_idx]; 2112} 2113EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 2114 2115/** 2116 * cxgb4_port_chan - get the HW channel of a port 2117 * @dev: the net device for the port 2118 * 2119 * Return the HW Tx channel of the given port. 2120 */ 2121unsigned int cxgb4_port_chan(const struct net_device *dev) 2122{ 2123 return netdev2pinfo(dev)->tx_chan; 2124} 2125EXPORT_SYMBOL(cxgb4_port_chan); 2126 2127/** 2128 * cxgb4_port_e2cchan - get the HW c-channel of a port 2129 * @dev: the net device for the port 2130 * 2131 * Return the HW RX c-channel of the given port. 2132 */ 2133unsigned int cxgb4_port_e2cchan(const struct net_device *dev) 2134{ 2135 return netdev2pinfo(dev)->rx_cchan; 2136} 2137EXPORT_SYMBOL(cxgb4_port_e2cchan); 2138 2139unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 2140{ 2141 struct adapter *adap = netdev2adap(dev); 2142 u32 v1, v2, lp_count, hp_count; 2143 2144 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2145 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2146 if (is_t4(adap->params.chip)) { 2147 lp_count = LP_COUNT_G(v1); 2148 hp_count = HP_COUNT_G(v1); 2149 } else { 2150 lp_count = LP_COUNT_T5_G(v1); 2151 hp_count = HP_COUNT_T5_G(v2); 2152 } 2153 return lpfifo ? lp_count : hp_count; 2154} 2155EXPORT_SYMBOL(cxgb4_dbfifo_count); 2156 2157/** 2158 * cxgb4_port_viid - get the VI id of a port 2159 * @dev: the net device for the port 2160 * 2161 * Return the VI id of the given port. 2162 */ 2163unsigned int cxgb4_port_viid(const struct net_device *dev) 2164{ 2165 return netdev2pinfo(dev)->viid; 2166} 2167EXPORT_SYMBOL(cxgb4_port_viid); 2168 2169/** 2170 * cxgb4_port_idx - get the index of a port 2171 * @dev: the net device for the port 2172 * 2173 * Return the index of the given port. 2174 */ 2175unsigned int cxgb4_port_idx(const struct net_device *dev) 2176{ 2177 return netdev2pinfo(dev)->port_id; 2178} 2179EXPORT_SYMBOL(cxgb4_port_idx); 2180 2181void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 2182 struct tp_tcp_stats *v6) 2183{ 2184 struct adapter *adap = pci_get_drvdata(pdev); 2185 2186 spin_lock(&adap->stats_lock); 2187 t4_tp_get_tcp_stats(adap, v4, v6, false); 2188 spin_unlock(&adap->stats_lock); 2189} 2190EXPORT_SYMBOL(cxgb4_get_tcp_stats); 2191 2192void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 2193 const unsigned int *pgsz_order) 2194{ 2195 struct adapter *adap = netdev2adap(dev); 2196 2197 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 2198 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 2199 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 2200 HPZ3_V(pgsz_order[3])); 2201} 2202EXPORT_SYMBOL(cxgb4_iscsi_init); 2203 2204int cxgb4_flush_eq_cache(struct net_device *dev) 2205{ 2206 struct adapter *adap = netdev2adap(dev); 2207 2208 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS); 2209} 2210EXPORT_SYMBOL(cxgb4_flush_eq_cache); 2211 2212static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 2213{ 2214 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 2215 __be64 indices; 2216 int ret; 2217 2218 spin_lock(&adap->win0_lock); 2219 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 2220 sizeof(indices), (__be32 *)&indices, 2221 T4_MEMORY_READ); 2222 spin_unlock(&adap->win0_lock); 2223 if (!ret) { 2224 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 2225 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 2226 } 2227 return ret; 2228} 2229 2230int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 2231 u16 size) 2232{ 2233 struct adapter *adap = netdev2adap(dev); 2234 u16 hw_pidx, hw_cidx; 2235 int ret; 2236 2237 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 2238 if (ret) 2239 goto out; 2240 2241 if (pidx != hw_pidx) { 2242 u16 delta; 2243 u32 val; 2244 2245 if (pidx >= hw_pidx) 2246 delta = pidx - hw_pidx; 2247 else 2248 delta = size - hw_pidx + pidx; 2249 2250 if (is_t4(adap->params.chip)) 2251 val = PIDX_V(delta); 2252 else 2253 val = PIDX_T5_V(delta); 2254 wmb(); 2255 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2256 QID_V(qid) | val); 2257 } 2258out: 2259 return ret; 2260} 2261EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 2262 2263int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 2264{ 2265 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 2266 u32 edc0_end, edc1_end, mc0_end, mc1_end; 2267 u32 offset, memtype, memaddr; 2268 struct adapter *adap; 2269 u32 hma_size = 0; 2270 int ret; 2271 2272 adap = netdev2adap(dev); 2273 2274 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 2275 2276 /* Figure out where the offset lands in the Memory Type/Address scheme. 2277 * This code assumes that the memory is laid out starting at offset 0 2278 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 2279 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 2280 * MC0, and some have both MC0 and MC1. 2281 */ 2282 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 2283 edc0_size = EDRAM0_SIZE_G(size) << 20; 2284 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2285 edc1_size = EDRAM1_SIZE_G(size) << 20; 2286 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2287 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 2288 2289 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { 2290 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2291 hma_size = EXT_MEM1_SIZE_G(size) << 20; 2292 } 2293 edc0_end = edc0_size; 2294 edc1_end = edc0_end + edc1_size; 2295 mc0_end = edc1_end + mc0_size; 2296 2297 if (offset < edc0_end) { 2298 memtype = MEM_EDC0; 2299 memaddr = offset; 2300 } else if (offset < edc1_end) { 2301 memtype = MEM_EDC1; 2302 memaddr = offset - edc0_end; 2303 } else { 2304 if (hma_size && (offset < (edc1_end + hma_size))) { 2305 memtype = MEM_HMA; 2306 memaddr = offset - edc1_end; 2307 } else if (offset < mc0_end) { 2308 memtype = MEM_MC0; 2309 memaddr = offset - edc1_end; 2310 } else if (is_t5(adap->params.chip)) { 2311 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2312 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 2313 mc1_end = mc0_end + mc1_size; 2314 if (offset < mc1_end) { 2315 memtype = MEM_MC1; 2316 memaddr = offset - mc0_end; 2317 } else { 2318 /* offset beyond the end of any memory */ 2319 goto err; 2320 } 2321 } else { 2322 /* T4/T6 only has a single memory channel */ 2323 goto err; 2324 } 2325 } 2326 2327 spin_lock(&adap->win0_lock); 2328 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 2329 spin_unlock(&adap->win0_lock); 2330 return ret; 2331 2332err: 2333 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 2334 stag, offset); 2335 return -EINVAL; 2336} 2337EXPORT_SYMBOL(cxgb4_read_tpte); 2338 2339u64 cxgb4_read_sge_timestamp(struct net_device *dev) 2340{ 2341 u32 hi, lo; 2342 struct adapter *adap; 2343 2344 adap = netdev2adap(dev); 2345 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 2346 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 2347 2348 return ((u64)hi << 32) | (u64)lo; 2349} 2350EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 2351 2352int cxgb4_bar2_sge_qregs(struct net_device *dev, 2353 unsigned int qid, 2354 enum cxgb4_bar2_qtype qtype, 2355 int user, 2356 u64 *pbar2_qoffset, 2357 unsigned int *pbar2_qid) 2358{ 2359 return t4_bar2_sge_qregs(netdev2adap(dev), 2360 qid, 2361 (qtype == CXGB4_BAR2_QTYPE_EGRESS 2362 ? T4_BAR2_QTYPE_EGRESS 2363 : T4_BAR2_QTYPE_INGRESS), 2364 user, 2365 pbar2_qoffset, 2366 pbar2_qid); 2367} 2368EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 2369 2370static struct pci_driver cxgb4_driver; 2371 2372static void check_neigh_update(struct neighbour *neigh) 2373{ 2374 const struct device *parent; 2375 const struct net_device *netdev = neigh->dev; 2376 2377 if (is_vlan_dev(netdev)) 2378 netdev = vlan_dev_real_dev(netdev); 2379 parent = netdev->dev.parent; 2380 if (parent && parent->driver == &cxgb4_driver.driver) 2381 t4_l2t_update(dev_get_drvdata(parent), neigh); 2382} 2383 2384static int netevent_cb(struct notifier_block *nb, unsigned long event, 2385 void *data) 2386{ 2387 switch (event) { 2388 case NETEVENT_NEIGH_UPDATE: 2389 check_neigh_update(data); 2390 break; 2391 case NETEVENT_REDIRECT: 2392 default: 2393 break; 2394 } 2395 return 0; 2396} 2397 2398static bool netevent_registered; 2399static struct notifier_block cxgb4_netevent_nb = { 2400 .notifier_call = netevent_cb 2401}; 2402 2403static void drain_db_fifo(struct adapter *adap, int usecs) 2404{ 2405 u32 v1, v2, lp_count, hp_count; 2406 2407 do { 2408 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2409 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2410 if (is_t4(adap->params.chip)) { 2411 lp_count = LP_COUNT_G(v1); 2412 hp_count = HP_COUNT_G(v1); 2413 } else { 2414 lp_count = LP_COUNT_T5_G(v1); 2415 hp_count = HP_COUNT_T5_G(v2); 2416 } 2417 2418 if (lp_count == 0 && hp_count == 0) 2419 break; 2420 set_current_state(TASK_UNINTERRUPTIBLE); 2421 schedule_timeout(usecs_to_jiffies(usecs)); 2422 } while (1); 2423} 2424 2425static void disable_txq_db(struct sge_txq *q) 2426{ 2427 unsigned long flags; 2428 2429 spin_lock_irqsave(&q->db_lock, flags); 2430 q->db_disabled = 1; 2431 spin_unlock_irqrestore(&q->db_lock, flags); 2432} 2433 2434static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 2435{ 2436 spin_lock_irq(&q->db_lock); 2437 if (q->db_pidx_inc) { 2438 /* Make sure that all writes to the TX descriptors 2439 * are committed before we tell HW about them. 2440 */ 2441 wmb(); 2442 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2443 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 2444 q->db_pidx_inc = 0; 2445 } 2446 q->db_disabled = 0; 2447 spin_unlock_irq(&q->db_lock); 2448} 2449 2450static void disable_dbs(struct adapter *adap) 2451{ 2452 int i; 2453 2454 for_each_ethrxq(&adap->sge, i) 2455 disable_txq_db(&adap->sge.ethtxq[i].q); 2456 if (is_offload(adap)) { 2457 struct sge_uld_txq_info *txq_info = 2458 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2459 2460 if (txq_info) { 2461 for_each_ofldtxq(&adap->sge, i) { 2462 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2463 2464 disable_txq_db(&txq->q); 2465 } 2466 } 2467 } 2468 for_each_port(adap, i) 2469 disable_txq_db(&adap->sge.ctrlq[i].q); 2470} 2471 2472static void enable_dbs(struct adapter *adap) 2473{ 2474 int i; 2475 2476 for_each_ethrxq(&adap->sge, i) 2477 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 2478 if (is_offload(adap)) { 2479 struct sge_uld_txq_info *txq_info = 2480 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2481 2482 if (txq_info) { 2483 for_each_ofldtxq(&adap->sge, i) { 2484 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2485 2486 enable_txq_db(adap, &txq->q); 2487 } 2488 } 2489 } 2490 for_each_port(adap, i) 2491 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 2492} 2493 2494static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 2495{ 2496 enum cxgb4_uld type = CXGB4_ULD_RDMA; 2497 2498 if (adap->uld && adap->uld[type].handle) 2499 adap->uld[type].control(adap->uld[type].handle, cmd); 2500} 2501 2502static void process_db_full(struct work_struct *work) 2503{ 2504 struct adapter *adap; 2505 2506 adap = container_of(work, struct adapter, db_full_task); 2507 2508 drain_db_fifo(adap, dbfifo_drain_delay); 2509 enable_dbs(adap); 2510 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2511 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2512 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2513 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2514 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2515 else 2516 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2517 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2518} 2519 2520static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2521{ 2522 u16 hw_pidx, hw_cidx; 2523 int ret; 2524 2525 spin_lock_irq(&q->db_lock); 2526 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2527 if (ret) 2528 goto out; 2529 if (q->db_pidx != hw_pidx) { 2530 u16 delta; 2531 u32 val; 2532 2533 if (q->db_pidx >= hw_pidx) 2534 delta = q->db_pidx - hw_pidx; 2535 else 2536 delta = q->size - hw_pidx + q->db_pidx; 2537 2538 if (is_t4(adap->params.chip)) 2539 val = PIDX_V(delta); 2540 else 2541 val = PIDX_T5_V(delta); 2542 wmb(); 2543 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2544 QID_V(q->cntxt_id) | val); 2545 } 2546out: 2547 q->db_disabled = 0; 2548 q->db_pidx_inc = 0; 2549 spin_unlock_irq(&q->db_lock); 2550 if (ret) 2551 CH_WARN(adap, "DB drop recovery failed.\n"); 2552} 2553 2554static void recover_all_queues(struct adapter *adap) 2555{ 2556 int i; 2557 2558 for_each_ethrxq(&adap->sge, i) 2559 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2560 if (is_offload(adap)) { 2561 struct sge_uld_txq_info *txq_info = 2562 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2563 if (txq_info) { 2564 for_each_ofldtxq(&adap->sge, i) { 2565 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2566 2567 sync_txq_pidx(adap, &txq->q); 2568 } 2569 } 2570 } 2571 for_each_port(adap, i) 2572 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2573} 2574 2575static void process_db_drop(struct work_struct *work) 2576{ 2577 struct adapter *adap; 2578 2579 adap = container_of(work, struct adapter, db_drop_task); 2580 2581 if (is_t4(adap->params.chip)) { 2582 drain_db_fifo(adap, dbfifo_drain_delay); 2583 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2584 drain_db_fifo(adap, dbfifo_drain_delay); 2585 recover_all_queues(adap); 2586 drain_db_fifo(adap, dbfifo_drain_delay); 2587 enable_dbs(adap); 2588 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2589 } else if (is_t5(adap->params.chip)) { 2590 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2591 u16 qid = (dropped_db >> 15) & 0x1ffff; 2592 u16 pidx_inc = dropped_db & 0x1fff; 2593 u64 bar2_qoffset; 2594 unsigned int bar2_qid; 2595 int ret; 2596 2597 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2598 0, &bar2_qoffset, &bar2_qid); 2599 if (ret) 2600 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2601 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2602 else 2603 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2604 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2605 2606 /* Re-enable BAR2 WC */ 2607 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2608 } 2609 2610 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2611 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2612} 2613 2614void t4_db_full(struct adapter *adap) 2615{ 2616 if (is_t4(adap->params.chip)) { 2617 disable_dbs(adap); 2618 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2619 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2620 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2621 queue_work(adap->workq, &adap->db_full_task); 2622 } 2623} 2624 2625void t4_db_dropped(struct adapter *adap) 2626{ 2627 if (is_t4(adap->params.chip)) { 2628 disable_dbs(adap); 2629 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2630 } 2631 queue_work(adap->workq, &adap->db_drop_task); 2632} 2633 2634void t4_register_netevent_notifier(void) 2635{ 2636 if (!netevent_registered) { 2637 register_netevent_notifier(&cxgb4_netevent_nb); 2638 netevent_registered = true; 2639 } 2640} 2641 2642static void detach_ulds(struct adapter *adap) 2643{ 2644 unsigned int i; 2645 2646 if (!is_uld(adap)) 2647 return; 2648 2649 mutex_lock(&uld_mutex); 2650 list_del(&adap->list_node); 2651 2652 for (i = 0; i < CXGB4_ULD_MAX; i++) 2653 if (adap->uld && adap->uld[i].handle) 2654 adap->uld[i].state_change(adap->uld[i].handle, 2655 CXGB4_STATE_DETACH); 2656 2657 if (netevent_registered && list_empty(&adapter_list)) { 2658 unregister_netevent_notifier(&cxgb4_netevent_nb); 2659 netevent_registered = false; 2660 } 2661 mutex_unlock(&uld_mutex); 2662} 2663 2664static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2665{ 2666 unsigned int i; 2667 2668 mutex_lock(&uld_mutex); 2669 for (i = 0; i < CXGB4_ULD_MAX; i++) 2670 if (adap->uld && adap->uld[i].handle) 2671 adap->uld[i].state_change(adap->uld[i].handle, 2672 new_state); 2673 mutex_unlock(&uld_mutex); 2674} 2675 2676#if IS_ENABLED(CONFIG_IPV6) 2677static int cxgb4_inet6addr_handler(struct notifier_block *this, 2678 unsigned long event, void *data) 2679{ 2680 struct inet6_ifaddr *ifa = data; 2681 struct net_device *event_dev = ifa->idev->dev; 2682 const struct device *parent = NULL; 2683#if IS_ENABLED(CONFIG_BONDING) 2684 struct adapter *adap; 2685#endif 2686 if (is_vlan_dev(event_dev)) 2687 event_dev = vlan_dev_real_dev(event_dev); 2688#if IS_ENABLED(CONFIG_BONDING) 2689 if (event_dev->flags & IFF_MASTER) { 2690 list_for_each_entry(adap, &adapter_list, list_node) { 2691 switch (event) { 2692 case NETDEV_UP: 2693 cxgb4_clip_get(adap->port[0], 2694 (const u32 *)ifa, 1); 2695 break; 2696 case NETDEV_DOWN: 2697 cxgb4_clip_release(adap->port[0], 2698 (const u32 *)ifa, 1); 2699 break; 2700 default: 2701 break; 2702 } 2703 } 2704 return NOTIFY_OK; 2705 } 2706#endif 2707 2708 if (event_dev) 2709 parent = event_dev->dev.parent; 2710 2711 if (parent && parent->driver == &cxgb4_driver.driver) { 2712 switch (event) { 2713 case NETDEV_UP: 2714 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2715 break; 2716 case NETDEV_DOWN: 2717 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2718 break; 2719 default: 2720 break; 2721 } 2722 } 2723 return NOTIFY_OK; 2724} 2725 2726static bool inet6addr_registered; 2727static struct notifier_block cxgb4_inet6addr_notifier = { 2728 .notifier_call = cxgb4_inet6addr_handler 2729}; 2730 2731static void update_clip(const struct adapter *adap) 2732{ 2733 int i; 2734 struct net_device *dev; 2735 int ret; 2736 2737 rcu_read_lock(); 2738 2739 for (i = 0; i < MAX_NPORTS; i++) { 2740 dev = adap->port[i]; 2741 ret = 0; 2742 2743 if (dev) 2744 ret = cxgb4_update_root_dev_clip(dev); 2745 2746 if (ret < 0) 2747 break; 2748 } 2749 rcu_read_unlock(); 2750} 2751#endif /* IS_ENABLED(CONFIG_IPV6) */ 2752 2753/** 2754 * cxgb_up - enable the adapter 2755 * @adap: adapter being enabled 2756 * 2757 * Called when the first port is enabled, this function performs the 2758 * actions necessary to make an adapter operational, such as completing 2759 * the initialization of HW modules, and enabling interrupts. 2760 * 2761 * Must be called with the rtnl lock held. 2762 */ 2763static int cxgb_up(struct adapter *adap) 2764{ 2765 struct sge *s = &adap->sge; 2766 int err; 2767 2768 mutex_lock(&uld_mutex); 2769 err = setup_sge_queues(adap); 2770 if (err) 2771 goto rel_lock; 2772 err = setup_rss(adap); 2773 if (err) 2774 goto freeq; 2775 2776 if (adap->flags & CXGB4_USING_MSIX) { 2777 if (s->nd_msix_idx < 0) { 2778 err = -ENOMEM; 2779 goto irq_err; 2780 } 2781 2782 err = request_irq(adap->msix_info[s->nd_msix_idx].vec, 2783 t4_nondata_intr, 0, 2784 adap->msix_info[s->nd_msix_idx].desc, adap); 2785 if (err) 2786 goto irq_err; 2787 2788 err = request_msix_queue_irqs(adap); 2789 if (err) 2790 goto irq_err_free_nd_msix; 2791 } else { 2792 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2793 (adap->flags & CXGB4_USING_MSI) ? 0 2794 : IRQF_SHARED, 2795 adap->port[0]->name, adap); 2796 if (err) 2797 goto irq_err; 2798 } 2799 2800 enable_rx(adap); 2801 t4_sge_start(adap); 2802 t4_intr_enable(adap); 2803 adap->flags |= CXGB4_FULL_INIT_DONE; 2804 mutex_unlock(&uld_mutex); 2805 2806 notify_ulds(adap, CXGB4_STATE_UP); 2807#if IS_ENABLED(CONFIG_IPV6) 2808 update_clip(adap); 2809#endif 2810 return err; 2811 2812irq_err_free_nd_msix: 2813 free_irq(adap->msix_info[s->nd_msix_idx].vec, adap); 2814irq_err: 2815 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2816freeq: 2817 t4_free_sge_resources(adap); 2818rel_lock: 2819 mutex_unlock(&uld_mutex); 2820 return err; 2821} 2822 2823static void cxgb_down(struct adapter *adapter) 2824{ 2825 cancel_work_sync(&adapter->tid_release_task); 2826 cancel_work_sync(&adapter->db_full_task); 2827 cancel_work_sync(&adapter->db_drop_task); 2828 adapter->tid_release_task_busy = false; 2829 adapter->tid_release_head = NULL; 2830 2831 t4_sge_stop(adapter); 2832 t4_free_sge_resources(adapter); 2833 2834 adapter->flags &= ~CXGB4_FULL_INIT_DONE; 2835} 2836 2837/* 2838 * net_device operations 2839 */ 2840static int cxgb_open(struct net_device *dev) 2841{ 2842 struct port_info *pi = netdev_priv(dev); 2843 struct adapter *adapter = pi->adapter; 2844 int err; 2845 2846 netif_carrier_off(dev); 2847 2848 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) { 2849 err = cxgb_up(adapter); 2850 if (err < 0) 2851 return err; 2852 } 2853 2854 /* It's possible that the basic port information could have 2855 * changed since we first read it. 2856 */ 2857 err = t4_update_port_info(pi); 2858 if (err < 0) 2859 return err; 2860 2861 err = link_start(dev); 2862 if (err) 2863 return err; 2864 2865 if (pi->nmirrorqsets) { 2866 mutex_lock(&pi->vi_mirror_mutex); 2867 err = cxgb4_port_mirror_alloc_queues(dev); 2868 if (err) 2869 goto out_unlock; 2870 2871 err = cxgb4_port_mirror_start(dev); 2872 if (err) 2873 goto out_free_queues; 2874 mutex_unlock(&pi->vi_mirror_mutex); 2875 } 2876 2877 netif_tx_start_all_queues(dev); 2878 return 0; 2879 2880out_free_queues: 2881 cxgb4_port_mirror_free_queues(dev); 2882 2883out_unlock: 2884 mutex_unlock(&pi->vi_mirror_mutex); 2885 return err; 2886} 2887 2888static int cxgb_close(struct net_device *dev) 2889{ 2890 struct port_info *pi = netdev_priv(dev); 2891 struct adapter *adapter = pi->adapter; 2892 int ret; 2893 2894 netif_tx_stop_all_queues(dev); 2895 netif_carrier_off(dev); 2896 ret = t4_enable_pi_params(adapter, adapter->pf, pi, 2897 false, false, false); 2898#ifdef CONFIG_CHELSIO_T4_DCB 2899 cxgb4_dcb_reset(dev); 2900 dcb_tx_queue_prio_enable(dev, false); 2901#endif 2902 if (ret) 2903 return ret; 2904 2905 if (pi->nmirrorqsets) { 2906 mutex_lock(&pi->vi_mirror_mutex); 2907 cxgb4_port_mirror_stop(dev); 2908 cxgb4_port_mirror_free_queues(dev); 2909 mutex_unlock(&pi->vi_mirror_mutex); 2910 } 2911 2912 return 0; 2913} 2914 2915int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2916 __be32 sip, __be16 sport, __be16 vlan, 2917 unsigned int queue, unsigned char port, unsigned char mask) 2918{ 2919 int ret; 2920 struct filter_entry *f; 2921 struct adapter *adap; 2922 int i; 2923 u8 *val; 2924 2925 adap = netdev2adap(dev); 2926 2927 /* Adjust stid to correct filter index */ 2928 stid -= adap->tids.sftid_base; 2929 stid += adap->tids.nftids; 2930 2931 /* Check to make sure the filter requested is writable ... 2932 */ 2933 f = &adap->tids.ftid_tab[stid]; 2934 ret = writable_filter(f); 2935 if (ret) 2936 return ret; 2937 2938 /* Clear out any old resources being used by the filter before 2939 * we start constructing the new filter. 2940 */ 2941 if (f->valid) 2942 clear_filter(adap, f); 2943 2944 /* Clear out filter specifications */ 2945 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2946 f->fs.val.lport = be16_to_cpu(sport); 2947 f->fs.mask.lport = ~0; 2948 val = (u8 *)&sip; 2949 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2950 for (i = 0; i < 4; i++) { 2951 f->fs.val.lip[i] = val[i]; 2952 f->fs.mask.lip[i] = ~0; 2953 } 2954 if (adap->params.tp.vlan_pri_map & PORT_F) { 2955 f->fs.val.iport = port; 2956 f->fs.mask.iport = mask; 2957 } 2958 } 2959 2960 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2961 f->fs.val.proto = IPPROTO_TCP; 2962 f->fs.mask.proto = ~0; 2963 } 2964 2965 f->fs.dirsteer = 1; 2966 f->fs.iq = queue; 2967 /* Mark filter as locked */ 2968 f->locked = 1; 2969 f->fs.rpttid = 1; 2970 2971 /* Save the actual tid. We need this to get the corresponding 2972 * filter entry structure in filter_rpl. 2973 */ 2974 f->tid = stid + adap->tids.ftid_base; 2975 ret = set_filter_wr(adap, stid); 2976 if (ret) { 2977 clear_filter(adap, f); 2978 return ret; 2979 } 2980 2981 return 0; 2982} 2983EXPORT_SYMBOL(cxgb4_create_server_filter); 2984 2985int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2986 unsigned int queue, bool ipv6) 2987{ 2988 struct filter_entry *f; 2989 struct adapter *adap; 2990 2991 adap = netdev2adap(dev); 2992 2993 /* Adjust stid to correct filter index */ 2994 stid -= adap->tids.sftid_base; 2995 stid += adap->tids.nftids; 2996 2997 f = &adap->tids.ftid_tab[stid]; 2998 /* Unlock the filter */ 2999 f->locked = 0; 3000 3001 return delete_filter(adap, stid); 3002} 3003EXPORT_SYMBOL(cxgb4_remove_server_filter); 3004 3005static void cxgb_get_stats(struct net_device *dev, 3006 struct rtnl_link_stats64 *ns) 3007{ 3008 struct port_stats stats; 3009 struct port_info *p = netdev_priv(dev); 3010 struct adapter *adapter = p->adapter; 3011 3012 /* Block retrieving statistics during EEH error 3013 * recovery. Otherwise, the recovery might fail 3014 * and the PCI device will be removed permanently 3015 */ 3016 spin_lock(&adapter->stats_lock); 3017 if (!netif_device_present(dev)) { 3018 spin_unlock(&adapter->stats_lock); 3019 return; 3020 } 3021 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 3022 &p->stats_base); 3023 spin_unlock(&adapter->stats_lock); 3024 3025 ns->tx_bytes = stats.tx_octets; 3026 ns->tx_packets = stats.tx_frames; 3027 ns->rx_bytes = stats.rx_octets; 3028 ns->rx_packets = stats.rx_frames; 3029 ns->multicast = stats.rx_mcast_frames; 3030 3031 /* detailed rx_errors */ 3032 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 3033 stats.rx_runt; 3034 ns->rx_over_errors = 0; 3035 ns->rx_crc_errors = stats.rx_fcs_err; 3036 ns->rx_frame_errors = stats.rx_symbol_err; 3037 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 3038 stats.rx_ovflow2 + stats.rx_ovflow3 + 3039 stats.rx_trunc0 + stats.rx_trunc1 + 3040 stats.rx_trunc2 + stats.rx_trunc3; 3041 ns->rx_missed_errors = 0; 3042 3043 /* detailed tx_errors */ 3044 ns->tx_aborted_errors = 0; 3045 ns->tx_carrier_errors = 0; 3046 ns->tx_fifo_errors = 0; 3047 ns->tx_heartbeat_errors = 0; 3048 ns->tx_window_errors = 0; 3049 3050 ns->tx_errors = stats.tx_error_frames; 3051 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 3052 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 3053} 3054 3055static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 3056{ 3057 unsigned int mbox; 3058 int ret = 0, prtad, devad; 3059 struct port_info *pi = netdev_priv(dev); 3060 struct adapter *adapter = pi->adapter; 3061 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 3062 3063 switch (cmd) { 3064 case SIOCGMIIPHY: 3065 if (pi->mdio_addr < 0) 3066 return -EOPNOTSUPP; 3067 data->phy_id = pi->mdio_addr; 3068 break; 3069 case SIOCGMIIREG: 3070 case SIOCSMIIREG: 3071 if (mdio_phy_id_is_c45(data->phy_id)) { 3072 prtad = mdio_phy_id_prtad(data->phy_id); 3073 devad = mdio_phy_id_devad(data->phy_id); 3074 } else if (data->phy_id < 32) { 3075 prtad = data->phy_id; 3076 devad = 0; 3077 data->reg_num &= 0x1f; 3078 } else 3079 return -EINVAL; 3080 3081 mbox = pi->adapter->pf; 3082 if (cmd == SIOCGMIIREG) 3083 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 3084 data->reg_num, &data->val_out); 3085 else 3086 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 3087 data->reg_num, data->val_in); 3088 break; 3089 case SIOCGHWTSTAMP: 3090 return copy_to_user(req->ifr_data, &pi->tstamp_config, 3091 sizeof(pi->tstamp_config)) ? 3092 -EFAULT : 0; 3093 case SIOCSHWTSTAMP: 3094 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 3095 sizeof(pi->tstamp_config))) 3096 return -EFAULT; 3097 3098 if (!is_t4(adapter->params.chip)) { 3099 switch (pi->tstamp_config.tx_type) { 3100 case HWTSTAMP_TX_OFF: 3101 case HWTSTAMP_TX_ON: 3102 break; 3103 default: 3104 return -ERANGE; 3105 } 3106 3107 switch (pi->tstamp_config.rx_filter) { 3108 case HWTSTAMP_FILTER_NONE: 3109 pi->rxtstamp = false; 3110 break; 3111 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3112 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3113 cxgb4_ptprx_timestamping(pi, pi->port_id, 3114 PTP_TS_L4); 3115 break; 3116 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3117 cxgb4_ptprx_timestamping(pi, pi->port_id, 3118 PTP_TS_L2_L4); 3119 break; 3120 case HWTSTAMP_FILTER_ALL: 3121 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3122 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3123 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3124 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3125 pi->rxtstamp = true; 3126 break; 3127 default: 3128 pi->tstamp_config.rx_filter = 3129 HWTSTAMP_FILTER_NONE; 3130 return -ERANGE; 3131 } 3132 3133 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 3134 (pi->tstamp_config.rx_filter == 3135 HWTSTAMP_FILTER_NONE)) { 3136 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 3137 pi->ptp_enable = false; 3138 } 3139 3140 if (pi->tstamp_config.rx_filter != 3141 HWTSTAMP_FILTER_NONE) { 3142 if (cxgb4_ptp_redirect_rx_packet(adapter, 3143 pi) >= 0) 3144 pi->ptp_enable = true; 3145 } 3146 } else { 3147 /* For T4 Adapters */ 3148 switch (pi->tstamp_config.rx_filter) { 3149 case HWTSTAMP_FILTER_NONE: 3150 pi->rxtstamp = false; 3151 break; 3152 case HWTSTAMP_FILTER_ALL: 3153 pi->rxtstamp = true; 3154 break; 3155 default: 3156 pi->tstamp_config.rx_filter = 3157 HWTSTAMP_FILTER_NONE; 3158 return -ERANGE; 3159 } 3160 } 3161 return copy_to_user(req->ifr_data, &pi->tstamp_config, 3162 sizeof(pi->tstamp_config)) ? 3163 -EFAULT : 0; 3164 default: 3165 return -EOPNOTSUPP; 3166 } 3167 return ret; 3168} 3169 3170static void cxgb_set_rxmode(struct net_device *dev) 3171{ 3172 /* unfortunately we can't return errors to the stack */ 3173 set_rxmode(dev, -1, false); 3174} 3175 3176static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 3177{ 3178 struct port_info *pi = netdev_priv(dev); 3179 int ret; 3180 3181 ret = t4_set_rxmode(pi->adapter, pi->adapter->mbox, pi->viid, 3182 pi->viid_mirror, new_mtu, -1, -1, -1, -1, true); 3183 if (!ret) 3184 dev->mtu = new_mtu; 3185 return ret; 3186} 3187 3188#ifdef CONFIG_PCI_IOV 3189static int cxgb4_mgmt_open(struct net_device *dev) 3190{ 3191 /* Turn carrier off since we don't have to transmit anything on this 3192 * interface. 3193 */ 3194 netif_carrier_off(dev); 3195 return 0; 3196} 3197 3198/* Fill MAC address that will be assigned by the FW */ 3199static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap) 3200{ 3201 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 3202 unsigned int i, vf, nvfs; 3203 u16 a, b; 3204 int err; 3205 u8 *na; 3206 3207 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev, 3208 PCI_CAP_ID_VPD); 3209 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 3210 if (err) 3211 return; 3212 3213 na = adap->params.vpd.na; 3214 for (i = 0; i < ETH_ALEN; i++) 3215 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 3216 hex2val(na[2 * i + 1])); 3217 3218 a = (hw_addr[0] << 8) | hw_addr[1]; 3219 b = (hw_addr[1] << 8) | hw_addr[2]; 3220 a ^= b; 3221 a |= 0x0200; /* locally assigned Ethernet MAC address */ 3222 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 3223 macaddr[0] = a >> 8; 3224 macaddr[1] = a & 0xff; 3225 3226 for (i = 2; i < 5; i++) 3227 macaddr[i] = hw_addr[i + 1]; 3228 3229 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev); 3230 vf < nvfs; vf++) { 3231 macaddr[5] = adap->pf * nvfs + vf; 3232 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr); 3233 } 3234} 3235 3236static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 3237{ 3238 struct port_info *pi = netdev_priv(dev); 3239 struct adapter *adap = pi->adapter; 3240 int ret; 3241 3242 /* verify MAC addr is valid */ 3243 if (!is_valid_ether_addr(mac)) { 3244 dev_err(pi->adapter->pdev_dev, 3245 "Invalid Ethernet address %pM for VF %d\n", 3246 mac, vf); 3247 return -EINVAL; 3248 } 3249 3250 dev_info(pi->adapter->pdev_dev, 3251 "Setting MAC %pM on VF %d\n", mac, vf); 3252 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 3253 if (!ret) 3254 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 3255 return ret; 3256} 3257 3258static int cxgb4_mgmt_get_vf_config(struct net_device *dev, 3259 int vf, struct ifla_vf_info *ivi) 3260{ 3261 struct port_info *pi = netdev_priv(dev); 3262 struct adapter *adap = pi->adapter; 3263 struct vf_info *vfinfo; 3264 3265 if (vf >= adap->num_vfs) 3266 return -EINVAL; 3267 vfinfo = &adap->vfinfo[vf]; 3268 3269 ivi->vf = vf; 3270 ivi->max_tx_rate = vfinfo->tx_rate; 3271 ivi->min_tx_rate = 0; 3272 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr); 3273 ivi->vlan = vfinfo->vlan; 3274 ivi->linkstate = vfinfo->link_state; 3275 return 0; 3276} 3277 3278static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev, 3279 struct netdev_phys_item_id *ppid) 3280{ 3281 struct port_info *pi = netdev_priv(dev); 3282 unsigned int phy_port_id; 3283 3284 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 3285 ppid->id_len = sizeof(phy_port_id); 3286 memcpy(ppid->id, &phy_port_id, ppid->id_len); 3287 return 0; 3288} 3289 3290static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf, 3291 int min_tx_rate, int max_tx_rate) 3292{ 3293 struct port_info *pi = netdev_priv(dev); 3294 struct adapter *adap = pi->adapter; 3295 unsigned int link_ok, speed, mtu; 3296 u32 fw_pfvf, fw_class; 3297 int class_id = vf; 3298 int ret; 3299 u16 pktsize; 3300 3301 if (vf >= adap->num_vfs) 3302 return -EINVAL; 3303 3304 if (min_tx_rate) { 3305 dev_err(adap->pdev_dev, 3306 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 3307 min_tx_rate, vf); 3308 return -EINVAL; 3309 } 3310 3311 if (max_tx_rate == 0) { 3312 /* unbind VF to to any Traffic Class */ 3313 fw_pfvf = 3314 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 3315 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 3316 fw_class = 0xffffffff; 3317 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 3318 &fw_pfvf, &fw_class); 3319 if (ret) { 3320 dev_err(adap->pdev_dev, 3321 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n", 3322 ret, adap->pf, vf); 3323 return -EINVAL; 3324 } 3325 dev_info(adap->pdev_dev, 3326 "PF %d VF %d is unbound from TX Rate Limiting\n", 3327 adap->pf, vf); 3328 adap->vfinfo[vf].tx_rate = 0; 3329 return 0; 3330 } 3331 3332 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 3333 if (ret != FW_SUCCESS) { 3334 dev_err(adap->pdev_dev, 3335 "Failed to get link information for VF %d\n", vf); 3336 return -EINVAL; 3337 } 3338 3339 if (!link_ok) { 3340 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 3341 return -EINVAL; 3342 } 3343 3344 if (max_tx_rate > speed) { 3345 dev_err(adap->pdev_dev, 3346 "Max tx rate %d for VF %d can't be > link-speed %u", 3347 max_tx_rate, vf, speed); 3348 return -EINVAL; 3349 } 3350 3351 pktsize = mtu; 3352 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 3353 pktsize = pktsize - sizeof(struct ethhdr) - 4; 3354 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 3355 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 3356 /* configure Traffic Class for rate-limiting */ 3357 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 3358 SCHED_CLASS_LEVEL_CL_RL, 3359 SCHED_CLASS_MODE_CLASS, 3360 SCHED_CLASS_RATEUNIT_BITS, 3361 SCHED_CLASS_RATEMODE_ABS, 3362 pi->tx_chan, class_id, 0, 3363 max_tx_rate * 1000, 0, pktsize, 0); 3364 if (ret) { 3365 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 3366 ret); 3367 return -EINVAL; 3368 } 3369 dev_info(adap->pdev_dev, 3370 "Class %d with MSS %u configured with rate %u\n", 3371 class_id, pktsize, max_tx_rate); 3372 3373 /* bind VF to configured Traffic Class */ 3374 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 3375 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 3376 fw_class = class_id; 3377 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 3378 &fw_class); 3379 if (ret) { 3380 dev_err(adap->pdev_dev, 3381 "Err %d in binding PF %d VF %d to Traffic Class %d\n", 3382 ret, adap->pf, vf, class_id); 3383 return -EINVAL; 3384 } 3385 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 3386 adap->pf, vf, class_id); 3387 adap->vfinfo[vf].tx_rate = max_tx_rate; 3388 return 0; 3389} 3390 3391static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf, 3392 u16 vlan, u8 qos, __be16 vlan_proto) 3393{ 3394 struct port_info *pi = netdev_priv(dev); 3395 struct adapter *adap = pi->adapter; 3396 int ret; 3397 3398 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7) 3399 return -EINVAL; 3400 3401 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0) 3402 return -EPROTONOSUPPORT; 3403 3404 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan); 3405 if (!ret) { 3406 adap->vfinfo[vf].vlan = vlan; 3407 return 0; 3408 } 3409 3410 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n", 3411 ret, (vlan ? "setting" : "clearing"), adap->pf, vf); 3412 return ret; 3413} 3414 3415static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf, 3416 int link) 3417{ 3418 struct port_info *pi = netdev_priv(dev); 3419 struct adapter *adap = pi->adapter; 3420 u32 param, val; 3421 int ret = 0; 3422 3423 if (vf >= adap->num_vfs) 3424 return -EINVAL; 3425 3426 switch (link) { 3427 case IFLA_VF_LINK_STATE_AUTO: 3428 val = FW_VF_LINK_STATE_AUTO; 3429 break; 3430 3431 case IFLA_VF_LINK_STATE_ENABLE: 3432 val = FW_VF_LINK_STATE_ENABLE; 3433 break; 3434 3435 case IFLA_VF_LINK_STATE_DISABLE: 3436 val = FW_VF_LINK_STATE_DISABLE; 3437 break; 3438 3439 default: 3440 return -EINVAL; 3441 } 3442 3443 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 3444 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE)); 3445 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 3446 ¶m, &val); 3447 if (ret) { 3448 dev_err(adap->pdev_dev, 3449 "Error %d in setting PF %d VF %d link state\n", 3450 ret, adap->pf, vf); 3451 return -EINVAL; 3452 } 3453 3454 adap->vfinfo[vf].link_state = link; 3455 return ret; 3456} 3457#endif /* CONFIG_PCI_IOV */ 3458 3459static int cxgb_set_mac_addr(struct net_device *dev, void *p) 3460{ 3461 int ret; 3462 struct sockaddr *addr = p; 3463 struct port_info *pi = netdev_priv(dev); 3464 3465 if (!is_valid_ether_addr(addr->sa_data)) 3466 return -EADDRNOTAVAIL; 3467 3468 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt, 3469 addr->sa_data, true, &pi->smt_idx); 3470 if (ret < 0) 3471 return ret; 3472 3473 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3474 return 0; 3475} 3476 3477#ifdef CONFIG_NET_POLL_CONTROLLER 3478static void cxgb_netpoll(struct net_device *dev) 3479{ 3480 struct port_info *pi = netdev_priv(dev); 3481 struct adapter *adap = pi->adapter; 3482 3483 if (adap->flags & CXGB4_USING_MSIX) { 3484 int i; 3485 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 3486 3487 for (i = pi->nqsets; i; i--, rx++) 3488 t4_sge_intr_msix(0, &rx->rspq); 3489 } else 3490 t4_intr_handler(adap)(0, adap); 3491} 3492#endif 3493 3494static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 3495{ 3496 struct port_info *pi = netdev_priv(dev); 3497 struct adapter *adap = pi->adapter; 3498 struct ch_sched_queue qe = { 0 }; 3499 struct ch_sched_params p = { 0 }; 3500 struct sched_class *e; 3501 u32 req_rate; 3502 int err = 0; 3503 3504 if (!can_sched(dev)) 3505 return -ENOTSUPP; 3506 3507 if (index < 0 || index > pi->nqsets - 1) 3508 return -EINVAL; 3509 3510 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3511 dev_err(adap->pdev_dev, 3512 "Failed to rate limit on queue %d. Link Down?\n", 3513 index); 3514 return -EINVAL; 3515 } 3516 3517 qe.queue = index; 3518 e = cxgb4_sched_queue_lookup(dev, &qe); 3519 if (e && e->info.u.params.level != SCHED_CLASS_LEVEL_CL_RL) { 3520 dev_err(adap->pdev_dev, 3521 "Queue %u already bound to class %u of type: %u\n", 3522 index, e->idx, e->info.u.params.level); 3523 return -EBUSY; 3524 } 3525 3526 /* Convert from Mbps to Kbps */ 3527 req_rate = rate * 1000; 3528 3529 /* Max rate is 100 Gbps */ 3530 if (req_rate > SCHED_MAX_RATE_KBPS) { 3531 dev_err(adap->pdev_dev, 3532 "Invalid rate %u Mbps, Max rate is %u Mbps\n", 3533 rate, SCHED_MAX_RATE_KBPS / 1000); 3534 return -ERANGE; 3535 } 3536 3537 /* First unbind the queue from any existing class */ 3538 memset(&qe, 0, sizeof(qe)); 3539 qe.queue = index; 3540 qe.class = SCHED_CLS_NONE; 3541 3542 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 3543 if (err) { 3544 dev_err(adap->pdev_dev, 3545 "Unbinding Queue %d on port %d fail. Err: %d\n", 3546 index, pi->port_id, err); 3547 return err; 3548 } 3549 3550 /* Queue already unbound */ 3551 if (!req_rate) 3552 return 0; 3553 3554 /* Fetch any available unused or matching scheduling class */ 3555 p.type = SCHED_CLASS_TYPE_PACKET; 3556 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 3557 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 3558 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 3559 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 3560 p.u.params.channel = pi->tx_chan; 3561 p.u.params.class = SCHED_CLS_NONE; 3562 p.u.params.minrate = 0; 3563 p.u.params.maxrate = req_rate; 3564 p.u.params.weight = 0; 3565 p.u.params.pktsize = dev->mtu; 3566 3567 e = cxgb4_sched_class_alloc(dev, &p); 3568 if (!e) 3569 return -ENOMEM; 3570 3571 /* Bind the queue to a scheduling class */ 3572 memset(&qe, 0, sizeof(qe)); 3573 qe.queue = index; 3574 qe.class = e->idx; 3575 3576 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 3577 if (err) 3578 dev_err(adap->pdev_dev, 3579 "Queue rate limiting failed. Err: %d\n", err); 3580 return err; 3581} 3582 3583static int cxgb_setup_tc_flower(struct net_device *dev, 3584 struct flow_cls_offload *cls_flower) 3585{ 3586 switch (cls_flower->command) { 3587 case FLOW_CLS_REPLACE: 3588 return cxgb4_tc_flower_replace(dev, cls_flower); 3589 case FLOW_CLS_DESTROY: 3590 return cxgb4_tc_flower_destroy(dev, cls_flower); 3591 case FLOW_CLS_STATS: 3592 return cxgb4_tc_flower_stats(dev, cls_flower); 3593 default: 3594 return -EOPNOTSUPP; 3595 } 3596} 3597 3598static int cxgb_setup_tc_cls_u32(struct net_device *dev, 3599 struct tc_cls_u32_offload *cls_u32) 3600{ 3601 switch (cls_u32->command) { 3602 case TC_CLSU32_NEW_KNODE: 3603 case TC_CLSU32_REPLACE_KNODE: 3604 return cxgb4_config_knode(dev, cls_u32); 3605 case TC_CLSU32_DELETE_KNODE: 3606 return cxgb4_delete_knode(dev, cls_u32); 3607 default: 3608 return -EOPNOTSUPP; 3609 } 3610} 3611 3612static int cxgb_setup_tc_matchall(struct net_device *dev, 3613 struct tc_cls_matchall_offload *cls_matchall, 3614 bool ingress) 3615{ 3616 struct adapter *adap = netdev2adap(dev); 3617 3618 if (!adap->tc_matchall) 3619 return -ENOMEM; 3620 3621 switch (cls_matchall->command) { 3622 case TC_CLSMATCHALL_REPLACE: 3623 return cxgb4_tc_matchall_replace(dev, cls_matchall, ingress); 3624 case TC_CLSMATCHALL_DESTROY: 3625 return cxgb4_tc_matchall_destroy(dev, cls_matchall, ingress); 3626 case TC_CLSMATCHALL_STATS: 3627 if (ingress) 3628 return cxgb4_tc_matchall_stats(dev, cls_matchall); 3629 break; 3630 default: 3631 break; 3632 } 3633 3634 return -EOPNOTSUPP; 3635} 3636 3637static int cxgb_setup_tc_block_ingress_cb(enum tc_setup_type type, 3638 void *type_data, void *cb_priv) 3639{ 3640 struct net_device *dev = cb_priv; 3641 struct port_info *pi = netdev2pinfo(dev); 3642 struct adapter *adap = netdev2adap(dev); 3643 3644 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3645 dev_err(adap->pdev_dev, 3646 "Failed to setup tc on port %d. Link Down?\n", 3647 pi->port_id); 3648 return -EINVAL; 3649 } 3650 3651 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 3652 return -EOPNOTSUPP; 3653 3654 switch (type) { 3655 case TC_SETUP_CLSU32: 3656 return cxgb_setup_tc_cls_u32(dev, type_data); 3657 case TC_SETUP_CLSFLOWER: 3658 return cxgb_setup_tc_flower(dev, type_data); 3659 case TC_SETUP_CLSMATCHALL: 3660 return cxgb_setup_tc_matchall(dev, type_data, true); 3661 default: 3662 return -EOPNOTSUPP; 3663 } 3664} 3665 3666static int cxgb_setup_tc_block_egress_cb(enum tc_setup_type type, 3667 void *type_data, void *cb_priv) 3668{ 3669 struct net_device *dev = cb_priv; 3670 struct port_info *pi = netdev2pinfo(dev); 3671 struct adapter *adap = netdev2adap(dev); 3672 3673 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3674 dev_err(adap->pdev_dev, 3675 "Failed to setup tc on port %d. Link Down?\n", 3676 pi->port_id); 3677 return -EINVAL; 3678 } 3679 3680 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 3681 return -EOPNOTSUPP; 3682 3683 switch (type) { 3684 case TC_SETUP_CLSMATCHALL: 3685 return cxgb_setup_tc_matchall(dev, type_data, false); 3686 default: 3687 break; 3688 } 3689 3690 return -EOPNOTSUPP; 3691} 3692 3693static int cxgb_setup_tc_mqprio(struct net_device *dev, 3694 struct tc_mqprio_qopt_offload *mqprio) 3695{ 3696 struct adapter *adap = netdev2adap(dev); 3697 3698 if (!is_ethofld(adap) || !adap->tc_mqprio) 3699 return -ENOMEM; 3700 3701 return cxgb4_setup_tc_mqprio(dev, mqprio); 3702} 3703 3704static LIST_HEAD(cxgb_block_cb_list); 3705 3706static int cxgb_setup_tc_block(struct net_device *dev, 3707 struct flow_block_offload *f) 3708{ 3709 struct port_info *pi = netdev_priv(dev); 3710 flow_setup_cb_t *cb; 3711 bool ingress_only; 3712 3713 pi->tc_block_shared = f->block_shared; 3714 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 3715 cb = cxgb_setup_tc_block_egress_cb; 3716 ingress_only = false; 3717 } else { 3718 cb = cxgb_setup_tc_block_ingress_cb; 3719 ingress_only = true; 3720 } 3721 3722 return flow_block_cb_setup_simple(f, &cxgb_block_cb_list, 3723 cb, pi, dev, ingress_only); 3724} 3725 3726static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 3727 void *type_data) 3728{ 3729 switch (type) { 3730 case TC_SETUP_QDISC_MQPRIO: 3731 return cxgb_setup_tc_mqprio(dev, type_data); 3732 case TC_SETUP_BLOCK: 3733 return cxgb_setup_tc_block(dev, type_data); 3734 default: 3735 return -EOPNOTSUPP; 3736 } 3737} 3738 3739static int cxgb_udp_tunnel_unset_port(struct net_device *netdev, 3740 unsigned int table, unsigned int entry, 3741 struct udp_tunnel_info *ti) 3742{ 3743 struct port_info *pi = netdev_priv(netdev); 3744 struct adapter *adapter = pi->adapter; 3745 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3746 int ret = 0, i; 3747 3748 switch (ti->type) { 3749 case UDP_TUNNEL_TYPE_VXLAN: 3750 adapter->vxlan_port = 0; 3751 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0); 3752 break; 3753 case UDP_TUNNEL_TYPE_GENEVE: 3754 adapter->geneve_port = 0; 3755 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0); 3756 break; 3757 default: 3758 return -EINVAL; 3759 } 3760 3761 /* Matchall mac entries can be deleted only after all tunnel ports 3762 * are brought down or removed. 3763 */ 3764 if (!adapter->rawf_cnt) 3765 return 0; 3766 for_each_port(adapter, i) { 3767 pi = adap2pinfo(adapter, i); 3768 ret = t4_free_raw_mac_filt(adapter, pi->viid, 3769 match_all_mac, match_all_mac, 3770 adapter->rawf_start + pi->port_id, 3771 1, pi->port_id, false); 3772 if (ret < 0) { 3773 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n", 3774 i); 3775 return ret; 3776 } 3777 } 3778 3779 return 0; 3780} 3781 3782static int cxgb_udp_tunnel_set_port(struct net_device *netdev, 3783 unsigned int table, unsigned int entry, 3784 struct udp_tunnel_info *ti) 3785{ 3786 struct port_info *pi = netdev_priv(netdev); 3787 struct adapter *adapter = pi->adapter; 3788 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3789 int i, ret; 3790 3791 switch (ti->type) { 3792 case UDP_TUNNEL_TYPE_VXLAN: 3793 adapter->vxlan_port = ti->port; 3794 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 3795 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F); 3796 break; 3797 case UDP_TUNNEL_TYPE_GENEVE: 3798 adapter->geneve_port = ti->port; 3799 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 3800 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F); 3801 break; 3802 default: 3803 return -EINVAL; 3804 } 3805 3806 /* Create a 'match all' mac filter entry for inner mac, 3807 * if raw mac interface is supported. Once the linux kernel provides 3808 * driver entry points for adding/deleting the inner mac addresses, 3809 * we will remove this 'match all' entry and fallback to adding 3810 * exact match filters. 3811 */ 3812 for_each_port(adapter, i) { 3813 pi = adap2pinfo(adapter, i); 3814 3815 ret = t4_alloc_raw_mac_filt(adapter, pi->viid, 3816 match_all_mac, 3817 match_all_mac, 3818 adapter->rawf_start + pi->port_id, 3819 1, pi->port_id, false); 3820 if (ret < 0) { 3821 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n", 3822 be16_to_cpu(ti->port)); 3823 return ret; 3824 } 3825 } 3826 3827 return 0; 3828} 3829 3830static const struct udp_tunnel_nic_info cxgb_udp_tunnels = { 3831 .set_port = cxgb_udp_tunnel_set_port, 3832 .unset_port = cxgb_udp_tunnel_unset_port, 3833 .tables = { 3834 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 3835 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 3836 }, 3837}; 3838 3839static netdev_features_t cxgb_features_check(struct sk_buff *skb, 3840 struct net_device *dev, 3841 netdev_features_t features) 3842{ 3843 struct port_info *pi = netdev_priv(dev); 3844 struct adapter *adapter = pi->adapter; 3845 3846 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3847 return features; 3848 3849 /* Check if hw supports offload for this packet */ 3850 if (!skb->encapsulation || cxgb_encap_offload_supported(skb)) 3851 return features; 3852 3853 /* Offload is not supported for this encapsulated packet */ 3854 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3855} 3856 3857static netdev_features_t cxgb_fix_features(struct net_device *dev, 3858 netdev_features_t features) 3859{ 3860 /* Disable GRO, if RX_CSUM is disabled */ 3861 if (!(features & NETIF_F_RXCSUM)) 3862 features &= ~NETIF_F_GRO; 3863 3864 return features; 3865} 3866 3867static const struct net_device_ops cxgb4_netdev_ops = { 3868 .ndo_open = cxgb_open, 3869 .ndo_stop = cxgb_close, 3870 .ndo_start_xmit = t4_start_xmit, 3871 .ndo_select_queue = cxgb_select_queue, 3872 .ndo_get_stats64 = cxgb_get_stats, 3873 .ndo_set_rx_mode = cxgb_set_rxmode, 3874 .ndo_set_mac_address = cxgb_set_mac_addr, 3875 .ndo_set_features = cxgb_set_features, 3876 .ndo_validate_addr = eth_validate_addr, 3877 .ndo_do_ioctl = cxgb_ioctl, 3878 .ndo_change_mtu = cxgb_change_mtu, 3879#ifdef CONFIG_NET_POLL_CONTROLLER 3880 .ndo_poll_controller = cxgb_netpoll, 3881#endif 3882#ifdef CONFIG_CHELSIO_T4_FCOE 3883 .ndo_fcoe_enable = cxgb_fcoe_enable, 3884 .ndo_fcoe_disable = cxgb_fcoe_disable, 3885#endif /* CONFIG_CHELSIO_T4_FCOE */ 3886 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 3887 .ndo_setup_tc = cxgb_setup_tc, 3888 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, 3889 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, 3890 .ndo_features_check = cxgb_features_check, 3891 .ndo_fix_features = cxgb_fix_features, 3892}; 3893 3894#ifdef CONFIG_PCI_IOV 3895static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 3896 .ndo_open = cxgb4_mgmt_open, 3897 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac, 3898 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config, 3899 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate, 3900 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id, 3901 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan, 3902 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state, 3903}; 3904#endif 3905 3906static void cxgb4_mgmt_get_drvinfo(struct net_device *dev, 3907 struct ethtool_drvinfo *info) 3908{ 3909 struct adapter *adapter = netdev2adap(dev); 3910 3911 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 3912 strlcpy(info->bus_info, pci_name(adapter->pdev), 3913 sizeof(info->bus_info)); 3914} 3915 3916static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 3917 .get_drvinfo = cxgb4_mgmt_get_drvinfo, 3918}; 3919 3920static void notify_fatal_err(struct work_struct *work) 3921{ 3922 struct adapter *adap; 3923 3924 adap = container_of(work, struct adapter, fatal_err_notify_task); 3925 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR); 3926} 3927 3928void t4_fatal_err(struct adapter *adap) 3929{ 3930 int port; 3931 3932 if (pci_channel_offline(adap->pdev)) 3933 return; 3934 3935 /* Disable the SGE since ULDs are going to free resources that 3936 * could be exposed to the adapter. RDMA MWs for example... 3937 */ 3938 t4_shutdown_adapter(adap); 3939 for_each_port(adap, port) { 3940 struct net_device *dev = adap->port[port]; 3941 3942 /* If we get here in very early initialization the network 3943 * devices may not have been set up yet. 3944 */ 3945 if (!dev) 3946 continue; 3947 3948 netif_tx_stop_all_queues(dev); 3949 netif_carrier_off(dev); 3950 } 3951 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3952 queue_work(adap->workq, &adap->fatal_err_notify_task); 3953} 3954 3955static void setup_memwin(struct adapter *adap) 3956{ 3957 u32 nic_win_base = t4_get_util_window(adap); 3958 3959 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3960} 3961 3962static void setup_memwin_rdma(struct adapter *adap) 3963{ 3964 if (adap->vres.ocq.size) { 3965 u32 start; 3966 unsigned int sz_kb; 3967 3968 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3969 start &= PCI_BASE_ADDRESS_MEM_MASK; 3970 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3971 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3972 t4_write_reg(adap, 3973 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3974 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3975 t4_write_reg(adap, 3976 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3977 adap->vres.ocq.start); 3978 t4_read_reg(adap, 3979 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3980 } 3981} 3982 3983/* HMA Definitions */ 3984 3985/* The maximum number of address that can be send in a single FW cmd */ 3986#define HMA_MAX_ADDR_IN_CMD 5 3987 3988#define HMA_PAGE_SIZE PAGE_SIZE 3989 3990#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */ 3991 3992#define HMA_PAGE_ORDER \ 3993 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \ 3994 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0) 3995 3996/* The minimum and maximum possible HMA sizes that can be specified in the FW 3997 * configuration(in units of MB). 3998 */ 3999#define HMA_MIN_TOTAL_SIZE 1 4000#define HMA_MAX_TOTAL_SIZE \ 4001 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \ 4002 HMA_MAX_NO_FW_ADDRESS) >> 20) 4003 4004static void adap_free_hma_mem(struct adapter *adapter) 4005{ 4006 struct scatterlist *iter; 4007 struct page *page; 4008 int i; 4009 4010 if (!adapter->hma.sgt) 4011 return; 4012 4013 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) { 4014 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl, 4015 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL); 4016 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG; 4017 } 4018 4019 for_each_sg(adapter->hma.sgt->sgl, iter, 4020 adapter->hma.sgt->orig_nents, i) { 4021 page = sg_page(iter); 4022 if (page) 4023 __free_pages(page, HMA_PAGE_ORDER); 4024 } 4025 4026 kfree(adapter->hma.phy_addr); 4027 sg_free_table(adapter->hma.sgt); 4028 kfree(adapter->hma.sgt); 4029 adapter->hma.sgt = NULL; 4030} 4031 4032static int adap_config_hma(struct adapter *adapter) 4033{ 4034 struct scatterlist *sgl, *iter; 4035 struct sg_table *sgt; 4036 struct page *newpage; 4037 unsigned int i, j, k; 4038 u32 param, hma_size; 4039 unsigned int ncmds; 4040 size_t page_size; 4041 u32 page_order; 4042 int node, ret; 4043 4044 /* HMA is supported only for T6+ cards. 4045 * Avoid initializing HMA in kdump kernels. 4046 */ 4047 if (is_kdump_kernel() || 4048 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 4049 return 0; 4050 4051 /* Get the HMA region size required by fw */ 4052 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4053 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE)); 4054 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 4055 1, ¶m, &hma_size); 4056 /* An error means card has its own memory or HMA is not supported by 4057 * the firmware. Return without any errors. 4058 */ 4059 if (ret || !hma_size) 4060 return 0; 4061 4062 if (hma_size < HMA_MIN_TOTAL_SIZE || 4063 hma_size > HMA_MAX_TOTAL_SIZE) { 4064 dev_err(adapter->pdev_dev, 4065 "HMA size %uMB beyond bounds(%u-%lu)MB\n", 4066 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE); 4067 return -EINVAL; 4068 } 4069 4070 page_size = HMA_PAGE_SIZE; 4071 page_order = HMA_PAGE_ORDER; 4072 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL); 4073 if (unlikely(!adapter->hma.sgt)) { 4074 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n"); 4075 return -ENOMEM; 4076 } 4077 sgt = adapter->hma.sgt; 4078 /* FW returned value will be in MB's 4079 */ 4080 sgt->orig_nents = (hma_size << 20) / (page_size << page_order); 4081 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) { 4082 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n"); 4083 kfree(adapter->hma.sgt); 4084 adapter->hma.sgt = NULL; 4085 return -ENOMEM; 4086 } 4087 4088 sgl = adapter->hma.sgt->sgl; 4089 node = dev_to_node(adapter->pdev_dev); 4090 for_each_sg(sgl, iter, sgt->orig_nents, i) { 4091 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL | 4092 __GFP_ZERO, page_order); 4093 if (!newpage) { 4094 dev_err(adapter->pdev_dev, 4095 "Not enough memory for HMA page allocation\n"); 4096 ret = -ENOMEM; 4097 goto free_hma; 4098 } 4099 sg_set_page(iter, newpage, page_size << page_order, 0); 4100 } 4101 4102 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents, 4103 DMA_BIDIRECTIONAL); 4104 if (!sgt->nents) { 4105 dev_err(adapter->pdev_dev, 4106 "Not enough memory for HMA DMA mapping"); 4107 ret = -ENOMEM; 4108 goto free_hma; 4109 } 4110 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG; 4111 4112 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t), 4113 GFP_KERNEL); 4114 if (unlikely(!adapter->hma.phy_addr)) 4115 goto free_hma; 4116 4117 for_each_sg(sgl, iter, sgt->nents, i) { 4118 newpage = sg_page(iter); 4119 adapter->hma.phy_addr[i] = sg_dma_address(iter); 4120 } 4121 4122 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD); 4123 /* Pass on the addresses to firmware */ 4124 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { 4125 struct fw_hma_cmd hma_cmd; 4126 u8 naddr = HMA_MAX_ADDR_IN_CMD; 4127 u8 soc = 0, eoc = 0; 4128 u8 hma_mode = 1; /* Presently we support only Page table mode */ 4129 4130 soc = (i == 0) ? 1 : 0; 4131 eoc = (i == ncmds - 1) ? 1 : 0; 4132 4133 /* For last cmd, set naddr corresponding to remaining 4134 * addresses 4135 */ 4136 if (i == ncmds - 1) { 4137 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD; 4138 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD; 4139 } 4140 memset(&hma_cmd, 0, sizeof(hma_cmd)); 4141 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) | 4142 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 4143 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd)); 4144 4145 hma_cmd.mode_to_pcie_params = 4146 htonl(FW_HMA_CMD_MODE_V(hma_mode) | 4147 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc)); 4148 4149 /* HMA cmd size specified in MB's */ 4150 hma_cmd.naddr_size = 4151 htonl(FW_HMA_CMD_SIZE_V(hma_size) | 4152 FW_HMA_CMD_NADDR_V(naddr)); 4153 4154 /* Total Page size specified in units of 4K */ 4155 hma_cmd.addr_size_pkd = 4156 htonl(FW_HMA_CMD_ADDR_SIZE_V 4157 ((page_size << page_order) >> 12)); 4158 4159 /* Fill the 5 addresses */ 4160 for (j = 0; j < naddr; j++) { 4161 hma_cmd.phy_address[j] = 4162 cpu_to_be64(adapter->hma.phy_addr[j + k]); 4163 } 4164 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd, 4165 sizeof(hma_cmd), &hma_cmd); 4166 if (ret) { 4167 dev_err(adapter->pdev_dev, 4168 "HMA FW command failed with err %d\n", ret); 4169 goto free_hma; 4170 } 4171 } 4172 4173 if (!ret) 4174 dev_info(adapter->pdev_dev, 4175 "Reserved %uMB host memory for HMA\n", hma_size); 4176 return ret; 4177 4178free_hma: 4179 adap_free_hma_mem(adapter); 4180 return ret; 4181} 4182 4183static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 4184{ 4185 u32 v; 4186 int ret; 4187 4188 /* Now that we've successfully configured and initialized the adapter 4189 * can ask the Firmware what resources it has provisioned for us. 4190 */ 4191 ret = t4_get_pfres(adap); 4192 if (ret) { 4193 dev_err(adap->pdev_dev, 4194 "Unable to retrieve resource provisioning information\n"); 4195 return ret; 4196 } 4197 4198 /* get device capabilities */ 4199 memset(c, 0, sizeof(*c)); 4200 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4201 FW_CMD_REQUEST_F | FW_CMD_READ_F); 4202 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 4203 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 4204 if (ret < 0) 4205 return ret; 4206 4207 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4208 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 4209 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 4210 if (ret < 0) 4211 return ret; 4212 4213 ret = t4_config_glbl_rss(adap, adap->pf, 4214 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 4215 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 4216 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 4217 if (ret < 0) 4218 return ret; 4219 4220 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 4221 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 4222 FW_CMD_CAP_PF); 4223 if (ret < 0) 4224 return ret; 4225 4226 t4_sge_init(adap); 4227 4228 /* tweak some settings */ 4229 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 4230 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 4231 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 4232 v = t4_read_reg(adap, TP_PIO_DATA_A); 4233 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 4234 4235 /* first 4 Tx modulation queues point to consecutive Tx channels */ 4236 adap->params.tp.tx_modq_map = 0xE4; 4237 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 4238 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 4239 4240 /* associate each Tx modulation queue with consecutive Tx channels */ 4241 v = 0x84218421; 4242 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4243 &v, 1, TP_TX_SCHED_HDR_A); 4244 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4245 &v, 1, TP_TX_SCHED_FIFO_A); 4246 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4247 &v, 1, TP_TX_SCHED_PCMD_A); 4248 4249#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 4250 if (is_offload(adap)) { 4251 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 4252 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4253 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4254 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4255 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 4256 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 4257 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4258 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4259 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4260 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 4261 } 4262 4263 /* get basic stuff going */ 4264 return t4_early_init(adap, adap->pf); 4265} 4266 4267/* 4268 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 4269 */ 4270#define MAX_ATIDS 8192U 4271 4272/* 4273 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 4274 * 4275 * If the firmware we're dealing with has Configuration File support, then 4276 * we use that to perform all configuration 4277 */ 4278 4279/* 4280 * Tweak configuration based on module parameters, etc. Most of these have 4281 * defaults assigned to them by Firmware Configuration Files (if we're using 4282 * them) but need to be explicitly set if we're using hard-coded 4283 * initialization. But even in the case of using Firmware Configuration 4284 * Files, we'd like to expose the ability to change these via module 4285 * parameters so these are essentially common tweaks/settings for 4286 * Configuration Files and hard-coded initialization ... 4287 */ 4288static int adap_init0_tweaks(struct adapter *adapter) 4289{ 4290 /* 4291 * Fix up various Host-Dependent Parameters like Page Size, Cache 4292 * Line Size, etc. The firmware default is for a 4KB Page Size and 4293 * 64B Cache Line Size ... 4294 */ 4295 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 4296 4297 /* 4298 * Process module parameters which affect early initialization. 4299 */ 4300 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 4301 dev_err(&adapter->pdev->dev, 4302 "Ignoring illegal rx_dma_offset=%d, using 2\n", 4303 rx_dma_offset); 4304 rx_dma_offset = 2; 4305 } 4306 t4_set_reg_field(adapter, SGE_CONTROL_A, 4307 PKTSHIFT_V(PKTSHIFT_M), 4308 PKTSHIFT_V(rx_dma_offset)); 4309 4310 /* 4311 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 4312 * adds the pseudo header itself. 4313 */ 4314 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 4315 CSUM_HAS_PSEUDO_HDR_F, 0); 4316 4317 return 0; 4318} 4319 4320/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 4321 * unto themselves and they contain their own firmware to perform their 4322 * tasks ... 4323 */ 4324static int phy_aq1202_version(const u8 *phy_fw_data, 4325 size_t phy_fw_size) 4326{ 4327 int offset; 4328 4329 /* At offset 0x8 you're looking for the primary image's 4330 * starting offset which is 3 Bytes wide 4331 * 4332 * At offset 0xa of the primary image, you look for the offset 4333 * of the DRAM segment which is 3 Bytes wide. 4334 * 4335 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 4336 * wide 4337 */ 4338 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 4339 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 4340 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 4341 4342 offset = le24(phy_fw_data + 0x8) << 12; 4343 offset = le24(phy_fw_data + offset + 0xa); 4344 return be16(phy_fw_data + offset + 0x27e); 4345 4346 #undef be16 4347 #undef le16 4348 #undef le24 4349} 4350 4351static struct info_10gbt_phy_fw { 4352 unsigned int phy_fw_id; /* PCI Device ID */ 4353 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 4354 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 4355 int phy_flash; /* Has FLASH for PHY Firmware */ 4356} phy_info_array[] = { 4357 { 4358 PHY_AQ1202_DEVICEID, 4359 PHY_AQ1202_FIRMWARE, 4360 phy_aq1202_version, 4361 1, 4362 }, 4363 { 4364 PHY_BCM84834_DEVICEID, 4365 PHY_BCM84834_FIRMWARE, 4366 NULL, 4367 0, 4368 }, 4369 { 0, NULL, NULL }, 4370}; 4371 4372static struct info_10gbt_phy_fw *find_phy_info(int devid) 4373{ 4374 int i; 4375 4376 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 4377 if (phy_info_array[i].phy_fw_id == devid) 4378 return &phy_info_array[i]; 4379 } 4380 return NULL; 4381} 4382 4383/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 4384 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 4385 * we return a negative error number. If we transfer new firmware we return 1 4386 * (from t4_load_phy_fw()). If we don't do anything we return 0. 4387 */ 4388static int adap_init0_phy(struct adapter *adap) 4389{ 4390 const struct firmware *phyf; 4391 int ret; 4392 struct info_10gbt_phy_fw *phy_info; 4393 4394 /* Use the device ID to determine which PHY file to flash. 4395 */ 4396 phy_info = find_phy_info(adap->pdev->device); 4397 if (!phy_info) { 4398 dev_warn(adap->pdev_dev, 4399 "No PHY Firmware file found for this PHY\n"); 4400 return -EOPNOTSUPP; 4401 } 4402 4403 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 4404 * use that. The adapter firmware provides us with a memory buffer 4405 * where we can load a PHY firmware file from the host if we want to 4406 * override the PHY firmware File in flash. 4407 */ 4408 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 4409 adap->pdev_dev); 4410 if (ret < 0) { 4411 /* For adapters without FLASH attached to PHY for their 4412 * firmware, it's obviously a fatal error if we can't get the 4413 * firmware to the adapter. For adapters with PHY firmware 4414 * FLASH storage, it's worth a warning if we can't find the 4415 * PHY Firmware but we'll neuter the error ... 4416 */ 4417 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 4418 "/lib/firmware/%s, error %d\n", 4419 phy_info->phy_fw_file, -ret); 4420 if (phy_info->phy_flash) { 4421 int cur_phy_fw_ver = 0; 4422 4423 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 4424 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 4425 "FLASH copy, version %#x\n", cur_phy_fw_ver); 4426 ret = 0; 4427 } 4428 4429 return ret; 4430 } 4431 4432 /* Load PHY Firmware onto adapter. 4433 */ 4434 ret = t4_load_phy_fw(adap, MEMWIN_NIC, phy_info->phy_fw_version, 4435 (u8 *)phyf->data, phyf->size); 4436 if (ret < 0) 4437 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 4438 -ret); 4439 else if (ret > 0) { 4440 int new_phy_fw_ver = 0; 4441 4442 if (phy_info->phy_fw_version) 4443 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 4444 phyf->size); 4445 dev_info(adap->pdev_dev, "Successfully transferred PHY " 4446 "Firmware /lib/firmware/%s, version %#x\n", 4447 phy_info->phy_fw_file, new_phy_fw_ver); 4448 } 4449 4450 release_firmware(phyf); 4451 4452 return ret; 4453} 4454 4455/* 4456 * Attempt to initialize the adapter via a Firmware Configuration File. 4457 */ 4458static int adap_init0_config(struct adapter *adapter, int reset) 4459{ 4460 char *fw_config_file, fw_config_file_path[256]; 4461 u32 finiver, finicsum, cfcsum, param, val; 4462 struct fw_caps_config_cmd caps_cmd; 4463 unsigned long mtype = 0, maddr = 0; 4464 const struct firmware *cf; 4465 char *config_name = NULL; 4466 int config_issued = 0; 4467 int ret; 4468 4469 /* 4470 * Reset device if necessary. 4471 */ 4472 if (reset) { 4473 ret = t4_fw_reset(adapter, adapter->mbox, 4474 PIORSTMODE_F | PIORST_F); 4475 if (ret < 0) 4476 goto bye; 4477 } 4478 4479 /* If this is a 10Gb/s-BT adapter make sure the chip-external 4480 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 4481 * to be performed after any global adapter RESET above since some 4482 * PHYs only have local RAM copies of the PHY firmware. 4483 */ 4484 if (is_10gbt_device(adapter->pdev->device)) { 4485 ret = adap_init0_phy(adapter); 4486 if (ret < 0) 4487 goto bye; 4488 } 4489 /* 4490 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 4491 * then use that. Otherwise, use the configuration file stored 4492 * in the adapter flash ... 4493 */ 4494 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 4495 case CHELSIO_T4: 4496 fw_config_file = FW4_CFNAME; 4497 break; 4498 case CHELSIO_T5: 4499 fw_config_file = FW5_CFNAME; 4500 break; 4501 case CHELSIO_T6: 4502 fw_config_file = FW6_CFNAME; 4503 break; 4504 default: 4505 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 4506 adapter->pdev->device); 4507 ret = -EINVAL; 4508 goto bye; 4509 } 4510 4511 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 4512 if (ret < 0) { 4513 config_name = "On FLASH"; 4514 mtype = FW_MEMTYPE_CF_FLASH; 4515 maddr = t4_flash_cfg_addr(adapter); 4516 } else { 4517 u32 params[7], val[7]; 4518 4519 sprintf(fw_config_file_path, 4520 "/lib/firmware/%s", fw_config_file); 4521 config_name = fw_config_file_path; 4522 4523 if (cf->size >= FLASH_CFG_MAX_SIZE) 4524 ret = -ENOMEM; 4525 else { 4526 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4527 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4528 ret = t4_query_params(adapter, adapter->mbox, 4529 adapter->pf, 0, 1, params, val); 4530 if (ret == 0) { 4531 /* 4532 * For t4_memory_rw() below addresses and 4533 * sizes have to be in terms of multiples of 4 4534 * bytes. So, if the Configuration File isn't 4535 * a multiple of 4 bytes in length we'll have 4536 * to write that out separately since we can't 4537 * guarantee that the bytes following the 4538 * residual byte in the buffer returned by 4539 * request_firmware() are zeroed out ... 4540 */ 4541 size_t resid = cf->size & 0x3; 4542 size_t size = cf->size & ~0x3; 4543 __be32 *data = (__be32 *)cf->data; 4544 4545 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 4546 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 4547 4548 spin_lock(&adapter->win0_lock); 4549 ret = t4_memory_rw(adapter, 0, mtype, maddr, 4550 size, data, T4_MEMORY_WRITE); 4551 if (ret == 0 && resid != 0) { 4552 union { 4553 __be32 word; 4554 char buf[4]; 4555 } last; 4556 int i; 4557 4558 last.word = data[size >> 2]; 4559 for (i = resid; i < 4; i++) 4560 last.buf[i] = 0; 4561 ret = t4_memory_rw(adapter, 0, mtype, 4562 maddr + size, 4563 4, &last.word, 4564 T4_MEMORY_WRITE); 4565 } 4566 spin_unlock(&adapter->win0_lock); 4567 } 4568 } 4569 4570 release_firmware(cf); 4571 if (ret) 4572 goto bye; 4573 } 4574 4575 val = 0; 4576 4577 /* Ofld + Hash filter is supported. Older fw will fail this request and 4578 * it is fine. 4579 */ 4580 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4581 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD)); 4582 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 4583 1, ¶m, &val); 4584 4585 /* FW doesn't know about Hash filter + ofld support, 4586 * it's not a problem, don't return an error. 4587 */ 4588 if (ret < 0) { 4589 dev_warn(adapter->pdev_dev, 4590 "Hash filter with ofld is not supported by FW\n"); 4591 } 4592 4593 /* 4594 * Issue a Capability Configuration command to the firmware to get it 4595 * to parse the Configuration File. We don't use t4_fw_config_file() 4596 * because we want the ability to modify various features after we've 4597 * processed the configuration file ... 4598 */ 4599 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4600 caps_cmd.op_to_write = 4601 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4602 FW_CMD_REQUEST_F | 4603 FW_CMD_READ_F); 4604 caps_cmd.cfvalid_to_len16 = 4605 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 4606 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 4607 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 4608 FW_LEN16(caps_cmd)); 4609 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4610 &caps_cmd); 4611 4612 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 4613 * Configuration File in FLASH), our last gasp effort is to use the 4614 * Firmware Configuration File which is embedded in the firmware. A 4615 * very few early versions of the firmware didn't have one embedded 4616 * but we can ignore those. 4617 */ 4618 if (ret == -ENOENT) { 4619 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4620 caps_cmd.op_to_write = 4621 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4622 FW_CMD_REQUEST_F | 4623 FW_CMD_READ_F); 4624 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4625 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 4626 sizeof(caps_cmd), &caps_cmd); 4627 config_name = "Firmware Default"; 4628 } 4629 4630 config_issued = 1; 4631 if (ret < 0) 4632 goto bye; 4633 4634 finiver = ntohl(caps_cmd.finiver); 4635 finicsum = ntohl(caps_cmd.finicsum); 4636 cfcsum = ntohl(caps_cmd.cfcsum); 4637 if (finicsum != cfcsum) 4638 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 4639 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 4640 finicsum, cfcsum); 4641 4642 /* 4643 * And now tell the firmware to use the configuration we just loaded. 4644 */ 4645 caps_cmd.op_to_write = 4646 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4647 FW_CMD_REQUEST_F | 4648 FW_CMD_WRITE_F); 4649 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4650 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4651 NULL); 4652 if (ret < 0) 4653 goto bye; 4654 4655 /* 4656 * Tweak configuration based on system architecture, module 4657 * parameters, etc. 4658 */ 4659 ret = adap_init0_tweaks(adapter); 4660 if (ret < 0) 4661 goto bye; 4662 4663 /* We will proceed even if HMA init fails. */ 4664 ret = adap_config_hma(adapter); 4665 if (ret) 4666 dev_err(adapter->pdev_dev, 4667 "HMA configuration failed with error %d\n", ret); 4668 4669 if (is_t6(adapter->params.chip)) { 4670 adap_config_hpfilter(adapter); 4671 ret = setup_ppod_edram(adapter); 4672 if (!ret) 4673 dev_info(adapter->pdev_dev, "Successfully enabled " 4674 "ppod edram feature\n"); 4675 } 4676 4677 /* 4678 * And finally tell the firmware to initialize itself using the 4679 * parameters from the Configuration File. 4680 */ 4681 ret = t4_fw_initialize(adapter, adapter->mbox); 4682 if (ret < 0) 4683 goto bye; 4684 4685 /* Emit Firmware Configuration File information and return 4686 * successfully. 4687 */ 4688 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 4689 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 4690 config_name, finiver, cfcsum); 4691 return 0; 4692 4693 /* 4694 * Something bad happened. Return the error ... (If the "error" 4695 * is that there's no Configuration File on the adapter we don't 4696 * want to issue a warning since this is fairly common.) 4697 */ 4698bye: 4699 if (config_issued && ret != -ENOENT) 4700 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 4701 config_name, -ret); 4702 return ret; 4703} 4704 4705static struct fw_info fw_info_array[] = { 4706 { 4707 .chip = CHELSIO_T4, 4708 .fs_name = FW4_CFNAME, 4709 .fw_mod_name = FW4_FNAME, 4710 .fw_hdr = { 4711 .chip = FW_HDR_CHIP_T4, 4712 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 4713 .intfver_nic = FW_INTFVER(T4, NIC), 4714 .intfver_vnic = FW_INTFVER(T4, VNIC), 4715 .intfver_ri = FW_INTFVER(T4, RI), 4716 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4717 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4718 }, 4719 }, { 4720 .chip = CHELSIO_T5, 4721 .fs_name = FW5_CFNAME, 4722 .fw_mod_name = FW5_FNAME, 4723 .fw_hdr = { 4724 .chip = FW_HDR_CHIP_T5, 4725 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 4726 .intfver_nic = FW_INTFVER(T5, NIC), 4727 .intfver_vnic = FW_INTFVER(T5, VNIC), 4728 .intfver_ri = FW_INTFVER(T5, RI), 4729 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4730 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4731 }, 4732 }, { 4733 .chip = CHELSIO_T6, 4734 .fs_name = FW6_CFNAME, 4735 .fw_mod_name = FW6_FNAME, 4736 .fw_hdr = { 4737 .chip = FW_HDR_CHIP_T6, 4738 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 4739 .intfver_nic = FW_INTFVER(T6, NIC), 4740 .intfver_vnic = FW_INTFVER(T6, VNIC), 4741 .intfver_ofld = FW_INTFVER(T6, OFLD), 4742 .intfver_ri = FW_INTFVER(T6, RI), 4743 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4744 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4745 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4746 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4747 }, 4748 } 4749 4750}; 4751 4752static struct fw_info *find_fw_info(int chip) 4753{ 4754 int i; 4755 4756 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 4757 if (fw_info_array[i].chip == chip) 4758 return &fw_info_array[i]; 4759 } 4760 return NULL; 4761} 4762 4763/* 4764 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 4765 */ 4766static int adap_init0(struct adapter *adap, int vpd_skip) 4767{ 4768 struct fw_caps_config_cmd caps_cmd; 4769 u32 params[7], val[7]; 4770 enum dev_state state; 4771 u32 v, port_vec; 4772 int reset = 1; 4773 int ret; 4774 4775 /* Grab Firmware Device Log parameters as early as possible so we have 4776 * access to it for debugging, etc. 4777 */ 4778 ret = t4_init_devlog_params(adap); 4779 if (ret < 0) 4780 return ret; 4781 4782 /* Contact FW, advertising Master capability */ 4783 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 4784 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 4785 if (ret < 0) { 4786 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 4787 ret); 4788 return ret; 4789 } 4790 if (ret == adap->mbox) 4791 adap->flags |= CXGB4_MASTER_PF; 4792 4793 /* 4794 * If we're the Master PF Driver and the device is uninitialized, 4795 * then let's consider upgrading the firmware ... (We always want 4796 * to check the firmware version number in order to A. get it for 4797 * later reporting and B. to warn if the currently loaded firmware 4798 * is excessively mismatched relative to the driver.) 4799 */ 4800 4801 t4_get_version_info(adap); 4802 ret = t4_check_fw_version(adap); 4803 /* If firmware is too old (not supported by driver) force an update. */ 4804 if (ret) 4805 state = DEV_STATE_UNINIT; 4806 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) { 4807 struct fw_info *fw_info; 4808 struct fw_hdr *card_fw; 4809 const struct firmware *fw; 4810 const u8 *fw_data = NULL; 4811 unsigned int fw_size = 0; 4812 4813 /* This is the firmware whose headers the driver was compiled 4814 * against 4815 */ 4816 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 4817 if (fw_info == NULL) { 4818 dev_err(adap->pdev_dev, 4819 "unable to get firmware info for chip %d.\n", 4820 CHELSIO_CHIP_VERSION(adap->params.chip)); 4821 return -EINVAL; 4822 } 4823 4824 /* allocate memory to read the header of the firmware on the 4825 * card 4826 */ 4827 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 4828 if (!card_fw) { 4829 ret = -ENOMEM; 4830 goto bye; 4831 } 4832 4833 /* Get FW from from /lib/firmware/ */ 4834 ret = request_firmware(&fw, fw_info->fw_mod_name, 4835 adap->pdev_dev); 4836 if (ret < 0) { 4837 dev_err(adap->pdev_dev, 4838 "unable to load firmware image %s, error %d\n", 4839 fw_info->fw_mod_name, ret); 4840 } else { 4841 fw_data = fw->data; 4842 fw_size = fw->size; 4843 } 4844 4845 /* upgrade FW logic */ 4846 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 4847 state, &reset); 4848 4849 /* Cleaning up */ 4850 release_firmware(fw); 4851 kvfree(card_fw); 4852 4853 if (ret < 0) 4854 goto bye; 4855 } 4856 4857 /* If the firmware is initialized already, emit a simply note to that 4858 * effect. Otherwise, it's time to try initializing the adapter. 4859 */ 4860 if (state == DEV_STATE_INIT) { 4861 ret = adap_config_hma(adap); 4862 if (ret) 4863 dev_err(adap->pdev_dev, 4864 "HMA configuration failed with error %d\n", 4865 ret); 4866 dev_info(adap->pdev_dev, "Coming up as %s: "\ 4867 "Adapter already initialized\n", 4868 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE"); 4869 } else { 4870 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 4871 "Initializing adapter\n"); 4872 4873 /* Find out whether we're dealing with a version of the 4874 * firmware which has configuration file support. 4875 */ 4876 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4877 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4878 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 4879 params, val); 4880 4881 /* If the firmware doesn't support Configuration Files, 4882 * return an error. 4883 */ 4884 if (ret < 0) { 4885 dev_err(adap->pdev_dev, "firmware doesn't support " 4886 "Firmware Configuration Files\n"); 4887 goto bye; 4888 } 4889 4890 /* The firmware provides us with a memory buffer where we can 4891 * load a Configuration File from the host if we want to 4892 * override the Configuration File in flash. 4893 */ 4894 ret = adap_init0_config(adap, reset); 4895 if (ret == -ENOENT) { 4896 dev_err(adap->pdev_dev, "no Configuration File " 4897 "present on adapter.\n"); 4898 goto bye; 4899 } 4900 if (ret < 0) { 4901 dev_err(adap->pdev_dev, "could not initialize " 4902 "adapter, error %d\n", -ret); 4903 goto bye; 4904 } 4905 } 4906 4907 /* Now that we've successfully configured and initialized the adapter 4908 * (or found it already initialized), we can ask the Firmware what 4909 * resources it has provisioned for us. 4910 */ 4911 ret = t4_get_pfres(adap); 4912 if (ret) { 4913 dev_err(adap->pdev_dev, 4914 "Unable to retrieve resource provisioning information\n"); 4915 goto bye; 4916 } 4917 4918 /* Grab VPD parameters. This should be done after we establish a 4919 * connection to the firmware since some of the VPD parameters 4920 * (notably the Core Clock frequency) are retrieved via requests to 4921 * the firmware. On the other hand, we need these fairly early on 4922 * so we do this right after getting ahold of the firmware. 4923 * 4924 * We need to do this after initializing the adapter because someone 4925 * could have FLASHed a new VPD which won't be read by the firmware 4926 * until we do the RESET ... 4927 */ 4928 if (!vpd_skip) { 4929 ret = t4_get_vpd_params(adap, &adap->params.vpd); 4930 if (ret < 0) 4931 goto bye; 4932 } 4933 4934 /* Find out what ports are available to us. Note that we need to do 4935 * this before calling adap_init0_no_config() since it needs nports 4936 * and portvec ... 4937 */ 4938 v = 4939 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4940 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 4941 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 4942 if (ret < 0) 4943 goto bye; 4944 4945 adap->params.nports = hweight32(port_vec); 4946 adap->params.portvec = port_vec; 4947 4948 /* Give the SGE code a chance to pull in anything that it needs ... 4949 * Note that this must be called after we retrieve our VPD parameters 4950 * in order to know how to convert core ticks to seconds, etc. 4951 */ 4952 ret = t4_sge_init(adap); 4953 if (ret < 0) 4954 goto bye; 4955 4956 /* Grab the SGE Doorbell Queue Timer values. If successful, that 4957 * indicates that the Firmware and Hardware support this. 4958 */ 4959 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4960 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK)); 4961 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4962 1, params, val); 4963 4964 if (!ret) { 4965 adap->sge.dbqtimer_tick = val[0]; 4966 ret = t4_read_sge_dbqtimers(adap, 4967 ARRAY_SIZE(adap->sge.dbqtimer_val), 4968 adap->sge.dbqtimer_val); 4969 } 4970 4971 if (!ret) 4972 adap->flags |= CXGB4_SGE_DBQ_TIMER; 4973 4974 if (is_bypass_device(adap->pdev->device)) 4975 adap->params.bypass = 1; 4976 4977 /* 4978 * Grab some of our basic fundamental operating parameters. 4979 */ 4980 params[0] = FW_PARAM_PFVF(EQ_START); 4981 params[1] = FW_PARAM_PFVF(L2T_START); 4982 params[2] = FW_PARAM_PFVF(L2T_END); 4983 params[3] = FW_PARAM_PFVF(FILTER_START); 4984 params[4] = FW_PARAM_PFVF(FILTER_END); 4985 params[5] = FW_PARAM_PFVF(IQFLINT_START); 4986 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 4987 if (ret < 0) 4988 goto bye; 4989 adap->sge.egr_start = val[0]; 4990 adap->l2t_start = val[1]; 4991 adap->l2t_end = val[2]; 4992 adap->tids.ftid_base = val[3]; 4993 adap->tids.nftids = val[4] - val[3] + 1; 4994 adap->sge.ingr_start = val[5]; 4995 4996 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 4997 params[0] = FW_PARAM_PFVF(HPFILTER_START); 4998 params[1] = FW_PARAM_PFVF(HPFILTER_END); 4999 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5000 params, val); 5001 if (ret < 0) 5002 goto bye; 5003 5004 adap->tids.hpftid_base = val[0]; 5005 adap->tids.nhpftids = val[1] - val[0] + 1; 5006 5007 /* Read the raw mps entries. In T6, the last 2 tcam entries 5008 * are reserved for raw mac addresses (rawf = 2, one per port). 5009 */ 5010 params[0] = FW_PARAM_PFVF(RAWF_START); 5011 params[1] = FW_PARAM_PFVF(RAWF_END); 5012 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5013 params, val); 5014 if (ret == 0) { 5015 adap->rawf_start = val[0]; 5016 adap->rawf_cnt = val[1] - val[0] + 1; 5017 } 5018 5019 adap->tids.tid_base = 5020 t4_read_reg(adap, LE_DB_ACTIVE_TABLE_START_INDEX_A); 5021 } 5022 5023 /* qids (ingress/egress) returned from firmware can be anywhere 5024 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 5025 * Hence driver needs to allocate memory for this range to 5026 * store the queue info. Get the highest IQFLINT/EQ index returned 5027 * in FW_EQ_*_CMD.alloc command. 5028 */ 5029 params[0] = FW_PARAM_PFVF(EQ_END); 5030 params[1] = FW_PARAM_PFVF(IQFLINT_END); 5031 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 5032 if (ret < 0) 5033 goto bye; 5034 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 5035 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 5036 5037 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 5038 sizeof(*adap->sge.egr_map), GFP_KERNEL); 5039 if (!adap->sge.egr_map) { 5040 ret = -ENOMEM; 5041 goto bye; 5042 } 5043 5044 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 5045 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 5046 if (!adap->sge.ingr_map) { 5047 ret = -ENOMEM; 5048 goto bye; 5049 } 5050 5051 /* Allocate the memory for the vaious egress queue bitmaps 5052 * ie starving_fl, txq_maperr and blocked_fl. 5053 */ 5054 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 5055 sizeof(long), GFP_KERNEL); 5056 if (!adap->sge.starving_fl) { 5057 ret = -ENOMEM; 5058 goto bye; 5059 } 5060 5061 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 5062 sizeof(long), GFP_KERNEL); 5063 if (!adap->sge.txq_maperr) { 5064 ret = -ENOMEM; 5065 goto bye; 5066 } 5067 5068#ifdef CONFIG_DEBUG_FS 5069 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 5070 sizeof(long), GFP_KERNEL); 5071 if (!adap->sge.blocked_fl) { 5072 ret = -ENOMEM; 5073 goto bye; 5074 } 5075 bitmap_zero(adap->sge.blocked_fl, adap->sge.egr_sz); 5076#endif 5077 5078 params[0] = FW_PARAM_PFVF(CLIP_START); 5079 params[1] = FW_PARAM_PFVF(CLIP_END); 5080 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 5081 if (ret < 0) 5082 goto bye; 5083 adap->clipt_start = val[0]; 5084 adap->clipt_end = val[1]; 5085 5086 /* Get the supported number of traffic classes */ 5087 params[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5088 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 5089 if (ret < 0) { 5090 /* We couldn't retrieve the number of Traffic Classes 5091 * supported by the hardware/firmware. So we hard 5092 * code it here. 5093 */ 5094 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 5095 } else { 5096 adap->params.nsched_cls = val[0]; 5097 } 5098 5099 /* query params related to active filter region */ 5100 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 5101 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 5102 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 5103 /* If Active filter size is set we enable establishing 5104 * offload connection through firmware work request 5105 */ 5106 if ((val[0] != val[1]) && (ret >= 0)) { 5107 adap->flags |= CXGB4_FW_OFLD_CONN; 5108 adap->tids.aftid_base = val[0]; 5109 adap->tids.aftid_end = val[1]; 5110 } 5111 5112 /* If we're running on newer firmware, let it know that we're 5113 * prepared to deal with encapsulated CPL messages. Older 5114 * firmware won't understand this and we'll just get 5115 * unencapsulated messages ... 5116 */ 5117 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5118 val[0] = 1; 5119 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 5120 5121 /* 5122 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 5123 * capability. Earlier versions of the firmware didn't have the 5124 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 5125 * permission to use ULPTX MEMWRITE DSGL. 5126 */ 5127 if (is_t4(adap->params.chip)) { 5128 adap->params.ulptx_memwrite_dsgl = false; 5129 } else { 5130 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5131 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5132 1, params, val); 5133 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 5134 } 5135 5136 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 5137 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5138 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5139 1, params, val); 5140 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 5141 5142 /* See if FW supports FW_FILTER2 work request */ 5143 if (is_t4(adap->params.chip)) { 5144 adap->params.filter2_wr_support = 0; 5145 } else { 5146 params[0] = FW_PARAM_DEV(FILTER2_WR); 5147 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5148 1, params, val); 5149 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 5150 } 5151 5152 /* Check if FW supports returning vin and smt index. 5153 * If this is not supported, driver will interpret 5154 * these values from viid. 5155 */ 5156 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5157 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5158 1, params, val); 5159 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); 5160 5161 /* 5162 * Get device capabilities so we can determine what resources we need 5163 * to manage. 5164 */ 5165 memset(&caps_cmd, 0, sizeof(caps_cmd)); 5166 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 5167 FW_CMD_REQUEST_F | FW_CMD_READ_F); 5168 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 5169 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 5170 &caps_cmd); 5171 if (ret < 0) 5172 goto bye; 5173 5174 /* hash filter has some mandatory register settings to be tested and for 5175 * that it needs to test whether offload is enabled or not, hence 5176 * checking and setting it here. 5177 */ 5178 if (caps_cmd.ofldcaps) 5179 adap->params.offload = 1; 5180 5181 if (caps_cmd.ofldcaps || 5182 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) || 5183 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD))) { 5184 /* query offload-related parameters */ 5185 params[0] = FW_PARAM_DEV(NTID); 5186 params[1] = FW_PARAM_PFVF(SERVER_START); 5187 params[2] = FW_PARAM_PFVF(SERVER_END); 5188 params[3] = FW_PARAM_PFVF(TDDP_START); 5189 params[4] = FW_PARAM_PFVF(TDDP_END); 5190 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5191 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 5192 params, val); 5193 if (ret < 0) 5194 goto bye; 5195 adap->tids.ntids = val[0]; 5196 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 5197 adap->tids.stid_base = val[1]; 5198 adap->tids.nstids = val[2] - val[1] + 1; 5199 /* 5200 * Setup server filter region. Divide the available filter 5201 * region into two parts. Regular filters get 1/3rd and server 5202 * filters get 2/3rd part. This is only enabled if workarond 5203 * path is enabled. 5204 * 1. For regular filters. 5205 * 2. Server filter: This are special filters which are used 5206 * to redirect SYN packets to offload queue. 5207 */ 5208 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) { 5209 adap->tids.sftid_base = adap->tids.ftid_base + 5210 DIV_ROUND_UP(adap->tids.nftids, 3); 5211 adap->tids.nsftids = adap->tids.nftids - 5212 DIV_ROUND_UP(adap->tids.nftids, 3); 5213 adap->tids.nftids = adap->tids.sftid_base - 5214 adap->tids.ftid_base; 5215 } 5216 adap->vres.ddp.start = val[3]; 5217 adap->vres.ddp.size = val[4] - val[3] + 1; 5218 adap->params.ofldq_wr_cred = val[5]; 5219 5220 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5221 init_hash_filter(adap); 5222 } else { 5223 adap->num_ofld_uld += 1; 5224 } 5225 5226 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD)) { 5227 params[0] = FW_PARAM_PFVF(ETHOFLD_START); 5228 params[1] = FW_PARAM_PFVF(ETHOFLD_END); 5229 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5230 params, val); 5231 if (!ret) { 5232 adap->tids.eotid_base = val[0]; 5233 adap->tids.neotids = min_t(u32, MAX_ATIDS, 5234 val[1] - val[0] + 1); 5235 adap->params.ethofld = 1; 5236 } 5237 } 5238 } 5239 if (caps_cmd.rdmacaps) { 5240 params[0] = FW_PARAM_PFVF(STAG_START); 5241 params[1] = FW_PARAM_PFVF(STAG_END); 5242 params[2] = FW_PARAM_PFVF(RQ_START); 5243 params[3] = FW_PARAM_PFVF(RQ_END); 5244 params[4] = FW_PARAM_PFVF(PBL_START); 5245 params[5] = FW_PARAM_PFVF(PBL_END); 5246 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 5247 params, val); 5248 if (ret < 0) 5249 goto bye; 5250 adap->vres.stag.start = val[0]; 5251 adap->vres.stag.size = val[1] - val[0] + 1; 5252 adap->vres.rq.start = val[2]; 5253 adap->vres.rq.size = val[3] - val[2] + 1; 5254 adap->vres.pbl.start = val[4]; 5255 adap->vres.pbl.size = val[5] - val[4] + 1; 5256 5257 params[0] = FW_PARAM_PFVF(SRQ_START); 5258 params[1] = FW_PARAM_PFVF(SRQ_END); 5259 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5260 params, val); 5261 if (!ret) { 5262 adap->vres.srq.start = val[0]; 5263 adap->vres.srq.size = val[1] - val[0] + 1; 5264 } 5265 if (adap->vres.srq.size) { 5266 adap->srq = t4_init_srq(adap->vres.srq.size); 5267 if (!adap->srq) 5268 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n"); 5269 } 5270 5271 params[0] = FW_PARAM_PFVF(SQRQ_START); 5272 params[1] = FW_PARAM_PFVF(SQRQ_END); 5273 params[2] = FW_PARAM_PFVF(CQ_START); 5274 params[3] = FW_PARAM_PFVF(CQ_END); 5275 params[4] = FW_PARAM_PFVF(OCQ_START); 5276 params[5] = FW_PARAM_PFVF(OCQ_END); 5277 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 5278 val); 5279 if (ret < 0) 5280 goto bye; 5281 adap->vres.qp.start = val[0]; 5282 adap->vres.qp.size = val[1] - val[0] + 1; 5283 adap->vres.cq.start = val[2]; 5284 adap->vres.cq.size = val[3] - val[2] + 1; 5285 adap->vres.ocq.start = val[4]; 5286 adap->vres.ocq.size = val[5] - val[4] + 1; 5287 5288 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 5289 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5290 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 5291 val); 5292 if (ret < 0) { 5293 adap->params.max_ordird_qp = 8; 5294 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 5295 ret = 0; 5296 } else { 5297 adap->params.max_ordird_qp = val[0]; 5298 adap->params.max_ird_adapter = val[1]; 5299 } 5300 dev_info(adap->pdev_dev, 5301 "max_ordird_qp %d max_ird_adapter %d\n", 5302 adap->params.max_ordird_qp, 5303 adap->params.max_ird_adapter); 5304 5305 /* Enable write_with_immediate if FW supports it */ 5306 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM); 5307 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 5308 val); 5309 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); 5310 5311 /* Enable write_cmpl if FW supports it */ 5312 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR); 5313 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 5314 val); 5315 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); 5316 adap->num_ofld_uld += 2; 5317 } 5318 if (caps_cmd.iscsicaps) { 5319 params[0] = FW_PARAM_PFVF(ISCSI_START); 5320 params[1] = FW_PARAM_PFVF(ISCSI_END); 5321 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5322 params, val); 5323 if (ret < 0) 5324 goto bye; 5325 adap->vres.iscsi.start = val[0]; 5326 adap->vres.iscsi.size = val[1] - val[0] + 1; 5327 if (is_t6(adap->params.chip)) { 5328 params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START); 5329 params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END); 5330 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5331 params, val); 5332 if (!ret) { 5333 adap->vres.ppod_edram.start = val[0]; 5334 adap->vres.ppod_edram.size = 5335 val[1] - val[0] + 1; 5336 5337 dev_info(adap->pdev_dev, 5338 "ppod edram start 0x%x end 0x%x size 0x%x\n", 5339 val[0], val[1], 5340 adap->vres.ppod_edram.size); 5341 } 5342 } 5343 /* LIO target and cxgb4i initiaitor */ 5344 adap->num_ofld_uld += 2; 5345 } 5346 if (caps_cmd.cryptocaps) { 5347 if (ntohs(caps_cmd.cryptocaps) & 5348 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) { 5349 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 5350 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5351 2, params, val); 5352 if (ret < 0) { 5353 if (ret != -EINVAL) 5354 goto bye; 5355 } else { 5356 adap->vres.ncrypto_fc = val[0]; 5357 } 5358 adap->num_ofld_uld += 1; 5359 } 5360 if (ntohs(caps_cmd.cryptocaps) & 5361 FW_CAPS_CONFIG_TLS_INLINE) { 5362 params[0] = FW_PARAM_PFVF(TLS_START); 5363 params[1] = FW_PARAM_PFVF(TLS_END); 5364 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5365 2, params, val); 5366 if (ret < 0) 5367 goto bye; 5368 adap->vres.key.start = val[0]; 5369 adap->vres.key.size = val[1] - val[0] + 1; 5370 adap->num_uld += 1; 5371 } 5372 adap->params.crypto = ntohs(caps_cmd.cryptocaps); 5373 } 5374 5375 /* The MTU/MSS Table is initialized by now, so load their values. If 5376 * we're initializing the adapter, then we'll make any modifications 5377 * we want to the MTU/MSS Table and also initialize the congestion 5378 * parameters. 5379 */ 5380 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 5381 if (state != DEV_STATE_INIT) { 5382 int i; 5383 5384 /* The default MTU Table contains values 1492 and 1500. 5385 * However, for TCP, it's better to have two values which are 5386 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 5387 * This allows us to have a TCP Data Payload which is a 5388 * multiple of 8 regardless of what combination of TCP Options 5389 * are in use (always a multiple of 4 bytes) which is 5390 * important for performance reasons. For instance, if no 5391 * options are in use, then we have a 20-byte IP header and a 5392 * 20-byte TCP header. In this case, a 1500-byte MSS would 5393 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 5394 * which is not a multiple of 8. So using an MSS of 1488 in 5395 * this case results in a TCP Data Payload of 1448 bytes which 5396 * is a multiple of 8. On the other hand, if 12-byte TCP Time 5397 * Stamps have been negotiated, then an MTU of 1500 bytes 5398 * results in a TCP Data Payload of 1448 bytes which, as 5399 * above, is a multiple of 8 bytes ... 5400 */ 5401 for (i = 0; i < NMTUS; i++) 5402 if (adap->params.mtus[i] == 1492) { 5403 adap->params.mtus[i] = 1488; 5404 break; 5405 } 5406 5407 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 5408 adap->params.b_wnd); 5409 } 5410 t4_init_sge_params(adap); 5411 adap->flags |= CXGB4_FW_OK; 5412 t4_init_tp_params(adap, true); 5413 return 0; 5414 5415 /* 5416 * Something bad happened. If a command timed out or failed with EIO 5417 * FW does not operate within its spec or something catastrophic 5418 * happened to HW/FW, stop issuing commands. 5419 */ 5420bye: 5421 adap_free_hma_mem(adap); 5422 kfree(adap->sge.egr_map); 5423 kfree(adap->sge.ingr_map); 5424 kfree(adap->sge.starving_fl); 5425 kfree(adap->sge.txq_maperr); 5426#ifdef CONFIG_DEBUG_FS 5427 kfree(adap->sge.blocked_fl); 5428#endif 5429 if (ret != -ETIMEDOUT && ret != -EIO) 5430 t4_fw_bye(adap, adap->mbox); 5431 return ret; 5432} 5433 5434/* EEH callbacks */ 5435 5436static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 5437 pci_channel_state_t state) 5438{ 5439 int i; 5440 struct adapter *adap = pci_get_drvdata(pdev); 5441 5442 if (!adap) 5443 goto out; 5444 5445 rtnl_lock(); 5446 adap->flags &= ~CXGB4_FW_OK; 5447 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 5448 spin_lock(&adap->stats_lock); 5449 for_each_port(adap, i) { 5450 struct net_device *dev = adap->port[i]; 5451 if (dev) { 5452 netif_device_detach(dev); 5453 netif_carrier_off(dev); 5454 } 5455 } 5456 spin_unlock(&adap->stats_lock); 5457 disable_interrupts(adap); 5458 if (adap->flags & CXGB4_FULL_INIT_DONE) 5459 cxgb_down(adap); 5460 rtnl_unlock(); 5461 if ((adap->flags & CXGB4_DEV_ENABLED)) { 5462 pci_disable_device(pdev); 5463 adap->flags &= ~CXGB4_DEV_ENABLED; 5464 } 5465out: return state == pci_channel_io_perm_failure ? 5466 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 5467} 5468 5469static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 5470{ 5471 int i, ret; 5472 struct fw_caps_config_cmd c; 5473 struct adapter *adap = pci_get_drvdata(pdev); 5474 5475 if (!adap) { 5476 pci_restore_state(pdev); 5477 pci_save_state(pdev); 5478 return PCI_ERS_RESULT_RECOVERED; 5479 } 5480 5481 if (!(adap->flags & CXGB4_DEV_ENABLED)) { 5482 if (pci_enable_device(pdev)) { 5483 dev_err(&pdev->dev, "Cannot reenable PCI " 5484 "device after reset\n"); 5485 return PCI_ERS_RESULT_DISCONNECT; 5486 } 5487 adap->flags |= CXGB4_DEV_ENABLED; 5488 } 5489 5490 pci_set_master(pdev); 5491 pci_restore_state(pdev); 5492 pci_save_state(pdev); 5493 5494 if (t4_wait_dev_ready(adap->regs) < 0) 5495 return PCI_ERS_RESULT_DISCONNECT; 5496 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 5497 return PCI_ERS_RESULT_DISCONNECT; 5498 adap->flags |= CXGB4_FW_OK; 5499 if (adap_init1(adap, &c)) 5500 return PCI_ERS_RESULT_DISCONNECT; 5501 5502 for_each_port(adap, i) { 5503 struct port_info *pi = adap2pinfo(adap, i); 5504 u8 vivld = 0, vin = 0; 5505 5506 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1, 5507 NULL, NULL, &vivld, &vin); 5508 if (ret < 0) 5509 return PCI_ERS_RESULT_DISCONNECT; 5510 pi->viid = ret; 5511 pi->xact_addr_filt = -1; 5512 /* If fw supports returning the VIN as part of FW_VI_CMD, 5513 * save the returned values. 5514 */ 5515 if (adap->params.viid_smt_extn_support) { 5516 pi->vivld = vivld; 5517 pi->vin = vin; 5518 } else { 5519 /* Retrieve the values from VIID */ 5520 pi->vivld = FW_VIID_VIVLD_G(pi->viid); 5521 pi->vin = FW_VIID_VIN_G(pi->viid); 5522 } 5523 } 5524 5525 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 5526 adap->params.b_wnd); 5527 setup_memwin(adap); 5528 if (cxgb_up(adap)) 5529 return PCI_ERS_RESULT_DISCONNECT; 5530 return PCI_ERS_RESULT_RECOVERED; 5531} 5532 5533static void eeh_resume(struct pci_dev *pdev) 5534{ 5535 int i; 5536 struct adapter *adap = pci_get_drvdata(pdev); 5537 5538 if (!adap) 5539 return; 5540 5541 rtnl_lock(); 5542 for_each_port(adap, i) { 5543 struct net_device *dev = adap->port[i]; 5544 if (dev) { 5545 if (netif_running(dev)) { 5546 link_start(dev); 5547 cxgb_set_rxmode(dev); 5548 } 5549 netif_device_attach(dev); 5550 } 5551 } 5552 rtnl_unlock(); 5553} 5554 5555static void eeh_reset_prepare(struct pci_dev *pdev) 5556{ 5557 struct adapter *adapter = pci_get_drvdata(pdev); 5558 int i; 5559 5560 if (adapter->pf != 4) 5561 return; 5562 5563 adapter->flags &= ~CXGB4_FW_OK; 5564 5565 notify_ulds(adapter, CXGB4_STATE_DOWN); 5566 5567 for_each_port(adapter, i) 5568 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5569 cxgb_close(adapter->port[i]); 5570 5571 disable_interrupts(adapter); 5572 cxgb4_free_mps_ref_entries(adapter); 5573 5574 adap_free_hma_mem(adapter); 5575 5576 if (adapter->flags & CXGB4_FULL_INIT_DONE) 5577 cxgb_down(adapter); 5578} 5579 5580static void eeh_reset_done(struct pci_dev *pdev) 5581{ 5582 struct adapter *adapter = pci_get_drvdata(pdev); 5583 int err, i; 5584 5585 if (adapter->pf != 4) 5586 return; 5587 5588 err = t4_wait_dev_ready(adapter->regs); 5589 if (err < 0) { 5590 dev_err(adapter->pdev_dev, 5591 "Device not ready, err %d", err); 5592 return; 5593 } 5594 5595 setup_memwin(adapter); 5596 5597 err = adap_init0(adapter, 1); 5598 if (err) { 5599 dev_err(adapter->pdev_dev, 5600 "Adapter init failed, err %d", err); 5601 return; 5602 } 5603 5604 setup_memwin_rdma(adapter); 5605 5606 if (adapter->flags & CXGB4_FW_OK) { 5607 err = t4_port_init(adapter, adapter->pf, adapter->pf, 0); 5608 if (err) { 5609 dev_err(adapter->pdev_dev, 5610 "Port init failed, err %d", err); 5611 return; 5612 } 5613 } 5614 5615 err = cfg_queues(adapter); 5616 if (err) { 5617 dev_err(adapter->pdev_dev, 5618 "Config queues failed, err %d", err); 5619 return; 5620 } 5621 5622 cxgb4_init_mps_ref_entries(adapter); 5623 5624 err = setup_fw_sge_queues(adapter); 5625 if (err) { 5626 dev_err(adapter->pdev_dev, 5627 "FW sge queue allocation failed, err %d", err); 5628 return; 5629 } 5630 5631 for_each_port(adapter, i) 5632 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5633 cxgb_open(adapter->port[i]); 5634} 5635 5636static const struct pci_error_handlers cxgb4_eeh = { 5637 .error_detected = eeh_err_detected, 5638 .slot_reset = eeh_slot_reset, 5639 .resume = eeh_resume, 5640 .reset_prepare = eeh_reset_prepare, 5641 .reset_done = eeh_reset_done, 5642}; 5643 5644/* Return true if the Link Configuration supports "High Speeds" (those greater 5645 * than 1Gb/s). 5646 */ 5647static inline bool is_x_10g_port(const struct link_config *lc) 5648{ 5649 unsigned int speeds, high_speeds; 5650 5651 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 5652 high_speeds = speeds & 5653 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 5654 5655 return high_speeds != 0; 5656} 5657 5658/* Perform default configuration of DMA queues depending on the number and type 5659 * of ports we found and the number of available CPUs. Most settings can be 5660 * modified by the admin prior to actual use. 5661 */ 5662static int cfg_queues(struct adapter *adap) 5663{ 5664 u32 avail_qsets, avail_eth_qsets, avail_uld_qsets; 5665 u32 ncpus = num_online_cpus(); 5666 u32 niqflint, neq, num_ulds; 5667 struct sge *s = &adap->sge; 5668 u32 i, n10g = 0, qidx = 0; 5669 u32 q10g = 0, q1g; 5670 5671 /* Reduce memory usage in kdump environment, disable all offload. */ 5672 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 5673 adap->params.offload = 0; 5674 adap->params.crypto = 0; 5675 adap->params.ethofld = 0; 5676 } 5677 5678 /* Calculate the number of Ethernet Queue Sets available based on 5679 * resources provisioned for us. We always have an Asynchronous 5680 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy 5681 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt 5682 * Ingress Queue. Meanwhile, we need two Egress Queues for each 5683 * Queue Set: one for the Free List and one for the Ethernet TX Queue. 5684 * 5685 * Note that we should also take into account all of the various 5686 * Offload Queues. But, in any situation where we're operating in 5687 * a Resource Constrained Provisioning environment, doing any Offload 5688 * at all is problematic ... 5689 */ 5690 niqflint = adap->params.pfres.niqflint - 1; 5691 if (!(adap->flags & CXGB4_USING_MSIX)) 5692 niqflint--; 5693 neq = adap->params.pfres.neq / 2; 5694 avail_qsets = min(niqflint, neq); 5695 5696 if (avail_qsets < adap->params.nports) { 5697 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n", 5698 avail_qsets, adap->params.nports); 5699 return -ENOMEM; 5700 } 5701 5702 /* Count the number of 10Gb/s or better ports */ 5703 for_each_port(adap, i) 5704 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 5705 5706 avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS); 5707 5708 /* We default to 1 queue per non-10G port and up to # of cores queues 5709 * per 10G port. 5710 */ 5711 if (n10g) 5712 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g; 5713 5714#ifdef CONFIG_CHELSIO_T4_DCB 5715 /* For Data Center Bridging support we need to be able to support up 5716 * to 8 Traffic Priorities; each of which will be assigned to its 5717 * own TX Queue in order to prevent Head-Of-Line Blocking. 5718 */ 5719 q1g = 8; 5720 if (adap->params.nports * 8 > avail_eth_qsets) { 5721 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n", 5722 avail_eth_qsets, adap->params.nports * 8); 5723 return -ENOMEM; 5724 } 5725 5726 if (adap->params.nports * ncpus < avail_eth_qsets) 5727 q10g = max(8U, ncpus); 5728 else 5729 q10g = max(8U, q10g); 5730 5731 while ((q10g * n10g) > 5732 (avail_eth_qsets - (adap->params.nports - n10g) * q1g)) 5733 q10g--; 5734 5735#else /* !CONFIG_CHELSIO_T4_DCB */ 5736 q1g = 1; 5737 q10g = min(q10g, ncpus); 5738#endif /* !CONFIG_CHELSIO_T4_DCB */ 5739 if (is_kdump_kernel()) { 5740 q10g = 1; 5741 q1g = 1; 5742 } 5743 5744 for_each_port(adap, i) { 5745 struct port_info *pi = adap2pinfo(adap, i); 5746 5747 pi->first_qset = qidx; 5748 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : q1g; 5749 qidx += pi->nqsets; 5750 } 5751 5752 s->ethqsets = qidx; 5753 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 5754 avail_qsets -= qidx; 5755 5756 if (is_uld(adap)) { 5757 /* For offload we use 1 queue/channel if all ports are up to 1G, 5758 * otherwise we divide all available queues amongst the channels 5759 * capped by the number of available cores. 5760 */ 5761 num_ulds = adap->num_uld + adap->num_ofld_uld; 5762 i = min_t(u32, MAX_OFLD_QSETS, ncpus); 5763 avail_uld_qsets = roundup(i, adap->params.nports); 5764 if (avail_qsets < num_ulds * adap->params.nports) { 5765 adap->params.offload = 0; 5766 adap->params.crypto = 0; 5767 s->ofldqsets = 0; 5768 } else if (avail_qsets < num_ulds * avail_uld_qsets || !n10g) { 5769 s->ofldqsets = adap->params.nports; 5770 } else { 5771 s->ofldqsets = avail_uld_qsets; 5772 } 5773 5774 avail_qsets -= num_ulds * s->ofldqsets; 5775 } 5776 5777 /* ETHOFLD Queues used for QoS offload should follow same 5778 * allocation scheme as normal Ethernet Queues. 5779 */ 5780 if (is_ethofld(adap)) { 5781 if (avail_qsets < s->max_ethqsets) { 5782 adap->params.ethofld = 0; 5783 s->eoqsets = 0; 5784 } else { 5785 s->eoqsets = s->max_ethqsets; 5786 } 5787 avail_qsets -= s->eoqsets; 5788 } 5789 5790 /* Mirror queues must follow same scheme as normal Ethernet 5791 * Queues, when there are enough queues available. Otherwise, 5792 * allocate at least 1 queue per port. If even 1 queue is not 5793 * available, then disable mirror queues support. 5794 */ 5795 if (avail_qsets >= s->max_ethqsets) 5796 s->mirrorqsets = s->max_ethqsets; 5797 else if (avail_qsets >= adap->params.nports) 5798 s->mirrorqsets = adap->params.nports; 5799 else 5800 s->mirrorqsets = 0; 5801 avail_qsets -= s->mirrorqsets; 5802 5803 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 5804 struct sge_eth_rxq *r = &s->ethrxq[i]; 5805 5806 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 5807 r->fl.size = 72; 5808 } 5809 5810 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 5811 s->ethtxq[i].q.size = 1024; 5812 5813 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 5814 s->ctrlq[i].q.size = 512; 5815 5816 if (!is_t4(adap->params.chip)) 5817 s->ptptxq.q.size = 8; 5818 5819 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 5820 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 5821 5822 return 0; 5823} 5824 5825/* 5826 * Reduce the number of Ethernet queues across all ports to at most n. 5827 * n provides at least one queue per port. 5828 */ 5829static void reduce_ethqs(struct adapter *adap, int n) 5830{ 5831 int i; 5832 struct port_info *pi; 5833 5834 while (n < adap->sge.ethqsets) 5835 for_each_port(adap, i) { 5836 pi = adap2pinfo(adap, i); 5837 if (pi->nqsets > 1) { 5838 pi->nqsets--; 5839 adap->sge.ethqsets--; 5840 if (adap->sge.ethqsets <= n) 5841 break; 5842 } 5843 } 5844 5845 n = 0; 5846 for_each_port(adap, i) { 5847 pi = adap2pinfo(adap, i); 5848 pi->first_qset = n; 5849 n += pi->nqsets; 5850 } 5851} 5852 5853static int alloc_msix_info(struct adapter *adap, u32 num_vec) 5854{ 5855 struct msix_info *msix_info; 5856 5857 msix_info = kcalloc(num_vec, sizeof(*msix_info), GFP_KERNEL); 5858 if (!msix_info) 5859 return -ENOMEM; 5860 5861 adap->msix_bmap.msix_bmap = kcalloc(BITS_TO_LONGS(num_vec), 5862 sizeof(long), GFP_KERNEL); 5863 if (!adap->msix_bmap.msix_bmap) { 5864 kfree(msix_info); 5865 return -ENOMEM; 5866 } 5867 5868 spin_lock_init(&adap->msix_bmap.lock); 5869 adap->msix_bmap.mapsize = num_vec; 5870 5871 adap->msix_info = msix_info; 5872 return 0; 5873} 5874 5875static void free_msix_info(struct adapter *adap) 5876{ 5877 kfree(adap->msix_bmap.msix_bmap); 5878 kfree(adap->msix_info); 5879} 5880 5881int cxgb4_get_msix_idx_from_bmap(struct adapter *adap) 5882{ 5883 struct msix_bmap *bmap = &adap->msix_bmap; 5884 unsigned int msix_idx; 5885 unsigned long flags; 5886 5887 spin_lock_irqsave(&bmap->lock, flags); 5888 msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize); 5889 if (msix_idx < bmap->mapsize) { 5890 __set_bit(msix_idx, bmap->msix_bmap); 5891 } else { 5892 spin_unlock_irqrestore(&bmap->lock, flags); 5893 return -ENOSPC; 5894 } 5895 5896 spin_unlock_irqrestore(&bmap->lock, flags); 5897 return msix_idx; 5898} 5899 5900void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, 5901 unsigned int msix_idx) 5902{ 5903 struct msix_bmap *bmap = &adap->msix_bmap; 5904 unsigned long flags; 5905 5906 spin_lock_irqsave(&bmap->lock, flags); 5907 __clear_bit(msix_idx, bmap->msix_bmap); 5908 spin_unlock_irqrestore(&bmap->lock, flags); 5909} 5910 5911/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 5912#define EXTRA_VECS 2 5913 5914static int enable_msix(struct adapter *adap) 5915{ 5916 u32 eth_need, uld_need = 0, ethofld_need = 0, mirror_need = 0; 5917 u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0, mirrorqsets = 0; 5918 u8 num_uld = 0, nchan = adap->params.nports; 5919 u32 i, want, need, num_vec; 5920 struct sge *s = &adap->sge; 5921 struct msix_entry *entries; 5922 struct port_info *pi; 5923 int allocated, ret; 5924 5925 want = s->max_ethqsets; 5926#ifdef CONFIG_CHELSIO_T4_DCB 5927 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 5928 * each port. 5929 */ 5930 need = 8 * nchan; 5931#else 5932 need = nchan; 5933#endif 5934 eth_need = need; 5935 if (is_uld(adap)) { 5936 num_uld = adap->num_ofld_uld + adap->num_uld; 5937 want += num_uld * s->ofldqsets; 5938 uld_need = num_uld * nchan; 5939 need += uld_need; 5940 } 5941 5942 if (is_ethofld(adap)) { 5943 want += s->eoqsets; 5944 ethofld_need = eth_need; 5945 need += ethofld_need; 5946 } 5947 5948 if (s->mirrorqsets) { 5949 want += s->mirrorqsets; 5950 mirror_need = nchan; 5951 need += mirror_need; 5952 } 5953 5954 want += EXTRA_VECS; 5955 need += EXTRA_VECS; 5956 5957 entries = kmalloc_array(want, sizeof(*entries), GFP_KERNEL); 5958 if (!entries) 5959 return -ENOMEM; 5960 5961 for (i = 0; i < want; i++) 5962 entries[i].entry = i; 5963 5964 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 5965 if (allocated < 0) { 5966 /* Disable offload and attempt to get vectors for NIC 5967 * only mode. 5968 */ 5969 want = s->max_ethqsets + EXTRA_VECS; 5970 need = eth_need + EXTRA_VECS; 5971 allocated = pci_enable_msix_range(adap->pdev, entries, 5972 need, want); 5973 if (allocated < 0) { 5974 dev_info(adap->pdev_dev, 5975 "Disabling MSI-X due to insufficient MSI-X vectors\n"); 5976 ret = allocated; 5977 goto out_free; 5978 } 5979 5980 dev_info(adap->pdev_dev, 5981 "Disabling offload due to insufficient MSI-X vectors\n"); 5982 adap->params.offload = 0; 5983 adap->params.crypto = 0; 5984 adap->params.ethofld = 0; 5985 s->ofldqsets = 0; 5986 s->eoqsets = 0; 5987 s->mirrorqsets = 0; 5988 uld_need = 0; 5989 ethofld_need = 0; 5990 mirror_need = 0; 5991 } 5992 5993 num_vec = allocated; 5994 if (num_vec < want) { 5995 /* Distribute available vectors to the various queue groups. 5996 * Every group gets its minimum requirement and NIC gets top 5997 * priority for leftovers. 5998 */ 5999 ethqsets = eth_need; 6000 if (is_uld(adap)) 6001 ofldqsets = nchan; 6002 if (is_ethofld(adap)) 6003 eoqsets = ethofld_need; 6004 if (s->mirrorqsets) 6005 mirrorqsets = mirror_need; 6006 6007 num_vec -= need; 6008 while (num_vec) { 6009 if (num_vec < eth_need + ethofld_need || 6010 ethqsets > s->max_ethqsets) 6011 break; 6012 6013 for_each_port(adap, i) { 6014 pi = adap2pinfo(adap, i); 6015 if (pi->nqsets < 2) 6016 continue; 6017 6018 ethqsets++; 6019 num_vec--; 6020 if (ethofld_need) { 6021 eoqsets++; 6022 num_vec--; 6023 } 6024 } 6025 } 6026 6027 if (is_uld(adap)) { 6028 while (num_vec) { 6029 if (num_vec < uld_need || 6030 ofldqsets > s->ofldqsets) 6031 break; 6032 6033 ofldqsets++; 6034 num_vec -= uld_need; 6035 } 6036 } 6037 6038 if (s->mirrorqsets) { 6039 while (num_vec) { 6040 if (num_vec < mirror_need || 6041 mirrorqsets > s->mirrorqsets) 6042 break; 6043 6044 mirrorqsets++; 6045 num_vec -= mirror_need; 6046 } 6047 } 6048 } else { 6049 ethqsets = s->max_ethqsets; 6050 if (is_uld(adap)) 6051 ofldqsets = s->ofldqsets; 6052 if (is_ethofld(adap)) 6053 eoqsets = s->eoqsets; 6054 if (s->mirrorqsets) 6055 mirrorqsets = s->mirrorqsets; 6056 } 6057 6058 if (ethqsets < s->max_ethqsets) { 6059 s->max_ethqsets = ethqsets; 6060 reduce_ethqs(adap, ethqsets); 6061 } 6062 6063 if (is_uld(adap)) { 6064 s->ofldqsets = ofldqsets; 6065 s->nqs_per_uld = s->ofldqsets; 6066 } 6067 6068 if (is_ethofld(adap)) 6069 s->eoqsets = eoqsets; 6070 6071 if (s->mirrorqsets) { 6072 s->mirrorqsets = mirrorqsets; 6073 for_each_port(adap, i) { 6074 pi = adap2pinfo(adap, i); 6075 pi->nmirrorqsets = s->mirrorqsets / nchan; 6076 mutex_init(&pi->vi_mirror_mutex); 6077 } 6078 } 6079 6080 /* map for msix */ 6081 ret = alloc_msix_info(adap, allocated); 6082 if (ret) 6083 goto out_disable_msix; 6084 6085 for (i = 0; i < allocated; i++) { 6086 adap->msix_info[i].vec = entries[i].vector; 6087 adap->msix_info[i].idx = i; 6088 } 6089 6090 dev_info(adap->pdev_dev, 6091 "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d mirrorqsets %d\n", 6092 allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld, 6093 s->mirrorqsets); 6094 6095 kfree(entries); 6096 return 0; 6097 6098out_disable_msix: 6099 pci_disable_msix(adap->pdev); 6100 6101out_free: 6102 kfree(entries); 6103 return ret; 6104} 6105 6106#undef EXTRA_VECS 6107 6108static int init_rss(struct adapter *adap) 6109{ 6110 unsigned int i; 6111 int err; 6112 6113 err = t4_init_rss_mode(adap, adap->mbox); 6114 if (err) 6115 return err; 6116 6117 for_each_port(adap, i) { 6118 struct port_info *pi = adap2pinfo(adap, i); 6119 6120 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 6121 if (!pi->rss) 6122 return -ENOMEM; 6123 } 6124 return 0; 6125} 6126 6127/* Dump basic information about the adapter */ 6128static void print_adapter_info(struct adapter *adapter) 6129{ 6130 /* Hardware/Firmware/etc. Version/Revision IDs */ 6131 t4_dump_version_info(adapter); 6132 6133 /* Software/Hardware configuration */ 6134 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 6135 is_offload(adapter) ? "R" : "", 6136 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" : 6137 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""), 6138 is_offload(adapter) ? "Offload" : "non-Offload"); 6139} 6140 6141static void print_port_info(const struct net_device *dev) 6142{ 6143 char buf[80]; 6144 char *bufp = buf; 6145 const struct port_info *pi = netdev_priv(dev); 6146 const struct adapter *adap = pi->adapter; 6147 6148 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 6149 bufp += sprintf(bufp, "100M/"); 6150 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 6151 bufp += sprintf(bufp, "1G/"); 6152 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 6153 bufp += sprintf(bufp, "10G/"); 6154 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 6155 bufp += sprintf(bufp, "25G/"); 6156 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 6157 bufp += sprintf(bufp, "40G/"); 6158 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 6159 bufp += sprintf(bufp, "50G/"); 6160 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 6161 bufp += sprintf(bufp, "100G/"); 6162 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 6163 bufp += sprintf(bufp, "200G/"); 6164 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 6165 bufp += sprintf(bufp, "400G/"); 6166 if (bufp != buf) 6167 --bufp; 6168 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 6169 6170 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 6171 dev->name, adap->params.vpd.id, adap->name, buf); 6172} 6173 6174/* 6175 * Free the following resources: 6176 * - memory used for tables 6177 * - MSI/MSI-X 6178 * - net devices 6179 * - resources FW is holding for us 6180 */ 6181static void free_some_resources(struct adapter *adapter) 6182{ 6183 unsigned int i; 6184 6185 kvfree(adapter->smt); 6186 kvfree(adapter->l2t); 6187 kvfree(adapter->srq); 6188 t4_cleanup_sched(adapter); 6189 kvfree(adapter->tids.tid_tab); 6190 cxgb4_cleanup_tc_matchall(adapter); 6191 cxgb4_cleanup_tc_mqprio(adapter); 6192 cxgb4_cleanup_tc_flower(adapter); 6193 cxgb4_cleanup_tc_u32(adapter); 6194 cxgb4_cleanup_ethtool_filters(adapter); 6195 kfree(adapter->sge.egr_map); 6196 kfree(adapter->sge.ingr_map); 6197 kfree(adapter->sge.starving_fl); 6198 kfree(adapter->sge.txq_maperr); 6199#ifdef CONFIG_DEBUG_FS 6200 kfree(adapter->sge.blocked_fl); 6201#endif 6202 disable_msi(adapter); 6203 6204 for_each_port(adapter, i) 6205 if (adapter->port[i]) { 6206 struct port_info *pi = adap2pinfo(adapter, i); 6207 6208 if (pi->viid != 0) 6209 t4_free_vi(adapter, adapter->mbox, adapter->pf, 6210 0, pi->viid); 6211 kfree(adap2pinfo(adapter, i)->rss); 6212 free_netdev(adapter->port[i]); 6213 } 6214 if (adapter->flags & CXGB4_FW_OK) 6215 t4_fw_bye(adapter, adapter->pf); 6216} 6217 6218#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \ 6219 NETIF_F_GSO_UDP_L4) 6220#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 6221 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 6222#define SEGMENT_SIZE 128 6223 6224static int t4_get_chip_type(struct adapter *adap, int ver) 6225{ 6226 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A)); 6227 6228 switch (ver) { 6229 case CHELSIO_T4: 6230 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 6231 case CHELSIO_T5: 6232 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 6233 case CHELSIO_T6: 6234 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 6235 default: 6236 break; 6237 } 6238 return -EINVAL; 6239} 6240 6241#ifdef CONFIG_PCI_IOV 6242static void cxgb4_mgmt_setup(struct net_device *dev) 6243{ 6244 dev->type = ARPHRD_NONE; 6245 dev->mtu = 0; 6246 dev->hard_header_len = 0; 6247 dev->addr_len = 0; 6248 dev->tx_queue_len = 0; 6249 dev->flags |= IFF_NOARP; 6250 dev->priv_flags |= IFF_NO_QUEUE; 6251 6252 /* Initialize the device structure. */ 6253 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 6254 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 6255} 6256 6257static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 6258{ 6259 struct adapter *adap = pci_get_drvdata(pdev); 6260 int err = 0; 6261 int current_vfs = pci_num_vf(pdev); 6262 u32 pcie_fw; 6263 6264 pcie_fw = readl(adap->regs + PCIE_FW_A); 6265 /* Check if fw is initialized */ 6266 if (!(pcie_fw & PCIE_FW_INIT_F)) { 6267 dev_warn(&pdev->dev, "Device not initialized\n"); 6268 return -EOPNOTSUPP; 6269 } 6270 6271 /* If any of the VF's is already assigned to Guest OS, then 6272 * SRIOV for the same cannot be modified 6273 */ 6274 if (current_vfs && pci_vfs_assigned(pdev)) { 6275 dev_err(&pdev->dev, 6276 "Cannot modify SR-IOV while VFs are assigned\n"); 6277 return current_vfs; 6278 } 6279 /* Note that the upper-level code ensures that we're never called with 6280 * a non-zero "num_vfs" when we already have VFs instantiated. But 6281 * it never hurts to code defensively. 6282 */ 6283 if (num_vfs != 0 && current_vfs != 0) 6284 return -EBUSY; 6285 6286 /* Nothing to do for no change. */ 6287 if (num_vfs == current_vfs) 6288 return num_vfs; 6289 6290 /* Disable SRIOV when zero is passed. */ 6291 if (!num_vfs) { 6292 pci_disable_sriov(pdev); 6293 /* free VF Management Interface */ 6294 unregister_netdev(adap->port[0]); 6295 free_netdev(adap->port[0]); 6296 adap->port[0] = NULL; 6297 6298 /* free VF resources */ 6299 adap->num_vfs = 0; 6300 kfree(adap->vfinfo); 6301 adap->vfinfo = NULL; 6302 return 0; 6303 } 6304 6305 if (!current_vfs) { 6306 struct fw_pfvf_cmd port_cmd, port_rpl; 6307 struct net_device *netdev; 6308 unsigned int pmask, port; 6309 struct pci_dev *pbridge; 6310 struct port_info *pi; 6311 char name[IFNAMSIZ]; 6312 u32 devcap2; 6313 u16 flags; 6314 6315 /* If we want to instantiate Virtual Functions, then our 6316 * parent bridge's PCI-E needs to support Alternative Routing 6317 * ID (ARI) because our VFs will show up at function offset 8 6318 * and above. 6319 */ 6320 pbridge = pdev->bus->self; 6321 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags); 6322 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2); 6323 6324 if ((flags & PCI_EXP_FLAGS_VERS) < 2 || 6325 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) { 6326 /* Our parent bridge does not support ARI so issue a 6327 * warning and skip instantiating the VFs. They 6328 * won't be reachable. 6329 */ 6330 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n", 6331 pbridge->bus->number, PCI_SLOT(pbridge->devfn), 6332 PCI_FUNC(pbridge->devfn)); 6333 return -ENOTSUPP; 6334 } 6335 memset(&port_cmd, 0, sizeof(port_cmd)); 6336 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | 6337 FW_CMD_REQUEST_F | 6338 FW_CMD_READ_F | 6339 FW_PFVF_CMD_PFN_V(adap->pf) | 6340 FW_PFVF_CMD_VFN_V(0)); 6341 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd)); 6342 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), 6343 &port_rpl); 6344 if (err) 6345 return err; 6346 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq)); 6347 port = ffs(pmask) - 1; 6348 /* Allocate VF Management Interface. */ 6349 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx, 6350 adap->pf); 6351 netdev = alloc_netdev(sizeof(struct port_info), 6352 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup); 6353 if (!netdev) 6354 return -ENOMEM; 6355 6356 pi = netdev_priv(netdev); 6357 pi->adapter = adap; 6358 pi->lport = port; 6359 pi->tx_chan = port; 6360 SET_NETDEV_DEV(netdev, &pdev->dev); 6361 6362 adap->port[0] = netdev; 6363 pi->port_id = 0; 6364 6365 err = register_netdev(adap->port[0]); 6366 if (err) { 6367 pr_info("Unable to register VF mgmt netdev %s\n", name); 6368 free_netdev(adap->port[0]); 6369 adap->port[0] = NULL; 6370 return err; 6371 } 6372 /* Allocate and set up VF Information. */ 6373 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev), 6374 sizeof(struct vf_info), GFP_KERNEL); 6375 if (!adap->vfinfo) { 6376 unregister_netdev(adap->port[0]); 6377 free_netdev(adap->port[0]); 6378 adap->port[0] = NULL; 6379 return -ENOMEM; 6380 } 6381 cxgb4_mgmt_fill_vf_station_mac_addr(adap); 6382 } 6383 /* Instantiate the requested number of VFs. */ 6384 err = pci_enable_sriov(pdev, num_vfs); 6385 if (err) { 6386 pr_info("Unable to instantiate %d VFs\n", num_vfs); 6387 if (!current_vfs) { 6388 unregister_netdev(adap->port[0]); 6389 free_netdev(adap->port[0]); 6390 adap->port[0] = NULL; 6391 kfree(adap->vfinfo); 6392 adap->vfinfo = NULL; 6393 } 6394 return err; 6395 } 6396 6397 adap->num_vfs = num_vfs; 6398 return num_vfs; 6399} 6400#endif /* CONFIG_PCI_IOV */ 6401 6402#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) || IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE) 6403 6404static int chcr_offload_state(struct adapter *adap, 6405 enum cxgb4_netdev_tls_ops op_val) 6406{ 6407 switch (op_val) { 6408#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 6409 case CXGB4_TLSDEV_OPS: 6410 if (!adap->uld[CXGB4_ULD_KTLS].handle) { 6411 dev_dbg(adap->pdev_dev, "ch_ktls driver is not loaded\n"); 6412 return -EOPNOTSUPP; 6413 } 6414 if (!adap->uld[CXGB4_ULD_KTLS].tlsdev_ops) { 6415 dev_dbg(adap->pdev_dev, 6416 "ch_ktls driver has no registered tlsdev_ops\n"); 6417 return -EOPNOTSUPP; 6418 } 6419 break; 6420#endif /* CONFIG_CHELSIO_TLS_DEVICE */ 6421#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE) 6422 case CXGB4_XFRMDEV_OPS: 6423 if (!adap->uld[CXGB4_ULD_IPSEC].handle) { 6424 dev_dbg(adap->pdev_dev, "chipsec driver is not loaded\n"); 6425 return -EOPNOTSUPP; 6426 } 6427 if (!adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops) { 6428 dev_dbg(adap->pdev_dev, 6429 "chipsec driver has no registered xfrmdev_ops\n"); 6430 return -EOPNOTSUPP; 6431 } 6432 break; 6433#endif /* CONFIG_CHELSIO_IPSEC_INLINE */ 6434 default: 6435 dev_dbg(adap->pdev_dev, 6436 "driver has no support for offload %d\n", op_val); 6437 return -EOPNOTSUPP; 6438 } 6439 6440 return 0; 6441} 6442 6443#endif /* CONFIG_CHELSIO_TLS_DEVICE || CONFIG_CHELSIO_IPSEC_INLINE */ 6444 6445#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 6446 6447static int cxgb4_ktls_dev_add(struct net_device *netdev, struct sock *sk, 6448 enum tls_offload_ctx_dir direction, 6449 struct tls_crypto_info *crypto_info, 6450 u32 tcp_sn) 6451{ 6452 struct adapter *adap = netdev2adap(netdev); 6453 int ret; 6454 6455 mutex_lock(&uld_mutex); 6456 ret = chcr_offload_state(adap, CXGB4_TLSDEV_OPS); 6457 if (ret) 6458 goto out_unlock; 6459 6460 ret = cxgb4_set_ktls_feature(adap, FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE); 6461 if (ret) 6462 goto out_unlock; 6463 6464 ret = adap->uld[CXGB4_ULD_KTLS].tlsdev_ops->tls_dev_add(netdev, sk, 6465 direction, 6466 crypto_info, 6467 tcp_sn); 6468 /* if there is a failure, clear the refcount */ 6469 if (ret) 6470 cxgb4_set_ktls_feature(adap, 6471 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE); 6472out_unlock: 6473 mutex_unlock(&uld_mutex); 6474 return ret; 6475} 6476 6477static void cxgb4_ktls_dev_del(struct net_device *netdev, 6478 struct tls_context *tls_ctx, 6479 enum tls_offload_ctx_dir direction) 6480{ 6481 struct adapter *adap = netdev2adap(netdev); 6482 6483 mutex_lock(&uld_mutex); 6484 if (chcr_offload_state(adap, CXGB4_TLSDEV_OPS)) 6485 goto out_unlock; 6486 6487 adap->uld[CXGB4_ULD_KTLS].tlsdev_ops->tls_dev_del(netdev, tls_ctx, 6488 direction); 6489 6490out_unlock: 6491 cxgb4_set_ktls_feature(adap, FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE); 6492 mutex_unlock(&uld_mutex); 6493} 6494 6495static const struct tlsdev_ops cxgb4_ktls_ops = { 6496 .tls_dev_add = cxgb4_ktls_dev_add, 6497 .tls_dev_del = cxgb4_ktls_dev_del, 6498}; 6499#endif /* CONFIG_CHELSIO_TLS_DEVICE */ 6500 6501#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE) 6502 6503static int cxgb4_xfrm_add_state(struct xfrm_state *x) 6504{ 6505 struct adapter *adap = netdev2adap(x->xso.dev); 6506 int ret; 6507 6508 if (!mutex_trylock(&uld_mutex)) { 6509 dev_dbg(adap->pdev_dev, 6510 "crypto uld critical resource is under use\n"); 6511 return -EBUSY; 6512 } 6513 ret = chcr_offload_state(adap, CXGB4_XFRMDEV_OPS); 6514 if (ret) 6515 goto out_unlock; 6516 6517 ret = adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops->xdo_dev_state_add(x); 6518 6519out_unlock: 6520 mutex_unlock(&uld_mutex); 6521 6522 return ret; 6523} 6524 6525static void cxgb4_xfrm_del_state(struct xfrm_state *x) 6526{ 6527 struct adapter *adap = netdev2adap(x->xso.dev); 6528 6529 if (!mutex_trylock(&uld_mutex)) { 6530 dev_dbg(adap->pdev_dev, 6531 "crypto uld critical resource is under use\n"); 6532 return; 6533 } 6534 if (chcr_offload_state(adap, CXGB4_XFRMDEV_OPS)) 6535 goto out_unlock; 6536 6537 adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops->xdo_dev_state_delete(x); 6538 6539out_unlock: 6540 mutex_unlock(&uld_mutex); 6541} 6542 6543static void cxgb4_xfrm_free_state(struct xfrm_state *x) 6544{ 6545 struct adapter *adap = netdev2adap(x->xso.dev); 6546 6547 if (!mutex_trylock(&uld_mutex)) { 6548 dev_dbg(adap->pdev_dev, 6549 "crypto uld critical resource is under use\n"); 6550 return; 6551 } 6552 if (chcr_offload_state(adap, CXGB4_XFRMDEV_OPS)) 6553 goto out_unlock; 6554 6555 adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops->xdo_dev_state_free(x); 6556 6557out_unlock: 6558 mutex_unlock(&uld_mutex); 6559} 6560 6561static bool cxgb4_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *x) 6562{ 6563 struct adapter *adap = netdev2adap(x->xso.dev); 6564 bool ret = false; 6565 6566 if (!mutex_trylock(&uld_mutex)) { 6567 dev_dbg(adap->pdev_dev, 6568 "crypto uld critical resource is under use\n"); 6569 return ret; 6570 } 6571 if (chcr_offload_state(adap, CXGB4_XFRMDEV_OPS)) 6572 goto out_unlock; 6573 6574 ret = adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops->xdo_dev_offload_ok(skb, x); 6575 6576out_unlock: 6577 mutex_unlock(&uld_mutex); 6578 return ret; 6579} 6580 6581static void cxgb4_advance_esn_state(struct xfrm_state *x) 6582{ 6583 struct adapter *adap = netdev2adap(x->xso.dev); 6584 6585 if (!mutex_trylock(&uld_mutex)) { 6586 dev_dbg(adap->pdev_dev, 6587 "crypto uld critical resource is under use\n"); 6588 return; 6589 } 6590 if (chcr_offload_state(adap, CXGB4_XFRMDEV_OPS)) 6591 goto out_unlock; 6592 6593 adap->uld[CXGB4_ULD_IPSEC].xfrmdev_ops->xdo_dev_state_advance_esn(x); 6594 6595out_unlock: 6596 mutex_unlock(&uld_mutex); 6597} 6598 6599static const struct xfrmdev_ops cxgb4_xfrmdev_ops = { 6600 .xdo_dev_state_add = cxgb4_xfrm_add_state, 6601 .xdo_dev_state_delete = cxgb4_xfrm_del_state, 6602 .xdo_dev_state_free = cxgb4_xfrm_free_state, 6603 .xdo_dev_offload_ok = cxgb4_ipsec_offload_ok, 6604 .xdo_dev_state_advance_esn = cxgb4_advance_esn_state, 6605}; 6606 6607#endif /* CONFIG_CHELSIO_IPSEC_INLINE */ 6608 6609static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6610{ 6611 struct net_device *netdev; 6612 struct adapter *adapter; 6613 static int adap_idx = 1; 6614 int s_qpp, qpp, num_seg; 6615 struct port_info *pi; 6616 bool highdma = false; 6617 enum chip_type chip; 6618 void __iomem *regs; 6619 int func, chip_ver; 6620 u16 device_id; 6621 int i, err; 6622 u32 whoami; 6623 6624 err = pci_request_regions(pdev, KBUILD_MODNAME); 6625 if (err) { 6626 /* Just info, some other driver may have claimed the device. */ 6627 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 6628 return err; 6629 } 6630 6631 err = pci_enable_device(pdev); 6632 if (err) { 6633 dev_err(&pdev->dev, "cannot enable PCI device\n"); 6634 goto out_release_regions; 6635 } 6636 6637 regs = pci_ioremap_bar(pdev, 0); 6638 if (!regs) { 6639 dev_err(&pdev->dev, "cannot map device registers\n"); 6640 err = -ENOMEM; 6641 goto out_disable_device; 6642 } 6643 6644 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 6645 if (!adapter) { 6646 err = -ENOMEM; 6647 goto out_unmap_bar0; 6648 } 6649 6650 adapter->regs = regs; 6651 err = t4_wait_dev_ready(regs); 6652 if (err < 0) 6653 goto out_free_adapter; 6654 6655 /* We control everything through one PF */ 6656 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 6657 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 6658 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id)); 6659 if ((int)chip < 0) { 6660 dev_err(&pdev->dev, "Device %d is not supported\n", device_id); 6661 err = chip; 6662 goto out_free_adapter; 6663 } 6664 chip_ver = CHELSIO_CHIP_VERSION(chip); 6665 func = chip_ver <= CHELSIO_T5 ? 6666 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 6667 6668 adapter->pdev = pdev; 6669 adapter->pdev_dev = &pdev->dev; 6670 adapter->name = pci_name(pdev); 6671 adapter->mbox = func; 6672 adapter->pf = func; 6673 adapter->params.chip = chip; 6674 adapter->adap_idx = adap_idx; 6675 adapter->msg_enable = DFLT_MSG_ENABLE; 6676 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 6677 (sizeof(struct mbox_cmd) * 6678 T4_OS_LOG_MBOX_CMDS), 6679 GFP_KERNEL); 6680 if (!adapter->mbox_log) { 6681 err = -ENOMEM; 6682 goto out_free_adapter; 6683 } 6684 spin_lock_init(&adapter->mbox_lock); 6685 INIT_LIST_HEAD(&adapter->mlist.list); 6686 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 6687 pci_set_drvdata(pdev, adapter); 6688 6689 if (func != ent->driver_data) { 6690 pci_disable_device(pdev); 6691 pci_save_state(pdev); /* to restore SR-IOV later */ 6692 return 0; 6693 } 6694 6695 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 6696 highdma = true; 6697 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 6698 if (err) { 6699 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 6700 "coherent allocations\n"); 6701 goto out_free_adapter; 6702 } 6703 } else { 6704 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 6705 if (err) { 6706 dev_err(&pdev->dev, "no usable DMA configuration\n"); 6707 goto out_free_adapter; 6708 } 6709 } 6710 6711 pci_enable_pcie_error_reporting(pdev); 6712 pci_set_master(pdev); 6713 pci_save_state(pdev); 6714 adap_idx++; 6715 adapter->workq = create_singlethread_workqueue("cxgb4"); 6716 if (!adapter->workq) { 6717 err = -ENOMEM; 6718 goto out_free_adapter; 6719 } 6720 6721 /* PCI device has been enabled */ 6722 adapter->flags |= CXGB4_DEV_ENABLED; 6723 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 6724 6725 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 6726 * Ingress Packet Data to Free List Buffers in order to allow for 6727 * chipset performance optimizations between the Root Complex and 6728 * Memory Controllers. (Messages to the associated Ingress Queue 6729 * notifying new Packet Placement in the Free Lists Buffers will be 6730 * send without the Relaxed Ordering Attribute thus guaranteeing that 6731 * all preceding PCIe Transaction Layer Packets will be processed 6732 * first.) But some Root Complexes have various issues with Upstream 6733 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 6734 * The PCIe devices which under the Root Complexes will be cleared the 6735 * Relaxed Ordering bit in the configuration space, So we check our 6736 * PCIe configuration space to see if it's flagged with advice against 6737 * using Relaxed Ordering. 6738 */ 6739 if (!pcie_relaxed_ordering_enabled(pdev)) 6740 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING; 6741 6742 spin_lock_init(&adapter->stats_lock); 6743 spin_lock_init(&adapter->tid_release_lock); 6744 spin_lock_init(&adapter->win0_lock); 6745 6746 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 6747 INIT_WORK(&adapter->db_full_task, process_db_full); 6748 INIT_WORK(&adapter->db_drop_task, process_db_drop); 6749 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err); 6750 6751 err = t4_prep_adapter(adapter); 6752 if (err) 6753 goto out_free_adapter; 6754 6755 if (is_kdump_kernel()) { 6756 /* Collect hardware state and append to /proc/vmcore */ 6757 err = cxgb4_cudbg_vmcore_add_dump(adapter); 6758 if (err) { 6759 dev_warn(adapter->pdev_dev, 6760 "Fail collecting vmcore device dump, err: %d. Continuing\n", 6761 err); 6762 err = 0; 6763 } 6764 } 6765 6766 if (!is_t4(adapter->params.chip)) { 6767 s_qpp = (QUEUESPERPAGEPF0_S + 6768 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 6769 adapter->pf); 6770 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 6771 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 6772 num_seg = PAGE_SIZE / SEGMENT_SIZE; 6773 6774 /* Each segment size is 128B. Write coalescing is enabled only 6775 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 6776 * queue is less no of segments that can be accommodated in 6777 * a page size. 6778 */ 6779 if (qpp > num_seg) { 6780 dev_err(&pdev->dev, 6781 "Incorrect number of egress queues per page\n"); 6782 err = -EINVAL; 6783 goto out_free_adapter; 6784 } 6785 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 6786 pci_resource_len(pdev, 2)); 6787 if (!adapter->bar2) { 6788 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 6789 err = -ENOMEM; 6790 goto out_free_adapter; 6791 } 6792 } 6793 6794 setup_memwin(adapter); 6795 err = adap_init0(adapter, 0); 6796 if (err) 6797 goto out_unmap_bar; 6798 6799 setup_memwin_rdma(adapter); 6800 6801 /* configure SGE_STAT_CFG_A to read WC stats */ 6802 if (!is_t4(adapter->params.chip)) 6803 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 6804 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 6805 T6_STATMODE_V(0))); 6806 6807 /* Initialize hash mac addr list */ 6808 INIT_LIST_HEAD(&adapter->mac_hlist); 6809 6810 for_each_port(adapter, i) { 6811 /* For supporting MQPRIO Offload, need some extra 6812 * queues for each ETHOFLD TIDs. Keep it equal to 6813 * MAX_ATIDs for now. Once we connect to firmware 6814 * later and query the EOTID params, we'll come to 6815 * know the actual # of EOTIDs supported. 6816 */ 6817 netdev = alloc_etherdev_mq(sizeof(struct port_info), 6818 MAX_ETH_QSETS + MAX_ATIDS); 6819 if (!netdev) { 6820 err = -ENOMEM; 6821 goto out_free_dev; 6822 } 6823 6824 SET_NETDEV_DEV(netdev, &pdev->dev); 6825 6826 adapter->port[i] = netdev; 6827 pi = netdev_priv(netdev); 6828 pi->adapter = adapter; 6829 pi->xact_addr_filt = -1; 6830 pi->port_id = i; 6831 netdev->irq = pdev->irq; 6832 6833 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 6834 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6835 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO | 6836 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 6837 NETIF_F_HW_TC | NETIF_F_NTUPLE; 6838 6839 if (chip_ver > CHELSIO_T5) { 6840 netdev->hw_enc_features |= NETIF_F_IP_CSUM | 6841 NETIF_F_IPV6_CSUM | 6842 NETIF_F_RXCSUM | 6843 NETIF_F_GSO_UDP_TUNNEL | 6844 NETIF_F_GSO_UDP_TUNNEL_CSUM | 6845 NETIF_F_TSO | NETIF_F_TSO6; 6846 6847 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 6848 NETIF_F_GSO_UDP_TUNNEL_CSUM | 6849 NETIF_F_HW_TLS_RECORD; 6850 6851 if (adapter->rawf_cnt) 6852 netdev->udp_tunnel_nic_info = &cxgb_udp_tunnels; 6853 } 6854 6855 if (highdma) 6856 netdev->hw_features |= NETIF_F_HIGHDMA; 6857 netdev->features |= netdev->hw_features; 6858 netdev->vlan_features = netdev->features & VLAN_FEAT; 6859#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 6860 if (pi->adapter->params.crypto & FW_CAPS_CONFIG_TLS_HW) { 6861 netdev->hw_features |= NETIF_F_HW_TLS_TX; 6862 netdev->tlsdev_ops = &cxgb4_ktls_ops; 6863 /* initialize the refcount */ 6864 refcount_set(&pi->adapter->chcr_ktls.ktls_refcount, 0); 6865 } 6866#endif /* CONFIG_CHELSIO_TLS_DEVICE */ 6867#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE) 6868 if (pi->adapter->params.crypto & FW_CAPS_CONFIG_IPSEC_INLINE) { 6869 netdev->hw_enc_features |= NETIF_F_HW_ESP; 6870 netdev->features |= NETIF_F_HW_ESP; 6871 netdev->xfrmdev_ops = &cxgb4_xfrmdev_ops; 6872 } 6873#endif /* CONFIG_CHELSIO_IPSEC_INLINE */ 6874 6875 netdev->priv_flags |= IFF_UNICAST_FLT; 6876 6877 /* MTU range: 81 - 9600 */ 6878 netdev->min_mtu = 81; /* accommodate SACK */ 6879 netdev->max_mtu = MAX_MTU; 6880 6881 netdev->netdev_ops = &cxgb4_netdev_ops; 6882#ifdef CONFIG_CHELSIO_T4_DCB 6883 netdev->dcbnl_ops = &cxgb4_dcb_ops; 6884 cxgb4_dcb_state_init(netdev); 6885 cxgb4_dcb_version_init(netdev); 6886#endif 6887 cxgb4_set_ethtool_ops(netdev); 6888 } 6889 6890 cxgb4_init_ethtool_dump(adapter); 6891 6892 pci_set_drvdata(pdev, adapter); 6893 6894 if (adapter->flags & CXGB4_FW_OK) { 6895 err = t4_port_init(adapter, func, func, 0); 6896 if (err) 6897 goto out_free_dev; 6898 } else if (adapter->params.nports == 1) { 6899 /* If we don't have a connection to the firmware -- possibly 6900 * because of an error -- grab the raw VPD parameters so we 6901 * can set the proper MAC Address on the debug network 6902 * interface that we've created. 6903 */ 6904 u8 hw_addr[ETH_ALEN]; 6905 u8 *na = adapter->params.vpd.na; 6906 6907 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 6908 if (!err) { 6909 for (i = 0; i < ETH_ALEN; i++) 6910 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 6911 hex2val(na[2 * i + 1])); 6912 t4_set_hw_addr(adapter, 0, hw_addr); 6913 } 6914 } 6915 6916 if (!(adapter->flags & CXGB4_FW_OK)) 6917 goto fw_attach_fail; 6918 6919 /* Configure queues and allocate tables now, they can be needed as 6920 * soon as the first register_netdev completes. 6921 */ 6922 err = cfg_queues(adapter); 6923 if (err) 6924 goto out_free_dev; 6925 6926 adapter->smt = t4_init_smt(); 6927 if (!adapter->smt) { 6928 /* We tolerate a lack of SMT, giving up some functionality */ 6929 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); 6930 } 6931 6932 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 6933 if (!adapter->l2t) { 6934 /* We tolerate a lack of L2T, giving up some functionality */ 6935 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 6936 adapter->params.offload = 0; 6937 } 6938 6939#if IS_ENABLED(CONFIG_IPV6) 6940 if (chip_ver <= CHELSIO_T5 && 6941 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 6942 /* CLIP functionality is not present in hardware, 6943 * hence disable all offload features 6944 */ 6945 dev_warn(&pdev->dev, 6946 "CLIP not enabled in hardware, continuing\n"); 6947 adapter->params.offload = 0; 6948 } else { 6949 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 6950 adapter->clipt_end); 6951 if (!adapter->clipt) { 6952 /* We tolerate a lack of clip_table, giving up 6953 * some functionality 6954 */ 6955 dev_warn(&pdev->dev, 6956 "could not allocate Clip table, continuing\n"); 6957 adapter->params.offload = 0; 6958 } 6959 } 6960#endif 6961 6962 for_each_port(adapter, i) { 6963 pi = adap2pinfo(adapter, i); 6964 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 6965 if (!pi->sched_tbl) 6966 dev_warn(&pdev->dev, 6967 "could not activate scheduling on port %d\n", 6968 i); 6969 } 6970 6971 if (is_offload(adapter) || is_hashfilter(adapter)) { 6972 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 6973 u32 v; 6974 6975 v = t4_read_reg(adapter, LE_DB_HASH_CONFIG_A); 6976 if (chip_ver <= CHELSIO_T5) { 6977 adapter->tids.nhash = 1 << HASHTIDSIZE_G(v); 6978 v = t4_read_reg(adapter, LE_DB_TID_HASHBASE_A); 6979 adapter->tids.hash_base = v / 4; 6980 } else { 6981 adapter->tids.nhash = HASHTBLSIZE_G(v) << 3; 6982 v = t4_read_reg(adapter, 6983 T6_LE_DB_HASH_TID_BASE_A); 6984 adapter->tids.hash_base = v; 6985 } 6986 } 6987 } 6988 6989 if (tid_init(&adapter->tids) < 0) { 6990 dev_warn(&pdev->dev, "could not allocate TID table, " 6991 "continuing\n"); 6992 adapter->params.offload = 0; 6993 } else { 6994 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 6995 if (!adapter->tc_u32) 6996 dev_warn(&pdev->dev, 6997 "could not offload tc u32, continuing\n"); 6998 6999 if (cxgb4_init_tc_flower(adapter)) 7000 dev_warn(&pdev->dev, 7001 "could not offload tc flower, continuing\n"); 7002 7003 if (cxgb4_init_tc_mqprio(adapter)) 7004 dev_warn(&pdev->dev, 7005 "could not offload tc mqprio, continuing\n"); 7006 7007 if (cxgb4_init_tc_matchall(adapter)) 7008 dev_warn(&pdev->dev, 7009 "could not offload tc matchall, continuing\n"); 7010 if (cxgb4_init_ethtool_filters(adapter)) 7011 dev_warn(&pdev->dev, 7012 "could not initialize ethtool filters, continuing\n"); 7013 } 7014 7015 /* See what interrupts we'll be using */ 7016 if (msi > 1 && enable_msix(adapter) == 0) 7017 adapter->flags |= CXGB4_USING_MSIX; 7018 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 7019 adapter->flags |= CXGB4_USING_MSI; 7020 if (msi > 1) 7021 free_msix_info(adapter); 7022 } 7023 7024 /* check for PCI Express bandwidth capabiltites */ 7025 pcie_print_link_status(pdev); 7026 7027 cxgb4_init_mps_ref_entries(adapter); 7028 7029 err = init_rss(adapter); 7030 if (err) 7031 goto out_free_dev; 7032 7033 err = setup_non_data_intr(adapter); 7034 if (err) { 7035 dev_err(adapter->pdev_dev, 7036 "Non Data interrupt allocation failed, err: %d\n", err); 7037 goto out_free_dev; 7038 } 7039 7040 err = setup_fw_sge_queues(adapter); 7041 if (err) { 7042 dev_err(adapter->pdev_dev, 7043 "FW sge queue allocation failed, err %d", err); 7044 goto out_free_dev; 7045 } 7046 7047fw_attach_fail: 7048 /* 7049 * The card is now ready to go. If any errors occur during device 7050 * registration we do not fail the whole card but rather proceed only 7051 * with the ports we manage to register successfully. However we must 7052 * register at least one net device. 7053 */ 7054 for_each_port(adapter, i) { 7055 pi = adap2pinfo(adapter, i); 7056 adapter->port[i]->dev_port = pi->lport; 7057 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 7058 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 7059 7060 netif_carrier_off(adapter->port[i]); 7061 7062 err = register_netdev(adapter->port[i]); 7063 if (err) 7064 break; 7065 adapter->chan_map[pi->tx_chan] = i; 7066 print_port_info(adapter->port[i]); 7067 } 7068 if (i == 0) { 7069 dev_err(&pdev->dev, "could not register any net devices\n"); 7070 goto out_free_dev; 7071 } 7072 if (err) { 7073 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 7074 err = 0; 7075 } 7076 7077 if (cxgb4_debugfs_root) { 7078 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 7079 cxgb4_debugfs_root); 7080 setup_debugfs(adapter); 7081 } 7082 7083 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 7084 pdev->needs_freset = 1; 7085 7086 if (is_uld(adapter)) 7087 cxgb4_uld_enable(adapter); 7088 7089 if (!is_t4(adapter->params.chip)) 7090 cxgb4_ptp_init(adapter); 7091 7092 if (IS_REACHABLE(CONFIG_THERMAL) && 7093 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK)) 7094 cxgb4_thermal_init(adapter); 7095 7096 print_adapter_info(adapter); 7097 return 0; 7098 7099 out_free_dev: 7100 t4_free_sge_resources(adapter); 7101 free_some_resources(adapter); 7102 if (adapter->flags & CXGB4_USING_MSIX) 7103 free_msix_info(adapter); 7104 if (adapter->num_uld || adapter->num_ofld_uld) 7105 t4_uld_mem_free(adapter); 7106 out_unmap_bar: 7107 if (!is_t4(adapter->params.chip)) 7108 iounmap(adapter->bar2); 7109 out_free_adapter: 7110 if (adapter->workq) 7111 destroy_workqueue(adapter->workq); 7112 7113 kfree(adapter->mbox_log); 7114 kfree(adapter); 7115 out_unmap_bar0: 7116 iounmap(regs); 7117 out_disable_device: 7118 pci_disable_pcie_error_reporting(pdev); 7119 pci_disable_device(pdev); 7120 out_release_regions: 7121 pci_release_regions(pdev); 7122 return err; 7123} 7124 7125static void remove_one(struct pci_dev *pdev) 7126{ 7127 struct adapter *adapter = pci_get_drvdata(pdev); 7128 struct hash_mac_addr *entry, *tmp; 7129 7130 if (!adapter) { 7131 pci_release_regions(pdev); 7132 return; 7133 } 7134 7135 /* If we allocated filters, free up state associated with any 7136 * valid filters ... 7137 */ 7138 clear_all_filters(adapter); 7139 7140 adapter->flags |= CXGB4_SHUTTING_DOWN; 7141 7142 if (adapter->pf == 4) { 7143 int i; 7144 7145 /* Tear down per-adapter Work Queue first since it can contain 7146 * references to our adapter data structure. 7147 */ 7148 destroy_workqueue(adapter->workq); 7149 7150 detach_ulds(adapter); 7151 7152 for_each_port(adapter, i) 7153 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 7154 unregister_netdev(adapter->port[i]); 7155 7156 t4_uld_clean_up(adapter); 7157 7158 adap_free_hma_mem(adapter); 7159 7160 disable_interrupts(adapter); 7161 7162 cxgb4_free_mps_ref_entries(adapter); 7163 7164 debugfs_remove_recursive(adapter->debugfs_root); 7165 7166 if (!is_t4(adapter->params.chip)) 7167 cxgb4_ptp_stop(adapter); 7168 if (IS_REACHABLE(CONFIG_THERMAL)) 7169 cxgb4_thermal_remove(adapter); 7170 7171 if (adapter->flags & CXGB4_FULL_INIT_DONE) 7172 cxgb_down(adapter); 7173 7174 if (adapter->flags & CXGB4_USING_MSIX) 7175 free_msix_info(adapter); 7176 if (adapter->num_uld || adapter->num_ofld_uld) 7177 t4_uld_mem_free(adapter); 7178 free_some_resources(adapter); 7179 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist, 7180 list) { 7181 list_del(&entry->list); 7182 kfree(entry); 7183 } 7184 7185#if IS_ENABLED(CONFIG_IPV6) 7186 t4_cleanup_clip_tbl(adapter); 7187#endif 7188 if (!is_t4(adapter->params.chip)) 7189 iounmap(adapter->bar2); 7190 } 7191#ifdef CONFIG_PCI_IOV 7192 else { 7193 cxgb4_iov_configure(adapter->pdev, 0); 7194 } 7195#endif 7196 iounmap(adapter->regs); 7197 pci_disable_pcie_error_reporting(pdev); 7198 if ((adapter->flags & CXGB4_DEV_ENABLED)) { 7199 pci_disable_device(pdev); 7200 adapter->flags &= ~CXGB4_DEV_ENABLED; 7201 } 7202 pci_release_regions(pdev); 7203 kfree(adapter->mbox_log); 7204 synchronize_rcu(); 7205 kfree(adapter); 7206} 7207 7208/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 7209 * delivery. This is essentially a stripped down version of the PCI remove() 7210 * function where we do the minimal amount of work necessary to shutdown any 7211 * further activity. 7212 */ 7213static void shutdown_one(struct pci_dev *pdev) 7214{ 7215 struct adapter *adapter = pci_get_drvdata(pdev); 7216 7217 /* As with remove_one() above (see extended comment), we only want do 7218 * do cleanup on PCI Devices which went all the way through init_one() 7219 * ... 7220 */ 7221 if (!adapter) { 7222 pci_release_regions(pdev); 7223 return; 7224 } 7225 7226 adapter->flags |= CXGB4_SHUTTING_DOWN; 7227 7228 if (adapter->pf == 4) { 7229 int i; 7230 7231 for_each_port(adapter, i) 7232 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 7233 cxgb_close(adapter->port[i]); 7234 7235 rtnl_lock(); 7236 cxgb4_mqprio_stop_offload(adapter); 7237 rtnl_unlock(); 7238 7239 if (is_uld(adapter)) { 7240 detach_ulds(adapter); 7241 t4_uld_clean_up(adapter); 7242 } 7243 7244 disable_interrupts(adapter); 7245 disable_msi(adapter); 7246 7247 t4_sge_stop(adapter); 7248 if (adapter->flags & CXGB4_FW_OK) 7249 t4_fw_bye(adapter, adapter->mbox); 7250 } 7251} 7252 7253static struct pci_driver cxgb4_driver = { 7254 .name = KBUILD_MODNAME, 7255 .id_table = cxgb4_pci_tbl, 7256 .probe = init_one, 7257 .remove = remove_one, 7258 .shutdown = shutdown_one, 7259#ifdef CONFIG_PCI_IOV 7260 .sriov_configure = cxgb4_iov_configure, 7261#endif 7262 .err_handler = &cxgb4_eeh, 7263}; 7264 7265static int __init cxgb4_init_module(void) 7266{ 7267 int ret; 7268 7269 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 7270 7271 ret = pci_register_driver(&cxgb4_driver); 7272 if (ret < 0) 7273 goto err_pci; 7274 7275#if IS_ENABLED(CONFIG_IPV6) 7276 if (!inet6addr_registered) { 7277 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 7278 if (ret) 7279 pci_unregister_driver(&cxgb4_driver); 7280 else 7281 inet6addr_registered = true; 7282 } 7283#endif 7284 7285 if (ret == 0) 7286 return ret; 7287 7288err_pci: 7289 debugfs_remove(cxgb4_debugfs_root); 7290 7291 return ret; 7292} 7293 7294static void __exit cxgb4_cleanup_module(void) 7295{ 7296#if IS_ENABLED(CONFIG_IPV6) 7297 if (inet6addr_registered) { 7298 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 7299 inet6addr_registered = false; 7300 } 7301#endif 7302 pci_unregister_driver(&cxgb4_driver); 7303 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 7304} 7305 7306module_init(cxgb4_init_module); 7307module_exit(cxgb4_cleanup_module); 7308