1/***************************************************************************** 2 * * 3 * File: sge.c * 4 * $Revision: 1.26 $ * 5 * $Date: 2005/06/21 18:29:48 $ * 6 * Description: * 7 * DMA engine. * 8 * part of the Chelsio 10Gb Ethernet Driver. * 9 * * 10 * This program is free software; you can redistribute it and/or modify * 11 * it under the terms of the GNU General Public License, version 2, as * 12 * published by the Free Software Foundation. * 13 * * 14 * You should have received a copy of the GNU General Public License along * 15 * with this program; if not, see <http://www.gnu.org/licenses/>. * 16 * * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * 18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * 20 * * 21 * http://www.chelsio.com * 22 * * 23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * 24 * All rights reserved. * 25 * * 26 * Maintainers: maintainers@chelsio.com * 27 * * 28 * Authors: Dimitrios Michailidis <dm@chelsio.com> * 29 * Tina Yang <tainay@chelsio.com> * 30 * Felix Marti <felix@chelsio.com> * 31 * Scott Bardone <sbardone@chelsio.com> * 32 * Kurt Ottaway <kottaway@chelsio.com> * 33 * Frank DiMambro <frank@chelsio.com> * 34 * * 35 * History: * 36 * * 37 ****************************************************************************/ 38 39#include "common.h" 40 41#include <linux/types.h> 42#include <linux/errno.h> 43#include <linux/pci.h> 44#include <linux/ktime.h> 45#include <linux/netdevice.h> 46#include <linux/etherdevice.h> 47#include <linux/if_vlan.h> 48#include <linux/skbuff.h> 49#include <linux/mm.h> 50#include <linux/tcp.h> 51#include <linux/ip.h> 52#include <linux/in.h> 53#include <linux/if_arp.h> 54#include <linux/slab.h> 55#include <linux/prefetch.h> 56 57#include "cpl5_cmd.h" 58#include "sge.h" 59#include "regs.h" 60#include "espi.h" 61 62/* This belongs in if_ether.h */ 63#define ETH_P_CPL5 0xf 64 65#define SGE_CMDQ_N 2 66#define SGE_FREELQ_N 2 67#define SGE_CMDQ0_E_N 1024 68#define SGE_CMDQ1_E_N 128 69#define SGE_FREEL_SIZE 4096 70#define SGE_JUMBO_FREEL_SIZE 512 71#define SGE_FREEL_REFILL_THRESH 16 72#define SGE_RESPQ_E_N 1024 73#define SGE_INTRTIMER_NRES 1000 74#define SGE_RX_SM_BUF_SIZE 1536 75#define SGE_TX_DESC_MAX_PLEN 16384 76 77#define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) 78 79/* 80 * Period of the TX buffer reclaim timer. This timer does not need to run 81 * frequently as TX buffers are usually reclaimed by new TX packets. 82 */ 83#define TX_RECLAIM_PERIOD (HZ / 4) 84 85#define M_CMD_LEN 0x7fffffff 86#define V_CMD_LEN(v) (v) 87#define G_CMD_LEN(v) ((v) & M_CMD_LEN) 88#define V_CMD_GEN1(v) ((v) << 31) 89#define V_CMD_GEN2(v) (v) 90#define F_CMD_DATAVALID (1 << 1) 91#define F_CMD_SOP (1 << 2) 92#define V_CMD_EOP(v) ((v) << 3) 93 94/* 95 * Command queue, receive buffer list, and response queue descriptors. 96 */ 97#if defined(__BIG_ENDIAN_BITFIELD) 98struct cmdQ_e { 99 u32 addr_lo; 100 u32 len_gen; 101 u32 flags; 102 u32 addr_hi; 103}; 104 105struct freelQ_e { 106 u32 addr_lo; 107 u32 len_gen; 108 u32 gen2; 109 u32 addr_hi; 110}; 111 112struct respQ_e { 113 u32 Qsleeping : 4; 114 u32 Cmdq1CreditReturn : 5; 115 u32 Cmdq1DmaComplete : 5; 116 u32 Cmdq0CreditReturn : 5; 117 u32 Cmdq0DmaComplete : 5; 118 u32 FreelistQid : 2; 119 u32 CreditValid : 1; 120 u32 DataValid : 1; 121 u32 Offload : 1; 122 u32 Eop : 1; 123 u32 Sop : 1; 124 u32 GenerationBit : 1; 125 u32 BufferLength; 126}; 127#elif defined(__LITTLE_ENDIAN_BITFIELD) 128struct cmdQ_e { 129 u32 len_gen; 130 u32 addr_lo; 131 u32 addr_hi; 132 u32 flags; 133}; 134 135struct freelQ_e { 136 u32 len_gen; 137 u32 addr_lo; 138 u32 addr_hi; 139 u32 gen2; 140}; 141 142struct respQ_e { 143 u32 BufferLength; 144 u32 GenerationBit : 1; 145 u32 Sop : 1; 146 u32 Eop : 1; 147 u32 Offload : 1; 148 u32 DataValid : 1; 149 u32 CreditValid : 1; 150 u32 FreelistQid : 2; 151 u32 Cmdq0DmaComplete : 5; 152 u32 Cmdq0CreditReturn : 5; 153 u32 Cmdq1DmaComplete : 5; 154 u32 Cmdq1CreditReturn : 5; 155 u32 Qsleeping : 4; 156} ; 157#endif 158 159/* 160 * SW Context Command and Freelist Queue Descriptors 161 */ 162struct cmdQ_ce { 163 struct sk_buff *skb; 164 DEFINE_DMA_UNMAP_ADDR(dma_addr); 165 DEFINE_DMA_UNMAP_LEN(dma_len); 166}; 167 168struct freelQ_ce { 169 struct sk_buff *skb; 170 DEFINE_DMA_UNMAP_ADDR(dma_addr); 171 DEFINE_DMA_UNMAP_LEN(dma_len); 172}; 173 174/* 175 * SW command, freelist and response rings 176 */ 177struct cmdQ { 178 unsigned long status; /* HW DMA fetch status */ 179 unsigned int in_use; /* # of in-use command descriptors */ 180 unsigned int size; /* # of descriptors */ 181 unsigned int processed; /* total # of descs HW has processed */ 182 unsigned int cleaned; /* total # of descs SW has reclaimed */ 183 unsigned int stop_thres; /* SW TX queue suspend threshold */ 184 u16 pidx; /* producer index (SW) */ 185 u16 cidx; /* consumer index (HW) */ 186 u8 genbit; /* current generation (=valid) bit */ 187 u8 sop; /* is next entry start of packet? */ 188 struct cmdQ_e *entries; /* HW command descriptor Q */ 189 struct cmdQ_ce *centries; /* SW command context descriptor Q */ 190 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ 191 spinlock_t lock; /* Lock to protect cmdQ enqueuing */ 192}; 193 194struct freelQ { 195 unsigned int credits; /* # of available RX buffers */ 196 unsigned int size; /* free list capacity */ 197 u16 pidx; /* producer index (SW) */ 198 u16 cidx; /* consumer index (HW) */ 199 u16 rx_buffer_size; /* Buffer size on this free list */ 200 u16 dma_offset; /* DMA offset to align IP headers */ 201 u16 recycleq_idx; /* skb recycle q to use */ 202 u8 genbit; /* current generation (=valid) bit */ 203 struct freelQ_e *entries; /* HW freelist descriptor Q */ 204 struct freelQ_ce *centries; /* SW freelist context descriptor Q */ 205 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ 206}; 207 208struct respQ { 209 unsigned int credits; /* credits to be returned to SGE */ 210 unsigned int size; /* # of response Q descriptors */ 211 u16 cidx; /* consumer index (SW) */ 212 u8 genbit; /* current generation(=valid) bit */ 213 struct respQ_e *entries; /* HW response descriptor Q */ 214 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ 215}; 216 217/* Bit flags for cmdQ.status */ 218enum { 219 CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ 220 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ 221}; 222 223/* T204 TX SW scheduler */ 224 225/* Per T204 TX port */ 226struct sched_port { 227 unsigned int avail; /* available bits - quota */ 228 unsigned int drain_bits_per_1024ns; /* drain rate */ 229 unsigned int speed; /* drain rate, mbps */ 230 unsigned int mtu; /* mtu size */ 231 struct sk_buff_head skbq; /* pending skbs */ 232}; 233 234/* Per T204 device */ 235struct sched { 236 ktime_t last_updated; /* last time quotas were computed */ 237 unsigned int max_avail; /* max bits to be sent to any port */ 238 unsigned int port; /* port index (round robin ports) */ 239 unsigned int num; /* num skbs in per port queues */ 240 struct sched_port p[MAX_NPORTS]; 241 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ 242 struct sge *sge; 243}; 244 245static void restart_sched(struct tasklet_struct *t); 246 247 248/* 249 * Main SGE data structure 250 * 251 * Interrupts are handled by a single CPU and it is likely that on a MP system 252 * the application is migrated to another CPU. In that scenario, we try to 253 * separate the RX(in irq context) and TX state in order to decrease memory 254 * contention. 255 */ 256struct sge { 257 struct adapter *adapter; /* adapter backpointer */ 258 struct net_device *netdev; /* netdevice backpointer */ 259 struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ 260 struct respQ respQ; /* response Q */ 261 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ 262 unsigned int rx_pkt_pad; /* RX padding for L2 packets */ 263 unsigned int jumbo_fl; /* jumbo freelist Q index */ 264 unsigned int intrtimer_nres; /* no-resource interrupt timer */ 265 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ 266 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ 267 struct timer_list espibug_timer; 268 unsigned long espibug_timeout; 269 struct sk_buff *espibug_skb[MAX_NPORTS]; 270 u32 sge_control; /* shadow value of sge control reg */ 271 struct sge_intr_counts stats; 272 struct sge_port_stats __percpu *port_stats[MAX_NPORTS]; 273 struct sched *tx_sched; 274 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; 275}; 276 277static const u8 ch_mac_addr[ETH_ALEN] = { 278 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 279}; 280 281/* 282 * stop tasklet and free all pending skb's 283 */ 284static void tx_sched_stop(struct sge *sge) 285{ 286 struct sched *s = sge->tx_sched; 287 int i; 288 289 tasklet_kill(&s->sched_tsk); 290 291 for (i = 0; i < MAX_NPORTS; i++) 292 __skb_queue_purge(&s->p[s->port].skbq); 293} 294 295/* 296 * t1_sched_update_parms() is called when the MTU or link speed changes. It 297 * re-computes scheduler parameters to scope with the change. 298 */ 299unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, 300 unsigned int mtu, unsigned int speed) 301{ 302 struct sched *s = sge->tx_sched; 303 struct sched_port *p = &s->p[port]; 304 unsigned int max_avail_segs; 305 306 pr_debug("%s mtu=%d speed=%d\n", __func__, mtu, speed); 307 if (speed) 308 p->speed = speed; 309 if (mtu) 310 p->mtu = mtu; 311 312 if (speed || mtu) { 313 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); 314 do_div(drain, (p->mtu + 50) * 1000); 315 p->drain_bits_per_1024ns = (unsigned int) drain; 316 317 if (p->speed < 1000) 318 p->drain_bits_per_1024ns = 319 90 * p->drain_bits_per_1024ns / 100; 320 } 321 322 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { 323 p->drain_bits_per_1024ns -= 16; 324 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); 325 max_avail_segs = max(1U, 4096 / (p->mtu - 40)); 326 } else { 327 s->max_avail = 16384; 328 max_avail_segs = max(1U, 9000 / (p->mtu - 40)); 329 } 330 331 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " 332 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, 333 p->speed, s->max_avail, max_avail_segs, 334 p->drain_bits_per_1024ns); 335 336 return max_avail_segs * (p->mtu - 40); 337} 338 339#if 0 340 341/* 342 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of 343 * data that can be pushed per port. 344 */ 345void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) 346{ 347 struct sched *s = sge->tx_sched; 348 unsigned int i; 349 350 s->max_avail = val; 351 for (i = 0; i < MAX_NPORTS; i++) 352 t1_sched_update_parms(sge, i, 0, 0); 353} 354 355/* 356 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port 357 * is draining. 358 */ 359void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, 360 unsigned int val) 361{ 362 struct sched *s = sge->tx_sched; 363 struct sched_port *p = &s->p[port]; 364 p->drain_bits_per_1024ns = val * 1024 / 1000; 365 t1_sched_update_parms(sge, port, 0, 0); 366} 367 368#endif /* 0 */ 369 370/* 371 * tx_sched_init() allocates resources and does basic initialization. 372 */ 373static int tx_sched_init(struct sge *sge) 374{ 375 struct sched *s; 376 int i; 377 378 s = kzalloc(sizeof (struct sched), GFP_KERNEL); 379 if (!s) 380 return -ENOMEM; 381 382 pr_debug("tx_sched_init\n"); 383 tasklet_setup(&s->sched_tsk, restart_sched); 384 s->sge = sge; 385 sge->tx_sched = s; 386 387 for (i = 0; i < MAX_NPORTS; i++) { 388 skb_queue_head_init(&s->p[i].skbq); 389 t1_sched_update_parms(sge, i, 1500, 1000); 390 } 391 392 return 0; 393} 394 395/* 396 * sched_update_avail() computes the delta since the last time it was called 397 * and updates the per port quota (number of bits that can be sent to the any 398 * port). 399 */ 400static inline int sched_update_avail(struct sge *sge) 401{ 402 struct sched *s = sge->tx_sched; 403 ktime_t now = ktime_get(); 404 unsigned int i; 405 long long delta_time_ns; 406 407 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); 408 409 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); 410 if (delta_time_ns < 15000) 411 return 0; 412 413 for (i = 0; i < MAX_NPORTS; i++) { 414 struct sched_port *p = &s->p[i]; 415 unsigned int delta_avail; 416 417 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; 418 p->avail = min(p->avail + delta_avail, s->max_avail); 419 } 420 421 s->last_updated = now; 422 423 return 1; 424} 425 426/* 427 * sched_skb() is called from two different places. In the tx path, any 428 * packet generating load on an output port will call sched_skb() 429 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq 430 * context (skb == NULL). 431 * The scheduler only returns a skb (which will then be sent) if the 432 * length of the skb is <= the current quota of the output port. 433 */ 434static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, 435 unsigned int credits) 436{ 437 struct sched *s = sge->tx_sched; 438 struct sk_buff_head *skbq; 439 unsigned int i, len, update = 1; 440 441 pr_debug("sched_skb %p\n", skb); 442 if (!skb) { 443 if (!s->num) 444 return NULL; 445 } else { 446 skbq = &s->p[skb->dev->if_port].skbq; 447 __skb_queue_tail(skbq, skb); 448 s->num++; 449 skb = NULL; 450 } 451 452 if (credits < MAX_SKB_FRAGS + 1) 453 goto out; 454 455again: 456 for (i = 0; i < MAX_NPORTS; i++) { 457 s->port = (s->port + 1) & (MAX_NPORTS - 1); 458 skbq = &s->p[s->port].skbq; 459 460 skb = skb_peek(skbq); 461 462 if (!skb) 463 continue; 464 465 len = skb->len; 466 if (len <= s->p[s->port].avail) { 467 s->p[s->port].avail -= len; 468 s->num--; 469 __skb_unlink(skb, skbq); 470 goto out; 471 } 472 skb = NULL; 473 } 474 475 if (update-- && sched_update_avail(sge)) 476 goto again; 477 478out: 479 /* If there are more pending skbs, we use the hardware to schedule us 480 * again. 481 */ 482 if (s->num && !skb) { 483 struct cmdQ *q = &sge->cmdQ[0]; 484 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 485 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { 486 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 487 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); 488 } 489 } 490 pr_debug("sched_skb ret %p\n", skb); 491 492 return skb; 493} 494 495/* 496 * PIO to indicate that memory mapped Q contains valid descriptor(s). 497 */ 498static inline void doorbell_pio(struct adapter *adapter, u32 val) 499{ 500 wmb(); 501 writel(val, adapter->regs + A_SG_DOORBELL); 502} 503 504/* 505 * Frees all RX buffers on the freelist Q. The caller must make sure that 506 * the SGE is turned off before calling this function. 507 */ 508static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) 509{ 510 unsigned int cidx = q->cidx; 511 512 while (q->credits--) { 513 struct freelQ_ce *ce = &q->centries[cidx]; 514 515 dma_unmap_single(&pdev->dev, dma_unmap_addr(ce, dma_addr), 516 dma_unmap_len(ce, dma_len), DMA_FROM_DEVICE); 517 dev_kfree_skb(ce->skb); 518 ce->skb = NULL; 519 if (++cidx == q->size) 520 cidx = 0; 521 } 522} 523 524/* 525 * Free RX free list and response queue resources. 526 */ 527static void free_rx_resources(struct sge *sge) 528{ 529 struct pci_dev *pdev = sge->adapter->pdev; 530 unsigned int size, i; 531 532 if (sge->respQ.entries) { 533 size = sizeof(struct respQ_e) * sge->respQ.size; 534 dma_free_coherent(&pdev->dev, size, sge->respQ.entries, 535 sge->respQ.dma_addr); 536 } 537 538 for (i = 0; i < SGE_FREELQ_N; i++) { 539 struct freelQ *q = &sge->freelQ[i]; 540 541 if (q->centries) { 542 free_freelQ_buffers(pdev, q); 543 kfree(q->centries); 544 } 545 if (q->entries) { 546 size = sizeof(struct freelQ_e) * q->size; 547 dma_free_coherent(&pdev->dev, size, q->entries, 548 q->dma_addr); 549 } 550 } 551} 552 553/* 554 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a 555 * response queue. 556 */ 557static int alloc_rx_resources(struct sge *sge, struct sge_params *p) 558{ 559 struct pci_dev *pdev = sge->adapter->pdev; 560 unsigned int size, i; 561 562 for (i = 0; i < SGE_FREELQ_N; i++) { 563 struct freelQ *q = &sge->freelQ[i]; 564 565 q->genbit = 1; 566 q->size = p->freelQ_size[i]; 567 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; 568 size = sizeof(struct freelQ_e) * q->size; 569 q->entries = dma_alloc_coherent(&pdev->dev, size, 570 &q->dma_addr, GFP_KERNEL); 571 if (!q->entries) 572 goto err_no_mem; 573 574 size = sizeof(struct freelQ_ce) * q->size; 575 q->centries = kzalloc(size, GFP_KERNEL); 576 if (!q->centries) 577 goto err_no_mem; 578 } 579 580 /* 581 * Calculate the buffer sizes for the two free lists. FL0 accommodates 582 * regular sized Ethernet frames, FL1 is sized not to exceed 16K, 583 * including all the sk_buff overhead. 584 * 585 * Note: For T2 FL0 and FL1 are reversed. 586 */ 587 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + 588 sizeof(struct cpl_rx_data) + 589 sge->freelQ[!sge->jumbo_fl].dma_offset; 590 591 size = (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 592 593 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; 594 595 /* 596 * Setup which skb recycle Q should be used when recycling buffers from 597 * each free list. 598 */ 599 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; 600 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; 601 602 sge->respQ.genbit = 1; 603 sge->respQ.size = SGE_RESPQ_E_N; 604 sge->respQ.credits = 0; 605 size = sizeof(struct respQ_e) * sge->respQ.size; 606 sge->respQ.entries = 607 dma_alloc_coherent(&pdev->dev, size, &sge->respQ.dma_addr, 608 GFP_KERNEL); 609 if (!sge->respQ.entries) 610 goto err_no_mem; 611 return 0; 612 613err_no_mem: 614 free_rx_resources(sge); 615 return -ENOMEM; 616} 617 618/* 619 * Reclaims n TX descriptors and frees the buffers associated with them. 620 */ 621static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) 622{ 623 struct cmdQ_ce *ce; 624 struct pci_dev *pdev = sge->adapter->pdev; 625 unsigned int cidx = q->cidx; 626 627 q->in_use -= n; 628 ce = &q->centries[cidx]; 629 while (n--) { 630 if (likely(dma_unmap_len(ce, dma_len))) { 631 dma_unmap_single(&pdev->dev, 632 dma_unmap_addr(ce, dma_addr), 633 dma_unmap_len(ce, dma_len), 634 DMA_TO_DEVICE); 635 if (q->sop) 636 q->sop = 0; 637 } 638 if (ce->skb) { 639 dev_kfree_skb_any(ce->skb); 640 q->sop = 1; 641 } 642 ce++; 643 if (++cidx == q->size) { 644 cidx = 0; 645 ce = q->centries; 646 } 647 } 648 q->cidx = cidx; 649} 650 651/* 652 * Free TX resources. 653 * 654 * Assumes that SGE is stopped and all interrupts are disabled. 655 */ 656static void free_tx_resources(struct sge *sge) 657{ 658 struct pci_dev *pdev = sge->adapter->pdev; 659 unsigned int size, i; 660 661 for (i = 0; i < SGE_CMDQ_N; i++) { 662 struct cmdQ *q = &sge->cmdQ[i]; 663 664 if (q->centries) { 665 if (q->in_use) 666 free_cmdQ_buffers(sge, q, q->in_use); 667 kfree(q->centries); 668 } 669 if (q->entries) { 670 size = sizeof(struct cmdQ_e) * q->size; 671 dma_free_coherent(&pdev->dev, size, q->entries, 672 q->dma_addr); 673 } 674 } 675} 676 677/* 678 * Allocates basic TX resources, consisting of memory mapped command Qs. 679 */ 680static int alloc_tx_resources(struct sge *sge, struct sge_params *p) 681{ 682 struct pci_dev *pdev = sge->adapter->pdev; 683 unsigned int size, i; 684 685 for (i = 0; i < SGE_CMDQ_N; i++) { 686 struct cmdQ *q = &sge->cmdQ[i]; 687 688 q->genbit = 1; 689 q->sop = 1; 690 q->size = p->cmdQ_size[i]; 691 q->in_use = 0; 692 q->status = 0; 693 q->processed = q->cleaned = 0; 694 q->stop_thres = 0; 695 spin_lock_init(&q->lock); 696 size = sizeof(struct cmdQ_e) * q->size; 697 q->entries = dma_alloc_coherent(&pdev->dev, size, 698 &q->dma_addr, GFP_KERNEL); 699 if (!q->entries) 700 goto err_no_mem; 701 702 size = sizeof(struct cmdQ_ce) * q->size; 703 q->centries = kzalloc(size, GFP_KERNEL); 704 if (!q->centries) 705 goto err_no_mem; 706 } 707 708 /* 709 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE 710 * only. For queue 0 set the stop threshold so we can handle one more 711 * packet from each port, plus reserve an additional 24 entries for 712 * Ethernet packets only. Queue 1 never suspends nor do we reserve 713 * space for Ethernet packets. 714 */ 715 sge->cmdQ[0].stop_thres = sge->adapter->params.nports * 716 (MAX_SKB_FRAGS + 1); 717 return 0; 718 719err_no_mem: 720 free_tx_resources(sge); 721 return -ENOMEM; 722} 723 724static inline void setup_ring_params(struct adapter *adapter, u64 addr, 725 u32 size, int base_reg_lo, 726 int base_reg_hi, int size_reg) 727{ 728 writel((u32)addr, adapter->regs + base_reg_lo); 729 writel(addr >> 32, adapter->regs + base_reg_hi); 730 writel(size, adapter->regs + size_reg); 731} 732 733/* 734 * Enable/disable VLAN acceleration. 735 */ 736void t1_vlan_mode(struct adapter *adapter, netdev_features_t features) 737{ 738 struct sge *sge = adapter->sge; 739 740 if (features & NETIF_F_HW_VLAN_CTAG_RX) 741 sge->sge_control |= F_VLAN_XTRACT; 742 else 743 sge->sge_control &= ~F_VLAN_XTRACT; 744 if (adapter->open_device_map) { 745 writel(sge->sge_control, adapter->regs + A_SG_CONTROL); 746 readl(adapter->regs + A_SG_CONTROL); /* flush */ 747 } 748} 749 750/* 751 * Programs the various SGE registers. However, the engine is not yet enabled, 752 * but sge->sge_control is setup and ready to go. 753 */ 754static void configure_sge(struct sge *sge, struct sge_params *p) 755{ 756 struct adapter *ap = sge->adapter; 757 758 writel(0, ap->regs + A_SG_CONTROL); 759 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, 760 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); 761 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, 762 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); 763 setup_ring_params(ap, sge->freelQ[0].dma_addr, 764 sge->freelQ[0].size, A_SG_FL0BASELWR, 765 A_SG_FL0BASEUPR, A_SG_FL0SIZE); 766 setup_ring_params(ap, sge->freelQ[1].dma_addr, 767 sge->freelQ[1].size, A_SG_FL1BASELWR, 768 A_SG_FL1BASEUPR, A_SG_FL1SIZE); 769 770 /* The threshold comparison uses <. */ 771 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); 772 773 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, 774 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); 775 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); 776 777 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | 778 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | 779 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | 780 V_RX_PKT_OFFSET(sge->rx_pkt_pad); 781 782#if defined(__BIG_ENDIAN_BITFIELD) 783 sge->sge_control |= F_ENABLE_BIG_ENDIAN; 784#endif 785 786 /* Initialize no-resource timer */ 787 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); 788 789 t1_sge_set_coalesce_params(sge, p); 790} 791 792/* 793 * Return the payload capacity of the jumbo free-list buffers. 794 */ 795static inline unsigned int jumbo_payload_capacity(const struct sge *sge) 796{ 797 return sge->freelQ[sge->jumbo_fl].rx_buffer_size - 798 sge->freelQ[sge->jumbo_fl].dma_offset - 799 sizeof(struct cpl_rx_data); 800} 801 802/* 803 * Frees all SGE related resources and the sge structure itself 804 */ 805void t1_sge_destroy(struct sge *sge) 806{ 807 int i; 808 809 for_each_port(sge->adapter, i) 810 free_percpu(sge->port_stats[i]); 811 812 kfree(sge->tx_sched); 813 free_tx_resources(sge); 814 free_rx_resources(sge); 815 kfree(sge); 816} 817 818/* 819 * Allocates new RX buffers on the freelist Q (and tracks them on the freelist 820 * context Q) until the Q is full or alloc_skb fails. 821 * 822 * It is possible that the generation bits already match, indicating that the 823 * buffer is already valid and nothing needs to be done. This happens when we 824 * copied a received buffer into a new sk_buff during the interrupt processing. 825 * 826 * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), 827 * we specify a RX_OFFSET in order to make sure that the IP header is 4B 828 * aligned. 829 */ 830static void refill_free_list(struct sge *sge, struct freelQ *q) 831{ 832 struct pci_dev *pdev = sge->adapter->pdev; 833 struct freelQ_ce *ce = &q->centries[q->pidx]; 834 struct freelQ_e *e = &q->entries[q->pidx]; 835 unsigned int dma_len = q->rx_buffer_size - q->dma_offset; 836 837 while (q->credits < q->size) { 838 struct sk_buff *skb; 839 dma_addr_t mapping; 840 841 skb = dev_alloc_skb(q->rx_buffer_size); 842 if (!skb) 843 break; 844 845 skb_reserve(skb, q->dma_offset); 846 mapping = dma_map_single(&pdev->dev, skb->data, dma_len, 847 DMA_FROM_DEVICE); 848 skb_reserve(skb, sge->rx_pkt_pad); 849 850 ce->skb = skb; 851 dma_unmap_addr_set(ce, dma_addr, mapping); 852 dma_unmap_len_set(ce, dma_len, dma_len); 853 e->addr_lo = (u32)mapping; 854 e->addr_hi = (u64)mapping >> 32; 855 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); 856 wmb(); 857 e->gen2 = V_CMD_GEN2(q->genbit); 858 859 e++; 860 ce++; 861 if (++q->pidx == q->size) { 862 q->pidx = 0; 863 q->genbit ^= 1; 864 ce = q->centries; 865 e = q->entries; 866 } 867 q->credits++; 868 } 869} 870 871/* 872 * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 873 * of both rings, we go into 'few interrupt mode' in order to give the system 874 * time to free up resources. 875 */ 876static void freelQs_empty(struct sge *sge) 877{ 878 struct adapter *adapter = sge->adapter; 879 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); 880 u32 irqholdoff_reg; 881 882 refill_free_list(sge, &sge->freelQ[0]); 883 refill_free_list(sge, &sge->freelQ[1]); 884 885 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && 886 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { 887 irq_reg |= F_FL_EXHAUSTED; 888 irqholdoff_reg = sge->fixed_intrtimer; 889 } else { 890 /* Clear the F_FL_EXHAUSTED interrupts for now */ 891 irq_reg &= ~F_FL_EXHAUSTED; 892 irqholdoff_reg = sge->intrtimer_nres; 893 } 894 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); 895 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); 896 897 /* We reenable the Qs to force a freelist GTS interrupt later */ 898 doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); 899} 900 901#define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) 902#define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) 903#define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ 904 F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) 905 906/* 907 * Disable SGE Interrupts 908 */ 909void t1_sge_intr_disable(struct sge *sge) 910{ 911 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); 912 913 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); 914 writel(0, sge->adapter->regs + A_SG_INT_ENABLE); 915} 916 917/* 918 * Enable SGE interrupts. 919 */ 920void t1_sge_intr_enable(struct sge *sge) 921{ 922 u32 en = SGE_INT_ENABLE; 923 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); 924 925 if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO) 926 en &= ~F_PACKET_TOO_BIG; 927 writel(en, sge->adapter->regs + A_SG_INT_ENABLE); 928 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); 929} 930 931/* 932 * Clear SGE interrupts. 933 */ 934void t1_sge_intr_clear(struct sge *sge) 935{ 936 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); 937 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); 938} 939 940/* 941 * SGE 'Error' interrupt handler 942 */ 943int t1_sge_intr_error_handler(struct sge *sge) 944{ 945 struct adapter *adapter = sge->adapter; 946 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); 947 948 if (adapter->port[0].dev->hw_features & NETIF_F_TSO) 949 cause &= ~F_PACKET_TOO_BIG; 950 if (cause & F_RESPQ_EXHAUSTED) 951 sge->stats.respQ_empty++; 952 if (cause & F_RESPQ_OVERFLOW) { 953 sge->stats.respQ_overflow++; 954 pr_alert("%s: SGE response queue overflow\n", 955 adapter->name); 956 } 957 if (cause & F_FL_EXHAUSTED) { 958 sge->stats.freelistQ_empty++; 959 freelQs_empty(sge); 960 } 961 if (cause & F_PACKET_TOO_BIG) { 962 sge->stats.pkt_too_big++; 963 pr_alert("%s: SGE max packet size exceeded\n", 964 adapter->name); 965 } 966 if (cause & F_PACKET_MISMATCH) { 967 sge->stats.pkt_mismatch++; 968 pr_alert("%s: SGE packet mismatch\n", adapter->name); 969 } 970 if (cause & SGE_INT_FATAL) 971 t1_fatal_err(adapter); 972 973 writel(cause, adapter->regs + A_SG_INT_CAUSE); 974 return 0; 975} 976 977const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) 978{ 979 return &sge->stats; 980} 981 982void t1_sge_get_port_stats(const struct sge *sge, int port, 983 struct sge_port_stats *ss) 984{ 985 int cpu; 986 987 memset(ss, 0, sizeof(*ss)); 988 for_each_possible_cpu(cpu) { 989 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); 990 991 ss->rx_cso_good += st->rx_cso_good; 992 ss->tx_cso += st->tx_cso; 993 ss->tx_tso += st->tx_tso; 994 ss->tx_need_hdrroom += st->tx_need_hdrroom; 995 ss->vlan_xtract += st->vlan_xtract; 996 ss->vlan_insert += st->vlan_insert; 997 } 998} 999 1000/** 1001 * recycle_fl_buf - recycle a free list buffer 1002 * @fl: the free list 1003 * @idx: index of buffer to recycle 1004 * 1005 * Recycles the specified buffer on the given free list by adding it at 1006 * the next available slot on the list. 1007 */ 1008static void recycle_fl_buf(struct freelQ *fl, int idx) 1009{ 1010 struct freelQ_e *from = &fl->entries[idx]; 1011 struct freelQ_e *to = &fl->entries[fl->pidx]; 1012 1013 fl->centries[fl->pidx] = fl->centries[idx]; 1014 to->addr_lo = from->addr_lo; 1015 to->addr_hi = from->addr_hi; 1016 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); 1017 wmb(); 1018 to->gen2 = V_CMD_GEN2(fl->genbit); 1019 fl->credits++; 1020 1021 if (++fl->pidx == fl->size) { 1022 fl->pidx = 0; 1023 fl->genbit ^= 1; 1024 } 1025} 1026 1027static int copybreak __read_mostly = 256; 1028module_param(copybreak, int, 0); 1029MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 1030 1031/** 1032 * get_packet - return the next ingress packet buffer 1033 * @adapter: the adapter that received the packet 1034 * @fl: the SGE free list holding the packet 1035 * @len: the actual packet length, excluding any SGE padding 1036 * 1037 * Get the next packet from a free list and complete setup of the 1038 * sk_buff. If the packet is small we make a copy and recycle the 1039 * original buffer, otherwise we use the original buffer itself. If a 1040 * positive drop threshold is supplied packets are dropped and their 1041 * buffers recycled if (a) the number of remaining buffers is under the 1042 * threshold and the packet is too big to copy, or (b) the packet should 1043 * be copied but there is no memory for the copy. 1044 */ 1045static inline struct sk_buff *get_packet(struct adapter *adapter, 1046 struct freelQ *fl, unsigned int len) 1047{ 1048 const struct freelQ_ce *ce = &fl->centries[fl->cidx]; 1049 struct pci_dev *pdev = adapter->pdev; 1050 struct sk_buff *skb; 1051 1052 if (len < copybreak) { 1053 skb = napi_alloc_skb(&adapter->napi, len); 1054 if (!skb) 1055 goto use_orig_buf; 1056 1057 skb_put(skb, len); 1058 dma_sync_single_for_cpu(&pdev->dev, 1059 dma_unmap_addr(ce, dma_addr), 1060 dma_unmap_len(ce, dma_len), 1061 DMA_FROM_DEVICE); 1062 skb_copy_from_linear_data(ce->skb, skb->data, len); 1063 dma_sync_single_for_device(&pdev->dev, 1064 dma_unmap_addr(ce, dma_addr), 1065 dma_unmap_len(ce, dma_len), 1066 DMA_FROM_DEVICE); 1067 recycle_fl_buf(fl, fl->cidx); 1068 return skb; 1069 } 1070 1071use_orig_buf: 1072 if (fl->credits < 2) { 1073 recycle_fl_buf(fl, fl->cidx); 1074 return NULL; 1075 } 1076 1077 dma_unmap_single(&pdev->dev, dma_unmap_addr(ce, dma_addr), 1078 dma_unmap_len(ce, dma_len), DMA_FROM_DEVICE); 1079 skb = ce->skb; 1080 prefetch(skb->data); 1081 1082 skb_put(skb, len); 1083 return skb; 1084} 1085 1086/** 1087 * unexpected_offload - handle an unexpected offload packet 1088 * @adapter: the adapter 1089 * @fl: the free list that received the packet 1090 * 1091 * Called when we receive an unexpected offload packet (e.g., the TOE 1092 * function is disabled or the card is a NIC). Prints a message and 1093 * recycles the buffer. 1094 */ 1095static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) 1096{ 1097 struct freelQ_ce *ce = &fl->centries[fl->cidx]; 1098 struct sk_buff *skb = ce->skb; 1099 1100 dma_sync_single_for_cpu(&adapter->pdev->dev, 1101 dma_unmap_addr(ce, dma_addr), 1102 dma_unmap_len(ce, dma_len), DMA_FROM_DEVICE); 1103 pr_err("%s: unexpected offload packet, cmd %u\n", 1104 adapter->name, *skb->data); 1105 recycle_fl_buf(fl, fl->cidx); 1106} 1107 1108/* 1109 * T1/T2 SGE limits the maximum DMA size per TX descriptor to 1110 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the 1111 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. 1112 * Note that the *_large_page_tx_descs stuff will be optimized out when 1113 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. 1114 * 1115 * compute_large_page_descs() computes how many additional descriptors are 1116 * required to break down the stack's request. 1117 */ 1118static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) 1119{ 1120 unsigned int count = 0; 1121 1122 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { 1123 unsigned int nfrags = skb_shinfo(skb)->nr_frags; 1124 unsigned int i, len = skb_headlen(skb); 1125 while (len > SGE_TX_DESC_MAX_PLEN) { 1126 count++; 1127 len -= SGE_TX_DESC_MAX_PLEN; 1128 } 1129 for (i = 0; nfrags--; i++) { 1130 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1131 len = skb_frag_size(frag); 1132 while (len > SGE_TX_DESC_MAX_PLEN) { 1133 count++; 1134 len -= SGE_TX_DESC_MAX_PLEN; 1135 } 1136 } 1137 } 1138 return count; 1139} 1140 1141/* 1142 * Write a cmdQ entry. 1143 * 1144 * Since this function writes the 'flags' field, it must not be used to 1145 * write the first cmdQ entry. 1146 */ 1147static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, 1148 unsigned int len, unsigned int gen, 1149 unsigned int eop) 1150{ 1151 BUG_ON(len > SGE_TX_DESC_MAX_PLEN); 1152 1153 e->addr_lo = (u32)mapping; 1154 e->addr_hi = (u64)mapping >> 32; 1155 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); 1156 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); 1157} 1158 1159/* 1160 * See comment for previous function. 1161 * 1162 * write_tx_descs_large_page() writes additional SGE tx descriptors if 1163 * *desc_len exceeds HW's capability. 1164 */ 1165static inline unsigned int write_large_page_tx_descs(unsigned int pidx, 1166 struct cmdQ_e **e, 1167 struct cmdQ_ce **ce, 1168 unsigned int *gen, 1169 dma_addr_t *desc_mapping, 1170 unsigned int *desc_len, 1171 unsigned int nfrags, 1172 struct cmdQ *q) 1173{ 1174 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { 1175 struct cmdQ_e *e1 = *e; 1176 struct cmdQ_ce *ce1 = *ce; 1177 1178 while (*desc_len > SGE_TX_DESC_MAX_PLEN) { 1179 *desc_len -= SGE_TX_DESC_MAX_PLEN; 1180 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, 1181 *gen, nfrags == 0 && *desc_len == 0); 1182 ce1->skb = NULL; 1183 dma_unmap_len_set(ce1, dma_len, 0); 1184 *desc_mapping += SGE_TX_DESC_MAX_PLEN; 1185 if (*desc_len) { 1186 ce1++; 1187 e1++; 1188 if (++pidx == q->size) { 1189 pidx = 0; 1190 *gen ^= 1; 1191 ce1 = q->centries; 1192 e1 = q->entries; 1193 } 1194 } 1195 } 1196 *e = e1; 1197 *ce = ce1; 1198 } 1199 return pidx; 1200} 1201 1202/* 1203 * Write the command descriptors to transmit the given skb starting at 1204 * descriptor pidx with the given generation. 1205 */ 1206static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, 1207 unsigned int pidx, unsigned int gen, 1208 struct cmdQ *q) 1209{ 1210 dma_addr_t mapping, desc_mapping; 1211 struct cmdQ_e *e, *e1; 1212 struct cmdQ_ce *ce; 1213 unsigned int i, flags, first_desc_len, desc_len, 1214 nfrags = skb_shinfo(skb)->nr_frags; 1215 1216 e = e1 = &q->entries[pidx]; 1217 ce = &q->centries[pidx]; 1218 1219 mapping = dma_map_single(&adapter->pdev->dev, skb->data, 1220 skb_headlen(skb), DMA_TO_DEVICE); 1221 1222 desc_mapping = mapping; 1223 desc_len = skb_headlen(skb); 1224 1225 flags = F_CMD_DATAVALID | F_CMD_SOP | 1226 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | 1227 V_CMD_GEN2(gen); 1228 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? 1229 desc_len : SGE_TX_DESC_MAX_PLEN; 1230 e->addr_lo = (u32)desc_mapping; 1231 e->addr_hi = (u64)desc_mapping >> 32; 1232 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); 1233 ce->skb = NULL; 1234 dma_unmap_len_set(ce, dma_len, 0); 1235 1236 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && 1237 desc_len > SGE_TX_DESC_MAX_PLEN) { 1238 desc_mapping += first_desc_len; 1239 desc_len -= first_desc_len; 1240 e1++; 1241 ce++; 1242 if (++pidx == q->size) { 1243 pidx = 0; 1244 gen ^= 1; 1245 e1 = q->entries; 1246 ce = q->centries; 1247 } 1248 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, 1249 &desc_mapping, &desc_len, 1250 nfrags, q); 1251 1252 if (likely(desc_len)) 1253 write_tx_desc(e1, desc_mapping, desc_len, gen, 1254 nfrags == 0); 1255 } 1256 1257 ce->skb = NULL; 1258 dma_unmap_addr_set(ce, dma_addr, mapping); 1259 dma_unmap_len_set(ce, dma_len, skb_headlen(skb)); 1260 1261 for (i = 0; nfrags--; i++) { 1262 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1263 e1++; 1264 ce++; 1265 if (++pidx == q->size) { 1266 pidx = 0; 1267 gen ^= 1; 1268 e1 = q->entries; 1269 ce = q->centries; 1270 } 1271 1272 mapping = skb_frag_dma_map(&adapter->pdev->dev, frag, 0, 1273 skb_frag_size(frag), DMA_TO_DEVICE); 1274 desc_mapping = mapping; 1275 desc_len = skb_frag_size(frag); 1276 1277 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, 1278 &desc_mapping, &desc_len, 1279 nfrags, q); 1280 if (likely(desc_len)) 1281 write_tx_desc(e1, desc_mapping, desc_len, gen, 1282 nfrags == 0); 1283 ce->skb = NULL; 1284 dma_unmap_addr_set(ce, dma_addr, mapping); 1285 dma_unmap_len_set(ce, dma_len, skb_frag_size(frag)); 1286 } 1287 ce->skb = skb; 1288 wmb(); 1289 e->flags = flags; 1290} 1291 1292/* 1293 * Clean up completed Tx buffers. 1294 */ 1295static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) 1296{ 1297 unsigned int reclaim = q->processed - q->cleaned; 1298 1299 if (reclaim) { 1300 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", 1301 q->processed, q->cleaned); 1302 free_cmdQ_buffers(sge, q, reclaim); 1303 q->cleaned += reclaim; 1304 } 1305} 1306 1307/* 1308 * Called from tasklet. Checks the scheduler for any 1309 * pending skbs that can be sent. 1310 */ 1311static void restart_sched(struct tasklet_struct *t) 1312{ 1313 struct sched *s = from_tasklet(s, t, sched_tsk); 1314 struct sge *sge = s->sge; 1315 struct adapter *adapter = sge->adapter; 1316 struct cmdQ *q = &sge->cmdQ[0]; 1317 struct sk_buff *skb; 1318 unsigned int credits, queued_skb = 0; 1319 1320 spin_lock(&q->lock); 1321 reclaim_completed_tx(sge, q); 1322 1323 credits = q->size - q->in_use; 1324 pr_debug("restart_sched credits=%d\n", credits); 1325 while ((skb = sched_skb(sge, NULL, credits)) != NULL) { 1326 unsigned int genbit, pidx, count; 1327 count = 1 + skb_shinfo(skb)->nr_frags; 1328 count += compute_large_page_tx_descs(skb); 1329 q->in_use += count; 1330 genbit = q->genbit; 1331 pidx = q->pidx; 1332 q->pidx += count; 1333 if (q->pidx >= q->size) { 1334 q->pidx -= q->size; 1335 q->genbit ^= 1; 1336 } 1337 write_tx_descs(adapter, skb, pidx, genbit, q); 1338 credits = q->size - q->in_use; 1339 queued_skb = 1; 1340 } 1341 1342 if (queued_skb) { 1343 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 1344 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { 1345 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 1346 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1347 } 1348 } 1349 spin_unlock(&q->lock); 1350} 1351 1352/** 1353 * sge_rx - process an ingress ethernet packet 1354 * @sge: the sge structure 1355 * @fl: the free list that contains the packet buffer 1356 * @len: the packet length 1357 * 1358 * Process an ingress ethernet pakcet and deliver it to the stack. 1359 */ 1360static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) 1361{ 1362 struct sk_buff *skb; 1363 const struct cpl_rx_pkt *p; 1364 struct adapter *adapter = sge->adapter; 1365 struct sge_port_stats *st; 1366 struct net_device *dev; 1367 1368 skb = get_packet(adapter, fl, len - sge->rx_pkt_pad); 1369 if (unlikely(!skb)) { 1370 sge->stats.rx_drops++; 1371 return; 1372 } 1373 1374 p = (const struct cpl_rx_pkt *) skb->data; 1375 if (p->iff >= adapter->params.nports) { 1376 kfree_skb(skb); 1377 return; 1378 } 1379 __skb_pull(skb, sizeof(*p)); 1380 1381 st = this_cpu_ptr(sge->port_stats[p->iff]); 1382 dev = adapter->port[p->iff].dev; 1383 1384 skb->protocol = eth_type_trans(skb, dev); 1385 if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff && 1386 skb->protocol == htons(ETH_P_IP) && 1387 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { 1388 ++st->rx_cso_good; 1389 skb->ip_summed = CHECKSUM_UNNECESSARY; 1390 } else 1391 skb_checksum_none_assert(skb); 1392 1393 if (p->vlan_valid) { 1394 st->vlan_xtract++; 1395 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(p->vlan)); 1396 } 1397 netif_receive_skb(skb); 1398} 1399 1400/* 1401 * Returns true if a command queue has enough available descriptors that 1402 * we can resume Tx operation after temporarily disabling its packet queue. 1403 */ 1404static inline int enough_free_Tx_descs(const struct cmdQ *q) 1405{ 1406 unsigned int r = q->processed - q->cleaned; 1407 1408 return q->in_use - r < (q->size >> 1); 1409} 1410 1411/* 1412 * Called when sufficient space has become available in the SGE command queues 1413 * after the Tx packet schedulers have been suspended to restart the Tx path. 1414 */ 1415static void restart_tx_queues(struct sge *sge) 1416{ 1417 struct adapter *adap = sge->adapter; 1418 int i; 1419 1420 if (!enough_free_Tx_descs(&sge->cmdQ[0])) 1421 return; 1422 1423 for_each_port(adap, i) { 1424 struct net_device *nd = adap->port[i].dev; 1425 1426 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && 1427 netif_running(nd)) { 1428 sge->stats.cmdQ_restarted[2]++; 1429 netif_wake_queue(nd); 1430 } 1431 } 1432} 1433 1434/* 1435 * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 1436 * information. 1437 */ 1438static unsigned int update_tx_info(struct adapter *adapter, 1439 unsigned int flags, 1440 unsigned int pr0) 1441{ 1442 struct sge *sge = adapter->sge; 1443 struct cmdQ *cmdq = &sge->cmdQ[0]; 1444 1445 cmdq->processed += pr0; 1446 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { 1447 freelQs_empty(sge); 1448 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); 1449 } 1450 if (flags & F_CMDQ0_ENABLE) { 1451 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1452 1453 if (cmdq->cleaned + cmdq->in_use != cmdq->processed && 1454 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { 1455 set_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1456 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1457 } 1458 if (sge->tx_sched) 1459 tasklet_hi_schedule(&sge->tx_sched->sched_tsk); 1460 1461 flags &= ~F_CMDQ0_ENABLE; 1462 } 1463 1464 if (unlikely(sge->stopped_tx_queues != 0)) 1465 restart_tx_queues(sge); 1466 1467 return flags; 1468} 1469 1470/* 1471 * Process SGE responses, up to the supplied budget. Returns the number of 1472 * responses processed. A negative budget is effectively unlimited. 1473 */ 1474static int process_responses(struct adapter *adapter, int budget) 1475{ 1476 struct sge *sge = adapter->sge; 1477 struct respQ *q = &sge->respQ; 1478 struct respQ_e *e = &q->entries[q->cidx]; 1479 int done = 0; 1480 unsigned int flags = 0; 1481 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; 1482 1483 while (done < budget && e->GenerationBit == q->genbit) { 1484 flags |= e->Qsleeping; 1485 1486 cmdq_processed[0] += e->Cmdq0CreditReturn; 1487 cmdq_processed[1] += e->Cmdq1CreditReturn; 1488 1489 /* We batch updates to the TX side to avoid cacheline 1490 * ping-pong of TX state information on MP where the sender 1491 * might run on a different CPU than this function... 1492 */ 1493 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) { 1494 flags = update_tx_info(adapter, flags, cmdq_processed[0]); 1495 cmdq_processed[0] = 0; 1496 } 1497 1498 if (unlikely(cmdq_processed[1] > 16)) { 1499 sge->cmdQ[1].processed += cmdq_processed[1]; 1500 cmdq_processed[1] = 0; 1501 } 1502 1503 if (likely(e->DataValid)) { 1504 struct freelQ *fl = &sge->freelQ[e->FreelistQid]; 1505 1506 BUG_ON(!e->Sop || !e->Eop); 1507 if (unlikely(e->Offload)) 1508 unexpected_offload(adapter, fl); 1509 else 1510 sge_rx(sge, fl, e->BufferLength); 1511 1512 ++done; 1513 1514 /* 1515 * Note: this depends on each packet consuming a 1516 * single free-list buffer; cf. the BUG above. 1517 */ 1518 if (++fl->cidx == fl->size) 1519 fl->cidx = 0; 1520 prefetch(fl->centries[fl->cidx].skb); 1521 1522 if (unlikely(--fl->credits < 1523 fl->size - SGE_FREEL_REFILL_THRESH)) 1524 refill_free_list(sge, fl); 1525 } else 1526 sge->stats.pure_rsps++; 1527 1528 e++; 1529 if (unlikely(++q->cidx == q->size)) { 1530 q->cidx = 0; 1531 q->genbit ^= 1; 1532 e = q->entries; 1533 } 1534 prefetch(e); 1535 1536 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { 1537 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); 1538 q->credits = 0; 1539 } 1540 } 1541 1542 flags = update_tx_info(adapter, flags, cmdq_processed[0]); 1543 sge->cmdQ[1].processed += cmdq_processed[1]; 1544 1545 return done; 1546} 1547 1548static inline int responses_pending(const struct adapter *adapter) 1549{ 1550 const struct respQ *Q = &adapter->sge->respQ; 1551 const struct respQ_e *e = &Q->entries[Q->cidx]; 1552 1553 return e->GenerationBit == Q->genbit; 1554} 1555 1556/* 1557 * A simpler version of process_responses() that handles only pure (i.e., 1558 * non data-carrying) responses. Such respones are too light-weight to justify 1559 * calling a softirq when using NAPI, so we handle them specially in hard 1560 * interrupt context. The function is called with a pointer to a response, 1561 * which the caller must ensure is a valid pure response. Returns 1 if it 1562 * encounters a valid data-carrying response, 0 otherwise. 1563 */ 1564static int process_pure_responses(struct adapter *adapter) 1565{ 1566 struct sge *sge = adapter->sge; 1567 struct respQ *q = &sge->respQ; 1568 struct respQ_e *e = &q->entries[q->cidx]; 1569 const struct freelQ *fl = &sge->freelQ[e->FreelistQid]; 1570 unsigned int flags = 0; 1571 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; 1572 1573 prefetch(fl->centries[fl->cidx].skb); 1574 if (e->DataValid) 1575 return 1; 1576 1577 do { 1578 flags |= e->Qsleeping; 1579 1580 cmdq_processed[0] += e->Cmdq0CreditReturn; 1581 cmdq_processed[1] += e->Cmdq1CreditReturn; 1582 1583 e++; 1584 if (unlikely(++q->cidx == q->size)) { 1585 q->cidx = 0; 1586 q->genbit ^= 1; 1587 e = q->entries; 1588 } 1589 prefetch(e); 1590 1591 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { 1592 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); 1593 q->credits = 0; 1594 } 1595 sge->stats.pure_rsps++; 1596 } while (e->GenerationBit == q->genbit && !e->DataValid); 1597 1598 flags = update_tx_info(adapter, flags, cmdq_processed[0]); 1599 sge->cmdQ[1].processed += cmdq_processed[1]; 1600 1601 return e->GenerationBit == q->genbit; 1602} 1603 1604/* 1605 * Handler for new data events when using NAPI. This does not need any locking 1606 * or protection from interrupts as data interrupts are off at this point and 1607 * other adapter interrupts do not interfere. 1608 */ 1609int t1_poll(struct napi_struct *napi, int budget) 1610{ 1611 struct adapter *adapter = container_of(napi, struct adapter, napi); 1612 int work_done = process_responses(adapter, budget); 1613 1614 if (likely(work_done < budget)) { 1615 napi_complete_done(napi, work_done); 1616 writel(adapter->sge->respQ.cidx, 1617 adapter->regs + A_SG_SLEEPING); 1618 } 1619 return work_done; 1620} 1621 1622irqreturn_t t1_interrupt(int irq, void *data) 1623{ 1624 struct adapter *adapter = data; 1625 struct sge *sge = adapter->sge; 1626 int handled; 1627 1628 if (likely(responses_pending(adapter))) { 1629 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); 1630 1631 if (napi_schedule_prep(&adapter->napi)) { 1632 if (process_pure_responses(adapter)) 1633 __napi_schedule(&adapter->napi); 1634 else { 1635 /* no data, no NAPI needed */ 1636 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); 1637 /* undo schedule_prep */ 1638 napi_enable(&adapter->napi); 1639 } 1640 } 1641 return IRQ_HANDLED; 1642 } 1643 1644 spin_lock(&adapter->async_lock); 1645 handled = t1_slow_intr_handler(adapter); 1646 spin_unlock(&adapter->async_lock); 1647 1648 if (!handled) 1649 sge->stats.unhandled_irqs++; 1650 1651 return IRQ_RETVAL(handled != 0); 1652} 1653 1654/* 1655 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. 1656 * 1657 * The code figures out how many entries the sk_buff will require in the 1658 * cmdQ and updates the cmdQ data structure with the state once the enqueue 1659 * has complete. Then, it doesn't access the global structure anymore, but 1660 * uses the corresponding fields on the stack. In conjunction with a spinlock 1661 * around that code, we can make the function reentrant without holding the 1662 * lock when we actually enqueue (which might be expensive, especially on 1663 * architectures with IO MMUs). 1664 * 1665 * This runs with softirqs disabled. 1666 */ 1667static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, 1668 unsigned int qid, struct net_device *dev) 1669{ 1670 struct sge *sge = adapter->sge; 1671 struct cmdQ *q = &sge->cmdQ[qid]; 1672 unsigned int credits, pidx, genbit, count, use_sched_skb = 0; 1673 1674 spin_lock(&q->lock); 1675 1676 reclaim_completed_tx(sge, q); 1677 1678 pidx = q->pidx; 1679 credits = q->size - q->in_use; 1680 count = 1 + skb_shinfo(skb)->nr_frags; 1681 count += compute_large_page_tx_descs(skb); 1682 1683 /* Ethernet packet */ 1684 if (unlikely(credits < count)) { 1685 if (!netif_queue_stopped(dev)) { 1686 netif_stop_queue(dev); 1687 set_bit(dev->if_port, &sge->stopped_tx_queues); 1688 sge->stats.cmdQ_full[2]++; 1689 pr_err("%s: Tx ring full while queue awake!\n", 1690 adapter->name); 1691 } 1692 spin_unlock(&q->lock); 1693 return NETDEV_TX_BUSY; 1694 } 1695 1696 if (unlikely(credits - count < q->stop_thres)) { 1697 netif_stop_queue(dev); 1698 set_bit(dev->if_port, &sge->stopped_tx_queues); 1699 sge->stats.cmdQ_full[2]++; 1700 } 1701 1702 /* T204 cmdQ0 skbs that are destined for a certain port have to go 1703 * through the scheduler. 1704 */ 1705 if (sge->tx_sched && !qid && skb->dev) { 1706use_sched: 1707 use_sched_skb = 1; 1708 /* Note that the scheduler might return a different skb than 1709 * the one passed in. 1710 */ 1711 skb = sched_skb(sge, skb, credits); 1712 if (!skb) { 1713 spin_unlock(&q->lock); 1714 return NETDEV_TX_OK; 1715 } 1716 pidx = q->pidx; 1717 count = 1 + skb_shinfo(skb)->nr_frags; 1718 count += compute_large_page_tx_descs(skb); 1719 } 1720 1721 q->in_use += count; 1722 genbit = q->genbit; 1723 pidx = q->pidx; 1724 q->pidx += count; 1725 if (q->pidx >= q->size) { 1726 q->pidx -= q->size; 1727 q->genbit ^= 1; 1728 } 1729 spin_unlock(&q->lock); 1730 1731 write_tx_descs(adapter, skb, pidx, genbit, q); 1732 1733 /* 1734 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring 1735 * the doorbell if the Q is asleep. There is a natural race, where 1736 * the hardware is going to sleep just after we checked, however, 1737 * then the interrupt handler will detect the outstanding TX packet 1738 * and ring the doorbell for us. 1739 */ 1740 if (qid) 1741 doorbell_pio(adapter, F_CMDQ1_ENABLE); 1742 else { 1743 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 1744 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { 1745 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); 1746 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1747 } 1748 } 1749 1750 if (use_sched_skb) { 1751 if (spin_trylock(&q->lock)) { 1752 credits = q->size - q->in_use; 1753 skb = NULL; 1754 goto use_sched; 1755 } 1756 } 1757 return NETDEV_TX_OK; 1758} 1759 1760#define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) 1761 1762/* 1763 * eth_hdr_len - return the length of an Ethernet header 1764 * @data: pointer to the start of the Ethernet header 1765 * 1766 * Returns the length of an Ethernet header, including optional VLAN tag. 1767 */ 1768static inline int eth_hdr_len(const void *data) 1769{ 1770 const struct ethhdr *e = data; 1771 1772 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; 1773} 1774 1775/* 1776 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. 1777 */ 1778netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev) 1779{ 1780 struct adapter *adapter = dev->ml_priv; 1781 struct sge *sge = adapter->sge; 1782 struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]); 1783 struct cpl_tx_pkt *cpl; 1784 struct sk_buff *orig_skb = skb; 1785 int ret; 1786 1787 if (skb->protocol == htons(ETH_P_CPL5)) 1788 goto send; 1789 1790 /* 1791 * We are using a non-standard hard_header_len. 1792 * Allocate more header room in the rare cases it is not big enough. 1793 */ 1794 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { 1795 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso)); 1796 ++st->tx_need_hdrroom; 1797 dev_kfree_skb_any(orig_skb); 1798 if (!skb) 1799 return NETDEV_TX_OK; 1800 } 1801 1802 if (skb_shinfo(skb)->gso_size) { 1803 int eth_type; 1804 struct cpl_tx_pkt_lso *hdr; 1805 1806 ++st->tx_tso; 1807 1808 eth_type = skb_network_offset(skb) == ETH_HLEN ? 1809 CPL_ETH_II : CPL_ETH_II_VLAN; 1810 1811 hdr = skb_push(skb, sizeof(*hdr)); 1812 hdr->opcode = CPL_TX_PKT_LSO; 1813 hdr->ip_csum_dis = hdr->l4_csum_dis = 0; 1814 hdr->ip_hdr_words = ip_hdr(skb)->ihl; 1815 hdr->tcp_hdr_words = tcp_hdr(skb)->doff; 1816 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, 1817 skb_shinfo(skb)->gso_size)); 1818 hdr->len = htonl(skb->len - sizeof(*hdr)); 1819 cpl = (struct cpl_tx_pkt *)hdr; 1820 } else { 1821 /* 1822 * Packets shorter than ETH_HLEN can break the MAC, drop them 1823 * early. Also, we may get oversized packets because some 1824 * parts of the kernel don't handle our unusual hard_header_len 1825 * right, drop those too. 1826 */ 1827 if (unlikely(skb->len < ETH_HLEN || 1828 skb->len > dev->mtu + eth_hdr_len(skb->data))) { 1829 netdev_dbg(dev, "packet size %d hdr %d mtu%d\n", 1830 skb->len, eth_hdr_len(skb->data), dev->mtu); 1831 dev_kfree_skb_any(skb); 1832 return NETDEV_TX_OK; 1833 } 1834 1835 if (skb->ip_summed == CHECKSUM_PARTIAL && 1836 ip_hdr(skb)->protocol == IPPROTO_UDP) { 1837 if (unlikely(skb_checksum_help(skb))) { 1838 netdev_dbg(dev, "unable to do udp checksum\n"); 1839 dev_kfree_skb_any(skb); 1840 return NETDEV_TX_OK; 1841 } 1842 } 1843 1844 /* Hmmm, assuming to catch the gratious arp... and we'll use 1845 * it to flush out stuck espi packets... 1846 */ 1847 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { 1848 if (skb->protocol == htons(ETH_P_ARP) && 1849 arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) { 1850 adapter->sge->espibug_skb[dev->if_port] = skb; 1851 /* We want to re-use this skb later. We 1852 * simply bump the reference count and it 1853 * will not be freed... 1854 */ 1855 skb = skb_get(skb); 1856 } 1857 } 1858 1859 cpl = __skb_push(skb, sizeof(*cpl)); 1860 cpl->opcode = CPL_TX_PKT; 1861 cpl->ip_csum_dis = 1; /* SW calculates IP csum */ 1862 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; 1863 /* the length field isn't used so don't bother setting it */ 1864 1865 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); 1866 } 1867 cpl->iff = dev->if_port; 1868 1869 if (skb_vlan_tag_present(skb)) { 1870 cpl->vlan_valid = 1; 1871 cpl->vlan = htons(skb_vlan_tag_get(skb)); 1872 st->vlan_insert++; 1873 } else 1874 cpl->vlan_valid = 0; 1875 1876send: 1877 ret = t1_sge_tx(skb, adapter, 0, dev); 1878 1879 /* If transmit busy, and we reallocated skb's due to headroom limit, 1880 * then silently discard to avoid leak. 1881 */ 1882 if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { 1883 dev_kfree_skb_any(skb); 1884 ret = NETDEV_TX_OK; 1885 } 1886 return ret; 1887} 1888 1889/* 1890 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. 1891 */ 1892static void sge_tx_reclaim_cb(struct timer_list *t) 1893{ 1894 int i; 1895 struct sge *sge = from_timer(sge, t, tx_reclaim_timer); 1896 1897 for (i = 0; i < SGE_CMDQ_N; ++i) { 1898 struct cmdQ *q = &sge->cmdQ[i]; 1899 1900 if (!spin_trylock(&q->lock)) 1901 continue; 1902 1903 reclaim_completed_tx(sge, q); 1904 if (i == 0 && q->in_use) { /* flush pending credits */ 1905 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); 1906 } 1907 spin_unlock(&q->lock); 1908 } 1909 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 1910} 1911 1912/* 1913 * Propagate changes of the SGE coalescing parameters to the HW. 1914 */ 1915int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) 1916{ 1917 sge->fixed_intrtimer = p->rx_coalesce_usecs * 1918 core_ticks_per_usec(sge->adapter); 1919 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); 1920 return 0; 1921} 1922 1923/* 1924 * Allocates both RX and TX resources and configures the SGE. However, 1925 * the hardware is not enabled yet. 1926 */ 1927int t1_sge_configure(struct sge *sge, struct sge_params *p) 1928{ 1929 if (alloc_rx_resources(sge, p)) 1930 return -ENOMEM; 1931 if (alloc_tx_resources(sge, p)) { 1932 free_rx_resources(sge); 1933 return -ENOMEM; 1934 } 1935 configure_sge(sge, p); 1936 1937 /* 1938 * Now that we have sized the free lists calculate the payload 1939 * capacity of the large buffers. Other parts of the driver use 1940 * this to set the max offload coalescing size so that RX packets 1941 * do not overflow our large buffers. 1942 */ 1943 p->large_buf_capacity = jumbo_payload_capacity(sge); 1944 return 0; 1945} 1946 1947/* 1948 * Disables the DMA engine. 1949 */ 1950void t1_sge_stop(struct sge *sge) 1951{ 1952 int i; 1953 writel(0, sge->adapter->regs + A_SG_CONTROL); 1954 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 1955 1956 if (is_T2(sge->adapter)) 1957 del_timer_sync(&sge->espibug_timer); 1958 1959 del_timer_sync(&sge->tx_reclaim_timer); 1960 if (sge->tx_sched) 1961 tx_sched_stop(sge); 1962 1963 for (i = 0; i < MAX_NPORTS; i++) 1964 kfree_skb(sge->espibug_skb[i]); 1965} 1966 1967/* 1968 * Enables the DMA engine. 1969 */ 1970void t1_sge_start(struct sge *sge) 1971{ 1972 refill_free_list(sge, &sge->freelQ[0]); 1973 refill_free_list(sge, &sge->freelQ[1]); 1974 1975 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); 1976 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); 1977 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 1978 1979 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 1980 1981 if (is_T2(sge->adapter)) 1982 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 1983} 1984 1985/* 1986 * Callback for the T2 ESPI 'stuck packet feature' workaorund 1987 */ 1988static void espibug_workaround_t204(struct timer_list *t) 1989{ 1990 struct sge *sge = from_timer(sge, t, espibug_timer); 1991 struct adapter *adapter = sge->adapter; 1992 unsigned int nports = adapter->params.nports; 1993 u32 seop[MAX_NPORTS]; 1994 1995 if (adapter->open_device_map & PORT_MASK) { 1996 int i; 1997 1998 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) 1999 return; 2000 2001 for (i = 0; i < nports; i++) { 2002 struct sk_buff *skb = sge->espibug_skb[i]; 2003 2004 if (!netif_running(adapter->port[i].dev) || 2005 netif_queue_stopped(adapter->port[i].dev) || 2006 !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) 2007 continue; 2008 2009 if (!skb->cb[0]) { 2010 skb_copy_to_linear_data_offset(skb, 2011 sizeof(struct cpl_tx_pkt), 2012 ch_mac_addr, 2013 ETH_ALEN); 2014 skb_copy_to_linear_data_offset(skb, 2015 skb->len - 10, 2016 ch_mac_addr, 2017 ETH_ALEN); 2018 skb->cb[0] = 0xff; 2019 } 2020 2021 /* bump the reference count to avoid freeing of 2022 * the skb once the DMA has completed. 2023 */ 2024 skb = skb_get(skb); 2025 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); 2026 } 2027 } 2028 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2029} 2030 2031static void espibug_workaround(struct timer_list *t) 2032{ 2033 struct sge *sge = from_timer(sge, t, espibug_timer); 2034 struct adapter *adapter = sge->adapter; 2035 2036 if (netif_running(adapter->port[0].dev)) { 2037 struct sk_buff *skb = sge->espibug_skb[0]; 2038 u32 seop = t1_espi_get_mon(adapter, 0x930, 0); 2039 2040 if ((seop & 0xfff0fff) == 0xfff && skb) { 2041 if (!skb->cb[0]) { 2042 skb_copy_to_linear_data_offset(skb, 2043 sizeof(struct cpl_tx_pkt), 2044 ch_mac_addr, 2045 ETH_ALEN); 2046 skb_copy_to_linear_data_offset(skb, 2047 skb->len - 10, 2048 ch_mac_addr, 2049 ETH_ALEN); 2050 skb->cb[0] = 0xff; 2051 } 2052 2053 /* bump the reference count to avoid freeing of the 2054 * skb once the DMA has completed. 2055 */ 2056 skb = skb_get(skb); 2057 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); 2058 } 2059 } 2060 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2061} 2062 2063/* 2064 * Creates a t1_sge structure and returns suggested resource parameters. 2065 */ 2066struct sge *t1_sge_create(struct adapter *adapter, struct sge_params *p) 2067{ 2068 struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); 2069 int i; 2070 2071 if (!sge) 2072 return NULL; 2073 2074 sge->adapter = adapter; 2075 sge->netdev = adapter->port[0].dev; 2076 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; 2077 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; 2078 2079 for_each_port(adapter, i) { 2080 sge->port_stats[i] = alloc_percpu(struct sge_port_stats); 2081 if (!sge->port_stats[i]) 2082 goto nomem_port; 2083 } 2084 2085 timer_setup(&sge->tx_reclaim_timer, sge_tx_reclaim_cb, 0); 2086 2087 if (is_T2(sge->adapter)) { 2088 timer_setup(&sge->espibug_timer, 2089 adapter->params.nports > 1 ? espibug_workaround_t204 : espibug_workaround, 2090 0); 2091 2092 if (adapter->params.nports > 1) 2093 tx_sched_init(sge); 2094 2095 sge->espibug_timeout = 1; 2096 /* for T204, every 10ms */ 2097 if (adapter->params.nports > 1) 2098 sge->espibug_timeout = HZ/100; 2099 } 2100 2101 2102 p->cmdQ_size[0] = SGE_CMDQ0_E_N; 2103 p->cmdQ_size[1] = SGE_CMDQ1_E_N; 2104 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; 2105 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; 2106 if (sge->tx_sched) { 2107 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) 2108 p->rx_coalesce_usecs = 15; 2109 else 2110 p->rx_coalesce_usecs = 50; 2111 } else 2112 p->rx_coalesce_usecs = 50; 2113 2114 p->coalesce_enable = 0; 2115 p->sample_interval_usecs = 0; 2116 2117 return sge; 2118nomem_port: 2119 while (i >= 0) { 2120 free_percpu(sge->port_stats[i]); 2121 --i; 2122 } 2123 kfree(sge); 2124 return NULL; 2125 2126} 2127