1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Linux network driver for QLogic BR-series Converged Network Adapter. 4 */ 5/* 6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 7 * Copyright (c) 2014-2015 QLogic Corporation 8 * All rights reserved 9 * www.qlogic.com 10 */ 11 12/* 13 * bfi_reg.h ASIC register defines for all QLogic BR-series adapter ASICs 14 */ 15 16#ifndef __BFI_REG_H__ 17#define __BFI_REG_H__ 18 19#define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */ 20#define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */ 21#define HOSTFN2_INT_STATUS 0x00014300 /* ct */ 22#define HOSTFN3_INT_STATUS 0x00014400 /* ct */ 23#define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */ 24#define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */ 25#define HOSTFN2_INT_MSK 0x00014304 /* ct */ 26#define HOSTFN3_INT_MSK 0x00014404 /* ct */ 27 28#define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */ 29#define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */ 30#define HOST_PAGE_NUM_FN2 0x00014308 /* ct */ 31#define HOST_PAGE_NUM_FN3 0x00014408 /* ct */ 32 33#define APP_PLL_LCLK_CTL_REG 0x00014204 /* cb/ct */ 34#define __P_LCLK_PLL_LOCK 0x80000000 35#define __APP_PLL_LCLK_SRAM_USE_100MHZ 0x00100000 36#define __APP_PLL_LCLK_RESET_TIMER_MK 0x000e0000 37#define __APP_PLL_LCLK_RESET_TIMER_SH 17 38#define __APP_PLL_LCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH) 39#define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000 40#define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000 41#define __APP_PLL_LCLK_CNTLMT0_1_SH 14 42#define __APP_PLL_LCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH) 43#define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000 44#define __APP_PLL_LCLK_JITLMT0_1_SH 12 45#define __APP_PLL_LCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH) 46#define __APP_PLL_LCLK_HREF 0x00000800 47#define __APP_PLL_LCLK_HDIV 0x00000400 48#define __APP_PLL_LCLK_P0_1_MK 0x00000300 49#define __APP_PLL_LCLK_P0_1_SH 8 50#define __APP_PLL_LCLK_P0_1(_v) ((_v) << __APP_PLL_LCLK_P0_1_SH) 51#define __APP_PLL_LCLK_Z0_2_MK 0x000000e0 52#define __APP_PLL_LCLK_Z0_2_SH 5 53#define __APP_PLL_LCLK_Z0_2(_v) ((_v) << __APP_PLL_LCLK_Z0_2_SH) 54#define __APP_PLL_LCLK_RSEL200500 0x00000010 55#define __APP_PLL_LCLK_ENARST 0x00000008 56#define __APP_PLL_LCLK_BYPASS 0x00000004 57#define __APP_PLL_LCLK_LRESETN 0x00000002 58#define __APP_PLL_LCLK_ENABLE 0x00000001 59#define APP_PLL_SCLK_CTL_REG 0x00014208 /* cb/ct */ 60#define __P_SCLK_PLL_LOCK 0x80000000 61#define __APP_PLL_SCLK_RESET_TIMER_MK 0x000e0000 62#define __APP_PLL_SCLK_RESET_TIMER_SH 17 63#define __APP_PLL_SCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH) 64#define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000 65#define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000 66#define __APP_PLL_SCLK_CNTLMT0_1_SH 14 67#define __APP_PLL_SCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH) 68#define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000 69#define __APP_PLL_SCLK_JITLMT0_1_SH 12 70#define __APP_PLL_SCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH) 71#define __APP_PLL_SCLK_HREF 0x00000800 72#define __APP_PLL_SCLK_HDIV 0x00000400 73#define __APP_PLL_SCLK_P0_1_MK 0x00000300 74#define __APP_PLL_SCLK_P0_1_SH 8 75#define __APP_PLL_SCLK_P0_1(_v) ((_v) << __APP_PLL_SCLK_P0_1_SH) 76#define __APP_PLL_SCLK_Z0_2_MK 0x000000e0 77#define __APP_PLL_SCLK_Z0_2_SH 5 78#define __APP_PLL_SCLK_Z0_2(_v) ((_v) << __APP_PLL_SCLK_Z0_2_SH) 79#define __APP_PLL_SCLK_RSEL200500 0x00000010 80#define __APP_PLL_SCLK_ENARST 0x00000008 81#define __APP_PLL_SCLK_BYPASS 0x00000004 82#define __APP_PLL_SCLK_LRESETN 0x00000002 83#define __APP_PLL_SCLK_ENABLE 0x00000001 84#define __ENABLE_MAC_AHB_1 0x00800000 /* ct */ 85#define __ENABLE_MAC_AHB_0 0x00400000 /* ct */ 86#define __ENABLE_MAC_1 0x00200000 /* ct */ 87#define __ENABLE_MAC_0 0x00100000 /* ct */ 88 89#define HOST_SEM0_REG 0x00014230 /* cb/ct */ 90#define HOST_SEM1_REG 0x00014234 /* cb/ct */ 91#define HOST_SEM2_REG 0x00014238 /* cb/ct */ 92#define HOST_SEM3_REG 0x0001423c /* cb/ct */ 93#define HOST_SEM4_REG 0x00014610 /* cb/ct */ 94#define HOST_SEM5_REG 0x00014614 /* cb/ct */ 95#define HOST_SEM6_REG 0x00014618 /* cb/ct */ 96#define HOST_SEM7_REG 0x0001461c /* cb/ct */ 97#define HOST_SEM0_INFO_REG 0x00014240 /* cb/ct */ 98#define HOST_SEM1_INFO_REG 0x00014244 /* cb/ct */ 99#define HOST_SEM2_INFO_REG 0x00014248 /* cb/ct */ 100#define HOST_SEM3_INFO_REG 0x0001424c /* cb/ct */ 101#define HOST_SEM4_INFO_REG 0x00014620 /* cb/ct */ 102#define HOST_SEM5_INFO_REG 0x00014624 /* cb/ct */ 103#define HOST_SEM6_INFO_REG 0x00014628 /* cb/ct */ 104#define HOST_SEM7_INFO_REG 0x0001462c /* cb/ct */ 105 106#define HOSTFN0_LPU0_CMD_STAT 0x00019000 /* cb/ct */ 107#define HOSTFN0_LPU1_CMD_STAT 0x00019004 /* cb/ct */ 108#define HOSTFN1_LPU0_CMD_STAT 0x00019010 /* cb/ct */ 109#define HOSTFN1_LPU1_CMD_STAT 0x00019014 /* cb/ct */ 110#define HOSTFN2_LPU0_CMD_STAT 0x00019150 /* ct */ 111#define HOSTFN2_LPU1_CMD_STAT 0x00019154 /* ct */ 112#define HOSTFN3_LPU0_CMD_STAT 0x00019160 /* ct */ 113#define HOSTFN3_LPU1_CMD_STAT 0x00019164 /* ct */ 114#define LPU0_HOSTFN0_CMD_STAT 0x00019008 /* cb/ct */ 115#define LPU1_HOSTFN0_CMD_STAT 0x0001900c /* cb/ct */ 116#define LPU0_HOSTFN1_CMD_STAT 0x00019018 /* cb/ct */ 117#define LPU1_HOSTFN1_CMD_STAT 0x0001901c /* cb/ct */ 118#define LPU0_HOSTFN2_CMD_STAT 0x00019158 /* ct */ 119#define LPU1_HOSTFN2_CMD_STAT 0x0001915c /* ct */ 120#define LPU0_HOSTFN3_CMD_STAT 0x00019168 /* ct */ 121#define LPU1_HOSTFN3_CMD_STAT 0x0001916c /* ct */ 122 123#define PSS_CTL_REG 0x00018800 /* cb/ct */ 124#define __PSS_I2C_CLK_DIV_MK 0x007f0000 125#define __PSS_I2C_CLK_DIV_SH 16 126#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH) 127#define __PSS_LMEM_INIT_DONE 0x00001000 128#define __PSS_LMEM_RESET 0x00000200 129#define __PSS_LMEM_INIT_EN 0x00000100 130#define __PSS_LPU1_RESET 0x00000002 131#define __PSS_LPU0_RESET 0x00000001 132#define PSS_ERR_STATUS_REG 0x00018810 /* cb/ct */ 133#define ERR_SET_REG 0x00018818 /* cb/ct */ 134#define PSS_GPIO_OUT_REG 0x000188c0 /* cb/ct */ 135#define __PSS_GPIO_OUT_REG 0x00000fff 136#define PSS_GPIO_OE_REG 0x000188c8 /* cb/ct */ 137#define __PSS_GPIO_OE_REG 0x000000ff 138 139#define HOSTFN0_LPU_MBOX0_0 0x00019200 /* cb/ct */ 140#define HOSTFN1_LPU_MBOX0_8 0x00019260 /* cb/ct */ 141#define LPU_HOSTFN0_MBOX0_0 0x00019280 /* cb/ct */ 142#define LPU_HOSTFN1_MBOX0_8 0x000192e0 /* cb/ct */ 143#define HOSTFN2_LPU_MBOX0_0 0x00019400 /* ct */ 144#define HOSTFN3_LPU_MBOX0_8 0x00019460 /* ct */ 145#define LPU_HOSTFN2_MBOX0_0 0x00019480 /* ct */ 146#define LPU_HOSTFN3_MBOX0_8 0x000194e0 /* ct */ 147 148#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c /* ct */ 149#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c /* ct */ 150#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c /* ct */ 151#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c /* ct */ 152 153#define MBIST_CTL_REG 0x00014220 /* ct */ 154#define __EDRAM_BISTR_START 0x00000004 155#define MBIST_STAT_REG 0x00014224 /* ct */ 156#define ETH_MAC_SER_REG 0x00014288 /* ct */ 157#define __APP_EMS_CKBUFAMPIN 0x00000020 158#define __APP_EMS_REFCLKSEL 0x00000010 159#define __APP_EMS_CMLCKSEL 0x00000008 160#define __APP_EMS_REFCKBUFEN2 0x00000004 161#define __APP_EMS_REFCKBUFEN1 0x00000002 162#define __APP_EMS_CHANNEL_SEL 0x00000001 163#define FNC_PERS_REG 0x00014604 /* ct */ 164#define __F3_FUNCTION_ACTIVE 0x80000000 165#define __F3_FUNCTION_MODE 0x40000000 166#define __F3_PORT_MAP_MK 0x30000000 167#define __F3_PORT_MAP_SH 28 168#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH) 169#define __F3_VM_MODE 0x08000000 170#define __F3_INTX_STATUS_MK 0x07000000 171#define __F3_INTX_STATUS_SH 24 172#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH) 173#define __F2_FUNCTION_ACTIVE 0x00800000 174#define __F2_FUNCTION_MODE 0x00400000 175#define __F2_PORT_MAP_MK 0x00300000 176#define __F2_PORT_MAP_SH 20 177#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH) 178#define __F2_VM_MODE 0x00080000 179#define __F2_INTX_STATUS_MK 0x00070000 180#define __F2_INTX_STATUS_SH 16 181#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH) 182#define __F1_FUNCTION_ACTIVE 0x00008000 183#define __F1_FUNCTION_MODE 0x00004000 184#define __F1_PORT_MAP_MK 0x00003000 185#define __F1_PORT_MAP_SH 12 186#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH) 187#define __F1_VM_MODE 0x00000800 188#define __F1_INTX_STATUS_MK 0x00000700 189#define __F1_INTX_STATUS_SH 8 190#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH) 191#define __F0_FUNCTION_ACTIVE 0x00000080 192#define __F0_FUNCTION_MODE 0x00000040 193#define __F0_PORT_MAP_MK 0x00000030 194#define __F0_PORT_MAP_SH 4 195#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH) 196#define __F0_VM_MODE 0x00000008 197#define __F0_INTX_STATUS 0x00000007 198enum { 199 __F0_INTX_STATUS_MSIX = 0x0, 200 __F0_INTX_STATUS_INTA = 0x1, 201 __F0_INTX_STATUS_INTB = 0x2, 202 __F0_INTX_STATUS_INTC = 0x3, 203 __F0_INTX_STATUS_INTD = 0x4, 204}; 205 206#define OP_MODE 0x0001460c 207#define __APP_ETH_CLK_LOWSPEED 0x00000004 208#define __GLOBAL_CORECLK_HALFSPEED 0x00000002 209#define __GLOBAL_FCOE_MODE 0x00000001 210#define FW_INIT_HALT_P0 0x000191ac 211#define __FW_INIT_HALT_P 0x00000001 212#define FW_INIT_HALT_P1 0x000191bc 213#define PMM_1T_RESET_REG_P0 0x0002381c 214#define __PMM_1T_RESET_P 0x00000001 215#define PMM_1T_RESET_REG_P1 0x00023c1c 216 217/* QLogic BR-series 1860 Adapter specific defines */ 218#define CT2_PCI_CPQ_BASE 0x00030000 219#define CT2_PCI_APP_BASE 0x00030100 220#define CT2_PCI_ETH_BASE 0x00030400 221 222/* 223 * APP block registers 224 */ 225#define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00) 226#define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04) 227#define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08) 228#define __PME_STATUS_ 0x00200000 229#define __PF_VF_BAR_SIZE_MODE__MK 0x00180000 230#define __PF_VF_BAR_SIZE_MODE__SH 19 231#define __PF_VF_BAR_SIZE_MODE_(_v) ((_v) << __PF_VF_BAR_SIZE_MODE__SH) 232#define __FC_LL_PORT_MAP__MK 0x00060000 233#define __FC_LL_PORT_MAP__SH 17 234#define __FC_LL_PORT_MAP_(_v) ((_v) << __FC_LL_PORT_MAP__SH) 235#define __PF_VF_ACTIVE_ 0x00010000 236#define __PF_VF_CFG_RDY_ 0x00008000 237#define __PF_VF_ENABLE_ 0x00004000 238#define __PF_DRIVER_ACTIVE_ 0x00002000 239#define __PF_PME_SEND_ENABLE_ 0x00001000 240#define __PF_EXROM_OFFSET__MK 0x00000ff0 241#define __PF_EXROM_OFFSET__SH 4 242#define __PF_EXROM_OFFSET_(_v) ((_v) << __PF_EXROM_OFFSET__SH) 243#define __FC_LL_MODE_ 0x00000008 244#define __PF_INTX_PIN_ 0x00000007 245#define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C) 246#define __PF_NUM_QUEUES1__MK 0xff000000 247#define __PF_NUM_QUEUES1__SH 24 248#define __PF_NUM_QUEUES1_(_v) ((_v) << __PF_NUM_QUEUES1__SH) 249#define __PF_VF_QUE_OFFSET1__MK 0x00ff0000 250#define __PF_VF_QUE_OFFSET1__SH 16 251#define __PF_VF_QUE_OFFSET1_(_v) ((_v) << __PF_VF_QUE_OFFSET1__SH) 252#define __PF_VF_NUM_QUEUES__MK 0x0000ff00 253#define __PF_VF_NUM_QUEUES__SH 8 254#define __PF_VF_NUM_QUEUES_(_v) ((_v) << __PF_VF_NUM_QUEUES__SH) 255#define __PF_VF_QUE_OFFSET_ 0x000000ff 256#define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18) 257#define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38) 258 259/* 260 * QLogic BR-series 1860 adapter CPQ block registers 261 */ 262#define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00) 263#define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20) 264#define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40) 265#define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60) 266#define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80) 267#define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84) 268#define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88) 269#define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c) 270#define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90) 271#define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94) 272#define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98) 273#define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C) 274#define CT2_HOST_SEM0_REG 0x000148f0 275#define CT2_HOST_SEM1_REG 0x000148f4 276#define CT2_HOST_SEM2_REG 0x000148f8 277#define CT2_HOST_SEM3_REG 0x000148fc 278#define CT2_HOST_SEM4_REG 0x00014900 279#define CT2_HOST_SEM5_REG 0x00014904 280#define CT2_HOST_SEM6_REG 0x00014908 281#define CT2_HOST_SEM7_REG 0x0001490c 282#define CT2_HOST_SEM0_INFO_REG 0x000148b0 283#define CT2_HOST_SEM1_INFO_REG 0x000148b4 284#define CT2_HOST_SEM2_INFO_REG 0x000148b8 285#define CT2_HOST_SEM3_INFO_REG 0x000148bc 286#define CT2_HOST_SEM4_INFO_REG 0x000148c0 287#define CT2_HOST_SEM5_INFO_REG 0x000148c4 288#define CT2_HOST_SEM6_INFO_REG 0x000148c8 289#define CT2_HOST_SEM7_INFO_REG 0x000148cc 290 291#define CT2_APP_PLL_LCLK_CTL_REG 0x00014808 292#define __APP_LPUCLK_HALFSPEED 0x40000000 293#define __APP_PLL_LCLK_LOAD 0x20000000 294#define __APP_PLL_LCLK_FBCNT_MK 0x1fe00000 295#define __APP_PLL_LCLK_FBCNT_SH 21 296#define __APP_PLL_LCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) 297enum { 298 __APP_PLL_LCLK_FBCNT_425_MHZ = 6, 299 __APP_PLL_LCLK_FBCNT_468_MHZ = 4, 300}; 301#define __APP_PLL_LCLK_EXTFB 0x00000800 302#define __APP_PLL_LCLK_ENOUTS 0x00000400 303#define __APP_PLL_LCLK_RATE 0x00000010 304#define CT2_APP_PLL_SCLK_CTL_REG 0x0001480c 305#define __P_SCLK_PLL_LOCK 0x80000000 306#define __APP_PLL_SCLK_REFCLK_SEL 0x40000000 307#define __APP_PLL_SCLK_CLK_DIV2 0x20000000 308#define __APP_PLL_SCLK_LOAD 0x10000000 309#define __APP_PLL_SCLK_FBCNT_MK 0x0ff00000 310#define __APP_PLL_SCLK_FBCNT_SH 20 311#define __APP_PLL_SCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) 312enum { 313 __APP_PLL_SCLK_FBCNT_NORM = 6, 314 __APP_PLL_SCLK_FBCNT_10G_FC = 10, 315}; 316#define __APP_PLL_SCLK_EXTFB 0x00000800 317#define __APP_PLL_SCLK_ENOUTS 0x00000400 318#define __APP_PLL_SCLK_RATE 0x00000010 319#define CT2_PCIE_MISC_REG 0x00014804 320#define __ETH_CLK_ENABLE_PORT1 0x00000010 321#define CT2_CHIP_MISC_PRG 0x000148a4 322#define __ETH_CLK_ENABLE_PORT0 0x00004000 323#define __APP_LPU_SPEED 0x00000002 324#define CT2_MBIST_STAT_REG 0x00014818 325#define CT2_MBIST_CTL_REG 0x0001481c 326#define CT2_PMM_1T_CONTROL_REG_P0 0x0002381c 327#define __PMM_1T_PNDB_P 0x00000002 328#define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c 329#define CT2_WGN_STATUS 0x00014990 330#define __A2T_AHB_LOAD 0x00000800 331#define __WGN_READY 0x00000400 332#define __GLBL_PF_VF_CFG_RDY 0x00000200 333#define CT2_NFC_CSR_CLR_REG 0x00027420 334#define CT2_NFC_CSR_SET_REG 0x00027424 335#define __HALT_NFC_CONTROLLER 0x00000002 336#define __NFC_CONTROLLER_HALTED 0x00001000 337 338#define CT2_RSC_GPR15_REG 0x0002765c 339#define CT2_CSI_FW_CTL_REG 0x00027080 340#define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000 341#define CT2_CSI_FW_CTL_SET_REG 0x00027088 342 343#define CT2_CSI_MAC0_CONTROL_REG 0x000270d0 344#define __CSI_MAC_RESET 0x00000010 345#define __CSI_MAC_AHB_RESET 0x00000008 346#define CT2_CSI_MAC1_CONTROL_REG 0x000270d4 347#define CT2_CSI_MAC_CONTROL_REG(__n) \ 348 (CT2_CSI_MAC0_CONTROL_REG + \ 349 (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG)) 350 351/* 352 * Name semaphore registers based on usage 353 */ 354#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG 355#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG 356#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG 357#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG 358#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG 359#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG 360 361/* 362 * CT2 semaphore register locations changed 363 */ 364#define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG 365#define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG 366#define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG 367#define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG 368#define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG 369#define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG 370 371#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 372#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 373 374/* 375 * And corresponding host interrupt status bit field defines 376 */ 377#define __HFN_INT_CPE_Q0 0x00000001U 378#define __HFN_INT_CPE_Q1 0x00000002U 379#define __HFN_INT_CPE_Q2 0x00000004U 380#define __HFN_INT_CPE_Q3 0x00000008U 381#define __HFN_INT_CPE_Q4 0x00000010U 382#define __HFN_INT_CPE_Q5 0x00000020U 383#define __HFN_INT_CPE_Q6 0x00000040U 384#define __HFN_INT_CPE_Q7 0x00000080U 385#define __HFN_INT_RME_Q0 0x00000100U 386#define __HFN_INT_RME_Q1 0x00000200U 387#define __HFN_INT_RME_Q2 0x00000400U 388#define __HFN_INT_RME_Q3 0x00000800U 389#define __HFN_INT_RME_Q4 0x00001000U 390#define __HFN_INT_RME_Q5 0x00002000U 391#define __HFN_INT_RME_Q6 0x00004000U 392#define __HFN_INT_RME_Q7 0x00008000U 393#define __HFN_INT_ERR_EMC 0x00010000U 394#define __HFN_INT_ERR_LPU0 0x00020000U 395#define __HFN_INT_ERR_LPU1 0x00040000U 396#define __HFN_INT_ERR_PSS 0x00080000U 397#define __HFN_INT_MBOX_LPU0 0x00100000U 398#define __HFN_INT_MBOX_LPU1 0x00200000U 399#define __HFN_INT_MBOX1_LPU0 0x00400000U 400#define __HFN_INT_MBOX1_LPU1 0x00800000U 401#define __HFN_INT_LL_HALT 0x01000000U 402#define __HFN_INT_CPE_MASK 0x000000ffU 403#define __HFN_INT_RME_MASK 0x0000ff00U 404#define __HFN_INT_ERR_MASK \ 405 (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \ 406 __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT) 407#define __HFN_INT_FN0_MASK \ 408 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ 409 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ 410 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0) 411#define __HFN_INT_FN1_MASK \ 412 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ 413 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ 414 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1) 415 416/* 417 * Host interrupt status defines for 1860 418 */ 419#define __HFN_INT_MBOX_LPU0_CT2 0x00010000U 420#define __HFN_INT_MBOX_LPU1_CT2 0x00020000U 421#define __HFN_INT_ERR_PSS_CT2 0x00040000U 422#define __HFN_INT_ERR_LPU0_CT2 0x00080000U 423#define __HFN_INT_ERR_LPU1_CT2 0x00100000U 424#define __HFN_INT_CPQ_HALT_CT2 0x00200000U 425#define __HFN_INT_ERR_WGN_CT2 0x00400000U 426#define __HFN_INT_ERR_LEHRX_CT2 0x00800000U 427#define __HFN_INT_ERR_LEHTX_CT2 0x01000000U 428#define __HFN_INT_ERR_MASK_CT2 \ 429 (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \ 430 __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \ 431 __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \ 432 __HFN_INT_ERR_LEHTX_CT2) 433#define __HFN_INT_FN0_MASK_CT2 \ 434 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ 435 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ 436 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2) 437#define __HFN_INT_FN1_MASK_CT2 \ 438 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ 439 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ 440 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2) 441 442/* 443 * asic memory map. 444 */ 445#define PSS_SMEM_PAGE_START 0x8000 446#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15)) 447#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff) 448 449#endif /* __BFI_REG_H__ */ 450