1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8#include <linux/acpi.h> 9#include <linux/types.h> 10#include <linux/delay.h> 11#include <linux/wait.h> 12#include <linux/mii.h> 13#include <linux/ethtool.h> 14#include <linux/bitops.h> 15#include <linux/netdevice.h> 16#include <linux/platform_device.h> 17#include <linux/phy.h> 18#include <linux/phy_fixed.h> 19#include <linux/brcmphy.h> 20#include <linux/of.h> 21#include <linux/of_net.h> 22#include <linux/of_mdio.h> 23#include <linux/platform_data/bcmgenet.h> 24#include <linux/platform_data/mdio-bcm-unimac.h> 25 26#include "bcmgenet.h" 27 28 29/* setup netdev link state when PHY link status change and 30 * update UMAC and RGMII block when link up 31 */ 32void bcmgenet_mii_setup(struct net_device *dev) 33{ 34 struct bcmgenet_priv *priv = netdev_priv(dev); 35 struct phy_device *phydev = dev->phydev; 36 u32 reg, cmd_bits = 0; 37 bool status_changed = false; 38 39 if (priv->old_link != phydev->link) { 40 status_changed = true; 41 priv->old_link = phydev->link; 42 } 43 44 if (phydev->link) { 45 /* check speed/duplex/pause changes */ 46 if (priv->old_speed != phydev->speed) { 47 status_changed = true; 48 priv->old_speed = phydev->speed; 49 } 50 51 if (priv->old_duplex != phydev->duplex) { 52 status_changed = true; 53 priv->old_duplex = phydev->duplex; 54 } 55 56 if (priv->old_pause != phydev->pause) { 57 status_changed = true; 58 priv->old_pause = phydev->pause; 59 } 60 61 /* done if nothing has changed */ 62 if (!status_changed) 63 return; 64 65 /* speed */ 66 if (phydev->speed == SPEED_1000) 67 cmd_bits = UMAC_SPEED_1000; 68 else if (phydev->speed == SPEED_100) 69 cmd_bits = UMAC_SPEED_100; 70 else 71 cmd_bits = UMAC_SPEED_10; 72 cmd_bits <<= CMD_SPEED_SHIFT; 73 74 /* duplex */ 75 if (phydev->duplex != DUPLEX_FULL) 76 cmd_bits |= CMD_HD_EN; 77 78 /* pause capability */ 79 if (!phydev->pause) 80 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 81 82 /* 83 * Program UMAC and RGMII block based on established 84 * link speed, duplex, and pause. The speed set in 85 * umac->cmd tell RGMII block which clock to use for 86 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 87 * Receive clock is provided by the PHY. 88 */ 89 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 90 reg &= ~OOB_DISABLE; 91 reg |= RGMII_LINK; 92 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 93 94 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 95 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 96 CMD_HD_EN | 97 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 98 reg |= cmd_bits; 99 if (reg & CMD_SW_RESET) { 100 reg &= ~CMD_SW_RESET; 101 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 102 udelay(2); 103 reg |= CMD_TX_EN | CMD_RX_EN; 104 } 105 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 106 107 priv->eee.eee_active = phy_init_eee(phydev, 0) >= 0; 108 bcmgenet_eee_enable_set(dev, 109 priv->eee.eee_enabled && priv->eee.eee_active, 110 priv->eee.tx_lpi_enabled); 111 } else { 112 /* done if nothing has changed */ 113 if (!status_changed) 114 return; 115 116 /* needed for MoCA fixed PHY to reflect correct link status */ 117 netif_carrier_off(dev); 118 } 119 120 phy_print_status(phydev); 121} 122 123 124static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 125 struct fixed_phy_status *status) 126{ 127 struct bcmgenet_priv *priv; 128 u32 reg; 129 130 if (dev && dev->phydev && status) { 131 priv = netdev_priv(dev); 132 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 133 status->link = !!(reg & MODE_LINK_STATUS); 134 } 135 136 return 0; 137} 138 139void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 140{ 141 struct bcmgenet_priv *priv = netdev_priv(dev); 142 u32 reg = 0; 143 144 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 145 if (GENET_IS_V4(priv)) { 146 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 147 if (enable) { 148 reg &= ~EXT_CK25_DIS; 149 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 150 mdelay(1); 151 152 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 153 reg |= EXT_GPHY_RESET; 154 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 155 mdelay(1); 156 157 reg &= ~EXT_GPHY_RESET; 158 } else { 159 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 160 EXT_GPHY_RESET; 161 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 162 mdelay(1); 163 reg |= EXT_CK25_DIS; 164 } 165 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 166 udelay(60); 167 } else { 168 mdelay(1); 169 } 170} 171 172static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 173{ 174 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 175 fixed_phy_set_link_update(priv->dev->phydev, 176 bcmgenet_fixed_phy_link_update); 177} 178 179int bcmgenet_mii_config(struct net_device *dev, bool init) 180{ 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 struct phy_device *phydev = dev->phydev; 183 struct device *kdev = &priv->pdev->dev; 184 const char *phy_name = NULL; 185 u32 id_mode_dis = 0; 186 u32 port_ctrl; 187 u32 reg; 188 189 switch (priv->phy_interface) { 190 case PHY_INTERFACE_MODE_INTERNAL: 191 phy_name = "internal PHY"; 192 fallthrough; 193 case PHY_INTERFACE_MODE_MOCA: 194 /* Irrespective of the actually configured PHY speed (100 or 195 * 1000) GENETv4 only has an internal GPHY so we will just end 196 * up masking the Gigabit features from what we support, not 197 * switching to the EPHY 198 */ 199 if (GENET_IS_V4(priv)) 200 port_ctrl = PORT_MODE_INT_GPHY; 201 else 202 port_ctrl = PORT_MODE_INT_EPHY; 203 204 if (!phy_name) { 205 phy_name = "MoCA"; 206 if (!GENET_IS_V5(priv)) 207 port_ctrl |= LED_ACT_SOURCE_MAC; 208 bcmgenet_moca_phy_setup(priv); 209 } 210 break; 211 212 case PHY_INTERFACE_MODE_MII: 213 phy_name = "external MII"; 214 phy_set_max_speed(phydev, SPEED_100); 215 port_ctrl = PORT_MODE_EXT_EPHY; 216 break; 217 218 case PHY_INTERFACE_MODE_REVMII: 219 phy_name = "external RvMII"; 220 /* of_mdiobus_register took care of reading the 'max-speed' 221 * PHY property for us, effectively limiting the PHY supported 222 * capabilities, use that knowledge to also configure the 223 * Reverse MII interface correctly. 224 */ 225 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 226 dev->phydev->supported)) 227 port_ctrl = PORT_MODE_EXT_RVMII_50; 228 else 229 port_ctrl = PORT_MODE_EXT_RVMII_25; 230 break; 231 232 case PHY_INTERFACE_MODE_RGMII: 233 /* RGMII_NO_ID: TXC transitions at the same time as TXD 234 * (requires PCB or receiver-side delay) 235 * 236 * ID is implicitly disabled for 100Mbps (RG)MII operation. 237 */ 238 phy_name = "external RGMII (no delay)"; 239 id_mode_dis = BIT(16); 240 port_ctrl = PORT_MODE_EXT_GPHY; 241 break; 242 243 case PHY_INTERFACE_MODE_RGMII_TXID: 244 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 245 phy_name = "external RGMII (TX delay)"; 246 port_ctrl = PORT_MODE_EXT_GPHY; 247 break; 248 249 case PHY_INTERFACE_MODE_RGMII_RXID: 250 phy_name = "external RGMII (RX delay)"; 251 port_ctrl = PORT_MODE_EXT_GPHY; 252 break; 253 default: 254 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 255 return -EINVAL; 256 } 257 258 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 259 260 priv->ext_phy = !priv->internal_phy && 261 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 262 263 /* This is an external PHY (xMII), so we need to enable the RGMII 264 * block for the interface to work 265 */ 266 if (priv->ext_phy) { 267 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 268 reg &= ~ID_MODE_DIS; 269 reg |= id_mode_dis; 270 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 271 reg |= RGMII_MODE_EN_V123; 272 else 273 reg |= RGMII_MODE_EN; 274 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 275 } 276 277 if (init) 278 dev_info(kdev, "configuring instance for %s\n", phy_name); 279 280 return 0; 281} 282 283int bcmgenet_mii_probe(struct net_device *dev) 284{ 285 struct bcmgenet_priv *priv = netdev_priv(dev); 286 struct device *kdev = &priv->pdev->dev; 287 struct device_node *dn = kdev->of_node; 288 struct phy_device *phydev; 289 u32 phy_flags = 0; 290 int ret; 291 292 /* Communicate the integrated PHY revision */ 293 if (priv->internal_phy) 294 phy_flags = priv->gphy_rev; 295 296 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 297 priv->old_link = -1; 298 priv->old_speed = -1; 299 priv->old_duplex = -1; 300 priv->old_pause = -1; 301 302 if (dn) { 303 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 304 phy_flags, priv->phy_interface); 305 if (!phydev) { 306 pr_err("could not attach to PHY\n"); 307 return -ENODEV; 308 } 309 } else { 310 if (has_acpi_companion(kdev)) { 311 char mdio_bus_id[MII_BUS_ID_SIZE]; 312 struct mii_bus *unimacbus; 313 314 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 315 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 316 317 unimacbus = mdio_find_bus(mdio_bus_id); 318 if (!unimacbus) { 319 pr_err("Unable to find mii\n"); 320 return -ENODEV; 321 } 322 phydev = phy_find_first(unimacbus); 323 put_device(&unimacbus->dev); 324 if (!phydev) { 325 pr_err("Unable to find PHY\n"); 326 return -ENODEV; 327 } 328 } else { 329 phydev = dev->phydev; 330 } 331 phydev->dev_flags = phy_flags; 332 333 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 334 priv->phy_interface); 335 if (ret) { 336 pr_err("could not attach to PHY\n"); 337 return -ENODEV; 338 } 339 } 340 341 /* Configure port multiplexer based on what the probed PHY device since 342 * reading the 'max-speed' property determines the maximum supported 343 * PHY speed which is needed for bcmgenet_mii_config() to configure 344 * things appropriately. 345 */ 346 ret = bcmgenet_mii_config(dev, true); 347 if (ret) { 348 phy_disconnect(dev->phydev); 349 return ret; 350 } 351 352 linkmode_copy(phydev->advertising, phydev->supported); 353 354 /* The internal PHY has its link interrupts routed to the 355 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 356 * that prevents the signaling of link UP interrupts when 357 * the link operates at 10Mbps, so fallback to polling for 358 * those versions of GENET. 359 */ 360 if (priv->internal_phy && !GENET_IS_V5(priv)) 361 dev->phydev->irq = PHY_IGNORE_INTERRUPT; 362 363 return 0; 364} 365 366static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 367{ 368 struct device_node *dn = priv->pdev->dev.of_node; 369 struct device *kdev = &priv->pdev->dev; 370 char *compat; 371 372 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 373 if (!compat) 374 return NULL; 375 376 priv->mdio_dn = of_get_compatible_child(dn, compat); 377 kfree(compat); 378 if (!priv->mdio_dn) { 379 dev_err(kdev, "unable to find MDIO bus node\n"); 380 return NULL; 381 } 382 383 return priv->mdio_dn; 384} 385 386static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 387 struct unimac_mdio_pdata *ppd) 388{ 389 struct device *kdev = &priv->pdev->dev; 390 struct bcmgenet_platform_data *pd = kdev->platform_data; 391 392 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 393 /* 394 * Internal or external PHY with MDIO access 395 */ 396 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 397 ppd->phy_mask = 1 << pd->phy_address; 398 else 399 ppd->phy_mask = 0; 400 } 401} 402 403static int bcmgenet_mii_wait(void *wait_func_data) 404{ 405 struct bcmgenet_priv *priv = wait_func_data; 406 407 wait_event_timeout(priv->wq, 408 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 409 & MDIO_START_BUSY), 410 HZ / 100); 411 return 0; 412} 413 414static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 415{ 416 struct platform_device *pdev = priv->pdev; 417 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 418 struct device_node *dn = pdev->dev.of_node; 419 struct unimac_mdio_pdata ppd; 420 struct platform_device *ppdev; 421 struct resource *pres, res; 422 int id, ret; 423 424 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 425 if (!pres) { 426 dev_err(&pdev->dev, "Invalid resource\n"); 427 return -EINVAL; 428 } 429 memset(&res, 0, sizeof(res)); 430 memset(&ppd, 0, sizeof(ppd)); 431 432 ppd.wait_func = bcmgenet_mii_wait; 433 ppd.wait_func_data = priv; 434 ppd.bus_name = "bcmgenet MII bus"; 435 436 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 437 * and is 2 * 32-bits word long, 8 bytes total. 438 */ 439 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 440 res.end = res.start + 8; 441 res.flags = IORESOURCE_MEM; 442 443 if (dn) 444 id = of_alias_get_id(dn, "eth"); 445 else 446 id = pdev->id; 447 448 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 449 if (!ppdev) 450 return -ENOMEM; 451 452 /* Retain this platform_device pointer for later cleanup */ 453 priv->mii_pdev = ppdev; 454 ppdev->dev.parent = &pdev->dev; 455 if (dn) 456 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 457 else if (pdata) 458 bcmgenet_mii_pdata_init(priv, &ppd); 459 else 460 ppd.phy_mask = ~0; 461 462 ret = platform_device_add_resources(ppdev, &res, 1); 463 if (ret) 464 goto out; 465 466 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 467 if (ret) 468 goto out; 469 470 ret = platform_device_add(ppdev); 471 if (ret) 472 goto out; 473 474 return 0; 475out: 476 platform_device_put(ppdev); 477 return ret; 478} 479 480static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 481{ 482 struct device *kdev = &priv->pdev->dev; 483 int phy_mode = device_get_phy_mode(kdev); 484 485 if (phy_mode < 0) { 486 dev_err(kdev, "invalid PHY mode property\n"); 487 return phy_mode; 488 } 489 490 priv->phy_interface = phy_mode; 491 492 /* We need to specifically look up whether this PHY interface is 493 * internal or not *before* we even try to probe the PHY driver 494 * over MDIO as we may have shut down the internal PHY for power 495 * saving purposes. 496 */ 497 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 498 priv->internal_phy = true; 499 500 return 0; 501} 502 503static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 504{ 505 struct device_node *dn = priv->pdev->dev.of_node; 506 struct phy_device *phydev; 507 int ret; 508 509 /* Fetch the PHY phandle */ 510 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 511 512 /* In the case of a fixed PHY, the DT node associated 513 * to the PHY is the Ethernet MAC DT node. 514 */ 515 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 516 ret = of_phy_register_fixed_link(dn); 517 if (ret) 518 return ret; 519 520 priv->phy_dn = of_node_get(dn); 521 } 522 523 /* Get the link mode */ 524 ret = bcmgenet_phy_interface_init(priv); 525 if (ret) 526 return ret; 527 528 /* Make sure we initialize MoCA PHYs with a link down */ 529 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 530 phydev = of_phy_find_device(dn); 531 if (phydev) { 532 phydev->link = 0; 533 put_device(&phydev->mdio.dev); 534 } 535 } 536 537 return 0; 538} 539 540static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 541{ 542 struct device *kdev = &priv->pdev->dev; 543 struct bcmgenet_platform_data *pd = kdev->platform_data; 544 char phy_name[MII_BUS_ID_SIZE + 3]; 545 char mdio_bus_id[MII_BUS_ID_SIZE]; 546 struct phy_device *phydev; 547 548 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 549 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 550 551 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 552 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 553 mdio_bus_id, pd->phy_address); 554 555 /* 556 * Internal or external PHY with MDIO access 557 */ 558 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 559 if (!phydev) { 560 dev_err(kdev, "failed to register PHY device\n"); 561 return -ENODEV; 562 } 563 } else { 564 /* 565 * MoCA port or no MDIO access. 566 * Use fixed PHY to represent the link layer. 567 */ 568 struct fixed_phy_status fphy_status = { 569 .link = 1, 570 .speed = pd->phy_speed, 571 .duplex = pd->phy_duplex, 572 .pause = 0, 573 .asym_pause = 0, 574 }; 575 576 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 577 if (IS_ERR(phydev)) { 578 dev_err(kdev, "failed to register fixed PHY device\n"); 579 return -ENODEV; 580 } 581 582 /* Make sure we initialize MoCA PHYs with a link down */ 583 phydev->link = 0; 584 585 } 586 587 priv->phy_interface = pd->phy_interface; 588 589 return 0; 590} 591 592static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 593{ 594 struct device *kdev = &priv->pdev->dev; 595 struct device_node *dn = kdev->of_node; 596 597 if (dn) 598 return bcmgenet_mii_of_init(priv); 599 else if (has_acpi_companion(kdev)) 600 return bcmgenet_phy_interface_init(priv); 601 else 602 return bcmgenet_mii_pd_init(priv); 603} 604 605int bcmgenet_mii_init(struct net_device *dev) 606{ 607 struct bcmgenet_priv *priv = netdev_priv(dev); 608 int ret; 609 610 ret = bcmgenet_mii_register(priv); 611 if (ret) 612 return ret; 613 614 ret = bcmgenet_mii_bus_init(priv); 615 if (ret) 616 goto out; 617 618 return 0; 619 620out: 621 bcmgenet_mii_exit(dev); 622 return ret; 623} 624 625void bcmgenet_mii_exit(struct net_device *dev) 626{ 627 struct bcmgenet_priv *priv = netdev_priv(dev); 628 struct device_node *dn = priv->pdev->dev.of_node; 629 630 if (of_phy_is_fixed_link(dn)) 631 of_phy_deregister_fixed_link(dn); 632 of_node_put(priv->phy_dn); 633 clk_prepare_enable(priv->clk); 634 platform_device_unregister(priv->mii_pdev); 635 clk_disable_unprepare(priv->clk); 636} 637