1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2020 Broadcom 6 */ 7 8#define pr_fmt(fmt) "bcmgenet: " fmt 9 10#include <linux/acpi.h> 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/sched.h> 14#include <linux/types.h> 15#include <linux/fcntl.h> 16#include <linux/interrupt.h> 17#include <linux/string.h> 18#include <linux/if_ether.h> 19#include <linux/init.h> 20#include <linux/errno.h> 21#include <linux/delay.h> 22#include <linux/platform_device.h> 23#include <linux/dma-mapping.h> 24#include <linux/pm.h> 25#include <linux/clk.h> 26#include <net/arp.h> 27 28#include <linux/mii.h> 29#include <linux/ethtool.h> 30#include <linux/netdevice.h> 31#include <linux/inetdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/in.h> 35#include <linux/ip.h> 36#include <linux/ipv6.h> 37#include <linux/phy.h> 38#include <linux/platform_data/bcmgenet.h> 39 40#include <asm/unaligned.h> 41 42#include "bcmgenet.h" 43 44/* Maximum number of hardware queues, downsized if needed */ 45#define GENET_MAX_MQ_CNT 4 46 47/* Default highest priority queue for multi queue support */ 48#define GENET_Q0_PRIORITY 0 49 50#define GENET_Q16_RX_BD_CNT \ 51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 52#define GENET_Q16_TX_BD_CNT \ 53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 54 55#define RX_BUF_LENGTH 2048 56#define SKB_ALIGNMENT 32 57 58/* Tx/Rx DMA register offset, skip 256 descriptors */ 59#define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 60#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 61 62#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 66 TOTAL_DESC * DMA_DESC_SIZE) 67 68/* Forward declarations */ 69static void bcmgenet_set_rx_mode(struct net_device *dev); 70 71static inline void bcmgenet_writel(u32 value, void __iomem *offset) 72{ 73 /* MIPS chips strapped for BE will automagically configure the 74 * peripheral registers for CPU-native byte order. 75 */ 76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 77 __raw_writel(value, offset); 78 else 79 writel_relaxed(value, offset); 80} 81 82static inline u32 bcmgenet_readl(void __iomem *offset) 83{ 84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 85 return __raw_readl(offset); 86 else 87 return readl_relaxed(offset); 88} 89 90static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 91 void __iomem *d, u32 value) 92{ 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 94} 95 96static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 97 void __iomem *d, 98 dma_addr_t addr) 99{ 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 101 102 /* Register writes to GISB bus can take couple hundred nanoseconds 103 * and are done for each packet, save these expensive writes unless 104 * the platform is explicitly configured for 64-bits/LPAE. 105 */ 106#ifdef CONFIG_PHYS_ADDR_T_64BIT 107 if (priv->hw_params->flags & GENET_HAS_40BITS) 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 109#endif 110} 111 112/* Combined address + length/status setter */ 113static inline void dmadesc_set(struct bcmgenet_priv *priv, 114 void __iomem *d, dma_addr_t addr, u32 val) 115{ 116 dmadesc_set_addr(priv, d, addr); 117 dmadesc_set_length_status(priv, d, val); 118} 119 120static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 121 void __iomem *d) 122{ 123 dma_addr_t addr; 124 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 126 127 /* Register writes to GISB bus can take couple hundred nanoseconds 128 * and are done for each packet, save these expensive writes unless 129 * the platform is explicitly configured for 64-bits/LPAE. 130 */ 131#ifdef CONFIG_PHYS_ADDR_T_64BIT 132 if (priv->hw_params->flags & GENET_HAS_40BITS) 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 134#endif 135 return addr; 136} 137 138#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 139 140#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 141 NETIF_MSG_LINK) 142 143static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 144{ 145 if (GENET_IS_V1(priv)) 146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 147 else 148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 149} 150 151static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152{ 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 155 else 156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 157} 158 159/* These macros are defined to deal with register map change 160 * between GENET1.1 and GENET2. Only those currently being used 161 * by driver are defined. 162 */ 163static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 164{ 165 if (GENET_IS_V1(priv)) 166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 167 else 168 return bcmgenet_readl(priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170} 171 172static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 173{ 174 if (GENET_IS_V1(priv)) 175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 176 else 177 bcmgenet_writel(val, priv->base + 178 priv->hw_params->tbuf_offset + TBUF_CTRL); 179} 180 181static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 182{ 183 if (GENET_IS_V1(priv)) 184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 185 else 186 return bcmgenet_readl(priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188} 189 190static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 191{ 192 if (GENET_IS_V1(priv)) 193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 194 else 195 bcmgenet_writel(val, priv->base + 196 priv->hw_params->tbuf_offset + TBUF_BP_MC); 197} 198 199/* RX/TX DMA register accessors */ 200enum dma_reg { 201 DMA_RING_CFG = 0, 202 DMA_CTRL, 203 DMA_STATUS, 204 DMA_SCB_BURST_SIZE, 205 DMA_ARB_CTRL, 206 DMA_PRIORITY_0, 207 DMA_PRIORITY_1, 208 DMA_PRIORITY_2, 209 DMA_INDEX2RING_0, 210 DMA_INDEX2RING_1, 211 DMA_INDEX2RING_2, 212 DMA_INDEX2RING_3, 213 DMA_INDEX2RING_4, 214 DMA_INDEX2RING_5, 215 DMA_INDEX2RING_6, 216 DMA_INDEX2RING_7, 217 DMA_RING0_TIMEOUT, 218 DMA_RING1_TIMEOUT, 219 DMA_RING2_TIMEOUT, 220 DMA_RING3_TIMEOUT, 221 DMA_RING4_TIMEOUT, 222 DMA_RING5_TIMEOUT, 223 DMA_RING6_TIMEOUT, 224 DMA_RING7_TIMEOUT, 225 DMA_RING8_TIMEOUT, 226 DMA_RING9_TIMEOUT, 227 DMA_RING10_TIMEOUT, 228 DMA_RING11_TIMEOUT, 229 DMA_RING12_TIMEOUT, 230 DMA_RING13_TIMEOUT, 231 DMA_RING14_TIMEOUT, 232 DMA_RING15_TIMEOUT, 233 DMA_RING16_TIMEOUT, 234}; 235 236static const u8 bcmgenet_dma_regs_v3plus[] = { 237 [DMA_RING_CFG] = 0x00, 238 [DMA_CTRL] = 0x04, 239 [DMA_STATUS] = 0x08, 240 [DMA_SCB_BURST_SIZE] = 0x0C, 241 [DMA_ARB_CTRL] = 0x2C, 242 [DMA_PRIORITY_0] = 0x30, 243 [DMA_PRIORITY_1] = 0x34, 244 [DMA_PRIORITY_2] = 0x38, 245 [DMA_RING0_TIMEOUT] = 0x2C, 246 [DMA_RING1_TIMEOUT] = 0x30, 247 [DMA_RING2_TIMEOUT] = 0x34, 248 [DMA_RING3_TIMEOUT] = 0x38, 249 [DMA_RING4_TIMEOUT] = 0x3c, 250 [DMA_RING5_TIMEOUT] = 0x40, 251 [DMA_RING6_TIMEOUT] = 0x44, 252 [DMA_RING7_TIMEOUT] = 0x48, 253 [DMA_RING8_TIMEOUT] = 0x4c, 254 [DMA_RING9_TIMEOUT] = 0x50, 255 [DMA_RING10_TIMEOUT] = 0x54, 256 [DMA_RING11_TIMEOUT] = 0x58, 257 [DMA_RING12_TIMEOUT] = 0x5c, 258 [DMA_RING13_TIMEOUT] = 0x60, 259 [DMA_RING14_TIMEOUT] = 0x64, 260 [DMA_RING15_TIMEOUT] = 0x68, 261 [DMA_RING16_TIMEOUT] = 0x6C, 262 [DMA_INDEX2RING_0] = 0x70, 263 [DMA_INDEX2RING_1] = 0x74, 264 [DMA_INDEX2RING_2] = 0x78, 265 [DMA_INDEX2RING_3] = 0x7C, 266 [DMA_INDEX2RING_4] = 0x80, 267 [DMA_INDEX2RING_5] = 0x84, 268 [DMA_INDEX2RING_6] = 0x88, 269 [DMA_INDEX2RING_7] = 0x8C, 270}; 271 272static const u8 bcmgenet_dma_regs_v2[] = { 273 [DMA_RING_CFG] = 0x00, 274 [DMA_CTRL] = 0x04, 275 [DMA_STATUS] = 0x08, 276 [DMA_SCB_BURST_SIZE] = 0x0C, 277 [DMA_ARB_CTRL] = 0x30, 278 [DMA_PRIORITY_0] = 0x34, 279 [DMA_PRIORITY_1] = 0x38, 280 [DMA_PRIORITY_2] = 0x3C, 281 [DMA_RING0_TIMEOUT] = 0x2C, 282 [DMA_RING1_TIMEOUT] = 0x30, 283 [DMA_RING2_TIMEOUT] = 0x34, 284 [DMA_RING3_TIMEOUT] = 0x38, 285 [DMA_RING4_TIMEOUT] = 0x3c, 286 [DMA_RING5_TIMEOUT] = 0x40, 287 [DMA_RING6_TIMEOUT] = 0x44, 288 [DMA_RING7_TIMEOUT] = 0x48, 289 [DMA_RING8_TIMEOUT] = 0x4c, 290 [DMA_RING9_TIMEOUT] = 0x50, 291 [DMA_RING10_TIMEOUT] = 0x54, 292 [DMA_RING11_TIMEOUT] = 0x58, 293 [DMA_RING12_TIMEOUT] = 0x5c, 294 [DMA_RING13_TIMEOUT] = 0x60, 295 [DMA_RING14_TIMEOUT] = 0x64, 296 [DMA_RING15_TIMEOUT] = 0x68, 297 [DMA_RING16_TIMEOUT] = 0x6C, 298}; 299 300static const u8 bcmgenet_dma_regs_v1[] = { 301 [DMA_CTRL] = 0x00, 302 [DMA_STATUS] = 0x04, 303 [DMA_SCB_BURST_SIZE] = 0x0C, 304 [DMA_ARB_CTRL] = 0x30, 305 [DMA_PRIORITY_0] = 0x34, 306 [DMA_PRIORITY_1] = 0x38, 307 [DMA_PRIORITY_2] = 0x3C, 308 [DMA_RING0_TIMEOUT] = 0x2C, 309 [DMA_RING1_TIMEOUT] = 0x30, 310 [DMA_RING2_TIMEOUT] = 0x34, 311 [DMA_RING3_TIMEOUT] = 0x38, 312 [DMA_RING4_TIMEOUT] = 0x3c, 313 [DMA_RING5_TIMEOUT] = 0x40, 314 [DMA_RING6_TIMEOUT] = 0x44, 315 [DMA_RING7_TIMEOUT] = 0x48, 316 [DMA_RING8_TIMEOUT] = 0x4c, 317 [DMA_RING9_TIMEOUT] = 0x50, 318 [DMA_RING10_TIMEOUT] = 0x54, 319 [DMA_RING11_TIMEOUT] = 0x58, 320 [DMA_RING12_TIMEOUT] = 0x5c, 321 [DMA_RING13_TIMEOUT] = 0x60, 322 [DMA_RING14_TIMEOUT] = 0x64, 323 [DMA_RING15_TIMEOUT] = 0x68, 324 [DMA_RING16_TIMEOUT] = 0x6C, 325}; 326 327/* Set at runtime once bcmgenet version is known */ 328static const u8 *bcmgenet_dma_regs; 329 330static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 331{ 332 return netdev_priv(dev_get_drvdata(dev)); 333} 334 335static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 336 enum dma_reg r) 337{ 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340} 341 342static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 343 u32 val, enum dma_reg r) 344{ 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347} 348 349static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 350 enum dma_reg r) 351{ 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354} 355 356static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 357 u32 val, enum dma_reg r) 358{ 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361} 362 363/* RDMA/TDMA ring registers and accessors 364 * we merge the common fields and just prefix with T/D the registers 365 * having different meaning depending on the direction 366 */ 367enum dma_ring_reg { 368 TDMA_READ_PTR = 0, 369 RDMA_WRITE_PTR = TDMA_READ_PTR, 370 TDMA_READ_PTR_HI, 371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 372 TDMA_CONS_INDEX, 373 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 374 TDMA_PROD_INDEX, 375 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 376 DMA_RING_BUF_SIZE, 377 DMA_START_ADDR, 378 DMA_START_ADDR_HI, 379 DMA_END_ADDR, 380 DMA_END_ADDR_HI, 381 DMA_MBUF_DONE_THRESH, 382 TDMA_FLOW_PERIOD, 383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 384 TDMA_WRITE_PTR, 385 RDMA_READ_PTR = TDMA_WRITE_PTR, 386 TDMA_WRITE_PTR_HI, 387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 388}; 389 390/* GENET v4 supports 40-bits pointer addressing 391 * for obvious reasons the LO and HI word parts 392 * are contiguous, but this offsets the other 393 * registers. 394 */ 395static const u8 genet_dma_ring_regs_v4[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_READ_PTR_HI] = 0x04, 398 [TDMA_CONS_INDEX] = 0x08, 399 [TDMA_PROD_INDEX] = 0x0C, 400 [DMA_RING_BUF_SIZE] = 0x10, 401 [DMA_START_ADDR] = 0x14, 402 [DMA_START_ADDR_HI] = 0x18, 403 [DMA_END_ADDR] = 0x1C, 404 [DMA_END_ADDR_HI] = 0x20, 405 [DMA_MBUF_DONE_THRESH] = 0x24, 406 [TDMA_FLOW_PERIOD] = 0x28, 407 [TDMA_WRITE_PTR] = 0x2C, 408 [TDMA_WRITE_PTR_HI] = 0x30, 409}; 410 411static const u8 genet_dma_ring_regs_v123[] = { 412 [TDMA_READ_PTR] = 0x00, 413 [TDMA_CONS_INDEX] = 0x04, 414 [TDMA_PROD_INDEX] = 0x08, 415 [DMA_RING_BUF_SIZE] = 0x0C, 416 [DMA_START_ADDR] = 0x10, 417 [DMA_END_ADDR] = 0x14, 418 [DMA_MBUF_DONE_THRESH] = 0x18, 419 [TDMA_FLOW_PERIOD] = 0x1C, 420 [TDMA_WRITE_PTR] = 0x20, 421}; 422 423/* Set at runtime once GENET version is known */ 424static const u8 *genet_dma_ring_regs; 425 426static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 427 unsigned int ring, 428 enum dma_ring_reg r) 429{ 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433} 434 435static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 436 unsigned int ring, u32 val, 437 enum dma_ring_reg r) 438{ 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442} 443 444static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 445 unsigned int ring, 446 enum dma_ring_reg r) 447{ 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451} 452 453static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 454 unsigned int ring, u32 val, 455 enum dma_ring_reg r) 456{ 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 458 (DMA_RING_SIZE * ring) + 459 genet_dma_ring_regs[r]); 460} 461 462static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 463{ 464 u32 offset; 465 u32 reg; 466 467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 468 reg = bcmgenet_hfb_reg_readl(priv, offset); 469 reg |= (1 << (f_index % 32)); 470 bcmgenet_hfb_reg_writel(priv, reg, offset); 471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 472 reg |= RBUF_HFB_EN; 473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 474} 475 476static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 477{ 478 u32 offset, reg, reg1; 479 480 offset = HFB_FLT_ENABLE_V3PLUS; 481 reg = bcmgenet_hfb_reg_readl(priv, offset); 482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 483 if (f_index < 32) { 484 reg1 &= ~(1 << (f_index % 32)); 485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 486 } else { 487 reg &= ~(1 << (f_index % 32)); 488 bcmgenet_hfb_reg_writel(priv, reg, offset); 489 } 490 if (!reg && !reg1) { 491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 492 reg &= ~RBUF_HFB_EN; 493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 494 } 495} 496 497static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 498 u32 f_index, u32 rx_queue) 499{ 500 u32 offset; 501 u32 reg; 502 503 offset = f_index / 8; 504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 505 reg &= ~(0xF << (4 * (f_index % 8))); 506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 508} 509 510static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 511 u32 f_index, u32 f_length) 512{ 513 u32 offset; 514 u32 reg; 515 516 offset = HFB_FLT_LEN_V3PLUS + 517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 518 sizeof(u32); 519 reg = bcmgenet_hfb_reg_readl(priv, offset); 520 reg &= ~(0xFF << (8 * (f_index % 4))); 521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 522 bcmgenet_hfb_reg_writel(priv, reg, offset); 523} 524 525static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 526{ 527 while (size) { 528 switch (*(unsigned char *)mask++) { 529 case 0x00: 530 case 0x0f: 531 case 0xf0: 532 case 0xff: 533 size--; 534 continue; 535 default: 536 return -EINVAL; 537 } 538 } 539 540 return 0; 541} 542 543#define VALIDATE_MASK(x) \ 544 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 545 546static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 547 u32 offset, void *val, void *mask, 548 size_t size) 549{ 550 u32 index, tmp; 551 552 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 553 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 554 555 while (size--) { 556 if (offset++ & 1) { 557 tmp &= ~0x300FF; 558 tmp |= (*(unsigned char *)val++); 559 switch ((*(unsigned char *)mask++)) { 560 case 0xFF: 561 tmp |= 0x30000; 562 break; 563 case 0xF0: 564 tmp |= 0x20000; 565 break; 566 case 0x0F: 567 tmp |= 0x10000; 568 break; 569 } 570 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 571 if (size) 572 tmp = bcmgenet_hfb_readl(priv, 573 index * sizeof(u32)); 574 } else { 575 tmp &= ~0xCFF00; 576 tmp |= (*(unsigned char *)val++) << 8; 577 switch ((*(unsigned char *)mask++)) { 578 case 0xFF: 579 tmp |= 0xC0000; 580 break; 581 case 0xF0: 582 tmp |= 0x80000; 583 break; 584 case 0x0F: 585 tmp |= 0x40000; 586 break; 587 } 588 if (!size) 589 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 590 } 591 } 592 593 return 0; 594} 595 596static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 597 struct bcmgenet_rxnfc_rule *rule) 598{ 599 struct ethtool_rx_flow_spec *fs = &rule->fs; 600 u32 offset = 0, f_length = 0, f; 601 u8 val_8, mask_8; 602 __be16 val_16; 603 u16 mask_16; 604 size_t size; 605 606 f = fs->location; 607 if (fs->flow_type & FLOW_MAC_EXT) { 608 bcmgenet_hfb_insert_data(priv, f, 0, 609 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 610 sizeof(fs->h_ext.h_dest)); 611 } 612 613 if (fs->flow_type & FLOW_EXT) { 614 if (fs->m_ext.vlan_etype || 615 fs->m_ext.vlan_tci) { 616 bcmgenet_hfb_insert_data(priv, f, 12, 617 &fs->h_ext.vlan_etype, 618 &fs->m_ext.vlan_etype, 619 sizeof(fs->h_ext.vlan_etype)); 620 bcmgenet_hfb_insert_data(priv, f, 14, 621 &fs->h_ext.vlan_tci, 622 &fs->m_ext.vlan_tci, 623 sizeof(fs->h_ext.vlan_tci)); 624 offset += VLAN_HLEN; 625 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 626 } 627 } 628 629 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 630 case ETHER_FLOW: 631 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 632 bcmgenet_hfb_insert_data(priv, f, 0, 633 &fs->h_u.ether_spec.h_dest, 634 &fs->m_u.ether_spec.h_dest, 635 sizeof(fs->h_u.ether_spec.h_dest)); 636 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 637 &fs->h_u.ether_spec.h_source, 638 &fs->m_u.ether_spec.h_source, 639 sizeof(fs->h_u.ether_spec.h_source)); 640 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 641 &fs->h_u.ether_spec.h_proto, 642 &fs->m_u.ether_spec.h_proto, 643 sizeof(fs->h_u.ether_spec.h_proto)); 644 break; 645 case IP_USER_FLOW: 646 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 647 /* Specify IP Ether Type */ 648 val_16 = htons(ETH_P_IP); 649 mask_16 = 0xFFFF; 650 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 651 &val_16, &mask_16, sizeof(val_16)); 652 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 653 &fs->h_u.usr_ip4_spec.tos, 654 &fs->m_u.usr_ip4_spec.tos, 655 sizeof(fs->h_u.usr_ip4_spec.tos)); 656 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 657 &fs->h_u.usr_ip4_spec.proto, 658 &fs->m_u.usr_ip4_spec.proto, 659 sizeof(fs->h_u.usr_ip4_spec.proto)); 660 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 661 &fs->h_u.usr_ip4_spec.ip4src, 662 &fs->m_u.usr_ip4_spec.ip4src, 663 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 664 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 665 &fs->h_u.usr_ip4_spec.ip4dst, 666 &fs->m_u.usr_ip4_spec.ip4dst, 667 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 668 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 669 break; 670 671 /* Only supports 20 byte IPv4 header */ 672 val_8 = 0x45; 673 mask_8 = 0xFF; 674 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 675 &val_8, &mask_8, 676 sizeof(val_8)); 677 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 678 bcmgenet_hfb_insert_data(priv, f, 679 ETH_HLEN + 20 + offset, 680 &fs->h_u.usr_ip4_spec.l4_4_bytes, 681 &fs->m_u.usr_ip4_spec.l4_4_bytes, 682 size); 683 f_length += DIV_ROUND_UP(size, 2); 684 break; 685 } 686 687 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 688 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) { 689 /* Ring 0 flows can be handled by the default Descriptor Ring 690 * We'll map them to ring 0, but don't enable the filter 691 */ 692 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0); 693 rule->state = BCMGENET_RXNFC_STATE_DISABLED; 694 } else { 695 /* Other Rx rings are direct mapped here */ 696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 697 fs->ring_cookie); 698 bcmgenet_hfb_enable_filter(priv, f); 699 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 700 } 701} 702 703/* bcmgenet_hfb_clear 704 * 705 * Clear Hardware Filter Block and disable all filtering. 706 */ 707static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 708{ 709 u32 base, i; 710 711 base = f_index * priv->hw_params->hfb_filter_size; 712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 714} 715 716static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 717{ 718 u32 i; 719 720 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 721 return; 722 723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 724 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 725 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 726 727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 728 bcmgenet_rdma_writel(priv, 0x0, i); 729 730 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 731 bcmgenet_hfb_reg_writel(priv, 0x0, 732 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 733 734 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 735 bcmgenet_hfb_clear_filter(priv, i); 736} 737 738static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 739{ 740 int i; 741 742 INIT_LIST_HEAD(&priv->rxnfc_list); 743 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 744 return; 745 746 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 747 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 748 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 749 } 750 751 bcmgenet_hfb_clear(priv); 752} 753 754static int bcmgenet_begin(struct net_device *dev) 755{ 756 struct bcmgenet_priv *priv = netdev_priv(dev); 757 758 /* Turn on the clock */ 759 return clk_prepare_enable(priv->clk); 760} 761 762static void bcmgenet_complete(struct net_device *dev) 763{ 764 struct bcmgenet_priv *priv = netdev_priv(dev); 765 766 /* Turn off the clock */ 767 clk_disable_unprepare(priv->clk); 768} 769 770static int bcmgenet_get_link_ksettings(struct net_device *dev, 771 struct ethtool_link_ksettings *cmd) 772{ 773 if (!netif_running(dev)) 774 return -EINVAL; 775 776 if (!dev->phydev) 777 return -ENODEV; 778 779 phy_ethtool_ksettings_get(dev->phydev, cmd); 780 781 return 0; 782} 783 784static int bcmgenet_set_link_ksettings(struct net_device *dev, 785 const struct ethtool_link_ksettings *cmd) 786{ 787 if (!netif_running(dev)) 788 return -EINVAL; 789 790 if (!dev->phydev) 791 return -ENODEV; 792 793 return phy_ethtool_ksettings_set(dev->phydev, cmd); 794} 795 796static int bcmgenet_set_features(struct net_device *dev, 797 netdev_features_t features) 798{ 799 struct bcmgenet_priv *priv = netdev_priv(dev); 800 u32 reg; 801 int ret; 802 803 ret = clk_prepare_enable(priv->clk); 804 if (ret) 805 return ret; 806 807 /* Make sure we reflect the value of CRC_CMD_FWD */ 808 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 809 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 810 811 clk_disable_unprepare(priv->clk); 812 813 return ret; 814} 815 816static u32 bcmgenet_get_msglevel(struct net_device *dev) 817{ 818 struct bcmgenet_priv *priv = netdev_priv(dev); 819 820 return priv->msg_enable; 821} 822 823static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 824{ 825 struct bcmgenet_priv *priv = netdev_priv(dev); 826 827 priv->msg_enable = level; 828} 829 830static int bcmgenet_get_coalesce(struct net_device *dev, 831 struct ethtool_coalesce *ec) 832{ 833 struct bcmgenet_priv *priv = netdev_priv(dev); 834 struct bcmgenet_rx_ring *ring; 835 unsigned int i; 836 837 ec->tx_max_coalesced_frames = 838 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 839 DMA_MBUF_DONE_THRESH); 840 ec->rx_max_coalesced_frames = 841 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 842 DMA_MBUF_DONE_THRESH); 843 ec->rx_coalesce_usecs = 844 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 845 846 for (i = 0; i < priv->hw_params->rx_queues; i++) { 847 ring = &priv->rx_rings[i]; 848 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 849 } 850 ring = &priv->rx_rings[DESC_INDEX]; 851 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 852 853 return 0; 854} 855 856static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 857 u32 usecs, u32 pkts) 858{ 859 struct bcmgenet_priv *priv = ring->priv; 860 unsigned int i = ring->index; 861 u32 reg; 862 863 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 864 865 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 866 reg &= ~DMA_TIMEOUT_MASK; 867 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 868 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 869} 870 871static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 872 struct ethtool_coalesce *ec) 873{ 874 struct dim_cq_moder moder; 875 u32 usecs, pkts; 876 877 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 878 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 879 usecs = ring->rx_coalesce_usecs; 880 pkts = ring->rx_max_coalesced_frames; 881 882 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 883 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 884 usecs = moder.usec; 885 pkts = moder.pkts; 886 } 887 888 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 889 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 890} 891 892static int bcmgenet_set_coalesce(struct net_device *dev, 893 struct ethtool_coalesce *ec) 894{ 895 struct bcmgenet_priv *priv = netdev_priv(dev); 896 unsigned int i; 897 898 /* Base system clock is 125Mhz, DMA timeout is this reference clock 899 * divided by 1024, which yields roughly 8.192us, our maximum value 900 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 901 */ 902 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 903 ec->tx_max_coalesced_frames == 0 || 904 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 905 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 906 return -EINVAL; 907 908 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 909 return -EINVAL; 910 911 /* GENET TDMA hardware does not support a configurable timeout, but will 912 * always generate an interrupt either after MBDONE packets have been 913 * transmitted, or when the ring is empty. 914 */ 915 916 /* Program all TX queues with the same values, as there is no 917 * ethtool knob to do coalescing on a per-queue basis 918 */ 919 for (i = 0; i < priv->hw_params->tx_queues; i++) 920 bcmgenet_tdma_ring_writel(priv, i, 921 ec->tx_max_coalesced_frames, 922 DMA_MBUF_DONE_THRESH); 923 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 924 ec->tx_max_coalesced_frames, 925 DMA_MBUF_DONE_THRESH); 926 927 for (i = 0; i < priv->hw_params->rx_queues; i++) 928 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 929 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 930 931 return 0; 932} 933 934/* standard ethtool support functions. */ 935enum bcmgenet_stat_type { 936 BCMGENET_STAT_NETDEV = -1, 937 BCMGENET_STAT_MIB_RX, 938 BCMGENET_STAT_MIB_TX, 939 BCMGENET_STAT_RUNT, 940 BCMGENET_STAT_MISC, 941 BCMGENET_STAT_SOFT, 942}; 943 944struct bcmgenet_stats { 945 char stat_string[ETH_GSTRING_LEN]; 946 int stat_sizeof; 947 int stat_offset; 948 enum bcmgenet_stat_type type; 949 /* reg offset from UMAC base for misc counters */ 950 u16 reg_offset; 951}; 952 953#define STAT_NETDEV(m) { \ 954 .stat_string = __stringify(m), \ 955 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 956 .stat_offset = offsetof(struct net_device_stats, m), \ 957 .type = BCMGENET_STAT_NETDEV, \ 958} 959 960#define STAT_GENET_MIB(str, m, _type) { \ 961 .stat_string = str, \ 962 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 963 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 964 .type = _type, \ 965} 966 967#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 968#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 969#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 970#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 971 972#define STAT_GENET_MISC(str, m, offset) { \ 973 .stat_string = str, \ 974 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 975 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 976 .type = BCMGENET_STAT_MISC, \ 977 .reg_offset = offset, \ 978} 979 980#define STAT_GENET_Q(num) \ 981 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 982 tx_rings[num].packets), \ 983 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 984 tx_rings[num].bytes), \ 985 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 986 rx_rings[num].bytes), \ 987 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 988 rx_rings[num].packets), \ 989 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 990 rx_rings[num].errors), \ 991 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 992 rx_rings[num].dropped) 993 994/* There is a 0xC gap between the end of RX and beginning of TX stats and then 995 * between the end of TX stats and the beginning of the RX RUNT 996 */ 997#define BCMGENET_STAT_OFFSET 0xc 998 999/* Hardware counters must be kept in sync because the order/offset 1000 * is important here (order in structure declaration = order in hardware) 1001 */ 1002static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1003 /* general stats */ 1004 STAT_NETDEV(rx_packets), 1005 STAT_NETDEV(tx_packets), 1006 STAT_NETDEV(rx_bytes), 1007 STAT_NETDEV(tx_bytes), 1008 STAT_NETDEV(rx_errors), 1009 STAT_NETDEV(tx_errors), 1010 STAT_NETDEV(rx_dropped), 1011 STAT_NETDEV(tx_dropped), 1012 STAT_NETDEV(multicast), 1013 /* UniMAC RSV counters */ 1014 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1015 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1016 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1017 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1018 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1019 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1020 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1021 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1022 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1023 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1024 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1025 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1026 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1027 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1028 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1029 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1030 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1031 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1032 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1033 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1034 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1035 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1036 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1037 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1038 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1039 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1040 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1041 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1042 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1043 /* UniMAC TSV counters */ 1044 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1045 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1046 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1047 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1048 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1049 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1050 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1051 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1052 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1053 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1054 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1055 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1056 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1057 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1058 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1059 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1060 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1061 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1062 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1063 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1064 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1065 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1066 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1067 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1068 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1069 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1070 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1071 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1072 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1073 /* UniMAC RUNT counters */ 1074 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1075 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1076 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1077 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1078 /* Misc UniMAC counters */ 1079 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1080 UMAC_RBUF_OVFL_CNT_V1), 1081 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1082 UMAC_RBUF_ERR_CNT_V1), 1083 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1084 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1085 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1086 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1087 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1088 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1089 mib.tx_realloc_tsb_failed), 1090 /* Per TX queues */ 1091 STAT_GENET_Q(0), 1092 STAT_GENET_Q(1), 1093 STAT_GENET_Q(2), 1094 STAT_GENET_Q(3), 1095 STAT_GENET_Q(16), 1096}; 1097 1098#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1099 1100static void bcmgenet_get_drvinfo(struct net_device *dev, 1101 struct ethtool_drvinfo *info) 1102{ 1103 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 1104} 1105 1106static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1107{ 1108 switch (string_set) { 1109 case ETH_SS_STATS: 1110 return BCMGENET_STATS_LEN; 1111 default: 1112 return -EOPNOTSUPP; 1113 } 1114} 1115 1116static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1117 u8 *data) 1118{ 1119 int i; 1120 1121 switch (stringset) { 1122 case ETH_SS_STATS: 1123 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1124 memcpy(data + i * ETH_GSTRING_LEN, 1125 bcmgenet_gstrings_stats[i].stat_string, 1126 ETH_GSTRING_LEN); 1127 } 1128 break; 1129 } 1130} 1131 1132static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1133{ 1134 u16 new_offset; 1135 u32 val; 1136 1137 switch (offset) { 1138 case UMAC_RBUF_OVFL_CNT_V1: 1139 if (GENET_IS_V2(priv)) 1140 new_offset = RBUF_OVFL_CNT_V2; 1141 else 1142 new_offset = RBUF_OVFL_CNT_V3PLUS; 1143 1144 val = bcmgenet_rbuf_readl(priv, new_offset); 1145 /* clear if overflowed */ 1146 if (val == ~0) 1147 bcmgenet_rbuf_writel(priv, 0, new_offset); 1148 break; 1149 case UMAC_RBUF_ERR_CNT_V1: 1150 if (GENET_IS_V2(priv)) 1151 new_offset = RBUF_ERR_CNT_V2; 1152 else 1153 new_offset = RBUF_ERR_CNT_V3PLUS; 1154 1155 val = bcmgenet_rbuf_readl(priv, new_offset); 1156 /* clear if overflowed */ 1157 if (val == ~0) 1158 bcmgenet_rbuf_writel(priv, 0, new_offset); 1159 break; 1160 default: 1161 val = bcmgenet_umac_readl(priv, offset); 1162 /* clear if overflowed */ 1163 if (val == ~0) 1164 bcmgenet_umac_writel(priv, 0, offset); 1165 break; 1166 } 1167 1168 return val; 1169} 1170 1171static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1172{ 1173 int i, j = 0; 1174 1175 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1176 const struct bcmgenet_stats *s; 1177 u8 offset = 0; 1178 u32 val = 0; 1179 char *p; 1180 1181 s = &bcmgenet_gstrings_stats[i]; 1182 switch (s->type) { 1183 case BCMGENET_STAT_NETDEV: 1184 case BCMGENET_STAT_SOFT: 1185 continue; 1186 case BCMGENET_STAT_RUNT: 1187 offset += BCMGENET_STAT_OFFSET; 1188 fallthrough; 1189 case BCMGENET_STAT_MIB_TX: 1190 offset += BCMGENET_STAT_OFFSET; 1191 fallthrough; 1192 case BCMGENET_STAT_MIB_RX: 1193 val = bcmgenet_umac_readl(priv, 1194 UMAC_MIB_START + j + offset); 1195 offset = 0; /* Reset Offset */ 1196 break; 1197 case BCMGENET_STAT_MISC: 1198 if (GENET_IS_V1(priv)) { 1199 val = bcmgenet_umac_readl(priv, s->reg_offset); 1200 /* clear if overflowed */ 1201 if (val == ~0) 1202 bcmgenet_umac_writel(priv, 0, 1203 s->reg_offset); 1204 } else { 1205 val = bcmgenet_update_stat_misc(priv, 1206 s->reg_offset); 1207 } 1208 break; 1209 } 1210 1211 j += s->stat_sizeof; 1212 p = (char *)priv + s->stat_offset; 1213 *(u32 *)p = val; 1214 } 1215} 1216 1217static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1218 struct ethtool_stats *stats, 1219 u64 *data) 1220{ 1221 struct bcmgenet_priv *priv = netdev_priv(dev); 1222 int i; 1223 1224 if (netif_running(dev)) 1225 bcmgenet_update_mib_counters(priv); 1226 1227 dev->netdev_ops->ndo_get_stats(dev); 1228 1229 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1230 const struct bcmgenet_stats *s; 1231 char *p; 1232 1233 s = &bcmgenet_gstrings_stats[i]; 1234 if (s->type == BCMGENET_STAT_NETDEV) 1235 p = (char *)&dev->stats; 1236 else 1237 p = (char *)priv; 1238 p += s->stat_offset; 1239 if (sizeof(unsigned long) != sizeof(u32) && 1240 s->stat_sizeof == sizeof(unsigned long)) 1241 data[i] = *(unsigned long *)p; 1242 else 1243 data[i] = *(u32 *)p; 1244 } 1245} 1246 1247void bcmgenet_eee_enable_set(struct net_device *dev, bool enable, 1248 bool tx_lpi_enabled) 1249{ 1250 struct bcmgenet_priv *priv = netdev_priv(dev); 1251 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1252 u32 reg; 1253 1254 if (enable && !priv->clk_eee_enabled) { 1255 clk_prepare_enable(priv->clk_eee); 1256 priv->clk_eee_enabled = true; 1257 } 1258 1259 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1260 if (enable) 1261 reg |= EEE_EN; 1262 else 1263 reg &= ~EEE_EN; 1264 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1265 1266 /* Enable EEE and switch to a 27Mhz clock automatically */ 1267 reg = bcmgenet_readl(priv->base + off); 1268 if (tx_lpi_enabled) 1269 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1270 else 1271 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1272 bcmgenet_writel(reg, priv->base + off); 1273 1274 /* Do the same for thing for RBUF */ 1275 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1276 if (enable) 1277 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1278 else 1279 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1280 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1281 1282 if (!enable && priv->clk_eee_enabled) { 1283 clk_disable_unprepare(priv->clk_eee); 1284 priv->clk_eee_enabled = false; 1285 } 1286 1287 priv->eee.eee_enabled = enable; 1288 priv->eee.eee_active = enable; 1289 priv->eee.tx_lpi_enabled = tx_lpi_enabled; 1290} 1291 1292static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1293{ 1294 struct bcmgenet_priv *priv = netdev_priv(dev); 1295 struct ethtool_eee *p = &priv->eee; 1296 1297 if (GENET_IS_V1(priv)) 1298 return -EOPNOTSUPP; 1299 1300 if (!dev->phydev) 1301 return -ENODEV; 1302 1303 e->eee_enabled = p->eee_enabled; 1304 e->eee_active = p->eee_active; 1305 e->tx_lpi_enabled = p->tx_lpi_enabled; 1306 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1307 1308 return phy_ethtool_get_eee(dev->phydev, e); 1309} 1310 1311static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1312{ 1313 struct bcmgenet_priv *priv = netdev_priv(dev); 1314 struct ethtool_eee *p = &priv->eee; 1315 1316 if (GENET_IS_V1(priv)) 1317 return -EOPNOTSUPP; 1318 1319 if (!dev->phydev) 1320 return -ENODEV; 1321 1322 p->eee_enabled = e->eee_enabled; 1323 1324 if (!p->eee_enabled) { 1325 bcmgenet_eee_enable_set(dev, false, false); 1326 } else { 1327 p->eee_active = phy_init_eee(dev->phydev, false) >= 0; 1328 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1329 bcmgenet_eee_enable_set(dev, p->eee_active, e->tx_lpi_enabled); 1330 } 1331 1332 return phy_ethtool_set_eee(dev->phydev, e); 1333} 1334 1335static int bcmgenet_validate_flow(struct net_device *dev, 1336 struct ethtool_rxnfc *cmd) 1337{ 1338 struct ethtool_usrip4_spec *l4_mask; 1339 struct ethhdr *eth_mask; 1340 1341 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) { 1342 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1343 cmd->fs.location); 1344 return -EINVAL; 1345 } 1346 1347 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1348 case IP_USER_FLOW: 1349 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1350 /* don't allow mask which isn't valid */ 1351 if (VALIDATE_MASK(l4_mask->ip4src) || 1352 VALIDATE_MASK(l4_mask->ip4dst) || 1353 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1354 VALIDATE_MASK(l4_mask->proto) || 1355 VALIDATE_MASK(l4_mask->ip_ver) || 1356 VALIDATE_MASK(l4_mask->tos)) { 1357 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1358 return -EINVAL; 1359 } 1360 break; 1361 case ETHER_FLOW: 1362 eth_mask = &cmd->fs.m_u.ether_spec; 1363 /* don't allow mask which isn't valid */ 1364 if (VALIDATE_MASK(eth_mask->h_dest) || 1365 VALIDATE_MASK(eth_mask->h_source) || 1366 VALIDATE_MASK(eth_mask->h_proto)) { 1367 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1368 return -EINVAL; 1369 } 1370 break; 1371 default: 1372 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1373 cmd->fs.flow_type); 1374 return -EINVAL; 1375 } 1376 1377 if ((cmd->fs.flow_type & FLOW_EXT)) { 1378 /* don't allow mask which isn't valid */ 1379 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1380 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1381 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1382 return -EINVAL; 1383 } 1384 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1385 netdev_err(dev, "rxnfc: user-def not supported\n"); 1386 return -EINVAL; 1387 } 1388 } 1389 1390 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1391 /* don't allow mask which isn't valid */ 1392 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1393 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1394 return -EINVAL; 1395 } 1396 } 1397 1398 return 0; 1399} 1400 1401static int bcmgenet_insert_flow(struct net_device *dev, 1402 struct ethtool_rxnfc *cmd) 1403{ 1404 struct bcmgenet_priv *priv = netdev_priv(dev); 1405 struct bcmgenet_rxnfc_rule *loc_rule; 1406 int err; 1407 1408 if (priv->hw_params->hfb_filter_size < 128) { 1409 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1410 return -EINVAL; 1411 } 1412 1413 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1414 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) { 1415 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1416 cmd->fs.ring_cookie); 1417 return -EINVAL; 1418 } 1419 1420 err = bcmgenet_validate_flow(dev, cmd); 1421 if (err) 1422 return err; 1423 1424 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1425 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1426 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1427 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1428 list_del(&loc_rule->list); 1429 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1430 } 1431 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1432 memcpy(&loc_rule->fs, &cmd->fs, 1433 sizeof(struct ethtool_rx_flow_spec)); 1434 1435 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1436 1437 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1438 1439 return 0; 1440} 1441 1442static int bcmgenet_delete_flow(struct net_device *dev, 1443 struct ethtool_rxnfc *cmd) 1444{ 1445 struct bcmgenet_priv *priv = netdev_priv(dev); 1446 struct bcmgenet_rxnfc_rule *rule; 1447 int err = 0; 1448 1449 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1450 return -EINVAL; 1451 1452 rule = &priv->rxnfc_rules[cmd->fs.location]; 1453 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1454 err = -ENOENT; 1455 goto out; 1456 } 1457 1458 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1459 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1460 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1461 list_del(&rule->list); 1462 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1463 } 1464 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1465 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1466 1467out: 1468 return err; 1469} 1470 1471static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1472{ 1473 struct bcmgenet_priv *priv = netdev_priv(dev); 1474 int err = 0; 1475 1476 switch (cmd->cmd) { 1477 case ETHTOOL_SRXCLSRLINS: 1478 err = bcmgenet_insert_flow(dev, cmd); 1479 break; 1480 case ETHTOOL_SRXCLSRLDEL: 1481 err = bcmgenet_delete_flow(dev, cmd); 1482 break; 1483 default: 1484 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1485 cmd->cmd); 1486 return -EINVAL; 1487 } 1488 1489 return err; 1490} 1491 1492static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1493 int loc) 1494{ 1495 struct bcmgenet_priv *priv = netdev_priv(dev); 1496 struct bcmgenet_rxnfc_rule *rule; 1497 int err = 0; 1498 1499 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1500 return -EINVAL; 1501 1502 rule = &priv->rxnfc_rules[loc]; 1503 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1504 err = -ENOENT; 1505 else 1506 memcpy(&cmd->fs, &rule->fs, 1507 sizeof(struct ethtool_rx_flow_spec)); 1508 1509 return err; 1510} 1511 1512static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1513{ 1514 struct list_head *pos; 1515 int res = 0; 1516 1517 list_for_each(pos, &priv->rxnfc_list) 1518 res++; 1519 1520 return res; 1521} 1522 1523static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1524 u32 *rule_locs) 1525{ 1526 struct bcmgenet_priv *priv = netdev_priv(dev); 1527 struct bcmgenet_rxnfc_rule *rule; 1528 int err = 0; 1529 int i = 0; 1530 1531 switch (cmd->cmd) { 1532 case ETHTOOL_GRXRINGS: 1533 cmd->data = priv->hw_params->rx_queues ?: 1; 1534 break; 1535 case ETHTOOL_GRXCLSRLCNT: 1536 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1537 cmd->data = MAX_NUM_OF_FS_RULES; 1538 break; 1539 case ETHTOOL_GRXCLSRULE: 1540 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1541 break; 1542 case ETHTOOL_GRXCLSRLALL: 1543 list_for_each_entry(rule, &priv->rxnfc_list, list) 1544 if (i < cmd->rule_cnt) 1545 rule_locs[i++] = rule->fs.location; 1546 cmd->rule_cnt = i; 1547 cmd->data = MAX_NUM_OF_FS_RULES; 1548 break; 1549 default: 1550 err = -EOPNOTSUPP; 1551 break; 1552 } 1553 1554 return err; 1555} 1556 1557/* standard ethtool support functions. */ 1558static const struct ethtool_ops bcmgenet_ethtool_ops = { 1559 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1560 ETHTOOL_COALESCE_MAX_FRAMES | 1561 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1562 .begin = bcmgenet_begin, 1563 .complete = bcmgenet_complete, 1564 .get_strings = bcmgenet_get_strings, 1565 .get_sset_count = bcmgenet_get_sset_count, 1566 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1567 .get_drvinfo = bcmgenet_get_drvinfo, 1568 .get_link = ethtool_op_get_link, 1569 .get_msglevel = bcmgenet_get_msglevel, 1570 .set_msglevel = bcmgenet_set_msglevel, 1571 .get_wol = bcmgenet_get_wol, 1572 .set_wol = bcmgenet_set_wol, 1573 .get_eee = bcmgenet_get_eee, 1574 .set_eee = bcmgenet_set_eee, 1575 .nway_reset = phy_ethtool_nway_reset, 1576 .get_coalesce = bcmgenet_get_coalesce, 1577 .set_coalesce = bcmgenet_set_coalesce, 1578 .get_link_ksettings = bcmgenet_get_link_ksettings, 1579 .set_link_ksettings = bcmgenet_set_link_ksettings, 1580 .get_ts_info = ethtool_op_get_ts_info, 1581 .get_rxnfc = bcmgenet_get_rxnfc, 1582 .set_rxnfc = bcmgenet_set_rxnfc, 1583}; 1584 1585/* Power down the unimac, based on mode. */ 1586static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1587 enum bcmgenet_power_mode mode) 1588{ 1589 int ret = 0; 1590 u32 reg; 1591 1592 switch (mode) { 1593 case GENET_POWER_CABLE_SENSE: 1594 phy_detach(priv->dev->phydev); 1595 break; 1596 1597 case GENET_POWER_WOL_MAGIC: 1598 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1599 break; 1600 1601 case GENET_POWER_PASSIVE: 1602 /* Power down LED */ 1603 if (priv->hw_params->flags & GENET_HAS_EXT) { 1604 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1605 if (GENET_IS_V5(priv)) 1606 reg |= EXT_PWR_DOWN_PHY_EN | 1607 EXT_PWR_DOWN_PHY_RD | 1608 EXT_PWR_DOWN_PHY_SD | 1609 EXT_PWR_DOWN_PHY_RX | 1610 EXT_PWR_DOWN_PHY_TX | 1611 EXT_IDDQ_GLBL_PWR; 1612 else 1613 reg |= EXT_PWR_DOWN_PHY; 1614 1615 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1616 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1617 1618 bcmgenet_phy_power_set(priv->dev, false); 1619 } 1620 break; 1621 default: 1622 break; 1623 } 1624 1625 return ret; 1626} 1627 1628static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1629 enum bcmgenet_power_mode mode) 1630{ 1631 u32 reg; 1632 1633 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1634 return; 1635 1636 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1637 1638 switch (mode) { 1639 case GENET_POWER_PASSIVE: 1640 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1641 EXT_ENERGY_DET_MASK); 1642 if (GENET_IS_V5(priv)) { 1643 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1644 EXT_PWR_DOWN_PHY_RD | 1645 EXT_PWR_DOWN_PHY_SD | 1646 EXT_PWR_DOWN_PHY_RX | 1647 EXT_PWR_DOWN_PHY_TX | 1648 EXT_IDDQ_GLBL_PWR); 1649 reg |= EXT_PHY_RESET; 1650 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1651 mdelay(1); 1652 1653 reg &= ~EXT_PHY_RESET; 1654 } else { 1655 reg &= ~EXT_PWR_DOWN_PHY; 1656 reg |= EXT_PWR_DN_EN_LD; 1657 } 1658 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1659 bcmgenet_phy_power_set(priv->dev, true); 1660 break; 1661 1662 case GENET_POWER_CABLE_SENSE: 1663 /* enable APD */ 1664 if (!GENET_IS_V5(priv)) { 1665 reg |= EXT_PWR_DN_EN_LD; 1666 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1667 } 1668 break; 1669 case GENET_POWER_WOL_MAGIC: 1670 bcmgenet_wol_power_up_cfg(priv, mode); 1671 return; 1672 default: 1673 break; 1674 } 1675} 1676 1677static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1678 struct bcmgenet_tx_ring *ring) 1679{ 1680 struct enet_cb *tx_cb_ptr; 1681 1682 tx_cb_ptr = ring->cbs; 1683 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1684 1685 /* Advancing local write pointer */ 1686 if (ring->write_ptr == ring->end_ptr) 1687 ring->write_ptr = ring->cb_ptr; 1688 else 1689 ring->write_ptr++; 1690 1691 return tx_cb_ptr; 1692} 1693 1694static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1695 struct bcmgenet_tx_ring *ring) 1696{ 1697 struct enet_cb *tx_cb_ptr; 1698 1699 tx_cb_ptr = ring->cbs; 1700 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1701 1702 /* Rewinding local write pointer */ 1703 if (ring->write_ptr == ring->cb_ptr) 1704 ring->write_ptr = ring->end_ptr; 1705 else 1706 ring->write_ptr--; 1707 1708 return tx_cb_ptr; 1709} 1710 1711static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1712{ 1713 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1714 INTRL2_CPU_MASK_SET); 1715} 1716 1717static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1718{ 1719 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1720 INTRL2_CPU_MASK_CLEAR); 1721} 1722 1723static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1724{ 1725 bcmgenet_intrl2_1_writel(ring->priv, 1726 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1727 INTRL2_CPU_MASK_SET); 1728} 1729 1730static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1731{ 1732 bcmgenet_intrl2_1_writel(ring->priv, 1733 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1734 INTRL2_CPU_MASK_CLEAR); 1735} 1736 1737static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1738{ 1739 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1740 INTRL2_CPU_MASK_SET); 1741} 1742 1743static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1744{ 1745 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1746 INTRL2_CPU_MASK_CLEAR); 1747} 1748 1749static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1750{ 1751 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1752 INTRL2_CPU_MASK_CLEAR); 1753} 1754 1755static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1756{ 1757 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1758 INTRL2_CPU_MASK_SET); 1759} 1760 1761/* Simple helper to free a transmit control block's resources 1762 * Returns an skb when the last transmit control block associated with the 1763 * skb is freed. The skb should be freed by the caller if necessary. 1764 */ 1765static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1766 struct enet_cb *cb) 1767{ 1768 struct sk_buff *skb; 1769 1770 skb = cb->skb; 1771 1772 if (skb) { 1773 cb->skb = NULL; 1774 if (cb == GENET_CB(skb)->first_cb) 1775 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1776 dma_unmap_len(cb, dma_len), 1777 DMA_TO_DEVICE); 1778 else 1779 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1780 dma_unmap_len(cb, dma_len), 1781 DMA_TO_DEVICE); 1782 dma_unmap_addr_set(cb, dma_addr, 0); 1783 1784 if (cb == GENET_CB(skb)->last_cb) 1785 return skb; 1786 1787 } else if (dma_unmap_addr(cb, dma_addr)) { 1788 dma_unmap_page(dev, 1789 dma_unmap_addr(cb, dma_addr), 1790 dma_unmap_len(cb, dma_len), 1791 DMA_TO_DEVICE); 1792 dma_unmap_addr_set(cb, dma_addr, 0); 1793 } 1794 1795 return NULL; 1796} 1797 1798/* Simple helper to free a receive control block's resources */ 1799static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1800 struct enet_cb *cb) 1801{ 1802 struct sk_buff *skb; 1803 1804 skb = cb->skb; 1805 cb->skb = NULL; 1806 1807 if (dma_unmap_addr(cb, dma_addr)) { 1808 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1809 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1810 dma_unmap_addr_set(cb, dma_addr, 0); 1811 } 1812 1813 return skb; 1814} 1815 1816/* Unlocked version of the reclaim routine */ 1817static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1818 struct bcmgenet_tx_ring *ring) 1819{ 1820 struct bcmgenet_priv *priv = netdev_priv(dev); 1821 unsigned int txbds_processed = 0; 1822 unsigned int bytes_compl = 0; 1823 unsigned int pkts_compl = 0; 1824 unsigned int txbds_ready; 1825 unsigned int c_index; 1826 struct sk_buff *skb; 1827 1828 /* Clear status before servicing to reduce spurious interrupts */ 1829 if (ring->index == DESC_INDEX) 1830 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1831 INTRL2_CPU_CLEAR); 1832 else 1833 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1834 INTRL2_CPU_CLEAR); 1835 1836 /* Compute how many buffers are transmitted since last xmit call */ 1837 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1838 & DMA_C_INDEX_MASK; 1839 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1840 1841 netif_dbg(priv, tx_done, dev, 1842 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1843 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1844 1845 /* Reclaim transmitted buffers */ 1846 while (txbds_processed < txbds_ready) { 1847 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1848 &priv->tx_cbs[ring->clean_ptr]); 1849 if (skb) { 1850 pkts_compl++; 1851 bytes_compl += GENET_CB(skb)->bytes_sent; 1852 dev_consume_skb_any(skb); 1853 } 1854 1855 txbds_processed++; 1856 if (likely(ring->clean_ptr < ring->end_ptr)) 1857 ring->clean_ptr++; 1858 else 1859 ring->clean_ptr = ring->cb_ptr; 1860 } 1861 1862 ring->free_bds += txbds_processed; 1863 ring->c_index = c_index; 1864 1865 ring->packets += pkts_compl; 1866 ring->bytes += bytes_compl; 1867 1868 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1869 pkts_compl, bytes_compl); 1870 1871 return txbds_processed; 1872} 1873 1874static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1875 struct bcmgenet_tx_ring *ring) 1876{ 1877 unsigned int released; 1878 1879 spin_lock_bh(&ring->lock); 1880 released = __bcmgenet_tx_reclaim(dev, ring); 1881 spin_unlock_bh(&ring->lock); 1882 1883 return released; 1884} 1885 1886static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1887{ 1888 struct bcmgenet_tx_ring *ring = 1889 container_of(napi, struct bcmgenet_tx_ring, napi); 1890 unsigned int work_done = 0; 1891 struct netdev_queue *txq; 1892 1893 spin_lock(&ring->lock); 1894 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1895 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1896 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1897 netif_tx_wake_queue(txq); 1898 } 1899 spin_unlock(&ring->lock); 1900 1901 if (work_done == 0) { 1902 napi_complete(napi); 1903 ring->int_enable(ring); 1904 1905 return 0; 1906 } 1907 1908 return budget; 1909} 1910 1911static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1912{ 1913 struct bcmgenet_priv *priv = netdev_priv(dev); 1914 int i; 1915 1916 if (netif_is_multiqueue(dev)) { 1917 for (i = 0; i < priv->hw_params->tx_queues; i++) 1918 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1919 } 1920 1921 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1922} 1923 1924/* Reallocate the SKB to put enough headroom in front of it and insert 1925 * the transmit checksum offsets in the descriptors 1926 */ 1927static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 1928 struct sk_buff *skb) 1929{ 1930 struct bcmgenet_priv *priv = netdev_priv(dev); 1931 struct status_64 *status = NULL; 1932 struct sk_buff *new_skb; 1933 u16 offset; 1934 u8 ip_proto; 1935 __be16 ip_ver; 1936 u32 tx_csum_info; 1937 1938 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1939 /* If 64 byte status block enabled, must make sure skb has 1940 * enough headroom for us to insert 64B status block. 1941 */ 1942 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1943 if (!new_skb) { 1944 dev_kfree_skb_any(skb); 1945 priv->mib.tx_realloc_tsb_failed++; 1946 dev->stats.tx_dropped++; 1947 return NULL; 1948 } 1949 dev_consume_skb_any(skb); 1950 skb = new_skb; 1951 priv->mib.tx_realloc_tsb++; 1952 } 1953 1954 skb_push(skb, sizeof(*status)); 1955 status = (struct status_64 *)skb->data; 1956 1957 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1958 ip_ver = skb->protocol; 1959 switch (ip_ver) { 1960 case htons(ETH_P_IP): 1961 ip_proto = ip_hdr(skb)->protocol; 1962 break; 1963 case htons(ETH_P_IPV6): 1964 ip_proto = ipv6_hdr(skb)->nexthdr; 1965 break; 1966 default: 1967 /* don't use UDP flag */ 1968 ip_proto = 0; 1969 break; 1970 } 1971 1972 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1973 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1974 (offset + skb->csum_offset) | 1975 STATUS_TX_CSUM_LV; 1976 1977 /* Set the special UDP flag for UDP */ 1978 if (ip_proto == IPPROTO_UDP) 1979 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1980 1981 status->tx_csum_info = tx_csum_info; 1982 } 1983 1984 return skb; 1985} 1986 1987static void bcmgenet_hide_tsb(struct sk_buff *skb) 1988{ 1989 __skb_pull(skb, sizeof(struct status_64)); 1990} 1991 1992static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1993{ 1994 struct bcmgenet_priv *priv = netdev_priv(dev); 1995 struct device *kdev = &priv->pdev->dev; 1996 struct bcmgenet_tx_ring *ring = NULL; 1997 struct enet_cb *tx_cb_ptr; 1998 struct netdev_queue *txq; 1999 int nr_frags, index; 2000 dma_addr_t mapping; 2001 unsigned int size; 2002 skb_frag_t *frag; 2003 u32 len_stat; 2004 int ret; 2005 int i; 2006 2007 index = skb_get_queue_mapping(skb); 2008 /* Mapping strategy: 2009 * queue_mapping = 0, unclassified, packet xmited through ring16 2010 * queue_mapping = 1, goes to ring 0. (highest priority queue 2011 * queue_mapping = 2, goes to ring 1. 2012 * queue_mapping = 3, goes to ring 2. 2013 * queue_mapping = 4, goes to ring 3. 2014 */ 2015 if (index == 0) 2016 index = DESC_INDEX; 2017 else 2018 index -= 1; 2019 2020 ring = &priv->tx_rings[index]; 2021 txq = netdev_get_tx_queue(dev, ring->queue); 2022 2023 nr_frags = skb_shinfo(skb)->nr_frags; 2024 2025 spin_lock(&ring->lock); 2026 if (ring->free_bds <= (nr_frags + 1)) { 2027 if (!netif_tx_queue_stopped(txq)) { 2028 netif_tx_stop_queue(txq); 2029 netdev_err(dev, 2030 "%s: tx ring %d full when queue %d awake\n", 2031 __func__, index, ring->queue); 2032 } 2033 ret = NETDEV_TX_BUSY; 2034 goto out; 2035 } 2036 2037 /* Retain how many bytes will be sent on the wire, without TSB inserted 2038 * by transmit checksum offload 2039 */ 2040 GENET_CB(skb)->bytes_sent = skb->len; 2041 2042 /* add the Transmit Status Block */ 2043 skb = bcmgenet_add_tsb(dev, skb); 2044 if (!skb) { 2045 ret = NETDEV_TX_OK; 2046 goto out; 2047 } 2048 2049 for (i = 0; i <= nr_frags; i++) { 2050 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2051 2052 BUG_ON(!tx_cb_ptr); 2053 2054 if (!i) { 2055 /* Transmit single SKB or head of fragment list */ 2056 GENET_CB(skb)->first_cb = tx_cb_ptr; 2057 size = skb_headlen(skb); 2058 mapping = dma_map_single(kdev, skb->data, size, 2059 DMA_TO_DEVICE); 2060 } else { 2061 /* xmit fragment */ 2062 frag = &skb_shinfo(skb)->frags[i - 1]; 2063 size = skb_frag_size(frag); 2064 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2065 DMA_TO_DEVICE); 2066 } 2067 2068 ret = dma_mapping_error(kdev, mapping); 2069 if (ret) { 2070 priv->mib.tx_dma_failed++; 2071 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2072 ret = NETDEV_TX_OK; 2073 goto out_unmap_frags; 2074 } 2075 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2076 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2077 2078 tx_cb_ptr->skb = skb; 2079 2080 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2081 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2082 2083 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2084 * will need to restore software padding of "runt" packets 2085 */ 2086 len_stat |= DMA_TX_APPEND_CRC; 2087 2088 if (!i) { 2089 len_stat |= DMA_SOP; 2090 if (skb->ip_summed == CHECKSUM_PARTIAL) 2091 len_stat |= DMA_TX_DO_CSUM; 2092 } 2093 if (i == nr_frags) 2094 len_stat |= DMA_EOP; 2095 2096 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2097 } 2098 2099 GENET_CB(skb)->last_cb = tx_cb_ptr; 2100 2101 bcmgenet_hide_tsb(skb); 2102 skb_tx_timestamp(skb); 2103 2104 /* Decrement total BD count and advance our write pointer */ 2105 ring->free_bds -= nr_frags + 1; 2106 ring->prod_index += nr_frags + 1; 2107 ring->prod_index &= DMA_P_INDEX_MASK; 2108 2109 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2110 2111 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2112 netif_tx_stop_queue(txq); 2113 2114 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2115 /* Packets are ready, update producer index */ 2116 bcmgenet_tdma_ring_writel(priv, ring->index, 2117 ring->prod_index, TDMA_PROD_INDEX); 2118out: 2119 spin_unlock(&ring->lock); 2120 2121 return ret; 2122 2123out_unmap_frags: 2124 /* Back up for failed control block mapping */ 2125 bcmgenet_put_txcb(priv, ring); 2126 2127 /* Unmap successfully mapped control blocks */ 2128 while (i-- > 0) { 2129 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2130 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2131 } 2132 2133 dev_kfree_skb(skb); 2134 goto out; 2135} 2136 2137static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2138 struct enet_cb *cb) 2139{ 2140 struct device *kdev = &priv->pdev->dev; 2141 struct sk_buff *skb; 2142 struct sk_buff *rx_skb; 2143 dma_addr_t mapping; 2144 2145 /* Allocate a new Rx skb */ 2146 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2147 GFP_ATOMIC | __GFP_NOWARN); 2148 if (!skb) { 2149 priv->mib.alloc_rx_buff_failed++; 2150 netif_err(priv, rx_err, priv->dev, 2151 "%s: Rx skb allocation failed\n", __func__); 2152 return NULL; 2153 } 2154 2155 /* DMA-map the new Rx skb */ 2156 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2157 DMA_FROM_DEVICE); 2158 if (dma_mapping_error(kdev, mapping)) { 2159 priv->mib.rx_dma_failed++; 2160 dev_kfree_skb_any(skb); 2161 netif_err(priv, rx_err, priv->dev, 2162 "%s: Rx skb DMA mapping failed\n", __func__); 2163 return NULL; 2164 } 2165 2166 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2167 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2168 2169 /* Put the new Rx skb on the ring */ 2170 cb->skb = skb; 2171 dma_unmap_addr_set(cb, dma_addr, mapping); 2172 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2173 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2174 2175 /* Return the current Rx skb to caller */ 2176 return rx_skb; 2177} 2178 2179/* bcmgenet_desc_rx - descriptor based rx process. 2180 * this could be called from bottom half, or from NAPI polling method. 2181 */ 2182static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2183 unsigned int budget) 2184{ 2185 struct bcmgenet_priv *priv = ring->priv; 2186 struct net_device *dev = priv->dev; 2187 struct enet_cb *cb; 2188 struct sk_buff *skb; 2189 u32 dma_length_status; 2190 unsigned long dma_flag; 2191 int len; 2192 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2193 unsigned int bytes_processed = 0; 2194 unsigned int p_index, mask; 2195 unsigned int discards; 2196 2197 /* Clear status before servicing to reduce spurious interrupts */ 2198 if (ring->index == DESC_INDEX) { 2199 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 2200 INTRL2_CPU_CLEAR); 2201 } else { 2202 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2203 bcmgenet_intrl2_1_writel(priv, 2204 mask, 2205 INTRL2_CPU_CLEAR); 2206 } 2207 2208 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2209 2210 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2211 DMA_P_INDEX_DISCARD_CNT_MASK; 2212 if (discards > ring->old_discards) { 2213 discards = discards - ring->old_discards; 2214 ring->errors += discards; 2215 ring->old_discards += discards; 2216 2217 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2218 if (ring->old_discards >= 0xC000) { 2219 ring->old_discards = 0; 2220 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2221 RDMA_PROD_INDEX); 2222 } 2223 } 2224 2225 p_index &= DMA_P_INDEX_MASK; 2226 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2227 2228 netif_dbg(priv, rx_status, dev, 2229 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2230 2231 while ((rxpktprocessed < rxpkttoprocess) && 2232 (rxpktprocessed < budget)) { 2233 struct status_64 *status; 2234 __be16 rx_csum; 2235 2236 cb = &priv->rx_cbs[ring->read_ptr]; 2237 skb = bcmgenet_rx_refill(priv, cb); 2238 2239 if (unlikely(!skb)) { 2240 ring->dropped++; 2241 goto next; 2242 } 2243 2244 status = (struct status_64 *)skb->data; 2245 dma_length_status = status->length_status; 2246 if (dev->features & NETIF_F_RXCSUM) { 2247 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2248 if (rx_csum) { 2249 skb->csum = (__force __wsum)ntohs(rx_csum); 2250 skb->ip_summed = CHECKSUM_COMPLETE; 2251 } 2252 } 2253 2254 /* DMA flags and length are still valid no matter how 2255 * we got the Receive Status Vector (64B RSB or register) 2256 */ 2257 dma_flag = dma_length_status & 0xffff; 2258 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2259 2260 netif_dbg(priv, rx_status, dev, 2261 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2262 __func__, p_index, ring->c_index, 2263 ring->read_ptr, dma_length_status); 2264 2265 if (unlikely(len > RX_BUF_LENGTH)) { 2266 netif_err(priv, rx_status, dev, "oversized packet\n"); 2267 dev->stats.rx_length_errors++; 2268 dev->stats.rx_errors++; 2269 dev_kfree_skb_any(skb); 2270 goto next; 2271 } 2272 2273 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2274 netif_err(priv, rx_status, dev, 2275 "dropping fragmented packet!\n"); 2276 ring->errors++; 2277 dev_kfree_skb_any(skb); 2278 goto next; 2279 } 2280 2281 /* report errors */ 2282 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2283 DMA_RX_OV | 2284 DMA_RX_NO | 2285 DMA_RX_LG | 2286 DMA_RX_RXER))) { 2287 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2288 (unsigned int)dma_flag); 2289 if (dma_flag & DMA_RX_CRC_ERROR) 2290 dev->stats.rx_crc_errors++; 2291 if (dma_flag & DMA_RX_OV) 2292 dev->stats.rx_over_errors++; 2293 if (dma_flag & DMA_RX_NO) 2294 dev->stats.rx_frame_errors++; 2295 if (dma_flag & DMA_RX_LG) 2296 dev->stats.rx_length_errors++; 2297 dev->stats.rx_errors++; 2298 dev_kfree_skb_any(skb); 2299 goto next; 2300 } /* error packet */ 2301 2302 skb_put(skb, len); 2303 2304 /* remove RSB and hardware 2bytes added for IP alignment */ 2305 skb_pull(skb, 66); 2306 len -= 66; 2307 2308 if (priv->crc_fwd_en) { 2309 skb_trim(skb, len - ETH_FCS_LEN); 2310 len -= ETH_FCS_LEN; 2311 } 2312 2313 bytes_processed += len; 2314 2315 /*Finish setting up the received SKB and send it to the kernel*/ 2316 skb->protocol = eth_type_trans(skb, priv->dev); 2317 ring->packets++; 2318 ring->bytes += len; 2319 if (dma_flag & DMA_RX_MULT) 2320 dev->stats.multicast++; 2321 2322 /* Notify kernel */ 2323 napi_gro_receive(&ring->napi, skb); 2324 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2325 2326next: 2327 rxpktprocessed++; 2328 if (likely(ring->read_ptr < ring->end_ptr)) 2329 ring->read_ptr++; 2330 else 2331 ring->read_ptr = ring->cb_ptr; 2332 2333 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2334 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2335 } 2336 2337 ring->dim.bytes = bytes_processed; 2338 ring->dim.packets = rxpktprocessed; 2339 2340 return rxpktprocessed; 2341} 2342 2343/* Rx NAPI polling method */ 2344static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2345{ 2346 struct bcmgenet_rx_ring *ring = container_of(napi, 2347 struct bcmgenet_rx_ring, napi); 2348 struct dim_sample dim_sample = {}; 2349 unsigned int work_done; 2350 2351 work_done = bcmgenet_desc_rx(ring, budget); 2352 2353 if (work_done < budget) { 2354 napi_complete_done(napi, work_done); 2355 ring->int_enable(ring); 2356 } 2357 2358 if (ring->dim.use_dim) { 2359 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2360 ring->dim.bytes, &dim_sample); 2361 net_dim(&ring->dim.dim, dim_sample); 2362 } 2363 2364 return work_done; 2365} 2366 2367static void bcmgenet_dim_work(struct work_struct *work) 2368{ 2369 struct dim *dim = container_of(work, struct dim, work); 2370 struct bcmgenet_net_dim *ndim = 2371 container_of(dim, struct bcmgenet_net_dim, dim); 2372 struct bcmgenet_rx_ring *ring = 2373 container_of(ndim, struct bcmgenet_rx_ring, dim); 2374 struct dim_cq_moder cur_profile = 2375 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2376 2377 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2378 dim->state = DIM_START_MEASURE; 2379} 2380 2381/* Assign skb to RX DMA descriptor. */ 2382static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2383 struct bcmgenet_rx_ring *ring) 2384{ 2385 struct enet_cb *cb; 2386 struct sk_buff *skb; 2387 int i; 2388 2389 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2390 2391 /* loop here for each buffer needing assign */ 2392 for (i = 0; i < ring->size; i++) { 2393 cb = ring->cbs + i; 2394 skb = bcmgenet_rx_refill(priv, cb); 2395 if (skb) 2396 dev_consume_skb_any(skb); 2397 if (!cb->skb) 2398 return -ENOMEM; 2399 } 2400 2401 return 0; 2402} 2403 2404static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2405{ 2406 struct sk_buff *skb; 2407 struct enet_cb *cb; 2408 int i; 2409 2410 for (i = 0; i < priv->num_rx_bds; i++) { 2411 cb = &priv->rx_cbs[i]; 2412 2413 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2414 if (skb) 2415 dev_consume_skb_any(skb); 2416 } 2417} 2418 2419static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2420{ 2421 u32 reg; 2422 2423 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2424 if (reg & CMD_SW_RESET) 2425 return; 2426 if (enable) 2427 reg |= mask; 2428 else 2429 reg &= ~mask; 2430 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2431 2432 /* UniMAC stops on a packet boundary, wait for a full-size packet 2433 * to be processed 2434 */ 2435 if (enable == 0) 2436 usleep_range(1000, 2000); 2437} 2438 2439static void reset_umac(struct bcmgenet_priv *priv) 2440{ 2441 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2442 bcmgenet_rbuf_ctrl_set(priv, 0); 2443 udelay(10); 2444 2445 /* issue soft reset and disable MAC while updating its registers */ 2446 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2447 udelay(2); 2448} 2449 2450static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2451{ 2452 /* Mask all interrupts.*/ 2453 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2454 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2455 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2456 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2457} 2458 2459static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2460{ 2461 u32 int0_enable = 0; 2462 2463 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2464 * and MoCA PHY 2465 */ 2466 if (priv->internal_phy) { 2467 int0_enable |= UMAC_IRQ_LINK_EVENT; 2468 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2469 int0_enable |= UMAC_IRQ_PHY_DET_R; 2470 } else if (priv->ext_phy) { 2471 int0_enable |= UMAC_IRQ_LINK_EVENT; 2472 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2473 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2474 int0_enable |= UMAC_IRQ_LINK_EVENT; 2475 } 2476 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2477} 2478 2479static void init_umac(struct bcmgenet_priv *priv) 2480{ 2481 struct device *kdev = &priv->pdev->dev; 2482 u32 reg; 2483 u32 int0_enable = 0; 2484 2485 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2486 2487 reset_umac(priv); 2488 2489 /* clear tx/rx counter */ 2490 bcmgenet_umac_writel(priv, 2491 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2492 UMAC_MIB_CTRL); 2493 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2494 2495 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2496 2497 /* init tx registers, enable TSB */ 2498 reg = bcmgenet_tbuf_ctrl_get(priv); 2499 reg |= TBUF_64B_EN; 2500 bcmgenet_tbuf_ctrl_set(priv, reg); 2501 2502 /* init rx registers, enable ip header optimization and RSB */ 2503 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2504 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2505 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2506 2507 /* enable rx checksumming */ 2508 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2509 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2510 /* If UniMAC forwards CRC, we need to skip over it to get 2511 * a valid CHK bit to be set in the per-packet status word 2512 */ 2513 if (priv->crc_fwd_en) 2514 reg |= RBUF_SKIP_FCS; 2515 else 2516 reg &= ~RBUF_SKIP_FCS; 2517 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2518 2519 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2520 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2521 2522 bcmgenet_intr_disable(priv); 2523 2524 /* Configure backpressure vectors for MoCA */ 2525 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2526 reg = bcmgenet_bp_mc_get(priv); 2527 reg |= BIT(priv->hw_params->bp_in_en_shift); 2528 2529 /* bp_mask: back pressure mask */ 2530 if (netif_is_multiqueue(priv->dev)) 2531 reg |= priv->hw_params->bp_in_mask; 2532 else 2533 reg &= ~priv->hw_params->bp_in_mask; 2534 bcmgenet_bp_mc_set(priv, reg); 2535 } 2536 2537 /* Enable MDIO interrupts on GENET v3+ */ 2538 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2539 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2540 2541 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2542 2543 dev_dbg(kdev, "done init umac\n"); 2544} 2545 2546static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2547 void (*cb)(struct work_struct *work)) 2548{ 2549 struct bcmgenet_net_dim *dim = &ring->dim; 2550 2551 INIT_WORK(&dim->dim.work, cb); 2552 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2553 dim->event_ctr = 0; 2554 dim->packets = 0; 2555 dim->bytes = 0; 2556} 2557 2558static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2559{ 2560 struct bcmgenet_net_dim *dim = &ring->dim; 2561 struct dim_cq_moder moder; 2562 u32 usecs, pkts; 2563 2564 usecs = ring->rx_coalesce_usecs; 2565 pkts = ring->rx_max_coalesced_frames; 2566 2567 /* If DIM was enabled, re-apply default parameters */ 2568 if (dim->use_dim) { 2569 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2570 usecs = moder.usec; 2571 pkts = moder.pkts; 2572 } 2573 2574 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2575} 2576 2577/* Initialize a Tx ring along with corresponding hardware registers */ 2578static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2579 unsigned int index, unsigned int size, 2580 unsigned int start_ptr, unsigned int end_ptr) 2581{ 2582 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2583 u32 words_per_bd = WORDS_PER_BD(priv); 2584 u32 flow_period_val = 0; 2585 2586 spin_lock_init(&ring->lock); 2587 ring->priv = priv; 2588 ring->index = index; 2589 if (index == DESC_INDEX) { 2590 ring->queue = 0; 2591 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2592 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2593 } else { 2594 ring->queue = index + 1; 2595 ring->int_enable = bcmgenet_tx_ring_int_enable; 2596 ring->int_disable = bcmgenet_tx_ring_int_disable; 2597 } 2598 ring->cbs = priv->tx_cbs + start_ptr; 2599 ring->size = size; 2600 ring->clean_ptr = start_ptr; 2601 ring->c_index = 0; 2602 ring->free_bds = size; 2603 ring->write_ptr = start_ptr; 2604 ring->cb_ptr = start_ptr; 2605 ring->end_ptr = end_ptr - 1; 2606 ring->prod_index = 0; 2607 2608 /* Set flow period for ring != 16 */ 2609 if (index != DESC_INDEX) 2610 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2611 2612 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2613 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2614 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2615 /* Disable rate control for now */ 2616 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2617 TDMA_FLOW_PERIOD); 2618 bcmgenet_tdma_ring_writel(priv, index, 2619 ((size << DMA_RING_SIZE_SHIFT) | 2620 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2621 2622 /* Set start and end address, read and write pointers */ 2623 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2624 DMA_START_ADDR); 2625 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2626 TDMA_READ_PTR); 2627 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2628 TDMA_WRITE_PTR); 2629 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2630 DMA_END_ADDR); 2631 2632 /* Initialize Tx NAPI */ 2633 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2634 NAPI_POLL_WEIGHT); 2635} 2636 2637/* Initialize a RDMA ring */ 2638static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2639 unsigned int index, unsigned int size, 2640 unsigned int start_ptr, unsigned int end_ptr) 2641{ 2642 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2643 u32 words_per_bd = WORDS_PER_BD(priv); 2644 int ret; 2645 2646 ring->priv = priv; 2647 ring->index = index; 2648 if (index == DESC_INDEX) { 2649 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2650 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2651 } else { 2652 ring->int_enable = bcmgenet_rx_ring_int_enable; 2653 ring->int_disable = bcmgenet_rx_ring_int_disable; 2654 } 2655 ring->cbs = priv->rx_cbs + start_ptr; 2656 ring->size = size; 2657 ring->c_index = 0; 2658 ring->read_ptr = start_ptr; 2659 ring->cb_ptr = start_ptr; 2660 ring->end_ptr = end_ptr - 1; 2661 2662 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2663 if (ret) 2664 return ret; 2665 2666 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2667 bcmgenet_init_rx_coalesce(ring); 2668 2669 /* Initialize Rx NAPI */ 2670 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2671 NAPI_POLL_WEIGHT); 2672 2673 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2674 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2675 bcmgenet_rdma_ring_writel(priv, index, 2676 ((size << DMA_RING_SIZE_SHIFT) | 2677 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2678 bcmgenet_rdma_ring_writel(priv, index, 2679 (DMA_FC_THRESH_LO << 2680 DMA_XOFF_THRESHOLD_SHIFT) | 2681 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2682 2683 /* Set start and end address, read and write pointers */ 2684 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2685 DMA_START_ADDR); 2686 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2687 RDMA_READ_PTR); 2688 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2689 RDMA_WRITE_PTR); 2690 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2691 DMA_END_ADDR); 2692 2693 return ret; 2694} 2695 2696static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2697{ 2698 unsigned int i; 2699 struct bcmgenet_tx_ring *ring; 2700 2701 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2702 ring = &priv->tx_rings[i]; 2703 napi_enable(&ring->napi); 2704 ring->int_enable(ring); 2705 } 2706 2707 ring = &priv->tx_rings[DESC_INDEX]; 2708 napi_enable(&ring->napi); 2709 ring->int_enable(ring); 2710} 2711 2712static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2713{ 2714 unsigned int i; 2715 struct bcmgenet_tx_ring *ring; 2716 2717 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2718 ring = &priv->tx_rings[i]; 2719 napi_disable(&ring->napi); 2720 } 2721 2722 ring = &priv->tx_rings[DESC_INDEX]; 2723 napi_disable(&ring->napi); 2724} 2725 2726static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2727{ 2728 unsigned int i; 2729 struct bcmgenet_tx_ring *ring; 2730 2731 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2732 ring = &priv->tx_rings[i]; 2733 netif_napi_del(&ring->napi); 2734 } 2735 2736 ring = &priv->tx_rings[DESC_INDEX]; 2737 netif_napi_del(&ring->napi); 2738} 2739 2740/* Initialize Tx queues 2741 * 2742 * Queues 0-3 are priority-based, each one has 32 descriptors, 2743 * with queue 0 being the highest priority queue. 2744 * 2745 * Queue 16 is the default Tx queue with 2746 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2747 * 2748 * The transmit control block pool is then partitioned as follows: 2749 * - Tx queue 0 uses tx_cbs[0..31] 2750 * - Tx queue 1 uses tx_cbs[32..63] 2751 * - Tx queue 2 uses tx_cbs[64..95] 2752 * - Tx queue 3 uses tx_cbs[96..127] 2753 * - Tx queue 16 uses tx_cbs[128..255] 2754 */ 2755static void bcmgenet_init_tx_queues(struct net_device *dev) 2756{ 2757 struct bcmgenet_priv *priv = netdev_priv(dev); 2758 u32 i, dma_enable; 2759 u32 dma_ctrl, ring_cfg; 2760 u32 dma_priority[3] = {0, 0, 0}; 2761 2762 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2763 dma_enable = dma_ctrl & DMA_EN; 2764 dma_ctrl &= ~DMA_EN; 2765 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2766 2767 dma_ctrl = 0; 2768 ring_cfg = 0; 2769 2770 /* Enable strict priority arbiter mode */ 2771 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2772 2773 /* Initialize Tx priority queues */ 2774 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2775 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2776 i * priv->hw_params->tx_bds_per_q, 2777 (i + 1) * priv->hw_params->tx_bds_per_q); 2778 ring_cfg |= (1 << i); 2779 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2780 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2781 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2782 } 2783 2784 /* Initialize Tx default queue 16 */ 2785 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2786 priv->hw_params->tx_queues * 2787 priv->hw_params->tx_bds_per_q, 2788 TOTAL_DESC); 2789 ring_cfg |= (1 << DESC_INDEX); 2790 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2791 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2792 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2793 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2794 2795 /* Set Tx queue priorities */ 2796 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2797 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2798 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2799 2800 /* Enable Tx queues */ 2801 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2802 2803 /* Enable Tx DMA */ 2804 if (dma_enable) 2805 dma_ctrl |= DMA_EN; 2806 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2807} 2808 2809static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2810{ 2811 unsigned int i; 2812 struct bcmgenet_rx_ring *ring; 2813 2814 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2815 ring = &priv->rx_rings[i]; 2816 napi_enable(&ring->napi); 2817 ring->int_enable(ring); 2818 } 2819 2820 ring = &priv->rx_rings[DESC_INDEX]; 2821 napi_enable(&ring->napi); 2822 ring->int_enable(ring); 2823} 2824 2825static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2826{ 2827 unsigned int i; 2828 struct bcmgenet_rx_ring *ring; 2829 2830 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2831 ring = &priv->rx_rings[i]; 2832 napi_disable(&ring->napi); 2833 cancel_work_sync(&ring->dim.dim.work); 2834 } 2835 2836 ring = &priv->rx_rings[DESC_INDEX]; 2837 napi_disable(&ring->napi); 2838 cancel_work_sync(&ring->dim.dim.work); 2839} 2840 2841static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2842{ 2843 unsigned int i; 2844 struct bcmgenet_rx_ring *ring; 2845 2846 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2847 ring = &priv->rx_rings[i]; 2848 netif_napi_del(&ring->napi); 2849 } 2850 2851 ring = &priv->rx_rings[DESC_INDEX]; 2852 netif_napi_del(&ring->napi); 2853} 2854 2855/* Initialize Rx queues 2856 * 2857 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2858 * used to direct traffic to these queues. 2859 * 2860 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2861 */ 2862static int bcmgenet_init_rx_queues(struct net_device *dev) 2863{ 2864 struct bcmgenet_priv *priv = netdev_priv(dev); 2865 u32 i; 2866 u32 dma_enable; 2867 u32 dma_ctrl; 2868 u32 ring_cfg; 2869 int ret; 2870 2871 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2872 dma_enable = dma_ctrl & DMA_EN; 2873 dma_ctrl &= ~DMA_EN; 2874 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2875 2876 dma_ctrl = 0; 2877 ring_cfg = 0; 2878 2879 /* Initialize Rx priority queues */ 2880 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2881 ret = bcmgenet_init_rx_ring(priv, i, 2882 priv->hw_params->rx_bds_per_q, 2883 i * priv->hw_params->rx_bds_per_q, 2884 (i + 1) * 2885 priv->hw_params->rx_bds_per_q); 2886 if (ret) 2887 return ret; 2888 2889 ring_cfg |= (1 << i); 2890 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2891 } 2892 2893 /* Initialize Rx default queue 16 */ 2894 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2895 priv->hw_params->rx_queues * 2896 priv->hw_params->rx_bds_per_q, 2897 TOTAL_DESC); 2898 if (ret) 2899 return ret; 2900 2901 ring_cfg |= (1 << DESC_INDEX); 2902 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2903 2904 /* Enable rings */ 2905 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2906 2907 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2908 if (dma_enable) 2909 dma_ctrl |= DMA_EN; 2910 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2911 2912 return 0; 2913} 2914 2915static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2916{ 2917 int ret = 0; 2918 int timeout = 0; 2919 u32 reg; 2920 u32 dma_ctrl; 2921 int i; 2922 2923 /* Disable TDMA to stop add more frames in TX DMA */ 2924 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2925 reg &= ~DMA_EN; 2926 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2927 2928 /* Check TDMA status register to confirm TDMA is disabled */ 2929 while (timeout++ < DMA_TIMEOUT_VAL) { 2930 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2931 if (reg & DMA_DISABLED) 2932 break; 2933 2934 udelay(1); 2935 } 2936 2937 if (timeout == DMA_TIMEOUT_VAL) { 2938 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2939 ret = -ETIMEDOUT; 2940 } 2941 2942 /* Wait 10ms for packet drain in both tx and rx dma */ 2943 usleep_range(10000, 20000); 2944 2945 /* Disable RDMA */ 2946 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2947 reg &= ~DMA_EN; 2948 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2949 2950 timeout = 0; 2951 /* Check RDMA status register to confirm RDMA is disabled */ 2952 while (timeout++ < DMA_TIMEOUT_VAL) { 2953 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2954 if (reg & DMA_DISABLED) 2955 break; 2956 2957 udelay(1); 2958 } 2959 2960 if (timeout == DMA_TIMEOUT_VAL) { 2961 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2962 ret = -ETIMEDOUT; 2963 } 2964 2965 dma_ctrl = 0; 2966 for (i = 0; i < priv->hw_params->rx_queues; i++) 2967 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2968 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2969 reg &= ~dma_ctrl; 2970 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2971 2972 dma_ctrl = 0; 2973 for (i = 0; i < priv->hw_params->tx_queues; i++) 2974 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2975 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2976 reg &= ~dma_ctrl; 2977 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2978 2979 return ret; 2980} 2981 2982static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2983{ 2984 struct netdev_queue *txq; 2985 int i; 2986 2987 bcmgenet_fini_rx_napi(priv); 2988 bcmgenet_fini_tx_napi(priv); 2989 2990 for (i = 0; i < priv->num_tx_bds; i++) 2991 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2992 priv->tx_cbs + i)); 2993 2994 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2995 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2996 netdev_tx_reset_queue(txq); 2997 } 2998 2999 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 3000 netdev_tx_reset_queue(txq); 3001 3002 bcmgenet_free_rx_buffers(priv); 3003 kfree(priv->rx_cbs); 3004 kfree(priv->tx_cbs); 3005} 3006 3007/* init_edma: Initialize DMA control register */ 3008static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 3009{ 3010 int ret; 3011 unsigned int i; 3012 struct enet_cb *cb; 3013 3014 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3015 3016 /* Initialize common Rx ring structures */ 3017 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3018 priv->num_rx_bds = TOTAL_DESC; 3019 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3020 GFP_KERNEL); 3021 if (!priv->rx_cbs) 3022 return -ENOMEM; 3023 3024 for (i = 0; i < priv->num_rx_bds; i++) { 3025 cb = priv->rx_cbs + i; 3026 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3027 } 3028 3029 /* Initialize common TX ring structures */ 3030 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3031 priv->num_tx_bds = TOTAL_DESC; 3032 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3033 GFP_KERNEL); 3034 if (!priv->tx_cbs) { 3035 kfree(priv->rx_cbs); 3036 return -ENOMEM; 3037 } 3038 3039 for (i = 0; i < priv->num_tx_bds; i++) { 3040 cb = priv->tx_cbs + i; 3041 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3042 } 3043 3044 /* Init rDma */ 3045 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3046 DMA_SCB_BURST_SIZE); 3047 3048 /* Initialize Rx queues */ 3049 ret = bcmgenet_init_rx_queues(priv->dev); 3050 if (ret) { 3051 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3052 bcmgenet_free_rx_buffers(priv); 3053 kfree(priv->rx_cbs); 3054 kfree(priv->tx_cbs); 3055 return ret; 3056 } 3057 3058 /* Init tDma */ 3059 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3060 DMA_SCB_BURST_SIZE); 3061 3062 /* Initialize Tx queues */ 3063 bcmgenet_init_tx_queues(priv->dev); 3064 3065 return 0; 3066} 3067 3068/* Interrupt bottom half */ 3069static void bcmgenet_irq_task(struct work_struct *work) 3070{ 3071 unsigned int status; 3072 struct bcmgenet_priv *priv = container_of( 3073 work, struct bcmgenet_priv, bcmgenet_irq_work); 3074 3075 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3076 3077 spin_lock_irq(&priv->lock); 3078 status = priv->irq0_stat; 3079 priv->irq0_stat = 0; 3080 spin_unlock_irq(&priv->lock); 3081 3082 if (status & UMAC_IRQ_PHY_DET_R && 3083 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3084 phy_init_hw(priv->dev->phydev); 3085 genphy_config_aneg(priv->dev->phydev); 3086 } 3087 3088 /* Link UP/DOWN event */ 3089 if (status & UMAC_IRQ_LINK_EVENT) 3090 phy_mac_interrupt(priv->dev->phydev); 3091 3092} 3093 3094/* bcmgenet_isr1: handle Rx and Tx priority queues */ 3095static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3096{ 3097 struct bcmgenet_priv *priv = dev_id; 3098 struct bcmgenet_rx_ring *rx_ring; 3099 struct bcmgenet_tx_ring *tx_ring; 3100 unsigned int index, status; 3101 3102 /* Read irq status */ 3103 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3104 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3105 3106 /* clear interrupts */ 3107 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3108 3109 netif_dbg(priv, intr, priv->dev, 3110 "%s: IRQ=0x%x\n", __func__, status); 3111 3112 /* Check Rx priority queue interrupts */ 3113 for (index = 0; index < priv->hw_params->rx_queues; index++) { 3114 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3115 continue; 3116 3117 rx_ring = &priv->rx_rings[index]; 3118 rx_ring->dim.event_ctr++; 3119 3120 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3121 rx_ring->int_disable(rx_ring); 3122 __napi_schedule_irqoff(&rx_ring->napi); 3123 } 3124 } 3125 3126 /* Check Tx priority queue interrupts */ 3127 for (index = 0; index < priv->hw_params->tx_queues; index++) { 3128 if (!(status & BIT(index))) 3129 continue; 3130 3131 tx_ring = &priv->tx_rings[index]; 3132 3133 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3134 tx_ring->int_disable(tx_ring); 3135 __napi_schedule_irqoff(&tx_ring->napi); 3136 } 3137 } 3138 3139 return IRQ_HANDLED; 3140} 3141 3142/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 3143static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3144{ 3145 struct bcmgenet_priv *priv = dev_id; 3146 struct bcmgenet_rx_ring *rx_ring; 3147 struct bcmgenet_tx_ring *tx_ring; 3148 unsigned int status; 3149 unsigned long flags; 3150 3151 /* Read irq status */ 3152 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3153 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3154 3155 /* clear interrupts */ 3156 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3157 3158 netif_dbg(priv, intr, priv->dev, 3159 "IRQ=0x%x\n", status); 3160 3161 if (status & UMAC_IRQ_RXDMA_DONE) { 3162 rx_ring = &priv->rx_rings[DESC_INDEX]; 3163 rx_ring->dim.event_ctr++; 3164 3165 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3166 rx_ring->int_disable(rx_ring); 3167 __napi_schedule_irqoff(&rx_ring->napi); 3168 } 3169 } 3170 3171 if (status & UMAC_IRQ_TXDMA_DONE) { 3172 tx_ring = &priv->tx_rings[DESC_INDEX]; 3173 3174 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3175 tx_ring->int_disable(tx_ring); 3176 __napi_schedule_irqoff(&tx_ring->napi); 3177 } 3178 } 3179 3180 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 3181 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 3182 wake_up(&priv->wq); 3183 } 3184 3185 /* all other interested interrupts handled in bottom half */ 3186 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3187 if (status) { 3188 /* Save irq status for bottom-half processing. */ 3189 spin_lock_irqsave(&priv->lock, flags); 3190 priv->irq0_stat |= status; 3191 spin_unlock_irqrestore(&priv->lock, flags); 3192 3193 schedule_work(&priv->bcmgenet_irq_work); 3194 } 3195 3196 return IRQ_HANDLED; 3197} 3198 3199static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3200{ 3201 /* Acknowledge the interrupt */ 3202 return IRQ_HANDLED; 3203} 3204 3205#ifdef CONFIG_NET_POLL_CONTROLLER 3206static void bcmgenet_poll_controller(struct net_device *dev) 3207{ 3208 struct bcmgenet_priv *priv = netdev_priv(dev); 3209 3210 /* Invoke the main RX/TX interrupt handler */ 3211 disable_irq(priv->irq0); 3212 bcmgenet_isr0(priv->irq0, priv); 3213 enable_irq(priv->irq0); 3214 3215 /* And the interrupt handler for RX/TX priority queues */ 3216 disable_irq(priv->irq1); 3217 bcmgenet_isr1(priv->irq1, priv); 3218 enable_irq(priv->irq1); 3219} 3220#endif 3221 3222static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3223{ 3224 u32 reg; 3225 3226 reg = bcmgenet_rbuf_ctrl_get(priv); 3227 reg |= BIT(1); 3228 bcmgenet_rbuf_ctrl_set(priv, reg); 3229 udelay(10); 3230 3231 reg &= ~BIT(1); 3232 bcmgenet_rbuf_ctrl_set(priv, reg); 3233 udelay(10); 3234} 3235 3236static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3237 unsigned char *addr) 3238{ 3239 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3240 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3241} 3242 3243static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3244 unsigned char *addr) 3245{ 3246 u32 addr_tmp; 3247 3248 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3249 put_unaligned_be32(addr_tmp, &addr[0]); 3250 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3251 put_unaligned_be16(addr_tmp, &addr[4]); 3252} 3253 3254/* Returns a reusable dma control register value */ 3255static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 3256{ 3257 unsigned int i; 3258 u32 reg; 3259 u32 dma_ctrl; 3260 3261 /* disable DMA */ 3262 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3263 for (i = 0; i < priv->hw_params->tx_queues; i++) 3264 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3265 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3266 reg &= ~dma_ctrl; 3267 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3268 3269 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3270 for (i = 0; i < priv->hw_params->rx_queues; i++) 3271 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3272 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3273 reg &= ~dma_ctrl; 3274 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3275 3276 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3277 udelay(10); 3278 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3279 3280 return dma_ctrl; 3281} 3282 3283static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 3284{ 3285 u32 reg; 3286 3287 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3288 reg |= dma_ctrl; 3289 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3290 3291 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3292 reg |= dma_ctrl; 3293 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3294} 3295 3296static void bcmgenet_netif_start(struct net_device *dev) 3297{ 3298 struct bcmgenet_priv *priv = netdev_priv(dev); 3299 3300 /* Start the network engine */ 3301 bcmgenet_set_rx_mode(dev); 3302 bcmgenet_enable_rx_napi(priv); 3303 3304 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3305 3306 bcmgenet_enable_tx_napi(priv); 3307 3308 /* Monitor link interrupts now */ 3309 bcmgenet_link_intr_enable(priv); 3310 3311 phy_start(dev->phydev); 3312} 3313 3314static int bcmgenet_open(struct net_device *dev) 3315{ 3316 struct bcmgenet_priv *priv = netdev_priv(dev); 3317 unsigned long dma_ctrl; 3318 int ret; 3319 3320 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3321 3322 /* Turn on the clock */ 3323 clk_prepare_enable(priv->clk); 3324 3325 /* If this is an internal GPHY, power it back on now, before UniMAC is 3326 * brought out of reset as absolutely no UniMAC activity is allowed 3327 */ 3328 if (priv->internal_phy) 3329 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3330 3331 /* take MAC out of reset */ 3332 bcmgenet_umac_reset(priv); 3333 3334 init_umac(priv); 3335 3336 /* Apply features again in case we changed them while interface was 3337 * down 3338 */ 3339 bcmgenet_set_features(dev, dev->features); 3340 3341 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3342 3343 /* Disable RX/TX DMA and flush TX queues */ 3344 dma_ctrl = bcmgenet_dma_disable(priv); 3345 3346 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3347 ret = bcmgenet_init_dma(priv); 3348 if (ret) { 3349 netdev_err(dev, "failed to initialize DMA\n"); 3350 goto err_clk_disable; 3351 } 3352 3353 /* Always enable ring 16 - descriptor ring */ 3354 bcmgenet_enable_dma(priv, dma_ctrl); 3355 3356 /* HFB init */ 3357 bcmgenet_hfb_init(priv); 3358 3359 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3360 dev->name, priv); 3361 if (ret < 0) { 3362 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3363 goto err_fini_dma; 3364 } 3365 3366 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3367 dev->name, priv); 3368 if (ret < 0) { 3369 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3370 goto err_irq0; 3371 } 3372 3373 ret = bcmgenet_mii_probe(dev); 3374 if (ret) { 3375 netdev_err(dev, "failed to connect to PHY\n"); 3376 goto err_irq1; 3377 } 3378 3379 bcmgenet_netif_start(dev); 3380 3381 netif_tx_start_all_queues(dev); 3382 3383 return 0; 3384 3385err_irq1: 3386 free_irq(priv->irq1, priv); 3387err_irq0: 3388 free_irq(priv->irq0, priv); 3389err_fini_dma: 3390 bcmgenet_dma_teardown(priv); 3391 bcmgenet_fini_dma(priv); 3392err_clk_disable: 3393 if (priv->internal_phy) 3394 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3395 clk_disable_unprepare(priv->clk); 3396 return ret; 3397} 3398 3399static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3400{ 3401 struct bcmgenet_priv *priv = netdev_priv(dev); 3402 3403 bcmgenet_disable_tx_napi(priv); 3404 netif_tx_disable(dev); 3405 3406 /* Disable MAC receive */ 3407 umac_enable_set(priv, CMD_RX_EN, false); 3408 3409 bcmgenet_dma_teardown(priv); 3410 3411 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3412 umac_enable_set(priv, CMD_TX_EN, false); 3413 3414 if (stop_phy) 3415 phy_stop(dev->phydev); 3416 bcmgenet_disable_rx_napi(priv); 3417 bcmgenet_intr_disable(priv); 3418 3419 /* Wait for pending work items to complete. Since interrupts are 3420 * disabled no new work will be scheduled. 3421 */ 3422 cancel_work_sync(&priv->bcmgenet_irq_work); 3423 3424 priv->old_link = -1; 3425 priv->old_speed = -1; 3426 priv->old_duplex = -1; 3427 priv->old_pause = -1; 3428 3429 /* tx reclaim */ 3430 bcmgenet_tx_reclaim_all(dev); 3431 bcmgenet_fini_dma(priv); 3432} 3433 3434static int bcmgenet_close(struct net_device *dev) 3435{ 3436 struct bcmgenet_priv *priv = netdev_priv(dev); 3437 int ret = 0; 3438 3439 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3440 3441 bcmgenet_netif_stop(dev, false); 3442 3443 /* Really kill the PHY state machine and disconnect from it */ 3444 phy_disconnect(dev->phydev); 3445 3446 free_irq(priv->irq0, priv); 3447 free_irq(priv->irq1, priv); 3448 3449 if (priv->internal_phy) 3450 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3451 3452 clk_disable_unprepare(priv->clk); 3453 3454 return ret; 3455} 3456 3457static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3458{ 3459 struct bcmgenet_priv *priv = ring->priv; 3460 u32 p_index, c_index, intsts, intmsk; 3461 struct netdev_queue *txq; 3462 unsigned int free_bds; 3463 bool txq_stopped; 3464 3465 if (!netif_msg_tx_err(priv)) 3466 return; 3467 3468 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3469 3470 spin_lock(&ring->lock); 3471 if (ring->index == DESC_INDEX) { 3472 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3473 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3474 } else { 3475 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3476 intmsk = 1 << ring->index; 3477 } 3478 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3479 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3480 txq_stopped = netif_tx_queue_stopped(txq); 3481 free_bds = ring->free_bds; 3482 spin_unlock(&ring->lock); 3483 3484 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3485 "TX queue status: %s, interrupts: %s\n" 3486 "(sw)free_bds: %d (sw)size: %d\n" 3487 "(sw)p_index: %d (hw)p_index: %d\n" 3488 "(sw)c_index: %d (hw)c_index: %d\n" 3489 "(sw)clean_p: %d (sw)write_p: %d\n" 3490 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3491 ring->index, ring->queue, 3492 txq_stopped ? "stopped" : "active", 3493 intsts & intmsk ? "enabled" : "disabled", 3494 free_bds, ring->size, 3495 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3496 ring->c_index, c_index & DMA_C_INDEX_MASK, 3497 ring->clean_ptr, ring->write_ptr, 3498 ring->cb_ptr, ring->end_ptr); 3499} 3500 3501static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3502{ 3503 struct bcmgenet_priv *priv = netdev_priv(dev); 3504 u32 int0_enable = 0; 3505 u32 int1_enable = 0; 3506 unsigned int q; 3507 3508 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3509 3510 for (q = 0; q < priv->hw_params->tx_queues; q++) 3511 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3512 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3513 3514 bcmgenet_tx_reclaim_all(dev); 3515 3516 for (q = 0; q < priv->hw_params->tx_queues; q++) 3517 int1_enable |= (1 << q); 3518 3519 int0_enable = UMAC_IRQ_TXDMA_DONE; 3520 3521 /* Re-enable TX interrupts if disabled */ 3522 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3523 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3524 3525 netif_trans_update(dev); 3526 3527 dev->stats.tx_errors++; 3528 3529 netif_tx_wake_all_queues(dev); 3530} 3531 3532#define MAX_MDF_FILTER 17 3533 3534static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3535 unsigned char *addr, 3536 int *i) 3537{ 3538 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3539 UMAC_MDF_ADDR + (*i * 4)); 3540 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3541 addr[4] << 8 | addr[5], 3542 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3543 *i += 2; 3544} 3545 3546static void bcmgenet_set_rx_mode(struct net_device *dev) 3547{ 3548 struct bcmgenet_priv *priv = netdev_priv(dev); 3549 struct netdev_hw_addr *ha; 3550 int i, nfilter; 3551 u32 reg; 3552 3553 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3554 3555 /* Number of filters needed */ 3556 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3557 3558 /* 3559 * Turn on promicuous mode for three scenarios 3560 * 1. IFF_PROMISC flag is set 3561 * 2. IFF_ALLMULTI flag is set 3562 * 3. The number of filters needed exceeds the number filters 3563 * supported by the hardware. 3564 */ 3565 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3566 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3567 (nfilter > MAX_MDF_FILTER)) { 3568 reg |= CMD_PROMISC; 3569 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3570 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3571 return; 3572 } else { 3573 reg &= ~CMD_PROMISC; 3574 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3575 } 3576 3577 /* update MDF filter */ 3578 i = 0; 3579 /* Broadcast */ 3580 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3581 /* my own address.*/ 3582 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3583 3584 /* Unicast */ 3585 netdev_for_each_uc_addr(ha, dev) 3586 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3587 3588 /* Multicast */ 3589 netdev_for_each_mc_addr(ha, dev) 3590 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3591 3592 /* Enable filters */ 3593 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3594 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3595} 3596 3597/* Set the hardware MAC address. */ 3598static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3599{ 3600 struct sockaddr *addr = p; 3601 3602 /* Setting the MAC address at the hardware level is not possible 3603 * without disabling the UniMAC RX/TX enable bits. 3604 */ 3605 if (netif_running(dev)) 3606 return -EBUSY; 3607 3608 ether_addr_copy(dev->dev_addr, addr->sa_data); 3609 3610 return 0; 3611} 3612 3613static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3614{ 3615 struct bcmgenet_priv *priv = netdev_priv(dev); 3616 unsigned long tx_bytes = 0, tx_packets = 0; 3617 unsigned long rx_bytes = 0, rx_packets = 0; 3618 unsigned long rx_errors = 0, rx_dropped = 0; 3619 struct bcmgenet_tx_ring *tx_ring; 3620 struct bcmgenet_rx_ring *rx_ring; 3621 unsigned int q; 3622 3623 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3624 tx_ring = &priv->tx_rings[q]; 3625 tx_bytes += tx_ring->bytes; 3626 tx_packets += tx_ring->packets; 3627 } 3628 tx_ring = &priv->tx_rings[DESC_INDEX]; 3629 tx_bytes += tx_ring->bytes; 3630 tx_packets += tx_ring->packets; 3631 3632 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3633 rx_ring = &priv->rx_rings[q]; 3634 3635 rx_bytes += rx_ring->bytes; 3636 rx_packets += rx_ring->packets; 3637 rx_errors += rx_ring->errors; 3638 rx_dropped += rx_ring->dropped; 3639 } 3640 rx_ring = &priv->rx_rings[DESC_INDEX]; 3641 rx_bytes += rx_ring->bytes; 3642 rx_packets += rx_ring->packets; 3643 rx_errors += rx_ring->errors; 3644 rx_dropped += rx_ring->dropped; 3645 3646 dev->stats.tx_bytes = tx_bytes; 3647 dev->stats.tx_packets = tx_packets; 3648 dev->stats.rx_bytes = rx_bytes; 3649 dev->stats.rx_packets = rx_packets; 3650 dev->stats.rx_errors = rx_errors; 3651 dev->stats.rx_missed_errors = rx_errors; 3652 dev->stats.rx_dropped = rx_dropped; 3653 return &dev->stats; 3654} 3655 3656static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3657{ 3658 struct bcmgenet_priv *priv = netdev_priv(dev); 3659 3660 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3661 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3662 return -EOPNOTSUPP; 3663 3664 if (new_carrier) 3665 netif_carrier_on(dev); 3666 else 3667 netif_carrier_off(dev); 3668 3669 return 0; 3670} 3671 3672static const struct net_device_ops bcmgenet_netdev_ops = { 3673 .ndo_open = bcmgenet_open, 3674 .ndo_stop = bcmgenet_close, 3675 .ndo_start_xmit = bcmgenet_xmit, 3676 .ndo_tx_timeout = bcmgenet_timeout, 3677 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3678 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3679 .ndo_do_ioctl = phy_do_ioctl_running, 3680 .ndo_set_features = bcmgenet_set_features, 3681#ifdef CONFIG_NET_POLL_CONTROLLER 3682 .ndo_poll_controller = bcmgenet_poll_controller, 3683#endif 3684 .ndo_get_stats = bcmgenet_get_stats, 3685 .ndo_change_carrier = bcmgenet_change_carrier, 3686}; 3687 3688/* Array of GENET hardware parameters/characteristics */ 3689static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3690 [GENET_V1] = { 3691 .tx_queues = 0, 3692 .tx_bds_per_q = 0, 3693 .rx_queues = 0, 3694 .rx_bds_per_q = 0, 3695 .bp_in_en_shift = 16, 3696 .bp_in_mask = 0xffff, 3697 .hfb_filter_cnt = 16, 3698 .qtag_mask = 0x1F, 3699 .hfb_offset = 0x1000, 3700 .rdma_offset = 0x2000, 3701 .tdma_offset = 0x3000, 3702 .words_per_bd = 2, 3703 }, 3704 [GENET_V2] = { 3705 .tx_queues = 4, 3706 .tx_bds_per_q = 32, 3707 .rx_queues = 0, 3708 .rx_bds_per_q = 0, 3709 .bp_in_en_shift = 16, 3710 .bp_in_mask = 0xffff, 3711 .hfb_filter_cnt = 16, 3712 .qtag_mask = 0x1F, 3713 .tbuf_offset = 0x0600, 3714 .hfb_offset = 0x1000, 3715 .hfb_reg_offset = 0x2000, 3716 .rdma_offset = 0x3000, 3717 .tdma_offset = 0x4000, 3718 .words_per_bd = 2, 3719 .flags = GENET_HAS_EXT, 3720 }, 3721 [GENET_V3] = { 3722 .tx_queues = 4, 3723 .tx_bds_per_q = 32, 3724 .rx_queues = 0, 3725 .rx_bds_per_q = 0, 3726 .bp_in_en_shift = 17, 3727 .bp_in_mask = 0x1ffff, 3728 .hfb_filter_cnt = 48, 3729 .hfb_filter_size = 128, 3730 .qtag_mask = 0x3F, 3731 .tbuf_offset = 0x0600, 3732 .hfb_offset = 0x8000, 3733 .hfb_reg_offset = 0xfc00, 3734 .rdma_offset = 0x10000, 3735 .tdma_offset = 0x11000, 3736 .words_per_bd = 2, 3737 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3738 GENET_HAS_MOCA_LINK_DET, 3739 }, 3740 [GENET_V4] = { 3741 .tx_queues = 4, 3742 .tx_bds_per_q = 32, 3743 .rx_queues = 0, 3744 .rx_bds_per_q = 0, 3745 .bp_in_en_shift = 17, 3746 .bp_in_mask = 0x1ffff, 3747 .hfb_filter_cnt = 48, 3748 .hfb_filter_size = 128, 3749 .qtag_mask = 0x3F, 3750 .tbuf_offset = 0x0600, 3751 .hfb_offset = 0x8000, 3752 .hfb_reg_offset = 0xfc00, 3753 .rdma_offset = 0x2000, 3754 .tdma_offset = 0x4000, 3755 .words_per_bd = 3, 3756 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3757 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3758 }, 3759 [GENET_V5] = { 3760 .tx_queues = 4, 3761 .tx_bds_per_q = 32, 3762 .rx_queues = 0, 3763 .rx_bds_per_q = 0, 3764 .bp_in_en_shift = 17, 3765 .bp_in_mask = 0x1ffff, 3766 .hfb_filter_cnt = 48, 3767 .hfb_filter_size = 128, 3768 .qtag_mask = 0x3F, 3769 .tbuf_offset = 0x0600, 3770 .hfb_offset = 0x8000, 3771 .hfb_reg_offset = 0xfc00, 3772 .rdma_offset = 0x2000, 3773 .tdma_offset = 0x4000, 3774 .words_per_bd = 3, 3775 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3776 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3777 }, 3778}; 3779 3780/* Infer hardware parameters from the detected GENET version */ 3781static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3782{ 3783 struct bcmgenet_hw_params *params; 3784 u32 reg; 3785 u8 major; 3786 u16 gphy_rev; 3787 3788 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3789 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3790 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3791 } else if (GENET_IS_V3(priv)) { 3792 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3793 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3794 } else if (GENET_IS_V2(priv)) { 3795 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3796 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3797 } else if (GENET_IS_V1(priv)) { 3798 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3799 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3800 } 3801 3802 /* enum genet_version starts at 1 */ 3803 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3804 params = priv->hw_params; 3805 3806 /* Read GENET HW version */ 3807 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3808 major = (reg >> 24 & 0x0f); 3809 if (major == 6) 3810 major = 5; 3811 else if (major == 5) 3812 major = 4; 3813 else if (major == 0) 3814 major = 1; 3815 if (major != priv->version) { 3816 dev_err(&priv->pdev->dev, 3817 "GENET version mismatch, got: %d, configured for: %d\n", 3818 major, priv->version); 3819 } 3820 3821 /* Print the GENET core version */ 3822 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3823 major, (reg >> 16) & 0x0f, reg & 0xffff); 3824 3825 /* Store the integrated PHY revision for the MDIO probing function 3826 * to pass this information to the PHY driver. The PHY driver expects 3827 * to find the PHY major revision in bits 15:8 while the GENET register 3828 * stores that information in bits 7:0, account for that. 3829 * 3830 * On newer chips, starting with PHY revision G0, a new scheme is 3831 * deployed similar to the Starfighter 2 switch with GPHY major 3832 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3833 * is reserved as well as special value 0x01ff, we have a small 3834 * heuristic to check for the new GPHY revision and re-arrange things 3835 * so the GPHY driver is happy. 3836 */ 3837 gphy_rev = reg & 0xffff; 3838 3839 if (GENET_IS_V5(priv)) { 3840 /* The EPHY revision should come from the MDIO registers of 3841 * the PHY not from GENET. 3842 */ 3843 if (gphy_rev != 0) { 3844 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3845 gphy_rev); 3846 } 3847 /* This is reserved so should require special treatment */ 3848 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3849 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3850 return; 3851 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3852 } else if ((gphy_rev & 0xf0) != 0) { 3853 priv->gphy_rev = gphy_rev << 8; 3854 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3855 } else if ((gphy_rev & 0xff00) != 0) { 3856 priv->gphy_rev = gphy_rev; 3857 } 3858 3859#ifdef CONFIG_PHYS_ADDR_T_64BIT 3860 if (!(params->flags & GENET_HAS_40BITS)) 3861 pr_warn("GENET does not support 40-bits PA\n"); 3862#endif 3863 3864 pr_debug("Configuration for version: %d\n" 3865 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3866 "BP << en: %2d, BP msk: 0x%05x\n" 3867 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3868 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3869 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3870 "Words/BD: %d\n", 3871 priv->version, 3872 params->tx_queues, params->tx_bds_per_q, 3873 params->rx_queues, params->rx_bds_per_q, 3874 params->bp_in_en_shift, params->bp_in_mask, 3875 params->hfb_filter_cnt, params->qtag_mask, 3876 params->tbuf_offset, params->hfb_offset, 3877 params->hfb_reg_offset, 3878 params->rdma_offset, params->tdma_offset, 3879 params->words_per_bd); 3880} 3881 3882struct bcmgenet_plat_data { 3883 enum bcmgenet_version version; 3884 u32 dma_max_burst_length; 3885}; 3886 3887static const struct bcmgenet_plat_data v1_plat_data = { 3888 .version = GENET_V1, 3889 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3890}; 3891 3892static const struct bcmgenet_plat_data v2_plat_data = { 3893 .version = GENET_V2, 3894 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3895}; 3896 3897static const struct bcmgenet_plat_data v3_plat_data = { 3898 .version = GENET_V3, 3899 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3900}; 3901 3902static const struct bcmgenet_plat_data v4_plat_data = { 3903 .version = GENET_V4, 3904 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3905}; 3906 3907static const struct bcmgenet_plat_data v5_plat_data = { 3908 .version = GENET_V5, 3909 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3910}; 3911 3912static const struct bcmgenet_plat_data bcm2711_plat_data = { 3913 .version = GENET_V5, 3914 .dma_max_burst_length = 0x08, 3915}; 3916 3917static const struct of_device_id bcmgenet_match[] = { 3918 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3919 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3920 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3921 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3922 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3923 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3924 { }, 3925}; 3926MODULE_DEVICE_TABLE(of, bcmgenet_match); 3927 3928static int bcmgenet_probe(struct platform_device *pdev) 3929{ 3930 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3931 const struct bcmgenet_plat_data *pdata; 3932 struct bcmgenet_priv *priv; 3933 struct net_device *dev; 3934 unsigned int i; 3935 int err = -EIO; 3936 3937 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3938 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3939 GENET_MAX_MQ_CNT + 1); 3940 if (!dev) { 3941 dev_err(&pdev->dev, "can't allocate net device\n"); 3942 return -ENOMEM; 3943 } 3944 3945 priv = netdev_priv(dev); 3946 priv->irq0 = platform_get_irq(pdev, 0); 3947 if (priv->irq0 < 0) { 3948 err = priv->irq0; 3949 goto err; 3950 } 3951 priv->irq1 = platform_get_irq(pdev, 1); 3952 if (priv->irq1 < 0) { 3953 err = priv->irq1; 3954 goto err; 3955 } 3956 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3957 if (priv->wol_irq == -EPROBE_DEFER) { 3958 err = priv->wol_irq; 3959 goto err; 3960 } 3961 3962 priv->base = devm_platform_ioremap_resource(pdev, 0); 3963 if (IS_ERR(priv->base)) { 3964 err = PTR_ERR(priv->base); 3965 goto err; 3966 } 3967 3968 spin_lock_init(&priv->lock); 3969 3970 SET_NETDEV_DEV(dev, &pdev->dev); 3971 dev_set_drvdata(&pdev->dev, dev); 3972 dev->watchdog_timeo = 2 * HZ; 3973 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3974 dev->netdev_ops = &bcmgenet_netdev_ops; 3975 3976 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3977 3978 /* Set default features */ 3979 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3980 NETIF_F_RXCSUM; 3981 dev->hw_features |= dev->features; 3982 dev->vlan_features |= dev->features; 3983 3984 /* Request the WOL interrupt and advertise suspend if available */ 3985 priv->wol_irq_disabled = true; 3986 if (priv->wol_irq > 0) { 3987 err = devm_request_irq(&pdev->dev, priv->wol_irq, 3988 bcmgenet_wol_isr, 0, dev->name, priv); 3989 if (!err) 3990 device_set_wakeup_capable(&pdev->dev, 1); 3991 } 3992 3993 /* Set the needed headroom to account for any possible 3994 * features enabling/disabling at runtime 3995 */ 3996 dev->needed_headroom += 64; 3997 3998 netdev_boot_setup_check(dev); 3999 4000 priv->dev = dev; 4001 priv->pdev = pdev; 4002 4003 pdata = device_get_match_data(&pdev->dev); 4004 if (pdata) { 4005 priv->version = pdata->version; 4006 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4007 } else { 4008 priv->version = pd->genet_version; 4009 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 4010 } 4011 4012 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4013 if (IS_ERR(priv->clk)) { 4014 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4015 err = PTR_ERR(priv->clk); 4016 goto err; 4017 } 4018 4019 err = clk_prepare_enable(priv->clk); 4020 if (err) 4021 goto err; 4022 4023 bcmgenet_set_hw_params(priv); 4024 4025 err = -EIO; 4026 if (priv->hw_params->flags & GENET_HAS_40BITS) 4027 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4028 if (err) 4029 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4030 if (err) 4031 goto err_clk_disable; 4032 4033 /* Mii wait queue */ 4034 init_waitqueue_head(&priv->wq); 4035 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4036 priv->rx_buf_len = RX_BUF_LENGTH; 4037 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4038 4039 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4040 if (IS_ERR(priv->clk_wol)) { 4041 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4042 err = PTR_ERR(priv->clk_wol); 4043 goto err_clk_disable; 4044 } 4045 4046 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4047 if (IS_ERR(priv->clk_eee)) { 4048 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4049 err = PTR_ERR(priv->clk_eee); 4050 goto err_clk_disable; 4051 } 4052 4053 /* If this is an internal GPHY, power it on now, before UniMAC is 4054 * brought out of reset as absolutely no UniMAC activity is allowed 4055 */ 4056 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4057 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4058 4059 if (pd && !IS_ERR_OR_NULL(pd->mac_address)) 4060 ether_addr_copy(dev->dev_addr, pd->mac_address); 4061 else 4062 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 4063 if (has_acpi_companion(&pdev->dev)) 4064 bcmgenet_get_hw_addr(priv, dev->dev_addr); 4065 4066 if (!is_valid_ether_addr(dev->dev_addr)) { 4067 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4068 eth_hw_addr_random(dev); 4069 } 4070 4071 reset_umac(priv); 4072 4073 err = bcmgenet_mii_init(dev); 4074 if (err) 4075 goto err_clk_disable; 4076 4077 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 4078 * just the ring 16 descriptor based TX 4079 */ 4080 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4081 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4082 4083 /* Set default coalescing parameters */ 4084 for (i = 0; i < priv->hw_params->rx_queues; i++) 4085 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4086 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 4087 4088 /* libphy will determine the link state */ 4089 netif_carrier_off(dev); 4090 4091 /* Turn off the main clock, WOL clock is handled separately */ 4092 clk_disable_unprepare(priv->clk); 4093 4094 err = register_netdev(dev); 4095 if (err) { 4096 bcmgenet_mii_exit(dev); 4097 goto err; 4098 } 4099 4100 return err; 4101 4102err_clk_disable: 4103 clk_disable_unprepare(priv->clk); 4104err: 4105 free_netdev(dev); 4106 return err; 4107} 4108 4109static int bcmgenet_remove(struct platform_device *pdev) 4110{ 4111 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4112 4113 dev_set_drvdata(&pdev->dev, NULL); 4114 unregister_netdev(priv->dev); 4115 bcmgenet_mii_exit(priv->dev); 4116 free_netdev(priv->dev); 4117 4118 return 0; 4119} 4120 4121static void bcmgenet_shutdown(struct platform_device *pdev) 4122{ 4123 bcmgenet_remove(pdev); 4124} 4125 4126#ifdef CONFIG_PM_SLEEP 4127static int bcmgenet_resume_noirq(struct device *d) 4128{ 4129 struct net_device *dev = dev_get_drvdata(d); 4130 struct bcmgenet_priv *priv = netdev_priv(dev); 4131 int ret; 4132 u32 reg; 4133 4134 if (!netif_running(dev)) 4135 return 0; 4136 4137 /* Turn on the clock */ 4138 ret = clk_prepare_enable(priv->clk); 4139 if (ret) 4140 return ret; 4141 4142 if (device_may_wakeup(d) && priv->wolopts) { 4143 /* Account for Wake-on-LAN events and clear those events 4144 * (Some devices need more time between enabling the clocks 4145 * and the interrupt register reflecting the wake event so 4146 * read the register twice) 4147 */ 4148 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4149 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4150 if (reg & UMAC_IRQ_WAKE_EVENT) 4151 pm_wakeup_event(&priv->pdev->dev, 0); 4152 } 4153 4154 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); 4155 4156 return 0; 4157} 4158 4159static int bcmgenet_resume(struct device *d) 4160{ 4161 struct net_device *dev = dev_get_drvdata(d); 4162 struct bcmgenet_priv *priv = netdev_priv(dev); 4163 struct bcmgenet_rxnfc_rule *rule; 4164 unsigned long dma_ctrl; 4165 int ret; 4166 4167 if (!netif_running(dev)) 4168 return 0; 4169 4170 /* From WOL-enabled suspend, switch to regular clock */ 4171 if (device_may_wakeup(d) && priv->wolopts) 4172 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 4173 4174 /* If this is an internal GPHY, power it back on now, before UniMAC is 4175 * brought out of reset as absolutely no UniMAC activity is allowed 4176 */ 4177 if (priv->internal_phy) 4178 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4179 4180 bcmgenet_umac_reset(priv); 4181 4182 init_umac(priv); 4183 4184 phy_init_hw(dev->phydev); 4185 4186 /* Speed settings must be restored */ 4187 genphy_config_aneg(dev->phydev); 4188 bcmgenet_mii_config(priv->dev, false); 4189 4190 /* Restore enabled features */ 4191 bcmgenet_set_features(dev, dev->features); 4192 4193 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4194 4195 /* Restore hardware filters */ 4196 bcmgenet_hfb_clear(priv); 4197 list_for_each_entry(rule, &priv->rxnfc_list, list) 4198 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4199 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4200 4201 /* Disable RX/TX DMA and flush TX queues */ 4202 dma_ctrl = bcmgenet_dma_disable(priv); 4203 4204 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4205 ret = bcmgenet_init_dma(priv); 4206 if (ret) { 4207 netdev_err(dev, "failed to initialize DMA\n"); 4208 goto out_clk_disable; 4209 } 4210 4211 /* Always enable ring 16 - descriptor ring */ 4212 bcmgenet_enable_dma(priv, dma_ctrl); 4213 4214 if (!device_may_wakeup(d)) 4215 phy_resume(dev->phydev); 4216 4217 bcmgenet_netif_start(dev); 4218 4219 netif_device_attach(dev); 4220 4221 return 0; 4222 4223out_clk_disable: 4224 if (priv->internal_phy) 4225 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4226 clk_disable_unprepare(priv->clk); 4227 return ret; 4228} 4229 4230static int bcmgenet_suspend(struct device *d) 4231{ 4232 struct net_device *dev = dev_get_drvdata(d); 4233 struct bcmgenet_priv *priv = netdev_priv(dev); 4234 4235 if (!netif_running(dev)) 4236 return 0; 4237 4238 netif_device_detach(dev); 4239 4240 bcmgenet_netif_stop(dev, true); 4241 4242 if (!device_may_wakeup(d)) 4243 phy_suspend(dev->phydev); 4244 4245 /* Disable filtering */ 4246 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 4247 4248 return 0; 4249} 4250 4251static int bcmgenet_suspend_noirq(struct device *d) 4252{ 4253 struct net_device *dev = dev_get_drvdata(d); 4254 struct bcmgenet_priv *priv = netdev_priv(dev); 4255 int ret = 0; 4256 4257 if (!netif_running(dev)) 4258 return 0; 4259 4260 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4261 if (device_may_wakeup(d) && priv->wolopts) 4262 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4263 else if (priv->internal_phy) 4264 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4265 4266 /* Let the framework handle resumption and leave the clocks on */ 4267 if (ret) 4268 return ret; 4269 4270 /* Turn off the clocks */ 4271 clk_disable_unprepare(priv->clk); 4272 4273 return 0; 4274} 4275#else 4276#define bcmgenet_suspend NULL 4277#define bcmgenet_suspend_noirq NULL 4278#define bcmgenet_resume NULL 4279#define bcmgenet_resume_noirq NULL 4280#endif /* CONFIG_PM_SLEEP */ 4281 4282static const struct dev_pm_ops bcmgenet_pm_ops = { 4283 .suspend = bcmgenet_suspend, 4284 .suspend_noirq = bcmgenet_suspend_noirq, 4285 .resume = bcmgenet_resume, 4286 .resume_noirq = bcmgenet_resume_noirq, 4287}; 4288 4289static const struct acpi_device_id genet_acpi_match[] = { 4290 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4291 { }, 4292}; 4293MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4294 4295static struct platform_driver bcmgenet_driver = { 4296 .probe = bcmgenet_probe, 4297 .remove = bcmgenet_remove, 4298 .shutdown = bcmgenet_shutdown, 4299 .driver = { 4300 .name = "bcmgenet", 4301 .of_match_table = bcmgenet_match, 4302 .pm = &bcmgenet_pm_ops, 4303 .acpi_match_table = genet_acpi_match, 4304 }, 4305}; 4306module_platform_driver(bcmgenet_driver); 4307 4308MODULE_AUTHOR("Broadcom Corporation"); 4309MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4310MODULE_ALIAS("platform:bcmgenet"); 4311MODULE_LICENSE("GPL"); 4312MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4313