18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Applied Micro X-Gene SoC Ethernet v2 Driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2017, Applied Micro Circuits Corporation 68c2ecf20Sopenharmony_ci * Author(s): Iyappan Subramanian <isubramanian@apm.com> 78c2ecf20Sopenharmony_ci * Keyur Chudgar <kchudgar@apm.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef __XGENE_ENET_V2_MAC_H__ 118c2ecf20Sopenharmony_ci#define __XGENE_ENET_V2_MAC_H__ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* Register offsets */ 148c2ecf20Sopenharmony_ci#define MAC_CONFIG_1 0xa000 158c2ecf20Sopenharmony_ci#define MAC_CONFIG_2 0xa004 168c2ecf20Sopenharmony_ci#define MII_MGMT_CONFIG 0xa020 178c2ecf20Sopenharmony_ci#define MII_MGMT_COMMAND 0xa024 188c2ecf20Sopenharmony_ci#define MII_MGMT_ADDRESS 0xa028 198c2ecf20Sopenharmony_ci#define MII_MGMT_CONTROL 0xa02c 208c2ecf20Sopenharmony_ci#define MII_MGMT_STATUS 0xa030 218c2ecf20Sopenharmony_ci#define MII_MGMT_INDICATORS 0xa034 228c2ecf20Sopenharmony_ci#define INTERFACE_CONTROL 0xa038 238c2ecf20Sopenharmony_ci#define STATION_ADDR0 0xa040 248c2ecf20Sopenharmony_ci#define STATION_ADDR1 0xa044 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#define RGMII_REG_0 0x27e0 278c2ecf20Sopenharmony_ci#define ICM_CONFIG0_REG_0 0x2c00 288c2ecf20Sopenharmony_ci#define ICM_CONFIG2_REG_0 0x2c08 298c2ecf20Sopenharmony_ci#define ECM_CONFIG0_REG_0 0x2d00 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci/* Register fields */ 328c2ecf20Sopenharmony_ci#define SOFT_RESET BIT(31) 338c2ecf20Sopenharmony_ci#define TX_EN BIT(0) 348c2ecf20Sopenharmony_ci#define RX_EN BIT(2) 358c2ecf20Sopenharmony_ci#define PAD_CRC BIT(2) 368c2ecf20Sopenharmony_ci#define CRC_EN BIT(1) 378c2ecf20Sopenharmony_ci#define FULL_DUPLEX BIT(0) 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci#define INTF_MODE_POS 8 408c2ecf20Sopenharmony_ci#define INTF_MODE_LEN 2 418c2ecf20Sopenharmony_ci#define HD_MODE_POS 25 428c2ecf20Sopenharmony_ci#define HD_MODE_LEN 2 438c2ecf20Sopenharmony_ci#define CFG_MACMODE_POS 18 448c2ecf20Sopenharmony_ci#define CFG_MACMODE_LEN 2 458c2ecf20Sopenharmony_ci#define CFG_WAITASYNCRD_POS 0 468c2ecf20Sopenharmony_ci#define CFG_WAITASYNCRD_LEN 16 478c2ecf20Sopenharmony_ci#define CFG_SPEED_125_POS 24 488c2ecf20Sopenharmony_ci#define CFG_WFIFOFULLTHR_POS 0 498c2ecf20Sopenharmony_ci#define CFG_WFIFOFULLTHR_LEN 7 508c2ecf20Sopenharmony_ci#define MGMT_CLOCK_SEL_POS 0 518c2ecf20Sopenharmony_ci#define MGMT_CLOCK_SEL_LEN 3 528c2ecf20Sopenharmony_ci#define PHY_ADDR_POS 8 538c2ecf20Sopenharmony_ci#define PHY_ADDR_LEN 5 548c2ecf20Sopenharmony_ci#define REG_ADDR_POS 0 558c2ecf20Sopenharmony_ci#define REG_ADDR_LEN 5 568c2ecf20Sopenharmony_ci#define MII_MGMT_BUSY BIT(0) 578c2ecf20Sopenharmony_ci#define MII_READ_CYCLE BIT(0) 588c2ecf20Sopenharmony_ci#define CFG_WAITASYNCRD_EN BIT(16) 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_cistatic inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val) 618c2ecf20Sopenharmony_ci{ 628c2ecf20Sopenharmony_ci u32 mask = GENMASK(pos + len, pos); 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci *var &= ~mask; 658c2ecf20Sopenharmony_ci *var |= ((val << pos) & mask); 668c2ecf20Sopenharmony_ci} 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_cistatic inline u32 xgene_get_reg_bits(u32 var, int pos, int len) 698c2ecf20Sopenharmony_ci{ 708c2ecf20Sopenharmony_ci u32 mask = GENMASK(pos + len, pos); 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci return (var & mask) >> pos; 738c2ecf20Sopenharmony_ci} 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci#define SET_REG_BITS(var, field, val) \ 768c2ecf20Sopenharmony_ci xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val) 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci#define SET_REG_BIT(var, field, val) \ 798c2ecf20Sopenharmony_ci xgene_set_reg_bits(var, field ## _POS, 1, val) 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ci#define GET_REG_BITS(var, field) \ 828c2ecf20Sopenharmony_ci xgene_get_reg_bits(var, field ## _POS, field ## _LEN) 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci#define GET_REG_BIT(var, field) ((var) & (field)) 858c2ecf20Sopenharmony_ci 868c2ecf20Sopenharmony_cistruct xge_pdata; 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_civoid xge_mac_reset(struct xge_pdata *pdata); 898c2ecf20Sopenharmony_civoid xge_mac_set_speed(struct xge_pdata *pdata); 908c2ecf20Sopenharmony_civoid xge_mac_enable(struct xge_pdata *pdata); 918c2ecf20Sopenharmony_civoid xge_mac_disable(struct xge_pdata *pdata); 928c2ecf20Sopenharmony_civoid xge_mac_init(struct xge_pdata *pdata); 938c2ecf20Sopenharmony_civoid xge_mac_set_station_addr(struct xge_pdata *pdata); 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci#endif /* __XGENE_ENET_V2_MAC_H__ */ 96