18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Applied Micro X-Gene SoC Ethernet v2 Driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2017, Applied Micro Circuits Corporation 68c2ecf20Sopenharmony_ci * Author(s): Iyappan Subramanian <isubramanian@apm.com> 78c2ecf20Sopenharmony_ci * Keyur Chudgar <kchudgar@apm.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef __XGENE_ENET_V2_ENET_H__ 118c2ecf20Sopenharmony_ci#define __XGENE_ENET_V2_ENET_H__ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#define ENET_CLKEN 0xc008 148c2ecf20Sopenharmony_ci#define ENET_SRST 0xc000 158c2ecf20Sopenharmony_ci#define ENET_SHIM 0xc010 168c2ecf20Sopenharmony_ci#define CFG_MEM_RAM_SHUTDOWN 0xd070 178c2ecf20Sopenharmony_ci#define BLOCK_MEM_RDY 0xd074 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci#define MEM_RDY 0xffffffff 208c2ecf20Sopenharmony_ci#define DEVM_ARAUX_COH BIT(19) 218c2ecf20Sopenharmony_ci#define DEVM_AWAUX_COH BIT(3) 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define CFG_FORCE_LINK_STATUS_EN 0x229c 248c2ecf20Sopenharmony_ci#define FORCE_LINK_STATUS 0x22a0 258c2ecf20Sopenharmony_ci#define CFG_LINK_AGGR_RESUME 0x27c8 268c2ecf20Sopenharmony_ci#define RX_DV_GATE_REG 0x2dfc 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_civoid xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val); 298c2ecf20Sopenharmony_ciu32 xge_rd_csr(struct xge_pdata *pdata, u32 offset); 308c2ecf20Sopenharmony_ciint xge_port_reset(struct net_device *ndev); 318c2ecf20Sopenharmony_civoid xge_port_init(struct net_device *ndev); 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#endif /* __XGENE_ENET_V2_ENET__H__ */ 34