1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117#include <linux/interrupt.h> 118#include <linux/module.h> 119#include <linux/kmod.h> 120#include <linux/mdio.h> 121#include <linux/phy.h> 122#include <linux/of.h> 123#include <linux/bitops.h> 124#include <linux/jiffies.h> 125 126#include "xgbe.h" 127#include "xgbe-common.h" 128 129static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 130 struct ethtool_eeprom *eeprom, u8 *data) 131{ 132 if (!pdata->phy_if.phy_impl.module_eeprom) 133 return -ENXIO; 134 135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); 136} 137 138static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 139 struct ethtool_modinfo *modinfo) 140{ 141 if (!pdata->phy_if.phy_impl.module_info) 142 return -ENXIO; 143 144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); 145} 146 147static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) 148{ 149 int reg; 150 151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 152 reg &= ~XGBE_AN_CL37_INT_MASK; 153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 154} 155 156static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) 157{ 158 int reg; 159 160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 161 reg &= ~XGBE_AN_CL37_INT_MASK; 162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 163 164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 165 reg &= ~XGBE_PCS_CL37_BP; 166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 167} 168 169static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) 170{ 171 int reg; 172 173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 174 reg |= XGBE_PCS_CL37_BP; 175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 176 177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 178 reg |= XGBE_AN_CL37_INT_MASK; 179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 180} 181 182static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) 183{ 184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 185} 186 187static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) 188{ 189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); 190} 191 192static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) 193{ 194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); 195} 196 197static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) 198{ 199 switch (pdata->an_mode) { 200 case XGBE_AN_MODE_CL73: 201 case XGBE_AN_MODE_CL73_REDRV: 202 xgbe_an73_enable_interrupts(pdata); 203 break; 204 case XGBE_AN_MODE_CL37: 205 case XGBE_AN_MODE_CL37_SGMII: 206 xgbe_an37_enable_interrupts(pdata); 207 break; 208 default: 209 break; 210 } 211} 212 213static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) 214{ 215 xgbe_an73_clear_interrupts(pdata); 216 xgbe_an37_clear_interrupts(pdata); 217} 218 219static void xgbe_kr_mode(struct xgbe_prv_data *pdata) 220{ 221 /* Set MAC to 10G speed */ 222 pdata->hw_if.set_speed(pdata, SPEED_10000); 223 224 /* Call PHY implementation support to complete rate change */ 225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); 226} 227 228static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) 229{ 230 /* Set MAC to 2.5G speed */ 231 pdata->hw_if.set_speed(pdata, SPEED_2500); 232 233 /* Call PHY implementation support to complete rate change */ 234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); 235} 236 237static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) 238{ 239 /* Set MAC to 1G speed */ 240 pdata->hw_if.set_speed(pdata, SPEED_1000); 241 242 /* Call PHY implementation support to complete rate change */ 243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); 244} 245 246static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) 247{ 248 /* If a KR re-driver is present, change to KR mode instead */ 249 if (pdata->kr_redrv) 250 return xgbe_kr_mode(pdata); 251 252 /* Set MAC to 10G speed */ 253 pdata->hw_if.set_speed(pdata, SPEED_10000); 254 255 /* Call PHY implementation support to complete rate change */ 256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); 257} 258 259static void xgbe_x_mode(struct xgbe_prv_data *pdata) 260{ 261 /* Set MAC to 1G speed */ 262 pdata->hw_if.set_speed(pdata, SPEED_1000); 263 264 /* Call PHY implementation support to complete rate change */ 265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); 266} 267 268static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) 269{ 270 /* Set MAC to 1G speed */ 271 pdata->hw_if.set_speed(pdata, SPEED_1000); 272 273 /* Call PHY implementation support to complete rate change */ 274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); 275} 276 277static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) 278{ 279 /* Set MAC to 1G speed */ 280 pdata->hw_if.set_speed(pdata, SPEED_1000); 281 282 /* Call PHY implementation support to complete rate change */ 283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); 284} 285 286static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) 287{ 288 return pdata->phy_if.phy_impl.cur_mode(pdata); 289} 290 291static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) 292{ 293 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); 294} 295 296static void xgbe_change_mode(struct xgbe_prv_data *pdata, 297 enum xgbe_mode mode) 298{ 299 switch (mode) { 300 case XGBE_MODE_KX_1000: 301 xgbe_kx_1000_mode(pdata); 302 break; 303 case XGBE_MODE_KX_2500: 304 xgbe_kx_2500_mode(pdata); 305 break; 306 case XGBE_MODE_KR: 307 xgbe_kr_mode(pdata); 308 break; 309 case XGBE_MODE_SGMII_100: 310 xgbe_sgmii_100_mode(pdata); 311 break; 312 case XGBE_MODE_SGMII_1000: 313 xgbe_sgmii_1000_mode(pdata); 314 break; 315 case XGBE_MODE_X: 316 xgbe_x_mode(pdata); 317 break; 318 case XGBE_MODE_SFI: 319 xgbe_sfi_mode(pdata); 320 break; 321 case XGBE_MODE_UNKNOWN: 322 break; 323 default: 324 netif_dbg(pdata, link, pdata->netdev, 325 "invalid operation mode requested (%u)\n", mode); 326 } 327} 328 329static void xgbe_switch_mode(struct xgbe_prv_data *pdata) 330{ 331 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); 332} 333 334static bool xgbe_set_mode(struct xgbe_prv_data *pdata, 335 enum xgbe_mode mode) 336{ 337 if (mode == xgbe_cur_mode(pdata)) 338 return false; 339 340 xgbe_change_mode(pdata, mode); 341 342 return true; 343} 344 345static bool xgbe_use_mode(struct xgbe_prv_data *pdata, 346 enum xgbe_mode mode) 347{ 348 return pdata->phy_if.phy_impl.use_mode(pdata, mode); 349} 350 351static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, 352 bool restart) 353{ 354 unsigned int reg; 355 356 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); 357 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; 358 359 if (enable) 360 reg |= MDIO_VEND2_CTRL1_AN_ENABLE; 361 362 if (restart) 363 reg |= MDIO_VEND2_CTRL1_AN_RESTART; 364 365 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); 366} 367 368static void xgbe_an37_restart(struct xgbe_prv_data *pdata) 369{ 370 xgbe_an37_enable_interrupts(pdata); 371 xgbe_an37_set(pdata, true, true); 372 373 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); 374} 375 376static void xgbe_an37_disable(struct xgbe_prv_data *pdata) 377{ 378 xgbe_an37_set(pdata, false, false); 379 xgbe_an37_disable_interrupts(pdata); 380 381 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); 382} 383 384static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, 385 bool restart) 386{ 387 unsigned int reg; 388 389 /* Disable KR training for now */ 390 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 391 reg &= ~XGBE_KR_TRAINING_ENABLE; 392 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 393 394 /* Update AN settings */ 395 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); 396 reg &= ~MDIO_AN_CTRL1_ENABLE; 397 398 if (enable) 399 reg |= MDIO_AN_CTRL1_ENABLE; 400 401 if (restart) 402 reg |= MDIO_AN_CTRL1_RESTART; 403 404 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); 405} 406 407static void xgbe_an73_restart(struct xgbe_prv_data *pdata) 408{ 409 xgbe_an73_enable_interrupts(pdata); 410 xgbe_an73_set(pdata, true, true); 411 412 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); 413} 414 415static void xgbe_an73_disable(struct xgbe_prv_data *pdata) 416{ 417 xgbe_an73_set(pdata, false, false); 418 xgbe_an73_disable_interrupts(pdata); 419 420 pdata->an_start = 0; 421 422 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); 423} 424 425static void xgbe_an_restart(struct xgbe_prv_data *pdata) 426{ 427 if (pdata->phy_if.phy_impl.an_pre) 428 pdata->phy_if.phy_impl.an_pre(pdata); 429 430 switch (pdata->an_mode) { 431 case XGBE_AN_MODE_CL73: 432 case XGBE_AN_MODE_CL73_REDRV: 433 xgbe_an73_restart(pdata); 434 break; 435 case XGBE_AN_MODE_CL37: 436 case XGBE_AN_MODE_CL37_SGMII: 437 xgbe_an37_restart(pdata); 438 break; 439 default: 440 break; 441 } 442} 443 444static void xgbe_an_disable(struct xgbe_prv_data *pdata) 445{ 446 if (pdata->phy_if.phy_impl.an_post) 447 pdata->phy_if.phy_impl.an_post(pdata); 448 449 switch (pdata->an_mode) { 450 case XGBE_AN_MODE_CL73: 451 case XGBE_AN_MODE_CL73_REDRV: 452 xgbe_an73_disable(pdata); 453 break; 454 case XGBE_AN_MODE_CL37: 455 case XGBE_AN_MODE_CL37_SGMII: 456 xgbe_an37_disable(pdata); 457 break; 458 default: 459 break; 460 } 461} 462 463static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) 464{ 465 xgbe_an73_disable(pdata); 466 xgbe_an37_disable(pdata); 467} 468 469static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, 470 enum xgbe_rx *state) 471{ 472 unsigned int ad_reg, lp_reg, reg; 473 474 *state = XGBE_RX_COMPLETE; 475 476 /* If we're not in KR mode then we're done */ 477 if (!xgbe_in_kr_mode(pdata)) 478 return XGBE_AN_PAGE_RECEIVED; 479 480 /* Enable/Disable FEC */ 481 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 482 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 483 484 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); 485 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); 486 if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) 487 reg |= pdata->fec_ability; 488 489 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); 490 491 /* Start KR training */ 492 if (pdata->phy_if.phy_impl.kr_training_pre) 493 pdata->phy_if.phy_impl.kr_training_pre(pdata); 494 495 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 496 reg |= XGBE_KR_TRAINING_ENABLE; 497 reg |= XGBE_KR_TRAINING_START; 498 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 499 pdata->kr_start_time = jiffies; 500 501 netif_dbg(pdata, link, pdata->netdev, 502 "KR training initiated\n"); 503 504 if (pdata->phy_if.phy_impl.kr_training_post) 505 pdata->phy_if.phy_impl.kr_training_post(pdata); 506 507 return XGBE_AN_PAGE_RECEIVED; 508} 509 510static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, 511 enum xgbe_rx *state) 512{ 513 u16 msg; 514 515 *state = XGBE_RX_XNP; 516 517 msg = XGBE_XNP_MCF_NULL_MESSAGE; 518 msg |= XGBE_XNP_MP_FORMATTED; 519 520 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); 521 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); 522 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); 523 524 return XGBE_AN_PAGE_RECEIVED; 525} 526 527static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, 528 enum xgbe_rx *state) 529{ 530 unsigned int link_support; 531 unsigned int reg, ad_reg, lp_reg; 532 533 /* Read Base Ability register 2 first */ 534 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 535 536 /* Check for a supported mode, otherwise restart in a different one */ 537 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; 538 if (!(reg & link_support)) 539 return XGBE_AN_INCOMPAT_LINK; 540 541 /* Check Extended Next Page support */ 542 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 543 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 544 545 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 546 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 547 ? xgbe_an73_tx_xnp(pdata, state) 548 : xgbe_an73_tx_training(pdata, state); 549} 550 551static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, 552 enum xgbe_rx *state) 553{ 554 unsigned int ad_reg, lp_reg; 555 556 /* Check Extended Next Page support */ 557 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); 558 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); 559 560 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 561 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 562 ? xgbe_an73_tx_xnp(pdata, state) 563 : xgbe_an73_tx_training(pdata, state); 564} 565 566static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) 567{ 568 enum xgbe_rx *state; 569 unsigned long an_timeout; 570 enum xgbe_an ret; 571 572 if (!pdata->an_start) { 573 pdata->an_start = jiffies; 574 } else { 575 an_timeout = pdata->an_start + 576 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 577 if (time_after(jiffies, an_timeout)) { 578 /* Auto-negotiation timed out, reset state */ 579 pdata->kr_state = XGBE_RX_BPA; 580 pdata->kx_state = XGBE_RX_BPA; 581 582 pdata->an_start = jiffies; 583 584 netif_dbg(pdata, link, pdata->netdev, 585 "CL73 AN timed out, resetting state\n"); 586 } 587 } 588 589 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state 590 : &pdata->kx_state; 591 592 switch (*state) { 593 case XGBE_RX_BPA: 594 ret = xgbe_an73_rx_bpa(pdata, state); 595 break; 596 597 case XGBE_RX_XNP: 598 ret = xgbe_an73_rx_xnp(pdata, state); 599 break; 600 601 default: 602 ret = XGBE_AN_ERROR; 603 } 604 605 return ret; 606} 607 608static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) 609{ 610 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 611 612 /* Be sure we aren't looping trying to negotiate */ 613 if (xgbe_in_kr_mode(pdata)) { 614 pdata->kr_state = XGBE_RX_ERROR; 615 616 if (!XGBE_ADV(lks, 1000baseKX_Full) && 617 !XGBE_ADV(lks, 2500baseX_Full)) 618 return XGBE_AN_NO_LINK; 619 620 if (pdata->kx_state != XGBE_RX_BPA) 621 return XGBE_AN_NO_LINK; 622 } else { 623 pdata->kx_state = XGBE_RX_ERROR; 624 625 if (!XGBE_ADV(lks, 10000baseKR_Full)) 626 return XGBE_AN_NO_LINK; 627 628 if (pdata->kr_state != XGBE_RX_BPA) 629 return XGBE_AN_NO_LINK; 630 } 631 632 xgbe_an_disable(pdata); 633 634 xgbe_switch_mode(pdata); 635 636 pdata->an_result = XGBE_AN_READY; 637 638 xgbe_an_restart(pdata); 639 640 return XGBE_AN_INCOMPAT_LINK; 641} 642 643static void xgbe_an37_isr(struct xgbe_prv_data *pdata) 644{ 645 unsigned int reg; 646 647 /* Disable AN interrupts */ 648 xgbe_an37_disable_interrupts(pdata); 649 650 /* Save the interrupt(s) that fired */ 651 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 652 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; 653 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; 654 655 if (pdata->an_int) { 656 /* Clear the interrupt(s) that fired and process them */ 657 reg &= ~XGBE_AN_CL37_INT_MASK; 658 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 659 660 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 661 } else { 662 /* Enable AN interrupts */ 663 xgbe_an37_enable_interrupts(pdata); 664 665 /* Reissue interrupt if status is not clear */ 666 if (pdata->vdata->irq_reissue_support) 667 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 668 } 669} 670 671static void xgbe_an73_isr(struct xgbe_prv_data *pdata) 672{ 673 /* Disable AN interrupts */ 674 xgbe_an73_disable_interrupts(pdata); 675 676 /* Save the interrupt(s) that fired */ 677 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); 678 679 if (pdata->an_int) { 680 /* Clear the interrupt(s) that fired and process them */ 681 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); 682 683 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 684 } else { 685 /* Enable AN interrupts */ 686 xgbe_an73_enable_interrupts(pdata); 687 688 /* Reissue interrupt if status is not clear */ 689 if (pdata->vdata->irq_reissue_support) 690 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 691 } 692} 693 694static void xgbe_an_isr_task(struct tasklet_struct *t) 695{ 696 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an); 697 698 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); 699 700 switch (pdata->an_mode) { 701 case XGBE_AN_MODE_CL73: 702 case XGBE_AN_MODE_CL73_REDRV: 703 xgbe_an73_isr(pdata); 704 break; 705 case XGBE_AN_MODE_CL37: 706 case XGBE_AN_MODE_CL37_SGMII: 707 xgbe_an37_isr(pdata); 708 break; 709 default: 710 break; 711 } 712} 713 714static irqreturn_t xgbe_an_isr(int irq, void *data) 715{ 716 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 717 718 if (pdata->isr_as_tasklet) 719 tasklet_schedule(&pdata->tasklet_an); 720 else 721 xgbe_an_isr_task(&pdata->tasklet_an); 722 723 return IRQ_HANDLED; 724} 725 726static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata) 727{ 728 xgbe_an_isr_task(&pdata->tasklet_an); 729 730 return IRQ_HANDLED; 731} 732 733static void xgbe_an_irq_work(struct work_struct *work) 734{ 735 struct xgbe_prv_data *pdata = container_of(work, 736 struct xgbe_prv_data, 737 an_irq_work); 738 739 /* Avoid a race between enabling the IRQ and exiting the work by 740 * waiting for the work to finish and then queueing it 741 */ 742 flush_work(&pdata->an_work); 743 queue_work(pdata->an_workqueue, &pdata->an_work); 744} 745 746static const char *xgbe_state_as_string(enum xgbe_an state) 747{ 748 switch (state) { 749 case XGBE_AN_READY: 750 return "Ready"; 751 case XGBE_AN_PAGE_RECEIVED: 752 return "Page-Received"; 753 case XGBE_AN_INCOMPAT_LINK: 754 return "Incompatible-Link"; 755 case XGBE_AN_COMPLETE: 756 return "Complete"; 757 case XGBE_AN_NO_LINK: 758 return "No-Link"; 759 case XGBE_AN_ERROR: 760 return "Error"; 761 default: 762 return "Undefined"; 763 } 764} 765 766static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) 767{ 768 enum xgbe_an cur_state = pdata->an_state; 769 770 if (!pdata->an_int) 771 return; 772 773 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { 774 pdata->an_state = XGBE_AN_COMPLETE; 775 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; 776 777 /* If SGMII is enabled, check the link status */ 778 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && 779 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) 780 pdata->an_state = XGBE_AN_NO_LINK; 781 } 782 783 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", 784 xgbe_state_as_string(pdata->an_state)); 785 786 cur_state = pdata->an_state; 787 788 switch (pdata->an_state) { 789 case XGBE_AN_READY: 790 break; 791 792 case XGBE_AN_COMPLETE: 793 netif_dbg(pdata, link, pdata->netdev, 794 "Auto negotiation successful\n"); 795 break; 796 797 case XGBE_AN_NO_LINK: 798 break; 799 800 default: 801 pdata->an_state = XGBE_AN_ERROR; 802 } 803 804 if (pdata->an_state == XGBE_AN_ERROR) { 805 netdev_err(pdata->netdev, 806 "error during auto-negotiation, state=%u\n", 807 cur_state); 808 809 pdata->an_int = 0; 810 xgbe_an37_clear_interrupts(pdata); 811 } 812 813 if (pdata->an_state >= XGBE_AN_COMPLETE) { 814 pdata->an_result = pdata->an_state; 815 pdata->an_state = XGBE_AN_READY; 816 817 if (pdata->phy_if.phy_impl.an_post) 818 pdata->phy_if.phy_impl.an_post(pdata); 819 820 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", 821 xgbe_state_as_string(pdata->an_result)); 822 } 823 824 xgbe_an37_enable_interrupts(pdata); 825} 826 827static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) 828{ 829 enum xgbe_an cur_state = pdata->an_state; 830 831 if (!pdata->an_int) 832 return; 833 834next_int: 835 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { 836 pdata->an_state = XGBE_AN_PAGE_RECEIVED; 837 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; 838 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { 839 pdata->an_state = XGBE_AN_INCOMPAT_LINK; 840 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; 841 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { 842 pdata->an_state = XGBE_AN_COMPLETE; 843 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; 844 } else { 845 pdata->an_state = XGBE_AN_ERROR; 846 } 847 848again: 849 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", 850 xgbe_state_as_string(pdata->an_state)); 851 852 cur_state = pdata->an_state; 853 854 switch (pdata->an_state) { 855 case XGBE_AN_READY: 856 pdata->an_supported = 0; 857 break; 858 859 case XGBE_AN_PAGE_RECEIVED: 860 pdata->an_state = xgbe_an73_page_received(pdata); 861 pdata->an_supported++; 862 break; 863 864 case XGBE_AN_INCOMPAT_LINK: 865 pdata->an_supported = 0; 866 pdata->parallel_detect = 0; 867 pdata->an_state = xgbe_an73_incompat_link(pdata); 868 break; 869 870 case XGBE_AN_COMPLETE: 871 pdata->parallel_detect = pdata->an_supported ? 0 : 1; 872 netif_dbg(pdata, link, pdata->netdev, "%s successful\n", 873 pdata->an_supported ? "Auto negotiation" 874 : "Parallel detection"); 875 break; 876 877 case XGBE_AN_NO_LINK: 878 break; 879 880 default: 881 pdata->an_state = XGBE_AN_ERROR; 882 } 883 884 if (pdata->an_state == XGBE_AN_NO_LINK) { 885 pdata->an_int = 0; 886 xgbe_an73_clear_interrupts(pdata); 887 } else if (pdata->an_state == XGBE_AN_ERROR) { 888 netdev_err(pdata->netdev, 889 "error during auto-negotiation, state=%u\n", 890 cur_state); 891 892 pdata->an_int = 0; 893 xgbe_an73_clear_interrupts(pdata); 894 } 895 896 if (pdata->an_state >= XGBE_AN_COMPLETE) { 897 pdata->an_result = pdata->an_state; 898 pdata->an_state = XGBE_AN_READY; 899 pdata->kr_state = XGBE_RX_BPA; 900 pdata->kx_state = XGBE_RX_BPA; 901 pdata->an_start = 0; 902 903 if (pdata->phy_if.phy_impl.an_post) 904 pdata->phy_if.phy_impl.an_post(pdata); 905 906 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", 907 xgbe_state_as_string(pdata->an_result)); 908 } 909 910 if (cur_state != pdata->an_state) 911 goto again; 912 913 if (pdata->an_int) 914 goto next_int; 915 916 xgbe_an73_enable_interrupts(pdata); 917} 918 919static void xgbe_an_state_machine(struct work_struct *work) 920{ 921 struct xgbe_prv_data *pdata = container_of(work, 922 struct xgbe_prv_data, 923 an_work); 924 925 mutex_lock(&pdata->an_mutex); 926 927 switch (pdata->an_mode) { 928 case XGBE_AN_MODE_CL73: 929 case XGBE_AN_MODE_CL73_REDRV: 930 xgbe_an73_state_machine(pdata); 931 break; 932 case XGBE_AN_MODE_CL37: 933 case XGBE_AN_MODE_CL37_SGMII: 934 xgbe_an37_state_machine(pdata); 935 break; 936 default: 937 break; 938 } 939 940 /* Reissue interrupt if status is not clear */ 941 if (pdata->vdata->irq_reissue_support) 942 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 943 944 mutex_unlock(&pdata->an_mutex); 945} 946 947static void xgbe_an37_init(struct xgbe_prv_data *pdata) 948{ 949 struct ethtool_link_ksettings lks; 950 unsigned int reg; 951 952 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 953 954 /* Set up Advertisement register */ 955 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 956 if (XGBE_ADV(&lks, Pause)) 957 reg |= 0x100; 958 else 959 reg &= ~0x100; 960 961 if (XGBE_ADV(&lks, Asym_Pause)) 962 reg |= 0x80; 963 else 964 reg &= ~0x80; 965 966 /* Full duplex, but not half */ 967 reg |= XGBE_AN_CL37_FD_MASK; 968 reg &= ~XGBE_AN_CL37_HD_MASK; 969 970 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); 971 972 /* Set up the Control register */ 973 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 974 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; 975 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; 976 977 switch (pdata->an_mode) { 978 case XGBE_AN_MODE_CL37: 979 reg |= XGBE_AN_CL37_PCS_MODE_BASEX; 980 break; 981 case XGBE_AN_MODE_CL37_SGMII: 982 reg |= XGBE_AN_CL37_PCS_MODE_SGMII; 983 break; 984 default: 985 break; 986 } 987 988 reg |= XGBE_AN_CL37_MII_CTRL_8BIT; 989 990 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 991 992 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", 993 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); 994} 995 996static void xgbe_an73_init(struct xgbe_prv_data *pdata) 997{ 998 struct ethtool_link_ksettings lks; 999 unsigned int reg; 1000 1001 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 1002 1003 /* Set up Advertisement register 3 first */ 1004 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1005 if (XGBE_ADV(&lks, 10000baseR_FEC)) 1006 reg |= 0xc000; 1007 else 1008 reg &= ~0xc000; 1009 1010 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); 1011 1012 /* Set up Advertisement register 2 next */ 1013 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1014 if (XGBE_ADV(&lks, 10000baseKR_Full)) 1015 reg |= 0x80; 1016 else 1017 reg &= ~0x80; 1018 1019 if (XGBE_ADV(&lks, 1000baseKX_Full) || 1020 XGBE_ADV(&lks, 2500baseX_Full)) 1021 reg |= 0x20; 1022 else 1023 reg &= ~0x20; 1024 1025 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); 1026 1027 /* Set up Advertisement register 1 last */ 1028 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1029 if (XGBE_ADV(&lks, Pause)) 1030 reg |= 0x400; 1031 else 1032 reg &= ~0x400; 1033 1034 if (XGBE_ADV(&lks, Asym_Pause)) 1035 reg |= 0x800; 1036 else 1037 reg &= ~0x800; 1038 1039 /* We don't intend to perform XNP */ 1040 reg &= ~XGBE_XNP_NP_EXCHANGE; 1041 1042 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); 1043 1044 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); 1045} 1046 1047static void xgbe_an_init(struct xgbe_prv_data *pdata) 1048{ 1049 /* Set up advertisement registers based on current settings */ 1050 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); 1051 switch (pdata->an_mode) { 1052 case XGBE_AN_MODE_CL73: 1053 case XGBE_AN_MODE_CL73_REDRV: 1054 xgbe_an73_init(pdata); 1055 break; 1056 case XGBE_AN_MODE_CL37: 1057 case XGBE_AN_MODE_CL37_SGMII: 1058 xgbe_an37_init(pdata); 1059 break; 1060 default: 1061 break; 1062 } 1063} 1064 1065static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) 1066{ 1067 if (pdata->tx_pause && pdata->rx_pause) 1068 return "rx/tx"; 1069 else if (pdata->rx_pause) 1070 return "rx"; 1071 else if (pdata->tx_pause) 1072 return "tx"; 1073 else 1074 return "off"; 1075} 1076 1077static const char *xgbe_phy_speed_string(int speed) 1078{ 1079 switch (speed) { 1080 case SPEED_100: 1081 return "100Mbps"; 1082 case SPEED_1000: 1083 return "1Gbps"; 1084 case SPEED_2500: 1085 return "2.5Gbps"; 1086 case SPEED_10000: 1087 return "10Gbps"; 1088 case SPEED_UNKNOWN: 1089 return "Unknown"; 1090 default: 1091 return "Unsupported"; 1092 } 1093} 1094 1095static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) 1096{ 1097 if (pdata->phy.link) 1098 netdev_info(pdata->netdev, 1099 "Link is Up - %s/%s - flow control %s\n", 1100 xgbe_phy_speed_string(pdata->phy.speed), 1101 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", 1102 xgbe_phy_fc_string(pdata)); 1103 else 1104 netdev_info(pdata->netdev, "Link is Down\n"); 1105} 1106 1107static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) 1108{ 1109 int new_state = 0; 1110 1111 if (pdata->phy.link) { 1112 /* Flow control support */ 1113 pdata->pause_autoneg = pdata->phy.pause_autoneg; 1114 1115 if (pdata->tx_pause != pdata->phy.tx_pause) { 1116 new_state = 1; 1117 pdata->tx_pause = pdata->phy.tx_pause; 1118 pdata->hw_if.config_tx_flow_control(pdata); 1119 } 1120 1121 if (pdata->rx_pause != pdata->phy.rx_pause) { 1122 new_state = 1; 1123 pdata->rx_pause = pdata->phy.rx_pause; 1124 pdata->hw_if.config_rx_flow_control(pdata); 1125 } 1126 1127 /* Speed support */ 1128 if (pdata->phy_speed != pdata->phy.speed) { 1129 new_state = 1; 1130 pdata->phy_speed = pdata->phy.speed; 1131 } 1132 1133 if (pdata->phy_link != pdata->phy.link) { 1134 new_state = 1; 1135 pdata->phy_link = pdata->phy.link; 1136 } 1137 } else if (pdata->phy_link) { 1138 new_state = 1; 1139 pdata->phy_link = 0; 1140 pdata->phy_speed = SPEED_UNKNOWN; 1141 } 1142 1143 if (new_state && netif_msg_link(pdata)) 1144 xgbe_phy_print_status(pdata); 1145} 1146 1147static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 1148{ 1149 return pdata->phy_if.phy_impl.valid_speed(pdata, speed); 1150} 1151 1152static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) 1153{ 1154 enum xgbe_mode mode; 1155 1156 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); 1157 1158 /* Disable auto-negotiation */ 1159 xgbe_an_disable(pdata); 1160 1161 /* Set specified mode for specified speed */ 1162 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); 1163 switch (mode) { 1164 case XGBE_MODE_KX_1000: 1165 case XGBE_MODE_KX_2500: 1166 case XGBE_MODE_KR: 1167 case XGBE_MODE_SGMII_100: 1168 case XGBE_MODE_SGMII_1000: 1169 case XGBE_MODE_X: 1170 case XGBE_MODE_SFI: 1171 break; 1172 case XGBE_MODE_UNKNOWN: 1173 default: 1174 return -EINVAL; 1175 } 1176 1177 /* Validate duplex mode */ 1178 if (pdata->phy.duplex != DUPLEX_FULL) 1179 return -EINVAL; 1180 1181 /* Force the mode change for SFI in Fixed PHY config. 1182 * Fixed PHY configs needs PLL to be enabled while doing mode set. 1183 * When the SFP module isn't connected during boot, driver assumes 1184 * AN is ON and attempts autonegotiation. However, if the connected 1185 * SFP comes up in Fixed PHY config, the link will not come up as 1186 * PLL isn't enabled while the initial mode set command is issued. 1187 * So, force the mode change for SFI in Fixed PHY configuration to 1188 * fix link issues. 1189 */ 1190 if (mode == XGBE_MODE_SFI) 1191 xgbe_change_mode(pdata, mode); 1192 else 1193 xgbe_set_mode(pdata, mode); 1194 1195 return 0; 1196} 1197 1198static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode) 1199{ 1200 int ret; 1201 1202 mutex_lock(&pdata->an_mutex); 1203 1204 set_bit(XGBE_LINK_INIT, &pdata->dev_state); 1205 pdata->link_check = jiffies; 1206 1207 ret = pdata->phy_if.phy_impl.an_config(pdata); 1208 if (ret) 1209 goto out; 1210 1211 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1212 ret = xgbe_phy_config_fixed(pdata); 1213 if (ret || !pdata->kr_redrv) 1214 goto out; 1215 1216 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); 1217 } else { 1218 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); 1219 } 1220 1221 /* Disable auto-negotiation interrupt */ 1222 disable_irq(pdata->an_irq); 1223 1224 if (set_mode) { 1225 /* Start auto-negotiation in a supported mode */ 1226 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1227 xgbe_set_mode(pdata, XGBE_MODE_KR); 1228 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1229 xgbe_set_mode(pdata, XGBE_MODE_KX_2500); 1230 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1231 xgbe_set_mode(pdata, XGBE_MODE_KX_1000); 1232 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1233 xgbe_set_mode(pdata, XGBE_MODE_SFI); 1234 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1235 xgbe_set_mode(pdata, XGBE_MODE_X); 1236 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1237 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); 1238 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1239 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); 1240 } else { 1241 enable_irq(pdata->an_irq); 1242 ret = -EINVAL; 1243 goto out; 1244 } 1245 } 1246 1247 /* Disable and stop any in progress auto-negotiation */ 1248 xgbe_an_disable_all(pdata); 1249 1250 /* Clear any auto-negotitation interrupts */ 1251 xgbe_an_clear_interrupts_all(pdata); 1252 1253 pdata->an_result = XGBE_AN_READY; 1254 pdata->an_state = XGBE_AN_READY; 1255 pdata->kr_state = XGBE_RX_BPA; 1256 pdata->kx_state = XGBE_RX_BPA; 1257 1258 /* Re-enable auto-negotiation interrupt */ 1259 enable_irq(pdata->an_irq); 1260 1261 xgbe_an_init(pdata); 1262 xgbe_an_restart(pdata); 1263 1264out: 1265 if (ret) 1266 set_bit(XGBE_LINK_ERR, &pdata->dev_state); 1267 else 1268 clear_bit(XGBE_LINK_ERR, &pdata->dev_state); 1269 1270 mutex_unlock(&pdata->an_mutex); 1271 1272 return ret; 1273} 1274 1275static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 1276{ 1277 return __xgbe_phy_config_aneg(pdata, true); 1278} 1279 1280static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata) 1281{ 1282 return __xgbe_phy_config_aneg(pdata, false); 1283} 1284 1285static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) 1286{ 1287 return (pdata->an_result == XGBE_AN_COMPLETE); 1288} 1289 1290static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) 1291{ 1292 unsigned long link_timeout; 1293 unsigned long kr_time; 1294 int wait; 1295 1296 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); 1297 if (time_after(jiffies, link_timeout)) { 1298 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) && 1299 pdata->phy.autoneg == AUTONEG_ENABLE) { 1300 /* AN restart should not happen while KR training is in progress. 1301 * The while loop ensures no AN restart during KR training, 1302 * waits up to 500ms and AN restart is triggered only if KR 1303 * training is failed. 1304 */ 1305 wait = XGBE_KR_TRAINING_WAIT_ITER; 1306 while (wait--) { 1307 kr_time = pdata->kr_start_time + 1308 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 1309 if (time_after(jiffies, kr_time)) 1310 break; 1311 /* AN restart is not required, if AN result is COMPLETE */ 1312 if (pdata->an_result == XGBE_AN_COMPLETE) 1313 return; 1314 usleep_range(10000, 11000); 1315 } 1316 } 1317 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); 1318 xgbe_phy_config_aneg(pdata); 1319 } 1320} 1321 1322static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) 1323{ 1324 return pdata->phy_if.phy_impl.an_outcome(pdata); 1325} 1326 1327static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata) 1328{ 1329 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1330 enum xgbe_mode mode; 1331 1332 XGBE_ZERO_LP_ADV(lks); 1333 1334 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) 1335 mode = xgbe_cur_mode(pdata); 1336 else 1337 mode = xgbe_phy_status_aneg(pdata); 1338 1339 switch (mode) { 1340 case XGBE_MODE_SGMII_100: 1341 pdata->phy.speed = SPEED_100; 1342 break; 1343 case XGBE_MODE_X: 1344 case XGBE_MODE_KX_1000: 1345 case XGBE_MODE_SGMII_1000: 1346 pdata->phy.speed = SPEED_1000; 1347 break; 1348 case XGBE_MODE_KX_2500: 1349 pdata->phy.speed = SPEED_2500; 1350 break; 1351 case XGBE_MODE_KR: 1352 case XGBE_MODE_SFI: 1353 pdata->phy.speed = SPEED_10000; 1354 break; 1355 case XGBE_MODE_UNKNOWN: 1356 default: 1357 pdata->phy.speed = SPEED_UNKNOWN; 1358 } 1359 1360 pdata->phy.duplex = DUPLEX_FULL; 1361 1362 if (!xgbe_set_mode(pdata, mode)) 1363 return false; 1364 1365 if (pdata->an_again) 1366 xgbe_phy_reconfig_aneg(pdata); 1367 1368 return true; 1369} 1370 1371static void xgbe_phy_status(struct xgbe_prv_data *pdata) 1372{ 1373 unsigned int link_aneg; 1374 int an_restart; 1375 1376 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { 1377 netif_carrier_off(pdata->netdev); 1378 1379 pdata->phy.link = 0; 1380 goto adjust_link; 1381 } 1382 1383 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); 1384 1385 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, 1386 &an_restart); 1387 if (an_restart) { 1388 xgbe_phy_config_aneg(pdata); 1389 goto adjust_link; 1390 } 1391 1392 if (pdata->phy.link) { 1393 if (link_aneg && !xgbe_phy_aneg_done(pdata)) { 1394 xgbe_check_link_timeout(pdata); 1395 return; 1396 } 1397 1398 if (xgbe_phy_status_result(pdata)) 1399 return; 1400 1401 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) 1402 clear_bit(XGBE_LINK_INIT, &pdata->dev_state); 1403 1404 netif_carrier_on(pdata->netdev); 1405 } else { 1406 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 1407 xgbe_check_link_timeout(pdata); 1408 1409 if (link_aneg) 1410 return; 1411 } 1412 1413 xgbe_phy_status_result(pdata); 1414 1415 netif_carrier_off(pdata->netdev); 1416 } 1417 1418adjust_link: 1419 xgbe_phy_adjust_link(pdata); 1420} 1421 1422static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 1423{ 1424 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); 1425 1426 if (!pdata->phy_started) 1427 return; 1428 1429 /* Indicate the PHY is down */ 1430 pdata->phy_started = 0; 1431 1432 /* Disable auto-negotiation */ 1433 xgbe_an_disable_all(pdata); 1434 1435 if (pdata->dev_irq != pdata->an_irq) { 1436 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1437 tasklet_kill(&pdata->tasklet_an); 1438 } 1439 1440 pdata->phy_if.phy_impl.stop(pdata); 1441 1442 pdata->phy.link = 0; 1443 1444 xgbe_phy_adjust_link(pdata); 1445} 1446 1447static int xgbe_phy_start(struct xgbe_prv_data *pdata) 1448{ 1449 struct net_device *netdev = pdata->netdev; 1450 int ret; 1451 1452 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); 1453 1454 ret = pdata->phy_if.phy_impl.start(pdata); 1455 if (ret) 1456 return ret; 1457 1458 /* If we have a separate AN irq, enable it */ 1459 if (pdata->dev_irq != pdata->an_irq) { 1460 tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task); 1461 1462 ret = devm_request_irq(pdata->dev, pdata->an_irq, 1463 xgbe_an_isr, 0, pdata->an_name, 1464 pdata); 1465 if (ret) { 1466 netdev_err(netdev, "phy irq request failed\n"); 1467 goto err_stop; 1468 } 1469 } 1470 1471 /* Set initial mode - call the mode setting routines 1472 * directly to insure we are properly configured 1473 */ 1474 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1475 xgbe_kr_mode(pdata); 1476 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1477 xgbe_kx_2500_mode(pdata); 1478 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1479 xgbe_kx_1000_mode(pdata); 1480 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1481 xgbe_sfi_mode(pdata); 1482 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1483 xgbe_x_mode(pdata); 1484 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1485 xgbe_sgmii_1000_mode(pdata); 1486 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1487 xgbe_sgmii_100_mode(pdata); 1488 } else { 1489 ret = -EINVAL; 1490 goto err_irq; 1491 } 1492 1493 /* Indicate the PHY is up and running */ 1494 pdata->phy_started = 1; 1495 1496 xgbe_an_init(pdata); 1497 xgbe_an_enable_interrupts(pdata); 1498 1499 return xgbe_phy_config_aneg(pdata); 1500 1501err_irq: 1502 if (pdata->dev_irq != pdata->an_irq) 1503 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1504 1505err_stop: 1506 pdata->phy_if.phy_impl.stop(pdata); 1507 1508 return ret; 1509} 1510 1511static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1512{ 1513 int ret; 1514 1515 ret = pdata->phy_if.phy_impl.reset(pdata); 1516 if (ret) 1517 return ret; 1518 1519 /* Disable auto-negotiation for now */ 1520 xgbe_an_disable_all(pdata); 1521 1522 /* Clear auto-negotiation interrupts */ 1523 xgbe_an_clear_interrupts_all(pdata); 1524 1525 return 0; 1526} 1527 1528static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 1529{ 1530 struct device *dev = pdata->dev; 1531 1532 dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); 1533 1534 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1535 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 1536 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1537 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 1538 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, 1539 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 1540 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, 1541 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 1542 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, 1543 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 1544 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, 1545 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 1546 1547 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1548 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 1549 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1550 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 1551 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", 1552 MDIO_AN_ADVERTISE, 1553 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 1554 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", 1555 MDIO_AN_ADVERTISE + 1, 1556 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 1557 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", 1558 MDIO_AN_ADVERTISE + 2, 1559 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 1560 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", 1561 MDIO_AN_COMP_STAT, 1562 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 1563 1564 dev_dbg(dev, "\n*************************************************\n"); 1565} 1566 1567static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) 1568{ 1569 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1570 1571 if (XGBE_ADV(lks, 10000baseKR_Full)) 1572 return SPEED_10000; 1573 else if (XGBE_ADV(lks, 10000baseT_Full)) 1574 return SPEED_10000; 1575 else if (XGBE_ADV(lks, 2500baseX_Full)) 1576 return SPEED_2500; 1577 else if (XGBE_ADV(lks, 2500baseT_Full)) 1578 return SPEED_2500; 1579 else if (XGBE_ADV(lks, 1000baseKX_Full)) 1580 return SPEED_1000; 1581 else if (XGBE_ADV(lks, 1000baseT_Full)) 1582 return SPEED_1000; 1583 else if (XGBE_ADV(lks, 100baseT_Full)) 1584 return SPEED_100; 1585 1586 return SPEED_UNKNOWN; 1587} 1588 1589static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 1590{ 1591 pdata->phy_if.phy_impl.exit(pdata); 1592} 1593 1594static int xgbe_phy_init(struct xgbe_prv_data *pdata) 1595{ 1596 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1597 int ret; 1598 1599 mutex_init(&pdata->an_mutex); 1600 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); 1601 INIT_WORK(&pdata->an_work, xgbe_an_state_machine); 1602 pdata->mdio_mmd = MDIO_MMD_PCS; 1603 1604 /* Check for FEC support */ 1605 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, 1606 MDIO_PMA_10GBR_FECABLE); 1607 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | 1608 MDIO_PMA_10GBR_FECABLE_ERRABLE); 1609 1610 /* Setup the phy (including supported features) */ 1611 ret = pdata->phy_if.phy_impl.init(pdata); 1612 if (ret) 1613 return ret; 1614 1615 /* Copy supported link modes to advertising link modes */ 1616 XGBE_LM_COPY(lks, advertising, lks, supported); 1617 1618 pdata->phy.address = 0; 1619 1620 if (XGBE_ADV(lks, Autoneg)) { 1621 pdata->phy.autoneg = AUTONEG_ENABLE; 1622 pdata->phy.speed = SPEED_UNKNOWN; 1623 pdata->phy.duplex = DUPLEX_UNKNOWN; 1624 } else { 1625 pdata->phy.autoneg = AUTONEG_DISABLE; 1626 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); 1627 pdata->phy.duplex = DUPLEX_FULL; 1628 } 1629 1630 pdata->phy.link = 0; 1631 1632 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1633 pdata->phy.tx_pause = pdata->tx_pause; 1634 pdata->phy.rx_pause = pdata->rx_pause; 1635 1636 /* Fix up Flow Control advertising */ 1637 XGBE_CLR_ADV(lks, Pause); 1638 XGBE_CLR_ADV(lks, Asym_Pause); 1639 1640 if (pdata->rx_pause) { 1641 XGBE_SET_ADV(lks, Pause); 1642 XGBE_SET_ADV(lks, Asym_Pause); 1643 } 1644 1645 if (pdata->tx_pause) { 1646 /* Equivalent to XOR of Asym_Pause */ 1647 if (XGBE_ADV(lks, Asym_Pause)) 1648 XGBE_CLR_ADV(lks, Asym_Pause); 1649 else 1650 XGBE_SET_ADV(lks, Asym_Pause); 1651 } 1652 1653 if (netif_msg_drv(pdata)) 1654 xgbe_dump_phy_registers(pdata); 1655 1656 return 0; 1657} 1658 1659void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) 1660{ 1661 phy_if->phy_init = xgbe_phy_init; 1662 phy_if->phy_exit = xgbe_phy_exit; 1663 1664 phy_if->phy_reset = xgbe_phy_reset; 1665 phy_if->phy_start = xgbe_phy_start; 1666 phy_if->phy_stop = xgbe_phy_stop; 1667 1668 phy_if->phy_status = xgbe_phy_status; 1669 phy_if->phy_config_aneg = xgbe_phy_config_aneg; 1670 1671 phy_if->phy_valid_speed = xgbe_phy_valid_speed; 1672 1673 phy_if->an_isr = xgbe_an_combined_isr; 1674 1675 phy_if->module_info = xgbe_phy_module_info; 1676 phy_if->module_eeprom = xgbe_phy_module_eeprom; 1677} 1678