1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117#include <linux/module.h> 118#include <linux/spinlock.h> 119#include <linux/tcp.h> 120#include <linux/if_vlan.h> 121#include <linux/interrupt.h> 122#include <linux/clk.h> 123#include <linux/if_ether.h> 124#include <linux/net_tstamp.h> 125#include <linux/phy.h> 126#include <net/vxlan.h> 127 128#include "xgbe.h" 129#include "xgbe-common.h" 130 131static unsigned int ecc_sec_info_threshold = 10; 132static unsigned int ecc_sec_warn_threshold = 10000; 133static unsigned int ecc_sec_period = 600; 134static unsigned int ecc_ded_threshold = 2; 135static unsigned int ecc_ded_period = 600; 136 137#ifdef CONFIG_AMD_XGBE_HAVE_ECC 138/* Only expose the ECC parameters if supported */ 139module_param(ecc_sec_info_threshold, uint, 0644); 140MODULE_PARM_DESC(ecc_sec_info_threshold, 141 " ECC corrected error informational threshold setting"); 142 143module_param(ecc_sec_warn_threshold, uint, 0644); 144MODULE_PARM_DESC(ecc_sec_warn_threshold, 145 " ECC corrected error warning threshold setting"); 146 147module_param(ecc_sec_period, uint, 0644); 148MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)"); 149 150module_param(ecc_ded_threshold, uint, 0644); 151MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting"); 152 153module_param(ecc_ded_period, uint, 0644); 154MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)"); 155#endif 156 157static int xgbe_one_poll(struct napi_struct *, int); 158static int xgbe_all_poll(struct napi_struct *, int); 159static void xgbe_stop(struct xgbe_prv_data *); 160 161static void *xgbe_alloc_node(size_t size, int node) 162{ 163 void *mem; 164 165 mem = kzalloc_node(size, GFP_KERNEL, node); 166 if (!mem) 167 mem = kzalloc(size, GFP_KERNEL); 168 169 return mem; 170} 171 172static void xgbe_free_channels(struct xgbe_prv_data *pdata) 173{ 174 unsigned int i; 175 176 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) { 177 if (!pdata->channel[i]) 178 continue; 179 180 kfree(pdata->channel[i]->rx_ring); 181 kfree(pdata->channel[i]->tx_ring); 182 kfree(pdata->channel[i]); 183 184 pdata->channel[i] = NULL; 185 } 186 187 pdata->channel_count = 0; 188} 189 190static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) 191{ 192 struct xgbe_channel *channel; 193 struct xgbe_ring *ring; 194 unsigned int count, i; 195 unsigned int cpu; 196 int node; 197 198 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 199 for (i = 0; i < count; i++) { 200 /* Attempt to use a CPU on the node the device is on */ 201 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev)); 202 203 /* Set the allocation node based on the returned CPU */ 204 node = cpu_to_node(cpu); 205 206 channel = xgbe_alloc_node(sizeof(*channel), node); 207 if (!channel) 208 goto err_mem; 209 pdata->channel[i] = channel; 210 211 snprintf(channel->name, sizeof(channel->name), "channel-%u", i); 212 channel->pdata = pdata; 213 channel->queue_index = i; 214 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + 215 (DMA_CH_INC * i); 216 channel->node = node; 217 cpumask_set_cpu(cpu, &channel->affinity_mask); 218 219 if (pdata->per_channel_irq) 220 channel->dma_irq = pdata->channel_irq[i]; 221 222 if (i < pdata->tx_ring_count) { 223 ring = xgbe_alloc_node(sizeof(*ring), node); 224 if (!ring) 225 goto err_mem; 226 227 spin_lock_init(&ring->lock); 228 ring->node = node; 229 230 channel->tx_ring = ring; 231 } 232 233 if (i < pdata->rx_ring_count) { 234 ring = xgbe_alloc_node(sizeof(*ring), node); 235 if (!ring) 236 goto err_mem; 237 238 spin_lock_init(&ring->lock); 239 ring->node = node; 240 241 channel->rx_ring = ring; 242 } 243 244 netif_dbg(pdata, drv, pdata->netdev, 245 "%s: cpu=%u, node=%d\n", channel->name, cpu, node); 246 247 netif_dbg(pdata, drv, pdata->netdev, 248 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", 249 channel->name, channel->dma_regs, channel->dma_irq, 250 channel->tx_ring, channel->rx_ring); 251 } 252 253 pdata->channel_count = count; 254 255 return 0; 256 257err_mem: 258 xgbe_free_channels(pdata); 259 260 return -ENOMEM; 261} 262 263static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) 264{ 265 return (ring->rdesc_count - (ring->cur - ring->dirty)); 266} 267 268static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) 269{ 270 return (ring->cur - ring->dirty); 271} 272 273static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, 274 struct xgbe_ring *ring, unsigned int count) 275{ 276 struct xgbe_prv_data *pdata = channel->pdata; 277 278 if (count > xgbe_tx_avail_desc(ring)) { 279 netif_info(pdata, drv, pdata->netdev, 280 "Tx queue stopped, not enough descriptors available\n"); 281 netif_stop_subqueue(pdata->netdev, channel->queue_index); 282 ring->tx.queue_stopped = 1; 283 284 /* If we haven't notified the hardware because of xmit_more 285 * support, tell it now 286 */ 287 if (ring->tx.xmit_more) 288 pdata->hw_if.tx_start_xmit(channel, ring); 289 290 return NETDEV_TX_BUSY; 291 } 292 293 return 0; 294} 295 296static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) 297{ 298 unsigned int rx_buf_size; 299 300 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 301 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); 302 303 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & 304 ~(XGBE_RX_BUF_ALIGN - 1); 305 306 return rx_buf_size; 307} 308 309static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, 310 struct xgbe_channel *channel) 311{ 312 struct xgbe_hw_if *hw_if = &pdata->hw_if; 313 enum xgbe_int int_id; 314 315 if (channel->tx_ring && channel->rx_ring) 316 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 317 else if (channel->tx_ring) 318 int_id = XGMAC_INT_DMA_CH_SR_TI; 319 else if (channel->rx_ring) 320 int_id = XGMAC_INT_DMA_CH_SR_RI; 321 else 322 return; 323 324 hw_if->enable_int(channel, int_id); 325} 326 327static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) 328{ 329 unsigned int i; 330 331 for (i = 0; i < pdata->channel_count; i++) 332 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]); 333} 334 335static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, 336 struct xgbe_channel *channel) 337{ 338 struct xgbe_hw_if *hw_if = &pdata->hw_if; 339 enum xgbe_int int_id; 340 341 if (channel->tx_ring && channel->rx_ring) 342 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 343 else if (channel->tx_ring) 344 int_id = XGMAC_INT_DMA_CH_SR_TI; 345 else if (channel->rx_ring) 346 int_id = XGMAC_INT_DMA_CH_SR_RI; 347 else 348 return; 349 350 hw_if->disable_int(channel, int_id); 351} 352 353static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 354{ 355 unsigned int i; 356 357 for (i = 0; i < pdata->channel_count; i++) 358 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]); 359} 360 361static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period, 362 unsigned int *count, const char *area) 363{ 364 if (time_before(jiffies, *period)) { 365 (*count)++; 366 } else { 367 *period = jiffies + (ecc_sec_period * HZ); 368 *count = 1; 369 } 370 371 if (*count > ecc_sec_info_threshold) 372 dev_warn_once(pdata->dev, 373 "%s ECC corrected errors exceed informational threshold\n", 374 area); 375 376 if (*count > ecc_sec_warn_threshold) { 377 dev_warn_once(pdata->dev, 378 "%s ECC corrected errors exceed warning threshold\n", 379 area); 380 return true; 381 } 382 383 return false; 384} 385 386static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period, 387 unsigned int *count, const char *area) 388{ 389 if (time_before(jiffies, *period)) { 390 (*count)++; 391 } else { 392 *period = jiffies + (ecc_ded_period * HZ); 393 *count = 1; 394 } 395 396 if (*count > ecc_ded_threshold) { 397 netdev_alert(pdata->netdev, 398 "%s ECC detected errors exceed threshold\n", 399 area); 400 return true; 401 } 402 403 return false; 404} 405 406static void xgbe_ecc_isr_task(struct tasklet_struct *t) 407{ 408 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_ecc); 409 unsigned int ecc_isr; 410 bool stop = false; 411 412 /* Mask status with only the interrupts we care about */ 413 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 414 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER); 415 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr); 416 417 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) { 418 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period, 419 &pdata->tx_ded_count, "TX fifo"); 420 } 421 422 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) { 423 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period, 424 &pdata->rx_ded_count, "RX fifo"); 425 } 426 427 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) { 428 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period, 429 &pdata->desc_ded_count, 430 "descriptor cache"); 431 } 432 433 if (stop) { 434 pdata->hw_if.disable_ecc_ded(pdata); 435 schedule_work(&pdata->stopdev_work); 436 goto out; 437 } 438 439 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) { 440 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period, 441 &pdata->tx_sec_count, "TX fifo")) 442 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX); 443 } 444 445 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC)) 446 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period, 447 &pdata->rx_sec_count, "RX fifo")) 448 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX); 449 450 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC)) 451 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period, 452 &pdata->desc_sec_count, "descriptor cache")) 453 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC); 454 455out: 456 /* Clear all ECC interrupts */ 457 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 458 459 /* Reissue interrupt if status is not clear */ 460 if (pdata->vdata->irq_reissue_support) 461 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1); 462} 463 464static irqreturn_t xgbe_ecc_isr(int irq, void *data) 465{ 466 struct xgbe_prv_data *pdata = data; 467 468 if (pdata->isr_as_tasklet) 469 tasklet_schedule(&pdata->tasklet_ecc); 470 else 471 xgbe_ecc_isr_task(&pdata->tasklet_ecc); 472 473 return IRQ_HANDLED; 474} 475 476static void xgbe_isr_task(struct tasklet_struct *t) 477{ 478 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_dev); 479 struct xgbe_hw_if *hw_if = &pdata->hw_if; 480 struct xgbe_channel *channel; 481 unsigned int dma_isr, dma_ch_isr; 482 unsigned int mac_isr, mac_tssr, mac_mdioisr; 483 unsigned int i; 484 485 /* The DMA interrupt status register also reports MAC and MTL 486 * interrupts. So for polling mode, we just need to check for 487 * this register to be non-zero 488 */ 489 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 490 if (!dma_isr) 491 goto isr_done; 492 493 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); 494 495 for (i = 0; i < pdata->channel_count; i++) { 496 if (!(dma_isr & (1 << i))) 497 continue; 498 499 channel = pdata->channel[i]; 500 501 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 502 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", 503 i, dma_ch_isr); 504 505 /* The TI or RI interrupt bits may still be set even if using 506 * per channel DMA interrupts. Check to be sure those are not 507 * enabled before using the private data napi structure. 508 */ 509 if (!pdata->per_channel_irq && 510 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 511 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 512 if (napi_schedule_prep(&pdata->napi)) { 513 /* Disable Tx and Rx interrupts */ 514 xgbe_disable_rx_tx_ints(pdata); 515 516 /* Turn on polling */ 517 __napi_schedule(&pdata->napi); 518 } 519 } else { 520 /* Don't clear Rx/Tx status if doing per channel DMA 521 * interrupts, these will be cleared by the ISR for 522 * per channel DMA interrupts. 523 */ 524 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); 525 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); 526 } 527 528 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) 529 pdata->ext_stats.rx_buffer_unavailable++; 530 531 /* Restart the device on a Fatal Bus Error */ 532 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 533 schedule_work(&pdata->restart_work); 534 535 /* Clear interrupt signals */ 536 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 537 } 538 539 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 540 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 541 542 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n", 543 mac_isr); 544 545 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 546 hw_if->tx_mmc_int(pdata); 547 548 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 549 hw_if->rx_mmc_int(pdata); 550 551 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { 552 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); 553 554 netif_dbg(pdata, intr, pdata->netdev, 555 "MAC_TSSR=%#010x\n", mac_tssr); 556 557 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { 558 /* Read Tx Timestamp to clear interrupt */ 559 pdata->tx_tstamp = 560 hw_if->get_tx_tstamp(pdata); 561 queue_work(pdata->dev_workqueue, 562 &pdata->tx_tstamp_work); 563 } 564 } 565 566 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { 567 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); 568 569 netif_dbg(pdata, intr, pdata->netdev, 570 "MAC_MDIOISR=%#010x\n", mac_mdioisr); 571 572 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, 573 SNGLCOMPINT)) 574 complete(&pdata->mdio_complete); 575 } 576 } 577 578isr_done: 579 /* If there is not a separate AN irq, handle it here */ 580 if (pdata->dev_irq == pdata->an_irq) 581 pdata->phy_if.an_isr(pdata); 582 583 /* If there is not a separate ECC irq, handle it here */ 584 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq)) 585 xgbe_ecc_isr_task(&pdata->tasklet_ecc); 586 587 /* If there is not a separate I2C irq, handle it here */ 588 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq)) 589 pdata->i2c_if.i2c_isr(pdata); 590 591 /* Reissue interrupt if status is not clear */ 592 if (pdata->vdata->irq_reissue_support) { 593 unsigned int reissue_mask; 594 595 reissue_mask = 1 << 0; 596 if (!pdata->per_channel_irq) 597 reissue_mask |= 0xffff << 4; 598 599 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask); 600 } 601} 602 603static irqreturn_t xgbe_isr(int irq, void *data) 604{ 605 struct xgbe_prv_data *pdata = data; 606 607 if (pdata->isr_as_tasklet) 608 tasklet_schedule(&pdata->tasklet_dev); 609 else 610 xgbe_isr_task(&pdata->tasklet_dev); 611 612 return IRQ_HANDLED; 613} 614 615static irqreturn_t xgbe_dma_isr(int irq, void *data) 616{ 617 struct xgbe_channel *channel = data; 618 struct xgbe_prv_data *pdata = channel->pdata; 619 unsigned int dma_status; 620 621 /* Per channel DMA interrupts are enabled, so we use the per 622 * channel napi structure and not the private data napi structure 623 */ 624 if (napi_schedule_prep(&channel->napi)) { 625 /* Disable Tx and Rx interrupts */ 626 if (pdata->channel_irq_mode) 627 xgbe_disable_rx_tx_int(pdata, channel); 628 else 629 disable_irq_nosync(channel->dma_irq); 630 631 /* Turn on polling */ 632 __napi_schedule_irqoff(&channel->napi); 633 } 634 635 /* Clear Tx/Rx signals */ 636 dma_status = 0; 637 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); 638 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); 639 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); 640 641 return IRQ_HANDLED; 642} 643 644static void xgbe_tx_timer(struct timer_list *t) 645{ 646 struct xgbe_channel *channel = from_timer(channel, t, tx_timer); 647 struct xgbe_prv_data *pdata = channel->pdata; 648 struct napi_struct *napi; 649 650 DBGPR("-->xgbe_tx_timer\n"); 651 652 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 653 654 if (napi_schedule_prep(napi)) { 655 /* Disable Tx and Rx interrupts */ 656 if (pdata->per_channel_irq) 657 if (pdata->channel_irq_mode) 658 xgbe_disable_rx_tx_int(pdata, channel); 659 else 660 disable_irq_nosync(channel->dma_irq); 661 else 662 xgbe_disable_rx_tx_ints(pdata); 663 664 /* Turn on polling */ 665 __napi_schedule(napi); 666 } 667 668 channel->tx_timer_active = 0; 669 670 DBGPR("<--xgbe_tx_timer\n"); 671} 672 673static void xgbe_service(struct work_struct *work) 674{ 675 struct xgbe_prv_data *pdata = container_of(work, 676 struct xgbe_prv_data, 677 service_work); 678 679 pdata->phy_if.phy_status(pdata); 680} 681 682static void xgbe_service_timer(struct timer_list *t) 683{ 684 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer); 685 struct xgbe_channel *channel; 686 unsigned int i; 687 688 queue_work(pdata->dev_workqueue, &pdata->service_work); 689 690 mod_timer(&pdata->service_timer, jiffies + HZ); 691 692 if (!pdata->tx_usecs) 693 return; 694 695 for (i = 0; i < pdata->channel_count; i++) { 696 channel = pdata->channel[i]; 697 if (!channel->tx_ring || channel->tx_timer_active) 698 break; 699 channel->tx_timer_active = 1; 700 mod_timer(&channel->tx_timer, 701 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 702 } 703} 704 705static void xgbe_init_timers(struct xgbe_prv_data *pdata) 706{ 707 struct xgbe_channel *channel; 708 unsigned int i; 709 710 timer_setup(&pdata->service_timer, xgbe_service_timer, 0); 711 712 for (i = 0; i < pdata->channel_count; i++) { 713 channel = pdata->channel[i]; 714 if (!channel->tx_ring) 715 break; 716 717 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0); 718 } 719} 720 721static void xgbe_start_timers(struct xgbe_prv_data *pdata) 722{ 723 mod_timer(&pdata->service_timer, jiffies + HZ); 724} 725 726static void xgbe_stop_timers(struct xgbe_prv_data *pdata) 727{ 728 struct xgbe_channel *channel; 729 unsigned int i; 730 731 del_timer_sync(&pdata->service_timer); 732 733 for (i = 0; i < pdata->channel_count; i++) { 734 channel = pdata->channel[i]; 735 if (!channel->tx_ring) 736 break; 737 738 /* Deactivate the Tx timer */ 739 del_timer_sync(&channel->tx_timer); 740 channel->tx_timer_active = 0; 741 } 742} 743 744void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 745{ 746 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 747 struct xgbe_hw_features *hw_feat = &pdata->hw_feat; 748 749 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); 750 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); 751 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); 752 753 memset(hw_feat, 0, sizeof(*hw_feat)); 754 755 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); 756 757 /* Hardware feature register 0 */ 758 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 759 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 760 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 761 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 762 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 763 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 764 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 765 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 766 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 767 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 768 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 769 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 770 ADDMACADRSEL); 771 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 772 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 773 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN); 774 775 /* Hardware feature register 1 */ 776 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 777 RXFIFOSIZE); 778 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 779 TXFIFOSIZE); 780 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); 781 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 782 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 783 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 784 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 785 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 786 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 787 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 788 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 789 HASHTBLSZ); 790 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 791 L3L4FNUM); 792 793 /* Hardware feature register 2 */ 794 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 795 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 796 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 797 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 798 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 799 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); 800 801 /* Translate the Hash Table size into actual number */ 802 switch (hw_feat->hash_table_size) { 803 case 0: 804 break; 805 case 1: 806 hw_feat->hash_table_size = 64; 807 break; 808 case 2: 809 hw_feat->hash_table_size = 128; 810 break; 811 case 3: 812 hw_feat->hash_table_size = 256; 813 break; 814 } 815 816 /* Translate the address width setting into actual number */ 817 switch (hw_feat->dma_width) { 818 case 0: 819 hw_feat->dma_width = 32; 820 break; 821 case 1: 822 hw_feat->dma_width = 40; 823 break; 824 case 2: 825 hw_feat->dma_width = 48; 826 break; 827 default: 828 hw_feat->dma_width = 32; 829 } 830 831 /* The Queue, Channel and TC counts are zero based so increment them 832 * to get the actual number 833 */ 834 hw_feat->rx_q_cnt++; 835 hw_feat->tx_q_cnt++; 836 hw_feat->rx_ch_cnt++; 837 hw_feat->tx_ch_cnt++; 838 hw_feat->tc_cnt++; 839 840 /* Translate the fifo sizes into actual numbers */ 841 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 842 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 843 844 if (netif_msg_probe(pdata)) { 845 dev_dbg(pdata->dev, "Hardware features:\n"); 846 847 /* Hardware feature register 0 */ 848 dev_dbg(pdata->dev, " 1GbE support : %s\n", 849 hw_feat->gmii ? "yes" : "no"); 850 dev_dbg(pdata->dev, " VLAN hash filter : %s\n", 851 hw_feat->vlhash ? "yes" : "no"); 852 dev_dbg(pdata->dev, " MDIO interface : %s\n", 853 hw_feat->sma ? "yes" : "no"); 854 dev_dbg(pdata->dev, " Wake-up packet support : %s\n", 855 hw_feat->rwk ? "yes" : "no"); 856 dev_dbg(pdata->dev, " Magic packet support : %s\n", 857 hw_feat->mgk ? "yes" : "no"); 858 dev_dbg(pdata->dev, " Management counters : %s\n", 859 hw_feat->mmc ? "yes" : "no"); 860 dev_dbg(pdata->dev, " ARP offload : %s\n", 861 hw_feat->aoe ? "yes" : "no"); 862 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n", 863 hw_feat->ts ? "yes" : "no"); 864 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n", 865 hw_feat->eee ? "yes" : "no"); 866 dev_dbg(pdata->dev, " TX checksum offload : %s\n", 867 hw_feat->tx_coe ? "yes" : "no"); 868 dev_dbg(pdata->dev, " RX checksum offload : %s\n", 869 hw_feat->rx_coe ? "yes" : "no"); 870 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n", 871 hw_feat->addn_mac); 872 dev_dbg(pdata->dev, " Timestamp source : %s\n", 873 (hw_feat->ts_src == 1) ? "internal" : 874 (hw_feat->ts_src == 2) ? "external" : 875 (hw_feat->ts_src == 3) ? "internal/external" : "n/a"); 876 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n", 877 hw_feat->sa_vlan_ins ? "yes" : "no"); 878 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n", 879 hw_feat->vxn ? "yes" : "no"); 880 881 /* Hardware feature register 1 */ 882 dev_dbg(pdata->dev, " RX fifo size : %u\n", 883 hw_feat->rx_fifo_size); 884 dev_dbg(pdata->dev, " TX fifo size : %u\n", 885 hw_feat->tx_fifo_size); 886 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n", 887 hw_feat->adv_ts_hi ? "yes" : "no"); 888 dev_dbg(pdata->dev, " DMA width : %u\n", 889 hw_feat->dma_width); 890 dev_dbg(pdata->dev, " Data Center Bridging : %s\n", 891 hw_feat->dcb ? "yes" : "no"); 892 dev_dbg(pdata->dev, " Split header : %s\n", 893 hw_feat->sph ? "yes" : "no"); 894 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n", 895 hw_feat->tso ? "yes" : "no"); 896 dev_dbg(pdata->dev, " Debug memory interface : %s\n", 897 hw_feat->dma_debug ? "yes" : "no"); 898 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n", 899 hw_feat->rss ? "yes" : "no"); 900 dev_dbg(pdata->dev, " Traffic Class count : %u\n", 901 hw_feat->tc_cnt); 902 dev_dbg(pdata->dev, " Hash table size : %u\n", 903 hw_feat->hash_table_size); 904 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n", 905 hw_feat->l3l4_filter_num); 906 907 /* Hardware feature register 2 */ 908 dev_dbg(pdata->dev, " RX queue count : %u\n", 909 hw_feat->rx_q_cnt); 910 dev_dbg(pdata->dev, " TX queue count : %u\n", 911 hw_feat->tx_q_cnt); 912 dev_dbg(pdata->dev, " RX DMA channel count : %u\n", 913 hw_feat->rx_ch_cnt); 914 dev_dbg(pdata->dev, " TX DMA channel count : %u\n", 915 hw_feat->rx_ch_cnt); 916 dev_dbg(pdata->dev, " PPS outputs : %u\n", 917 hw_feat->pps_out_num); 918 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n", 919 hw_feat->aux_snap_num); 920 } 921} 922 923static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table, 924 unsigned int entry, struct udp_tunnel_info *ti) 925{ 926 struct xgbe_prv_data *pdata = netdev_priv(netdev); 927 928 pdata->vxlan_port = be16_to_cpu(ti->port); 929 pdata->hw_if.enable_vxlan(pdata); 930 931 return 0; 932} 933 934static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table, 935 unsigned int entry, struct udp_tunnel_info *ti) 936{ 937 struct xgbe_prv_data *pdata = netdev_priv(netdev); 938 939 pdata->hw_if.disable_vxlan(pdata); 940 pdata->vxlan_port = 0; 941 942 return 0; 943} 944 945static const struct udp_tunnel_nic_info xgbe_udp_tunnels = { 946 .set_port = xgbe_vxlan_set_port, 947 .unset_port = xgbe_vxlan_unset_port, 948 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 949 .tables = { 950 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 951 }, 952}; 953 954const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void) 955{ 956 return &xgbe_udp_tunnels; 957} 958 959static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) 960{ 961 struct xgbe_channel *channel; 962 unsigned int i; 963 964 if (pdata->per_channel_irq) { 965 for (i = 0; i < pdata->channel_count; i++) { 966 channel = pdata->channel[i]; 967 if (add) 968 netif_napi_add(pdata->netdev, &channel->napi, 969 xgbe_one_poll, NAPI_POLL_WEIGHT); 970 971 napi_enable(&channel->napi); 972 } 973 } else { 974 if (add) 975 netif_napi_add(pdata->netdev, &pdata->napi, 976 xgbe_all_poll, NAPI_POLL_WEIGHT); 977 978 napi_enable(&pdata->napi); 979 } 980} 981 982static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) 983{ 984 struct xgbe_channel *channel; 985 unsigned int i; 986 987 if (pdata->per_channel_irq) { 988 for (i = 0; i < pdata->channel_count; i++) { 989 channel = pdata->channel[i]; 990 napi_disable(&channel->napi); 991 992 if (del) 993 netif_napi_del(&channel->napi); 994 } 995 } else { 996 napi_disable(&pdata->napi); 997 998 if (del) 999 netif_napi_del(&pdata->napi); 1000 } 1001} 1002 1003static int xgbe_request_irqs(struct xgbe_prv_data *pdata) 1004{ 1005 struct xgbe_channel *channel; 1006 struct net_device *netdev = pdata->netdev; 1007 unsigned int i; 1008 int ret; 1009 1010 tasklet_setup(&pdata->tasklet_dev, xgbe_isr_task); 1011 tasklet_setup(&pdata->tasklet_ecc, xgbe_ecc_isr_task); 1012 1013 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, 1014 netdev_name(netdev), pdata); 1015 if (ret) { 1016 netdev_alert(netdev, "error requesting irq %d\n", 1017 pdata->dev_irq); 1018 return ret; 1019 } 1020 1021 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) { 1022 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr, 1023 0, pdata->ecc_name, pdata); 1024 if (ret) { 1025 netdev_alert(netdev, "error requesting ecc irq %d\n", 1026 pdata->ecc_irq); 1027 goto err_dev_irq; 1028 } 1029 } 1030 1031 if (!pdata->per_channel_irq) 1032 return 0; 1033 1034 for (i = 0; i < pdata->channel_count; i++) { 1035 channel = pdata->channel[i]; 1036 snprintf(channel->dma_irq_name, 1037 sizeof(channel->dma_irq_name) - 1, 1038 "%s-TxRx-%u", netdev_name(netdev), 1039 channel->queue_index); 1040 1041 ret = devm_request_irq(pdata->dev, channel->dma_irq, 1042 xgbe_dma_isr, 0, 1043 channel->dma_irq_name, channel); 1044 if (ret) { 1045 netdev_alert(netdev, "error requesting irq %d\n", 1046 channel->dma_irq); 1047 goto err_dma_irq; 1048 } 1049 1050 irq_set_affinity_hint(channel->dma_irq, 1051 &channel->affinity_mask); 1052 } 1053 1054 return 0; 1055 1056err_dma_irq: 1057 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ 1058 for (i--; i < pdata->channel_count; i--) { 1059 channel = pdata->channel[i]; 1060 1061 irq_set_affinity_hint(channel->dma_irq, NULL); 1062 devm_free_irq(pdata->dev, channel->dma_irq, channel); 1063 } 1064 1065 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 1066 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 1067 1068err_dev_irq: 1069 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 1070 1071 return ret; 1072} 1073 1074static void xgbe_free_irqs(struct xgbe_prv_data *pdata) 1075{ 1076 struct xgbe_channel *channel; 1077 unsigned int i; 1078 1079 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 1080 1081 tasklet_kill(&pdata->tasklet_dev); 1082 tasklet_kill(&pdata->tasklet_ecc); 1083 1084 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 1085 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 1086 1087 if (!pdata->per_channel_irq) 1088 return; 1089 1090 for (i = 0; i < pdata->channel_count; i++) { 1091 channel = pdata->channel[i]; 1092 1093 irq_set_affinity_hint(channel->dma_irq, NULL); 1094 devm_free_irq(pdata->dev, channel->dma_irq, channel); 1095 } 1096} 1097 1098void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) 1099{ 1100 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1101 1102 DBGPR("-->xgbe_init_tx_coalesce\n"); 1103 1104 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; 1105 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; 1106 1107 hw_if->config_tx_coalesce(pdata); 1108 1109 DBGPR("<--xgbe_init_tx_coalesce\n"); 1110} 1111 1112void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) 1113{ 1114 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1115 1116 DBGPR("-->xgbe_init_rx_coalesce\n"); 1117 1118 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); 1119 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; 1120 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; 1121 1122 hw_if->config_rx_coalesce(pdata); 1123 1124 DBGPR("<--xgbe_init_rx_coalesce\n"); 1125} 1126 1127static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) 1128{ 1129 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1130 struct xgbe_ring *ring; 1131 struct xgbe_ring_data *rdata; 1132 unsigned int i, j; 1133 1134 DBGPR("-->xgbe_free_tx_data\n"); 1135 1136 for (i = 0; i < pdata->channel_count; i++) { 1137 ring = pdata->channel[i]->tx_ring; 1138 if (!ring) 1139 break; 1140 1141 for (j = 0; j < ring->rdesc_count; j++) { 1142 rdata = XGBE_GET_DESC_DATA(ring, j); 1143 desc_if->unmap_rdata(pdata, rdata); 1144 } 1145 } 1146 1147 DBGPR("<--xgbe_free_tx_data\n"); 1148} 1149 1150static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) 1151{ 1152 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1153 struct xgbe_ring *ring; 1154 struct xgbe_ring_data *rdata; 1155 unsigned int i, j; 1156 1157 DBGPR("-->xgbe_free_rx_data\n"); 1158 1159 for (i = 0; i < pdata->channel_count; i++) { 1160 ring = pdata->channel[i]->rx_ring; 1161 if (!ring) 1162 break; 1163 1164 for (j = 0; j < ring->rdesc_count; j++) { 1165 rdata = XGBE_GET_DESC_DATA(ring, j); 1166 desc_if->unmap_rdata(pdata, rdata); 1167 } 1168 } 1169 1170 DBGPR("<--xgbe_free_rx_data\n"); 1171} 1172 1173static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1174{ 1175 pdata->phy_link = -1; 1176 pdata->phy_speed = SPEED_UNKNOWN; 1177 1178 return pdata->phy_if.phy_reset(pdata); 1179} 1180 1181int xgbe_powerdown(struct net_device *netdev, unsigned int caller) 1182{ 1183 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1184 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1185 unsigned long flags; 1186 1187 DBGPR("-->xgbe_powerdown\n"); 1188 1189 if (!netif_running(netdev) || 1190 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { 1191 netdev_alert(netdev, "Device is already powered down\n"); 1192 DBGPR("<--xgbe_powerdown\n"); 1193 return -EINVAL; 1194 } 1195 1196 spin_lock_irqsave(&pdata->lock, flags); 1197 1198 if (caller == XGMAC_DRIVER_CONTEXT) 1199 netif_device_detach(netdev); 1200 1201 netif_tx_stop_all_queues(netdev); 1202 1203 xgbe_stop_timers(pdata); 1204 flush_workqueue(pdata->dev_workqueue); 1205 1206 hw_if->powerdown_tx(pdata); 1207 hw_if->powerdown_rx(pdata); 1208 1209 xgbe_napi_disable(pdata, 0); 1210 1211 pdata->power_down = 1; 1212 1213 spin_unlock_irqrestore(&pdata->lock, flags); 1214 1215 DBGPR("<--xgbe_powerdown\n"); 1216 1217 return 0; 1218} 1219 1220int xgbe_powerup(struct net_device *netdev, unsigned int caller) 1221{ 1222 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1223 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1224 unsigned long flags; 1225 1226 DBGPR("-->xgbe_powerup\n"); 1227 1228 if (!netif_running(netdev) || 1229 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { 1230 netdev_alert(netdev, "Device is already powered up\n"); 1231 DBGPR("<--xgbe_powerup\n"); 1232 return -EINVAL; 1233 } 1234 1235 spin_lock_irqsave(&pdata->lock, flags); 1236 1237 pdata->power_down = 0; 1238 1239 xgbe_napi_enable(pdata, 0); 1240 1241 hw_if->powerup_tx(pdata); 1242 hw_if->powerup_rx(pdata); 1243 1244 if (caller == XGMAC_DRIVER_CONTEXT) 1245 netif_device_attach(netdev); 1246 1247 netif_tx_start_all_queues(netdev); 1248 1249 xgbe_start_timers(pdata); 1250 1251 spin_unlock_irqrestore(&pdata->lock, flags); 1252 1253 DBGPR("<--xgbe_powerup\n"); 1254 1255 return 0; 1256} 1257 1258static void xgbe_free_memory(struct xgbe_prv_data *pdata) 1259{ 1260 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1261 1262 /* Free the ring descriptors and buffers */ 1263 desc_if->free_ring_resources(pdata); 1264 1265 /* Free the channel and ring structures */ 1266 xgbe_free_channels(pdata); 1267} 1268 1269static int xgbe_alloc_memory(struct xgbe_prv_data *pdata) 1270{ 1271 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1272 struct net_device *netdev = pdata->netdev; 1273 int ret; 1274 1275 if (pdata->new_tx_ring_count) { 1276 pdata->tx_ring_count = pdata->new_tx_ring_count; 1277 pdata->tx_q_count = pdata->tx_ring_count; 1278 pdata->new_tx_ring_count = 0; 1279 } 1280 1281 if (pdata->new_rx_ring_count) { 1282 pdata->rx_ring_count = pdata->new_rx_ring_count; 1283 pdata->new_rx_ring_count = 0; 1284 } 1285 1286 /* Calculate the Rx buffer size before allocating rings */ 1287 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu); 1288 1289 /* Allocate the channel and ring structures */ 1290 ret = xgbe_alloc_channels(pdata); 1291 if (ret) 1292 return ret; 1293 1294 /* Allocate the ring descriptors and buffers */ 1295 ret = desc_if->alloc_ring_resources(pdata); 1296 if (ret) 1297 goto err_channels; 1298 1299 /* Initialize the service and Tx timers */ 1300 xgbe_init_timers(pdata); 1301 1302 return 0; 1303 1304err_channels: 1305 xgbe_free_memory(pdata); 1306 1307 return ret; 1308} 1309 1310static int xgbe_start(struct xgbe_prv_data *pdata) 1311{ 1312 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1313 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1314 struct net_device *netdev = pdata->netdev; 1315 unsigned int i; 1316 int ret; 1317 1318 /* Set the number of queues */ 1319 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count); 1320 if (ret) { 1321 netdev_err(netdev, "error setting real tx queue count\n"); 1322 return ret; 1323 } 1324 1325 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count); 1326 if (ret) { 1327 netdev_err(netdev, "error setting real rx queue count\n"); 1328 return ret; 1329 } 1330 1331 /* Set RSS lookup table data for programming */ 1332 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) 1333 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, 1334 i % pdata->rx_ring_count); 1335 1336 ret = hw_if->init(pdata); 1337 if (ret) 1338 return ret; 1339 1340 xgbe_napi_enable(pdata, 1); 1341 1342 ret = xgbe_request_irqs(pdata); 1343 if (ret) 1344 goto err_napi; 1345 1346 ret = phy_if->phy_start(pdata); 1347 if (ret) 1348 goto err_irqs; 1349 1350 hw_if->enable_tx(pdata); 1351 hw_if->enable_rx(pdata); 1352 1353 udp_tunnel_nic_reset_ntf(netdev); 1354 1355 netif_tx_start_all_queues(netdev); 1356 1357 xgbe_start_timers(pdata); 1358 queue_work(pdata->dev_workqueue, &pdata->service_work); 1359 1360 clear_bit(XGBE_STOPPED, &pdata->dev_state); 1361 1362 return 0; 1363 1364err_irqs: 1365 xgbe_free_irqs(pdata); 1366 1367err_napi: 1368 xgbe_napi_disable(pdata, 1); 1369 1370 hw_if->exit(pdata); 1371 1372 return ret; 1373} 1374 1375static void xgbe_stop(struct xgbe_prv_data *pdata) 1376{ 1377 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1378 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1379 struct xgbe_channel *channel; 1380 struct net_device *netdev = pdata->netdev; 1381 struct netdev_queue *txq; 1382 unsigned int i; 1383 1384 DBGPR("-->xgbe_stop\n"); 1385 1386 if (test_bit(XGBE_STOPPED, &pdata->dev_state)) 1387 return; 1388 1389 netif_tx_stop_all_queues(netdev); 1390 netif_carrier_off(pdata->netdev); 1391 1392 xgbe_stop_timers(pdata); 1393 flush_workqueue(pdata->dev_workqueue); 1394 1395 xgbe_vxlan_unset_port(netdev, 0, 0, NULL); 1396 1397 hw_if->disable_tx(pdata); 1398 hw_if->disable_rx(pdata); 1399 1400 phy_if->phy_stop(pdata); 1401 1402 xgbe_free_irqs(pdata); 1403 1404 xgbe_napi_disable(pdata, 1); 1405 1406 hw_if->exit(pdata); 1407 1408 for (i = 0; i < pdata->channel_count; i++) { 1409 channel = pdata->channel[i]; 1410 if (!channel->tx_ring) 1411 continue; 1412 1413 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1414 netdev_tx_reset_queue(txq); 1415 } 1416 1417 set_bit(XGBE_STOPPED, &pdata->dev_state); 1418 1419 DBGPR("<--xgbe_stop\n"); 1420} 1421 1422static void xgbe_stopdev(struct work_struct *work) 1423{ 1424 struct xgbe_prv_data *pdata = container_of(work, 1425 struct xgbe_prv_data, 1426 stopdev_work); 1427 1428 rtnl_lock(); 1429 1430 xgbe_stop(pdata); 1431 1432 xgbe_free_tx_data(pdata); 1433 xgbe_free_rx_data(pdata); 1434 1435 rtnl_unlock(); 1436 1437 netdev_alert(pdata->netdev, "device stopped\n"); 1438} 1439 1440void xgbe_full_restart_dev(struct xgbe_prv_data *pdata) 1441{ 1442 /* If not running, "restart" will happen on open */ 1443 if (!netif_running(pdata->netdev)) 1444 return; 1445 1446 xgbe_stop(pdata); 1447 1448 xgbe_free_memory(pdata); 1449 xgbe_alloc_memory(pdata); 1450 1451 xgbe_start(pdata); 1452} 1453 1454void xgbe_restart_dev(struct xgbe_prv_data *pdata) 1455{ 1456 /* If not running, "restart" will happen on open */ 1457 if (!netif_running(pdata->netdev)) 1458 return; 1459 1460 xgbe_stop(pdata); 1461 1462 xgbe_free_tx_data(pdata); 1463 xgbe_free_rx_data(pdata); 1464 1465 xgbe_start(pdata); 1466} 1467 1468static void xgbe_restart(struct work_struct *work) 1469{ 1470 struct xgbe_prv_data *pdata = container_of(work, 1471 struct xgbe_prv_data, 1472 restart_work); 1473 1474 rtnl_lock(); 1475 1476 xgbe_restart_dev(pdata); 1477 1478 rtnl_unlock(); 1479} 1480 1481static void xgbe_tx_tstamp(struct work_struct *work) 1482{ 1483 struct xgbe_prv_data *pdata = container_of(work, 1484 struct xgbe_prv_data, 1485 tx_tstamp_work); 1486 struct skb_shared_hwtstamps hwtstamps; 1487 u64 nsec; 1488 unsigned long flags; 1489 1490 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1491 if (!pdata->tx_tstamp_skb) 1492 goto unlock; 1493 1494 if (pdata->tx_tstamp) { 1495 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 1496 pdata->tx_tstamp); 1497 1498 memset(&hwtstamps, 0, sizeof(hwtstamps)); 1499 hwtstamps.hwtstamp = ns_to_ktime(nsec); 1500 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); 1501 } 1502 1503 dev_kfree_skb_any(pdata->tx_tstamp_skb); 1504 1505 pdata->tx_tstamp_skb = NULL; 1506 1507unlock: 1508 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1509} 1510 1511static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, 1512 struct ifreq *ifreq) 1513{ 1514 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, 1515 sizeof(pdata->tstamp_config))) 1516 return -EFAULT; 1517 1518 return 0; 1519} 1520 1521static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, 1522 struct ifreq *ifreq) 1523{ 1524 struct hwtstamp_config config; 1525 unsigned int mac_tscr; 1526 1527 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) 1528 return -EFAULT; 1529 1530 if (config.flags) 1531 return -EINVAL; 1532 1533 mac_tscr = 0; 1534 1535 switch (config.tx_type) { 1536 case HWTSTAMP_TX_OFF: 1537 break; 1538 1539 case HWTSTAMP_TX_ON: 1540 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1541 break; 1542 1543 default: 1544 return -ERANGE; 1545 } 1546 1547 switch (config.rx_filter) { 1548 case HWTSTAMP_FILTER_NONE: 1549 break; 1550 1551 case HWTSTAMP_FILTER_NTP_ALL: 1552 case HWTSTAMP_FILTER_ALL: 1553 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1554 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1555 break; 1556 1557 /* PTP v2, UDP, any kind of event packet */ 1558 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1559 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1560 fallthrough; /* to PTP v1, UDP, any kind of event packet */ 1561 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1562 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1563 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1564 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1565 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1566 break; 1567 1568 /* PTP v2, UDP, Sync packet */ 1569 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1570 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1571 fallthrough; /* to PTP v1, UDP, Sync packet */ 1572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1573 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1574 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1575 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1576 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1577 break; 1578 1579 /* PTP v2, UDP, Delay_req packet */ 1580 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1581 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1582 fallthrough; /* to PTP v1, UDP, Delay_req packet */ 1583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1584 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1585 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1586 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1587 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1588 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1589 break; 1590 1591 /* 802.AS1, Ethernet, any kind of event packet */ 1592 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1593 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1594 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1595 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1596 break; 1597 1598 /* 802.AS1, Ethernet, Sync packet */ 1599 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1600 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1601 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1602 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1603 break; 1604 1605 /* 802.AS1, Ethernet, Delay_req packet */ 1606 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1607 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1608 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1609 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1610 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1611 break; 1612 1613 /* PTP v2/802.AS1, any layer, any kind of event packet */ 1614 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1615 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1616 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1617 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1618 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1619 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1620 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1621 break; 1622 1623 /* PTP v2/802.AS1, any layer, Sync packet */ 1624 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1625 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1626 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1627 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1628 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1629 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1630 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1631 break; 1632 1633 /* PTP v2/802.AS1, any layer, Delay_req packet */ 1634 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1635 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1636 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1637 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1638 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1639 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1640 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1641 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1642 break; 1643 1644 default: 1645 return -ERANGE; 1646 } 1647 1648 pdata->hw_if.config_tstamp(pdata, mac_tscr); 1649 1650 memcpy(&pdata->tstamp_config, &config, sizeof(config)); 1651 1652 return 0; 1653} 1654 1655static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1656 struct sk_buff *skb, 1657 struct xgbe_packet_data *packet) 1658{ 1659 unsigned long flags; 1660 1661 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { 1662 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1663 if (pdata->tx_tstamp_skb) { 1664 /* Another timestamp in progress, ignore this one */ 1665 XGMAC_SET_BITS(packet->attributes, 1666 TX_PACKET_ATTRIBUTES, PTP, 0); 1667 } else { 1668 pdata->tx_tstamp_skb = skb_get(skb); 1669 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1670 } 1671 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1672 } 1673 1674 skb_tx_timestamp(skb); 1675} 1676 1677static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) 1678{ 1679 if (skb_vlan_tag_present(skb)) 1680 packet->vlan_ctag = skb_vlan_tag_get(skb); 1681} 1682 1683static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) 1684{ 1685 int ret; 1686 1687 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1688 TSO_ENABLE)) 1689 return 0; 1690 1691 ret = skb_cow_head(skb, 0); 1692 if (ret) 1693 return ret; 1694 1695 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) { 1696 packet->header_len = skb_inner_transport_offset(skb) + 1697 inner_tcp_hdrlen(skb); 1698 packet->tcp_header_len = inner_tcp_hdrlen(skb); 1699 } else { 1700 packet->header_len = skb_transport_offset(skb) + 1701 tcp_hdrlen(skb); 1702 packet->tcp_header_len = tcp_hdrlen(skb); 1703 } 1704 packet->tcp_payload_len = skb->len - packet->header_len; 1705 packet->mss = skb_shinfo(skb)->gso_size; 1706 1707 DBGPR(" packet->header_len=%u\n", packet->header_len); 1708 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", 1709 packet->tcp_header_len, packet->tcp_payload_len); 1710 DBGPR(" packet->mss=%u\n", packet->mss); 1711 1712 /* Update the number of packets that will ultimately be transmitted 1713 * along with the extra bytes for each extra packet 1714 */ 1715 packet->tx_packets = skb_shinfo(skb)->gso_segs; 1716 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; 1717 1718 return 0; 1719} 1720 1721static bool xgbe_is_vxlan(struct sk_buff *skb) 1722{ 1723 if (!skb->encapsulation) 1724 return false; 1725 1726 if (skb->ip_summed != CHECKSUM_PARTIAL) 1727 return false; 1728 1729 switch (skb->protocol) { 1730 case htons(ETH_P_IP): 1731 if (ip_hdr(skb)->protocol != IPPROTO_UDP) 1732 return false; 1733 break; 1734 1735 case htons(ETH_P_IPV6): 1736 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP) 1737 return false; 1738 break; 1739 1740 default: 1741 return false; 1742 } 1743 1744 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1745 skb->inner_protocol != htons(ETH_P_TEB) || 1746 (skb_inner_mac_header(skb) - skb_transport_header(skb) != 1747 sizeof(struct udphdr) + sizeof(struct vxlanhdr))) 1748 return false; 1749 1750 return true; 1751} 1752 1753static int xgbe_is_tso(struct sk_buff *skb) 1754{ 1755 if (skb->ip_summed != CHECKSUM_PARTIAL) 1756 return 0; 1757 1758 if (!skb_is_gso(skb)) 1759 return 0; 1760 1761 DBGPR(" TSO packet to be processed\n"); 1762 1763 return 1; 1764} 1765 1766static void xgbe_packet_info(struct xgbe_prv_data *pdata, 1767 struct xgbe_ring *ring, struct sk_buff *skb, 1768 struct xgbe_packet_data *packet) 1769{ 1770 skb_frag_t *frag; 1771 unsigned int context_desc; 1772 unsigned int len; 1773 unsigned int i; 1774 1775 packet->skb = skb; 1776 1777 context_desc = 0; 1778 packet->rdesc_count = 0; 1779 1780 packet->tx_packets = 1; 1781 packet->tx_bytes = skb->len; 1782 1783 if (xgbe_is_tso(skb)) { 1784 /* TSO requires an extra descriptor if mss is different */ 1785 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { 1786 context_desc = 1; 1787 packet->rdesc_count++; 1788 } 1789 1790 /* TSO requires an extra descriptor for TSO header */ 1791 packet->rdesc_count++; 1792 1793 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1794 TSO_ENABLE, 1); 1795 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1796 CSUM_ENABLE, 1); 1797 } else if (skb->ip_summed == CHECKSUM_PARTIAL) 1798 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1799 CSUM_ENABLE, 1); 1800 1801 if (xgbe_is_vxlan(skb)) 1802 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1803 VXLAN, 1); 1804 1805 if (skb_vlan_tag_present(skb)) { 1806 /* VLAN requires an extra descriptor if tag is different */ 1807 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) 1808 /* We can share with the TSO context descriptor */ 1809 if (!context_desc) { 1810 context_desc = 1; 1811 packet->rdesc_count++; 1812 } 1813 1814 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1815 VLAN_CTAG, 1); 1816 } 1817 1818 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1819 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) 1820 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1821 PTP, 1); 1822 1823 for (len = skb_headlen(skb); len;) { 1824 packet->rdesc_count++; 1825 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1826 } 1827 1828 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1829 frag = &skb_shinfo(skb)->frags[i]; 1830 for (len = skb_frag_size(frag); len; ) { 1831 packet->rdesc_count++; 1832 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1833 } 1834 } 1835} 1836 1837static int xgbe_open(struct net_device *netdev) 1838{ 1839 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1840 int ret; 1841 1842 /* Create the various names based on netdev name */ 1843 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs", 1844 netdev_name(netdev)); 1845 1846 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc", 1847 netdev_name(netdev)); 1848 1849 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c", 1850 netdev_name(netdev)); 1851 1852 /* Create workqueues */ 1853 pdata->dev_workqueue = 1854 create_singlethread_workqueue(netdev_name(netdev)); 1855 if (!pdata->dev_workqueue) { 1856 netdev_err(netdev, "device workqueue creation failed\n"); 1857 return -ENOMEM; 1858 } 1859 1860 pdata->an_workqueue = 1861 create_singlethread_workqueue(pdata->an_name); 1862 if (!pdata->an_workqueue) { 1863 netdev_err(netdev, "phy workqueue creation failed\n"); 1864 ret = -ENOMEM; 1865 goto err_dev_wq; 1866 } 1867 1868 /* Reset the phy settings */ 1869 ret = xgbe_phy_reset(pdata); 1870 if (ret) 1871 goto err_an_wq; 1872 1873 /* Enable the clocks */ 1874 ret = clk_prepare_enable(pdata->sysclk); 1875 if (ret) { 1876 netdev_alert(netdev, "dma clk_prepare_enable failed\n"); 1877 goto err_an_wq; 1878 } 1879 1880 ret = clk_prepare_enable(pdata->ptpclk); 1881 if (ret) { 1882 netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); 1883 goto err_sysclk; 1884 } 1885 1886 INIT_WORK(&pdata->service_work, xgbe_service); 1887 INIT_WORK(&pdata->restart_work, xgbe_restart); 1888 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev); 1889 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); 1890 1891 ret = xgbe_alloc_memory(pdata); 1892 if (ret) 1893 goto err_ptpclk; 1894 1895 ret = xgbe_start(pdata); 1896 if (ret) 1897 goto err_mem; 1898 1899 clear_bit(XGBE_DOWN, &pdata->dev_state); 1900 1901 return 0; 1902 1903err_mem: 1904 xgbe_free_memory(pdata); 1905 1906err_ptpclk: 1907 clk_disable_unprepare(pdata->ptpclk); 1908 1909err_sysclk: 1910 clk_disable_unprepare(pdata->sysclk); 1911 1912err_an_wq: 1913 destroy_workqueue(pdata->an_workqueue); 1914 1915err_dev_wq: 1916 destroy_workqueue(pdata->dev_workqueue); 1917 1918 return ret; 1919} 1920 1921static int xgbe_close(struct net_device *netdev) 1922{ 1923 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1924 1925 /* Stop the device */ 1926 xgbe_stop(pdata); 1927 1928 xgbe_free_memory(pdata); 1929 1930 /* Disable the clocks */ 1931 clk_disable_unprepare(pdata->ptpclk); 1932 clk_disable_unprepare(pdata->sysclk); 1933 1934 flush_workqueue(pdata->an_workqueue); 1935 destroy_workqueue(pdata->an_workqueue); 1936 1937 flush_workqueue(pdata->dev_workqueue); 1938 destroy_workqueue(pdata->dev_workqueue); 1939 1940 set_bit(XGBE_DOWN, &pdata->dev_state); 1941 1942 return 0; 1943} 1944 1945static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) 1946{ 1947 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1948 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1949 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1950 struct xgbe_channel *channel; 1951 struct xgbe_ring *ring; 1952 struct xgbe_packet_data *packet; 1953 struct netdev_queue *txq; 1954 netdev_tx_t ret; 1955 1956 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); 1957 1958 channel = pdata->channel[skb->queue_mapping]; 1959 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1960 ring = channel->tx_ring; 1961 packet = &ring->packet_data; 1962 1963 ret = NETDEV_TX_OK; 1964 1965 if (skb->len == 0) { 1966 netif_err(pdata, tx_err, netdev, 1967 "empty skb received from stack\n"); 1968 dev_kfree_skb_any(skb); 1969 goto tx_netdev_return; 1970 } 1971 1972 /* Calculate preliminary packet info */ 1973 memset(packet, 0, sizeof(*packet)); 1974 xgbe_packet_info(pdata, ring, skb, packet); 1975 1976 /* Check that there are enough descriptors available */ 1977 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); 1978 if (ret) 1979 goto tx_netdev_return; 1980 1981 ret = xgbe_prep_tso(skb, packet); 1982 if (ret) { 1983 netif_err(pdata, tx_err, netdev, 1984 "error processing TSO packet\n"); 1985 dev_kfree_skb_any(skb); 1986 goto tx_netdev_return; 1987 } 1988 xgbe_prep_vlan(skb, packet); 1989 1990 if (!desc_if->map_tx_skb(channel, skb)) { 1991 dev_kfree_skb_any(skb); 1992 goto tx_netdev_return; 1993 } 1994 1995 xgbe_prep_tx_tstamp(pdata, skb, packet); 1996 1997 /* Report on the actual number of bytes (to be) sent */ 1998 netdev_tx_sent_queue(txq, packet->tx_bytes); 1999 2000 /* Configure required descriptor fields for transmission */ 2001 hw_if->dev_xmit(channel); 2002 2003 if (netif_msg_pktdata(pdata)) 2004 xgbe_print_pkt(netdev, skb, true); 2005 2006 /* Stop the queue in advance if there may not be enough descriptors */ 2007 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); 2008 2009 ret = NETDEV_TX_OK; 2010 2011tx_netdev_return: 2012 return ret; 2013} 2014 2015static void xgbe_set_rx_mode(struct net_device *netdev) 2016{ 2017 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2018 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2019 2020 DBGPR("-->xgbe_set_rx_mode\n"); 2021 2022 hw_if->config_rx_mode(pdata); 2023 2024 DBGPR("<--xgbe_set_rx_mode\n"); 2025} 2026 2027static int xgbe_set_mac_address(struct net_device *netdev, void *addr) 2028{ 2029 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2030 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2031 struct sockaddr *saddr = addr; 2032 2033 DBGPR("-->xgbe_set_mac_address\n"); 2034 2035 if (!is_valid_ether_addr(saddr->sa_data)) 2036 return -EADDRNOTAVAIL; 2037 2038 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); 2039 2040 hw_if->set_mac_address(pdata, netdev->dev_addr); 2041 2042 DBGPR("<--xgbe_set_mac_address\n"); 2043 2044 return 0; 2045} 2046 2047static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) 2048{ 2049 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2050 int ret; 2051 2052 switch (cmd) { 2053 case SIOCGHWTSTAMP: 2054 ret = xgbe_get_hwtstamp_settings(pdata, ifreq); 2055 break; 2056 2057 case SIOCSHWTSTAMP: 2058 ret = xgbe_set_hwtstamp_settings(pdata, ifreq); 2059 break; 2060 2061 default: 2062 ret = -EOPNOTSUPP; 2063 } 2064 2065 return ret; 2066} 2067 2068static int xgbe_change_mtu(struct net_device *netdev, int mtu) 2069{ 2070 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2071 int ret; 2072 2073 DBGPR("-->xgbe_change_mtu\n"); 2074 2075 ret = xgbe_calc_rx_buf_size(netdev, mtu); 2076 if (ret < 0) 2077 return ret; 2078 2079 pdata->rx_buf_size = ret; 2080 netdev->mtu = mtu; 2081 2082 xgbe_restart_dev(pdata); 2083 2084 DBGPR("<--xgbe_change_mtu\n"); 2085 2086 return 0; 2087} 2088 2089static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2090{ 2091 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2092 2093 netdev_warn(netdev, "tx timeout, device restarting\n"); 2094 schedule_work(&pdata->restart_work); 2095} 2096 2097static void xgbe_get_stats64(struct net_device *netdev, 2098 struct rtnl_link_stats64 *s) 2099{ 2100 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2101 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 2102 2103 DBGPR("-->%s\n", __func__); 2104 2105 pdata->hw_if.read_mmc_stats(pdata); 2106 2107 s->rx_packets = pstats->rxframecount_gb; 2108 s->rx_bytes = pstats->rxoctetcount_gb; 2109 s->rx_errors = pstats->rxframecount_gb - 2110 pstats->rxbroadcastframes_g - 2111 pstats->rxmulticastframes_g - 2112 pstats->rxunicastframes_g; 2113 s->multicast = pstats->rxmulticastframes_g; 2114 s->rx_length_errors = pstats->rxlengtherror; 2115 s->rx_crc_errors = pstats->rxcrcerror; 2116 s->rx_fifo_errors = pstats->rxfifooverflow; 2117 2118 s->tx_packets = pstats->txframecount_gb; 2119 s->tx_bytes = pstats->txoctetcount_gb; 2120 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; 2121 s->tx_dropped = netdev->stats.tx_dropped; 2122 2123 DBGPR("<--%s\n", __func__); 2124} 2125 2126static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 2127 u16 vid) 2128{ 2129 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2130 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2131 2132 DBGPR("-->%s\n", __func__); 2133 2134 set_bit(vid, pdata->active_vlans); 2135 hw_if->update_vlan_hash_table(pdata); 2136 2137 DBGPR("<--%s\n", __func__); 2138 2139 return 0; 2140} 2141 2142static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 2143 u16 vid) 2144{ 2145 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2146 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2147 2148 DBGPR("-->%s\n", __func__); 2149 2150 clear_bit(vid, pdata->active_vlans); 2151 hw_if->update_vlan_hash_table(pdata); 2152 2153 DBGPR("<--%s\n", __func__); 2154 2155 return 0; 2156} 2157 2158#ifdef CONFIG_NET_POLL_CONTROLLER 2159static void xgbe_poll_controller(struct net_device *netdev) 2160{ 2161 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2162 struct xgbe_channel *channel; 2163 unsigned int i; 2164 2165 DBGPR("-->xgbe_poll_controller\n"); 2166 2167 if (pdata->per_channel_irq) { 2168 for (i = 0; i < pdata->channel_count; i++) { 2169 channel = pdata->channel[i]; 2170 xgbe_dma_isr(channel->dma_irq, channel); 2171 } 2172 } else { 2173 disable_irq(pdata->dev_irq); 2174 xgbe_isr(pdata->dev_irq, pdata); 2175 enable_irq(pdata->dev_irq); 2176 } 2177 2178 DBGPR("<--xgbe_poll_controller\n"); 2179} 2180#endif /* End CONFIG_NET_POLL_CONTROLLER */ 2181 2182static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type, 2183 void *type_data) 2184{ 2185 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2186 struct tc_mqprio_qopt *mqprio = type_data; 2187 u8 tc; 2188 2189 if (type != TC_SETUP_QDISC_MQPRIO) 2190 return -EOPNOTSUPP; 2191 2192 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 2193 tc = mqprio->num_tc; 2194 2195 if (tc > pdata->hw_feat.tc_cnt) 2196 return -EINVAL; 2197 2198 pdata->num_tcs = tc; 2199 pdata->hw_if.config_tc(pdata); 2200 2201 return 0; 2202} 2203 2204static netdev_features_t xgbe_fix_features(struct net_device *netdev, 2205 netdev_features_t features) 2206{ 2207 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2208 netdev_features_t vxlan_base; 2209 2210 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT; 2211 2212 if (!pdata->hw_feat.vxn) 2213 return features; 2214 2215 /* VXLAN CSUM requires VXLAN base */ 2216 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) && 2217 !(features & NETIF_F_GSO_UDP_TUNNEL)) { 2218 netdev_notice(netdev, 2219 "forcing tx udp tunnel support\n"); 2220 features |= NETIF_F_GSO_UDP_TUNNEL; 2221 } 2222 2223 /* Can't do one without doing the other */ 2224 if ((features & vxlan_base) != vxlan_base) { 2225 netdev_notice(netdev, 2226 "forcing both tx and rx udp tunnel support\n"); 2227 features |= vxlan_base; 2228 } 2229 2230 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) { 2231 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) { 2232 netdev_notice(netdev, 2233 "forcing tx udp tunnel checksumming on\n"); 2234 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2235 } 2236 } else { 2237 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) { 2238 netdev_notice(netdev, 2239 "forcing tx udp tunnel checksumming off\n"); 2240 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM; 2241 } 2242 } 2243 2244 return features; 2245} 2246 2247static int xgbe_set_features(struct net_device *netdev, 2248 netdev_features_t features) 2249{ 2250 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2251 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2252 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; 2253 int ret = 0; 2254 2255 rxhash = pdata->netdev_features & NETIF_F_RXHASH; 2256 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; 2257 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; 2258 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; 2259 2260 if ((features & NETIF_F_RXHASH) && !rxhash) 2261 ret = hw_if->enable_rss(pdata); 2262 else if (!(features & NETIF_F_RXHASH) && rxhash) 2263 ret = hw_if->disable_rss(pdata); 2264 if (ret) 2265 return ret; 2266 2267 if ((features & NETIF_F_RXCSUM) && !rxcsum) 2268 hw_if->enable_rx_csum(pdata); 2269 else if (!(features & NETIF_F_RXCSUM) && rxcsum) 2270 hw_if->disable_rx_csum(pdata); 2271 2272 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) 2273 hw_if->enable_rx_vlan_stripping(pdata); 2274 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) 2275 hw_if->disable_rx_vlan_stripping(pdata); 2276 2277 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) 2278 hw_if->enable_rx_vlan_filtering(pdata); 2279 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) 2280 hw_if->disable_rx_vlan_filtering(pdata); 2281 2282 pdata->netdev_features = features; 2283 2284 DBGPR("<--xgbe_set_features\n"); 2285 2286 return 0; 2287} 2288 2289static netdev_features_t xgbe_features_check(struct sk_buff *skb, 2290 struct net_device *netdev, 2291 netdev_features_t features) 2292{ 2293 features = vlan_features_check(skb, features); 2294 features = vxlan_features_check(skb, features); 2295 2296 return features; 2297} 2298 2299static const struct net_device_ops xgbe_netdev_ops = { 2300 .ndo_open = xgbe_open, 2301 .ndo_stop = xgbe_close, 2302 .ndo_start_xmit = xgbe_xmit, 2303 .ndo_set_rx_mode = xgbe_set_rx_mode, 2304 .ndo_set_mac_address = xgbe_set_mac_address, 2305 .ndo_validate_addr = eth_validate_addr, 2306 .ndo_do_ioctl = xgbe_ioctl, 2307 .ndo_change_mtu = xgbe_change_mtu, 2308 .ndo_tx_timeout = xgbe_tx_timeout, 2309 .ndo_get_stats64 = xgbe_get_stats64, 2310 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, 2311 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, 2312#ifdef CONFIG_NET_POLL_CONTROLLER 2313 .ndo_poll_controller = xgbe_poll_controller, 2314#endif 2315 .ndo_setup_tc = xgbe_setup_tc, 2316 .ndo_fix_features = xgbe_fix_features, 2317 .ndo_set_features = xgbe_set_features, 2318 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, 2319 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, 2320 .ndo_features_check = xgbe_features_check, 2321}; 2322 2323const struct net_device_ops *xgbe_get_netdev_ops(void) 2324{ 2325 return &xgbe_netdev_ops; 2326} 2327 2328static void xgbe_rx_refresh(struct xgbe_channel *channel) 2329{ 2330 struct xgbe_prv_data *pdata = channel->pdata; 2331 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2332 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2333 struct xgbe_ring *ring = channel->rx_ring; 2334 struct xgbe_ring_data *rdata; 2335 2336 while (ring->dirty != ring->cur) { 2337 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 2338 2339 /* Reset rdata values */ 2340 desc_if->unmap_rdata(pdata, rdata); 2341 2342 if (desc_if->map_rx_buffer(pdata, ring, rdata)) 2343 break; 2344 2345 hw_if->rx_desc_reset(pdata, rdata, ring->dirty); 2346 2347 ring->dirty++; 2348 } 2349 2350 /* Make sure everything is written before the register write */ 2351 wmb(); 2352 2353 /* Update the Rx Tail Pointer Register with address of 2354 * the last cleaned entry */ 2355 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); 2356 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 2357 lower_32_bits(rdata->rdesc_dma)); 2358} 2359 2360static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, 2361 struct napi_struct *napi, 2362 struct xgbe_ring_data *rdata, 2363 unsigned int len) 2364{ 2365 struct sk_buff *skb; 2366 u8 *packet; 2367 2368 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); 2369 if (!skb) 2370 return NULL; 2371 2372 /* Pull in the header buffer which may contain just the header 2373 * or the header plus data 2374 */ 2375 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, 2376 rdata->rx.hdr.dma_off, 2377 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); 2378 2379 packet = page_address(rdata->rx.hdr.pa.pages) + 2380 rdata->rx.hdr.pa.pages_offset; 2381 skb_copy_to_linear_data(skb, packet, len); 2382 skb_put(skb, len); 2383 2384 return skb; 2385} 2386 2387static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata, 2388 struct xgbe_packet_data *packet) 2389{ 2390 /* Always zero if not the first descriptor */ 2391 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) 2392 return 0; 2393 2394 /* First descriptor with split header, return header length */ 2395 if (rdata->rx.hdr_len) 2396 return rdata->rx.hdr_len; 2397 2398 /* First descriptor but not the last descriptor and no split header, 2399 * so the full buffer was used 2400 */ 2401 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) 2402 return rdata->rx.hdr.dma_len; 2403 2404 /* First descriptor and last descriptor and no split header, so 2405 * calculate how much of the buffer was used 2406 */ 2407 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len); 2408} 2409 2410static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata, 2411 struct xgbe_packet_data *packet, 2412 unsigned int len) 2413{ 2414 /* Always the full buffer if not the last descriptor */ 2415 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) 2416 return rdata->rx.buf.dma_len; 2417 2418 /* Last descriptor so calculate how much of the buffer was used 2419 * for the last bit of data 2420 */ 2421 return rdata->rx.len - len; 2422} 2423 2424static int xgbe_tx_poll(struct xgbe_channel *channel) 2425{ 2426 struct xgbe_prv_data *pdata = channel->pdata; 2427 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2428 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2429 struct xgbe_ring *ring = channel->tx_ring; 2430 struct xgbe_ring_data *rdata; 2431 struct xgbe_ring_desc *rdesc; 2432 struct net_device *netdev = pdata->netdev; 2433 struct netdev_queue *txq; 2434 int processed = 0; 2435 unsigned int tx_packets = 0, tx_bytes = 0; 2436 unsigned int cur; 2437 2438 DBGPR("-->xgbe_tx_poll\n"); 2439 2440 /* Nothing to do if there isn't a Tx ring for this channel */ 2441 if (!ring) 2442 return 0; 2443 2444 cur = ring->cur; 2445 2446 /* Be sure we get ring->cur before accessing descriptor data */ 2447 smp_rmb(); 2448 2449 txq = netdev_get_tx_queue(netdev, channel->queue_index); 2450 2451 while ((processed < XGBE_TX_DESC_MAX_PROC) && 2452 (ring->dirty != cur)) { 2453 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 2454 rdesc = rdata->rdesc; 2455 2456 if (!hw_if->tx_complete(rdesc)) 2457 break; 2458 2459 /* Make sure descriptor fields are read after reading the OWN 2460 * bit */ 2461 dma_rmb(); 2462 2463 if (netif_msg_tx_done(pdata)) 2464 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); 2465 2466 if (hw_if->is_last_desc(rdesc)) { 2467 tx_packets += rdata->tx.packets; 2468 tx_bytes += rdata->tx.bytes; 2469 } 2470 2471 /* Free the SKB and reset the descriptor for re-use */ 2472 desc_if->unmap_rdata(pdata, rdata); 2473 hw_if->tx_desc_reset(rdata); 2474 2475 processed++; 2476 ring->dirty++; 2477 } 2478 2479 if (!processed) 2480 return 0; 2481 2482 netdev_tx_completed_queue(txq, tx_packets, tx_bytes); 2483 2484 if ((ring->tx.queue_stopped == 1) && 2485 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { 2486 ring->tx.queue_stopped = 0; 2487 netif_tx_wake_queue(txq); 2488 } 2489 2490 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); 2491 2492 return processed; 2493} 2494 2495static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) 2496{ 2497 struct xgbe_prv_data *pdata = channel->pdata; 2498 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2499 struct xgbe_ring *ring = channel->rx_ring; 2500 struct xgbe_ring_data *rdata; 2501 struct xgbe_packet_data *packet; 2502 struct net_device *netdev = pdata->netdev; 2503 struct napi_struct *napi; 2504 struct sk_buff *skb; 2505 struct skb_shared_hwtstamps *hwtstamps; 2506 unsigned int last, error, context_next, context; 2507 unsigned int len, buf1_len, buf2_len, max_len; 2508 unsigned int received = 0; 2509 int packet_count = 0; 2510 2511 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); 2512 2513 /* Nothing to do if there isn't a Rx ring for this channel */ 2514 if (!ring) 2515 return 0; 2516 2517 last = 0; 2518 context_next = 0; 2519 2520 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 2521 2522 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2523 packet = &ring->packet_data; 2524 while (packet_count < budget) { 2525 DBGPR(" cur = %d\n", ring->cur); 2526 2527 /* First time in loop see if we need to restore state */ 2528 if (!received && rdata->state_saved) { 2529 skb = rdata->state.skb; 2530 error = rdata->state.error; 2531 len = rdata->state.len; 2532 } else { 2533 memset(packet, 0, sizeof(*packet)); 2534 skb = NULL; 2535 error = 0; 2536 len = 0; 2537 } 2538 2539read_again: 2540 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2541 2542 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) 2543 xgbe_rx_refresh(channel); 2544 2545 if (hw_if->dev_read(channel)) 2546 break; 2547 2548 received++; 2549 ring->cur++; 2550 2551 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2552 LAST); 2553 context_next = XGMAC_GET_BITS(packet->attributes, 2554 RX_PACKET_ATTRIBUTES, 2555 CONTEXT_NEXT); 2556 context = XGMAC_GET_BITS(packet->attributes, 2557 RX_PACKET_ATTRIBUTES, 2558 CONTEXT); 2559 2560 /* Earlier error, just drain the remaining data */ 2561 if ((!last || context_next) && error) 2562 goto read_again; 2563 2564 if (error || packet->errors) { 2565 if (packet->errors) 2566 netif_err(pdata, rx_err, netdev, 2567 "error in received packet\n"); 2568 dev_kfree_skb(skb); 2569 goto next_packet; 2570 } 2571 2572 if (!context) { 2573 /* Get the data length in the descriptor buffers */ 2574 buf1_len = xgbe_rx_buf1_len(rdata, packet); 2575 len += buf1_len; 2576 buf2_len = xgbe_rx_buf2_len(rdata, packet, len); 2577 len += buf2_len; 2578 2579 if (buf2_len > rdata->rx.buf.dma_len) { 2580 /* Hardware inconsistency within the descriptors 2581 * that has resulted in a length underflow. 2582 */ 2583 error = 1; 2584 goto skip_data; 2585 } 2586 2587 if (!skb) { 2588 skb = xgbe_create_skb(pdata, napi, rdata, 2589 buf1_len); 2590 if (!skb) { 2591 error = 1; 2592 goto skip_data; 2593 } 2594 } 2595 2596 if (buf2_len) { 2597 dma_sync_single_range_for_cpu(pdata->dev, 2598 rdata->rx.buf.dma_base, 2599 rdata->rx.buf.dma_off, 2600 rdata->rx.buf.dma_len, 2601 DMA_FROM_DEVICE); 2602 2603 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2604 rdata->rx.buf.pa.pages, 2605 rdata->rx.buf.pa.pages_offset, 2606 buf2_len, 2607 rdata->rx.buf.dma_len); 2608 rdata->rx.buf.pa.pages = NULL; 2609 } 2610 } 2611 2612skip_data: 2613 if (!last || context_next) 2614 goto read_again; 2615 2616 if (!skb || error) { 2617 dev_kfree_skb(skb); 2618 goto next_packet; 2619 } 2620 2621 /* Be sure we don't exceed the configured MTU */ 2622 max_len = netdev->mtu + ETH_HLEN; 2623 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 2624 (skb->protocol == htons(ETH_P_8021Q))) 2625 max_len += VLAN_HLEN; 2626 2627 if (skb->len > max_len) { 2628 netif_err(pdata, rx_err, netdev, 2629 "packet length exceeds configured MTU\n"); 2630 dev_kfree_skb(skb); 2631 goto next_packet; 2632 } 2633 2634 if (netif_msg_pktdata(pdata)) 2635 xgbe_print_pkt(netdev, skb, false); 2636 2637 skb_checksum_none_assert(skb); 2638 if (XGMAC_GET_BITS(packet->attributes, 2639 RX_PACKET_ATTRIBUTES, CSUM_DONE)) 2640 skb->ip_summed = CHECKSUM_UNNECESSARY; 2641 2642 if (XGMAC_GET_BITS(packet->attributes, 2643 RX_PACKET_ATTRIBUTES, TNP)) { 2644 skb->encapsulation = 1; 2645 2646 if (XGMAC_GET_BITS(packet->attributes, 2647 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE)) 2648 skb->csum_level = 1; 2649 } 2650 2651 if (XGMAC_GET_BITS(packet->attributes, 2652 RX_PACKET_ATTRIBUTES, VLAN_CTAG)) 2653 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2654 packet->vlan_ctag); 2655 2656 if (XGMAC_GET_BITS(packet->attributes, 2657 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { 2658 u64 nsec; 2659 2660 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 2661 packet->rx_tstamp); 2662 hwtstamps = skb_hwtstamps(skb); 2663 hwtstamps->hwtstamp = ns_to_ktime(nsec); 2664 } 2665 2666 if (XGMAC_GET_BITS(packet->attributes, 2667 RX_PACKET_ATTRIBUTES, RSS_HASH)) 2668 skb_set_hash(skb, packet->rss_hash, 2669 packet->rss_hash_type); 2670 2671 skb->dev = netdev; 2672 skb->protocol = eth_type_trans(skb, netdev); 2673 skb_record_rx_queue(skb, channel->queue_index); 2674 2675 napi_gro_receive(napi, skb); 2676 2677next_packet: 2678 packet_count++; 2679 } 2680 2681 /* Check if we need to save state before leaving */ 2682 if (received && (!last || context_next)) { 2683 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2684 rdata->state_saved = 1; 2685 rdata->state.skb = skb; 2686 rdata->state.len = len; 2687 rdata->state.error = error; 2688 } 2689 2690 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); 2691 2692 return packet_count; 2693} 2694 2695static int xgbe_one_poll(struct napi_struct *napi, int budget) 2696{ 2697 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, 2698 napi); 2699 struct xgbe_prv_data *pdata = channel->pdata; 2700 int processed = 0; 2701 2702 DBGPR("-->xgbe_one_poll: budget=%d\n", budget); 2703 2704 /* Cleanup Tx ring first */ 2705 xgbe_tx_poll(channel); 2706 2707 /* Process Rx ring next */ 2708 processed = xgbe_rx_poll(channel, budget); 2709 2710 /* If we processed everything, we are done */ 2711 if ((processed < budget) && napi_complete_done(napi, processed)) { 2712 /* Enable Tx and Rx interrupts */ 2713 if (pdata->channel_irq_mode) 2714 xgbe_enable_rx_tx_int(pdata, channel); 2715 else 2716 enable_irq(channel->dma_irq); 2717 } 2718 2719 DBGPR("<--xgbe_one_poll: received = %d\n", processed); 2720 2721 return processed; 2722} 2723 2724static int xgbe_all_poll(struct napi_struct *napi, int budget) 2725{ 2726 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, 2727 napi); 2728 struct xgbe_channel *channel; 2729 int ring_budget; 2730 int processed, last_processed; 2731 unsigned int i; 2732 2733 DBGPR("-->xgbe_all_poll: budget=%d\n", budget); 2734 2735 processed = 0; 2736 ring_budget = budget / pdata->rx_ring_count; 2737 do { 2738 last_processed = processed; 2739 2740 for (i = 0; i < pdata->channel_count; i++) { 2741 channel = pdata->channel[i]; 2742 2743 /* Cleanup Tx ring first */ 2744 xgbe_tx_poll(channel); 2745 2746 /* Process Rx ring next */ 2747 if (ring_budget > (budget - processed)) 2748 ring_budget = budget - processed; 2749 processed += xgbe_rx_poll(channel, ring_budget); 2750 } 2751 } while ((processed < budget) && (processed != last_processed)); 2752 2753 /* If we processed everything, we are done */ 2754 if ((processed < budget) && napi_complete_done(napi, processed)) { 2755 /* Enable Tx and Rx interrupts */ 2756 xgbe_enable_rx_tx_ints(pdata); 2757 } 2758 2759 DBGPR("<--xgbe_all_poll: received = %d\n", processed); 2760 2761 return processed; 2762} 2763 2764void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2765 unsigned int idx, unsigned int count, unsigned int flag) 2766{ 2767 struct xgbe_ring_data *rdata; 2768 struct xgbe_ring_desc *rdesc; 2769 2770 while (count--) { 2771 rdata = XGBE_GET_DESC_DATA(ring, idx); 2772 rdesc = rdata->rdesc; 2773 netdev_dbg(pdata->netdev, 2774 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 2775 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 2776 le32_to_cpu(rdesc->desc0), 2777 le32_to_cpu(rdesc->desc1), 2778 le32_to_cpu(rdesc->desc2), 2779 le32_to_cpu(rdesc->desc3)); 2780 idx++; 2781 } 2782} 2783 2784void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2785 unsigned int idx) 2786{ 2787 struct xgbe_ring_data *rdata; 2788 struct xgbe_ring_desc *rdesc; 2789 2790 rdata = XGBE_GET_DESC_DATA(ring, idx); 2791 rdesc = rdata->rdesc; 2792 netdev_dbg(pdata->netdev, 2793 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", 2794 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), 2795 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); 2796} 2797 2798void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) 2799{ 2800 struct ethhdr *eth = (struct ethhdr *)skb->data; 2801 unsigned char buffer[128]; 2802 unsigned int i; 2803 2804 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2805 2806 netdev_dbg(netdev, "%s packet of %d bytes\n", 2807 (tx_rx ? "TX" : "RX"), skb->len); 2808 2809 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 2810 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); 2811 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); 2812 2813 for (i = 0; i < skb->len; i += 32) { 2814 unsigned int len = min(skb->len - i, 32U); 2815 2816 hex_dump_to_buffer(&skb->data[i], len, 32, 1, 2817 buffer, sizeof(buffer), false); 2818 netdev_dbg(netdev, " %#06x: %s\n", i, buffer); 2819 } 2820 2821 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2822} 2823