1/* ---------------------------------------------------------------------------- 2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN. 3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao 4 5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media 6 Access Controller for Ethernet (MACE). It is essentially the Am2150 7 PCMCIA Ethernet card contained in the Am2150 Demo Kit. 8 9Written by Roger C. Pao <rpao@paonet.org> 10 Copyright 1995 Roger C. Pao 11 Linux 2.5 cleanups Copyright Red Hat 2003 12 13 This software may be used and distributed according to the terms of 14 the GNU General Public License. 15 16Ported to Linux 1.3.* network driver environment by 17 Matti Aarnio <mea@utu.fi> 18 19References 20 21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993 22 Am79C940 (MACE) Data Sheet, 1994 23 Am79C90 (C-LANCE) Data Sheet, 1994 24 Linux PCMCIA Programmer's Guide v1.17 25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8 26 27 Eric Mears, New Media Corporation 28 Tom Pollard, New Media Corporation 29 Dean Siasoyco, New Media Corporation 30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com> 31 Donald Becker <becker@scyld.com> 32 David Hinds <dahinds@users.sourceforge.net> 33 34 The Linux client driver is based on the 3c589_cs.c client driver by 35 David Hinds. 36 37 The Linux network driver outline is based on the 3c589_cs.c driver, 38 the 8390.c driver, and the example skeleton.c kernel code, which are 39 by Donald Becker. 40 41 The Am2150 network driver hardware interface code is based on the 42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears. 43 44 Special thanks for testing and help in debugging this driver goes 45 to Ken Lesniak. 46 47------------------------------------------------------------------------------- 48Driver Notes and Issues 49------------------------------------------------------------------------------- 50 511. Developed on a Dell 320SLi 52 PCMCIA Card Services 2.6.2 53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386 54 552. rc.pcmcia may require loading pcmcia_core with io_speed=300: 56 'insmod pcmcia_core.o io_speed=300'. 57 This will avoid problems with fast systems which causes rx_framecnt 58 to return random values. 59 603. If hot extraction does not work for you, use 'ifconfig eth0 down' 61 before extraction. 62 634. There is a bad slow-down problem in this driver. 64 655. Future: Multicast processing. In the meantime, do _not_ compile your 66 kernel with multicast ip enabled. 67 68------------------------------------------------------------------------------- 69History 70------------------------------------------------------------------------------- 71Log: nmclan_cs.c,v 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk> 73 * Fixed hang on card eject as we probe it 74 * Cleaned up to use new style locking. 75 * 76 * Revision 0.16 1995/07/01 06:42:17 rpao 77 * Bug fix: nmclan_reset() called CardServices incorrectly. 78 * 79 * Revision 0.15 1995/05/24 08:09:47 rpao 80 * Re-implement MULTI_TX dev->tbusy handling. 81 * 82 * Revision 0.14 1995/05/23 03:19:30 rpao 83 * Added, in nmclan_config(), "tuple.Attributes = 0;". 84 * Modified MACE ID check to ignore chip revision level. 85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt. 86 * 87 * Revision 0.13 1995/05/18 05:56:34 rpao 88 * Statistics changes. 89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list. 90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup. 91 * 92 * Revision 0.12 1995/05/14 00:12:23 rpao 93 * Statistics overhaul. 94 * 95 9695/05/13 rpao V0.10a 97 Bug fix: MACE statistics counters used wrong I/O ports. 98 Bug fix: mace_interrupt() needed to allow statistics to be 99 processed without RX or TX interrupts pending. 10095/05/11 rpao V0.10 101 Multiple transmit request processing. 102 Modified statistics to use MACE counters where possible. 10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO. 104 *Released 10595/05/10 rpao V0.08 106 Bug fix: Make all non-exported functions private by using 107 static keyword. 108 Bug fix: Test IntrCnt _before_ reading MACE_IR. 10995/05/10 rpao V0.07 Statistics. 11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states. 111 112---------------------------------------------------------------------------- */ 113 114#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 115 116#define DRV_NAME "nmclan_cs" 117 118/* ---------------------------------------------------------------------------- 119Conditional Compilation Options 120---------------------------------------------------------------------------- */ 121 122#define MULTI_TX 0 123#define RESET_ON_TIMEOUT 1 124#define TX_INTERRUPTABLE 1 125#define RESET_XILINX 0 126 127/* ---------------------------------------------------------------------------- 128Include Files 129---------------------------------------------------------------------------- */ 130 131#include <linux/module.h> 132#include <linux/kernel.h> 133#include <linux/ptrace.h> 134#include <linux/slab.h> 135#include <linux/string.h> 136#include <linux/timer.h> 137#include <linux/interrupt.h> 138#include <linux/in.h> 139#include <linux/delay.h> 140#include <linux/ethtool.h> 141#include <linux/netdevice.h> 142#include <linux/etherdevice.h> 143#include <linux/skbuff.h> 144#include <linux/if_arp.h> 145#include <linux/ioport.h> 146#include <linux/bitops.h> 147 148#include <pcmcia/cisreg.h> 149#include <pcmcia/cistpl.h> 150#include <pcmcia/ds.h> 151 152#include <linux/uaccess.h> 153#include <asm/io.h> 154 155/* ---------------------------------------------------------------------------- 156Defines 157---------------------------------------------------------------------------- */ 158 159#define MACE_LADRF_LEN 8 160 /* 8 bytes in Logical Address Filter */ 161 162/* Loop Control Defines */ 163#define MACE_MAX_IR_ITERATIONS 10 164#define MACE_MAX_RX_ITERATIONS 12 165 /* 166 TBD: Dean brought this up, and I assumed the hardware would 167 handle it: 168 169 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be 170 non-zero when the isr exits. We may not get another interrupt 171 to process the remaining packets for some time. 172 */ 173 174/* 175The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA) 176which manages the interface between the MACE and the PCMCIA bus. It 177also includes buffer management for the 32K x 8 SRAM to control up to 178four transmit and 12 receive frames at a time. 179*/ 180#define AM2150_MAX_TX_FRAMES 4 181#define AM2150_MAX_RX_FRAMES 12 182 183/* Am2150 Ethernet Card I/O Mapping */ 184#define AM2150_RCV 0x00 185#define AM2150_XMT 0x04 186#define AM2150_XMT_SKIP 0x09 187#define AM2150_RCV_NEXT 0x0A 188#define AM2150_RCV_FRAME_COUNT 0x0B 189#define AM2150_MACE_BANK 0x0C 190#define AM2150_MACE_BASE 0x10 191 192/* MACE Registers */ 193#define MACE_RCVFIFO 0 194#define MACE_XMTFIFO 1 195#define MACE_XMTFC 2 196#define MACE_XMTFS 3 197#define MACE_XMTRC 4 198#define MACE_RCVFC 5 199#define MACE_RCVFS 6 200#define MACE_FIFOFC 7 201#define MACE_IR 8 202#define MACE_IMR 9 203#define MACE_PR 10 204#define MACE_BIUCC 11 205#define MACE_FIFOCC 12 206#define MACE_MACCC 13 207#define MACE_PLSCC 14 208#define MACE_PHYCC 15 209#define MACE_CHIPIDL 16 210#define MACE_CHIPIDH 17 211#define MACE_IAC 18 212/* Reserved */ 213#define MACE_LADRF 20 214#define MACE_PADR 21 215/* Reserved */ 216/* Reserved */ 217#define MACE_MPC 24 218/* Reserved */ 219#define MACE_RNTPC 26 220#define MACE_RCVCC 27 221/* Reserved */ 222#define MACE_UTR 29 223#define MACE_RTR1 30 224#define MACE_RTR2 31 225 226/* MACE Bit Masks */ 227#define MACE_XMTRC_EXDEF 0x80 228#define MACE_XMTRC_XMTRC 0x0F 229 230#define MACE_XMTFS_XMTSV 0x80 231#define MACE_XMTFS_UFLO 0x40 232#define MACE_XMTFS_LCOL 0x20 233#define MACE_XMTFS_MORE 0x10 234#define MACE_XMTFS_ONE 0x08 235#define MACE_XMTFS_DEFER 0x04 236#define MACE_XMTFS_LCAR 0x02 237#define MACE_XMTFS_RTRY 0x01 238 239#define MACE_RCVFS_RCVSTS 0xF000 240#define MACE_RCVFS_OFLO 0x8000 241#define MACE_RCVFS_CLSN 0x4000 242#define MACE_RCVFS_FRAM 0x2000 243#define MACE_RCVFS_FCS 0x1000 244 245#define MACE_FIFOFC_RCVFC 0xF0 246#define MACE_FIFOFC_XMTFC 0x0F 247 248#define MACE_IR_JAB 0x80 249#define MACE_IR_BABL 0x40 250#define MACE_IR_CERR 0x20 251#define MACE_IR_RCVCCO 0x10 252#define MACE_IR_RNTPCO 0x08 253#define MACE_IR_MPCO 0x04 254#define MACE_IR_RCVINT 0x02 255#define MACE_IR_XMTINT 0x01 256 257#define MACE_MACCC_PROM 0x80 258#define MACE_MACCC_DXMT2PD 0x40 259#define MACE_MACCC_EMBA 0x20 260#define MACE_MACCC_RESERVED 0x10 261#define MACE_MACCC_DRCVPA 0x08 262#define MACE_MACCC_DRCVBC 0x04 263#define MACE_MACCC_ENXMT 0x02 264#define MACE_MACCC_ENRCV 0x01 265 266#define MACE_PHYCC_LNKFL 0x80 267#define MACE_PHYCC_DLNKTST 0x40 268#define MACE_PHYCC_REVPOL 0x20 269#define MACE_PHYCC_DAPC 0x10 270#define MACE_PHYCC_LRT 0x08 271#define MACE_PHYCC_ASEL 0x04 272#define MACE_PHYCC_RWAKE 0x02 273#define MACE_PHYCC_AWAKE 0x01 274 275#define MACE_IAC_ADDRCHG 0x80 276#define MACE_IAC_PHYADDR 0x04 277#define MACE_IAC_LOGADDR 0x02 278 279#define MACE_UTR_RTRE 0x80 280#define MACE_UTR_RTRD 0x40 281#define MACE_UTR_RPA 0x20 282#define MACE_UTR_FCOLL 0x10 283#define MACE_UTR_RCVFCSE 0x08 284#define MACE_UTR_LOOP_INCL_MENDEC 0x06 285#define MACE_UTR_LOOP_NO_MENDEC 0x04 286#define MACE_UTR_LOOP_EXTERNAL 0x02 287#define MACE_UTR_LOOP_NONE 0x00 288#define MACE_UTR_RESERVED 0x01 289 290/* Switch MACE register bank (only 0 and 1 are valid) */ 291#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) 292 293#define MACE_IMR_DEFAULT \ 294 (0xFF - \ 295 ( \ 296 MACE_IR_CERR | \ 297 MACE_IR_RCVCCO | \ 298 MACE_IR_RNTPCO | \ 299 MACE_IR_MPCO | \ 300 MACE_IR_RCVINT | \ 301 MACE_IR_XMTINT \ 302 ) \ 303 ) 304#undef MACE_IMR_DEFAULT 305#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */ 306 307#define TX_TIMEOUT ((400*HZ)/1000) 308 309/* ---------------------------------------------------------------------------- 310Type Definitions 311---------------------------------------------------------------------------- */ 312 313typedef struct _mace_statistics { 314 /* MACE_XMTFS */ 315 int xmtsv; 316 int uflo; 317 int lcol; 318 int more; 319 int one; 320 int defer; 321 int lcar; 322 int rtry; 323 324 /* MACE_XMTRC */ 325 int exdef; 326 int xmtrc; 327 328 /* RFS1--Receive Status (RCVSTS) */ 329 int oflo; 330 int clsn; 331 int fram; 332 int fcs; 333 334 /* RFS2--Runt Packet Count (RNTPC) */ 335 int rfs_rntpc; 336 337 /* RFS3--Receive Collision Count (RCVCC) */ 338 int rfs_rcvcc; 339 340 /* MACE_IR */ 341 int jab; 342 int babl; 343 int cerr; 344 int rcvcco; 345 int rntpco; 346 int mpco; 347 348 /* MACE_MPC */ 349 int mpc; 350 351 /* MACE_RNTPC */ 352 int rntpc; 353 354 /* MACE_RCVCC */ 355 int rcvcc; 356} mace_statistics; 357 358typedef struct _mace_private { 359 struct pcmcia_device *p_dev; 360 mace_statistics mace_stats; /* MACE chip statistics counters */ 361 362 /* restore_multicast_list() state variables */ 363 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */ 364 int multicast_num_addrs; 365 366 char tx_free_frames; /* Number of free transmit frame buffers */ 367 char tx_irq_disabled; /* MACE TX interrupt disabled */ 368 369 spinlock_t bank_lock; /* Must be held if you step off bank 0 */ 370} mace_private; 371 372/* ---------------------------------------------------------------------------- 373Private Global Variables 374---------------------------------------------------------------------------- */ 375 376static const char *if_names[]={ 377 "Auto", "10baseT", "BNC", 378}; 379 380/* ---------------------------------------------------------------------------- 381Parameters 382 These are the parameters that can be set during loading with 383 'insmod'. 384---------------------------------------------------------------------------- */ 385 386MODULE_DESCRIPTION("New Media PCMCIA ethernet driver"); 387MODULE_LICENSE("GPL"); 388 389#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) 390 391/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */ 392INT_MODULE_PARM(if_port, 0); 393 394 395/* ---------------------------------------------------------------------------- 396Function Prototypes 397---------------------------------------------------------------------------- */ 398 399static int nmclan_config(struct pcmcia_device *link); 400static void nmclan_release(struct pcmcia_device *link); 401 402static void nmclan_reset(struct net_device *dev); 403static int mace_config(struct net_device *dev, struct ifmap *map); 404static int mace_open(struct net_device *dev); 405static int mace_close(struct net_device *dev); 406static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 407 struct net_device *dev); 408static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue); 409static irqreturn_t mace_interrupt(int irq, void *dev_id); 410static struct net_device_stats *mace_get_stats(struct net_device *dev); 411static int mace_rx(struct net_device *dev, unsigned char RxCnt); 412static void restore_multicast_list(struct net_device *dev); 413static void set_multicast_list(struct net_device *dev); 414static const struct ethtool_ops netdev_ethtool_ops; 415 416 417static void nmclan_detach(struct pcmcia_device *p_dev); 418 419static const struct net_device_ops mace_netdev_ops = { 420 .ndo_open = mace_open, 421 .ndo_stop = mace_close, 422 .ndo_start_xmit = mace_start_xmit, 423 .ndo_tx_timeout = mace_tx_timeout, 424 .ndo_set_config = mace_config, 425 .ndo_get_stats = mace_get_stats, 426 .ndo_set_rx_mode = set_multicast_list, 427 .ndo_set_mac_address = eth_mac_addr, 428 .ndo_validate_addr = eth_validate_addr, 429}; 430 431static int nmclan_probe(struct pcmcia_device *link) 432{ 433 mace_private *lp; 434 struct net_device *dev; 435 436 dev_dbg(&link->dev, "nmclan_attach()\n"); 437 438 /* Create new ethernet device */ 439 dev = alloc_etherdev(sizeof(mace_private)); 440 if (!dev) 441 return -ENOMEM; 442 lp = netdev_priv(dev); 443 lp->p_dev = link; 444 link->priv = dev; 445 446 spin_lock_init(&lp->bank_lock); 447 link->resource[0]->end = 32; 448 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; 449 link->config_flags |= CONF_ENABLE_IRQ; 450 link->config_index = 1; 451 link->config_regs = PRESENT_OPTION; 452 453 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 454 455 dev->netdev_ops = &mace_netdev_ops; 456 dev->ethtool_ops = &netdev_ethtool_ops; 457 dev->watchdog_timeo = TX_TIMEOUT; 458 459 return nmclan_config(link); 460} /* nmclan_attach */ 461 462static void nmclan_detach(struct pcmcia_device *link) 463{ 464 struct net_device *dev = link->priv; 465 466 dev_dbg(&link->dev, "nmclan_detach\n"); 467 468 unregister_netdev(dev); 469 470 nmclan_release(link); 471 472 free_netdev(dev); 473} /* nmclan_detach */ 474 475/* ---------------------------------------------------------------------------- 476mace_read 477 Reads a MACE register. This is bank independent; however, the 478 caller must ensure that this call is not interruptable. We are 479 assuming that during normal operation, the MACE is always in 480 bank 0. 481---------------------------------------------------------------------------- */ 482static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) 483{ 484 int data = 0xFF; 485 unsigned long flags; 486 487 switch (reg >> 4) { 488 case 0: /* register 0-15 */ 489 data = inb(ioaddr + AM2150_MACE_BASE + reg); 490 break; 491 case 1: /* register 16-31 */ 492 spin_lock_irqsave(&lp->bank_lock, flags); 493 MACEBANK(1); 494 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 495 MACEBANK(0); 496 spin_unlock_irqrestore(&lp->bank_lock, flags); 497 break; 498 } 499 return data & 0xFF; 500} /* mace_read */ 501 502/* ---------------------------------------------------------------------------- 503mace_write 504 Writes to a MACE register. This is bank independent; however, 505 the caller must ensure that this call is not interruptable. We 506 are assuming that during normal operation, the MACE is always in 507 bank 0. 508---------------------------------------------------------------------------- */ 509static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, 510 int data) 511{ 512 unsigned long flags; 513 514 switch (reg >> 4) { 515 case 0: /* register 0-15 */ 516 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); 517 break; 518 case 1: /* register 16-31 */ 519 spin_lock_irqsave(&lp->bank_lock, flags); 520 MACEBANK(1); 521 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 522 MACEBANK(0); 523 spin_unlock_irqrestore(&lp->bank_lock, flags); 524 break; 525 } 526} /* mace_write */ 527 528/* ---------------------------------------------------------------------------- 529mace_init 530 Resets the MACE chip. 531---------------------------------------------------------------------------- */ 532static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr) 533{ 534 int i; 535 int ct = 0; 536 537 /* MACE Software reset */ 538 mace_write(lp, ioaddr, MACE_BIUCC, 1); 539 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) { 540 /* Wait for reset bit to be cleared automatically after <= 200ns */; 541 if(++ct > 500) 542 { 543 pr_err("reset failed, card removed?\n"); 544 return -1; 545 } 546 udelay(1); 547 } 548 mace_write(lp, ioaddr, MACE_BIUCC, 0); 549 550 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */ 551 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F); 552 553 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */ 554 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */ 555 556 /* 557 * Bit 2-1 PORTSEL[1-0] Port Select. 558 * 00 AUI/10Base-2 559 * 01 10Base-T 560 * 10 DAI Port (reserved in Am2150) 561 * 11 GPSI 562 * For this card, only the first two are valid. 563 * So, PLSCC should be set to 564 * 0x00 for 10Base-2 565 * 0x02 for 10Base-T 566 * Or just set ASEL in PHYCC below! 567 */ 568 switch (if_port) { 569 case 1: 570 mace_write(lp, ioaddr, MACE_PLSCC, 0x02); 571 break; 572 case 2: 573 mace_write(lp, ioaddr, MACE_PLSCC, 0x00); 574 break; 575 default: 576 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4); 577 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden, 578 and the MACE device will automatically select the operating media 579 interface port. */ 580 break; 581 } 582 583 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR); 584 /* Poll ADDRCHG bit */ 585 ct = 0; 586 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 587 { 588 if(++ ct > 500) 589 { 590 pr_err("ADDRCHG timeout, card removed?\n"); 591 return -1; 592 } 593 } 594 /* Set PADR register */ 595 for (i = 0; i < ETH_ALEN; i++) 596 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]); 597 598 /* MAC Configuration Control Register should be written last */ 599 /* Let set_multicast_list set this. */ 600 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */ 601 mace_write(lp, ioaddr, MACE_MACCC, 0x00); 602 return 0; 603} /* mace_init */ 604 605static int nmclan_config(struct pcmcia_device *link) 606{ 607 struct net_device *dev = link->priv; 608 mace_private *lp = netdev_priv(dev); 609 u8 *buf; 610 size_t len; 611 int i, ret; 612 unsigned int ioaddr; 613 614 dev_dbg(&link->dev, "nmclan_config\n"); 615 616 link->io_lines = 5; 617 ret = pcmcia_request_io(link); 618 if (ret) 619 goto failed; 620 ret = pcmcia_request_irq(link, mace_interrupt); 621 if (ret) 622 goto failed; 623 ret = pcmcia_enable_device(link); 624 if (ret) 625 goto failed; 626 627 dev->irq = link->irq; 628 dev->base_addr = link->resource[0]->start; 629 630 ioaddr = dev->base_addr; 631 632 /* Read the ethernet address from the CIS. */ 633 len = pcmcia_get_tuple(link, 0x80, &buf); 634 if (!buf || len < ETH_ALEN) { 635 kfree(buf); 636 goto failed; 637 } 638 memcpy(dev->dev_addr, buf, ETH_ALEN); 639 kfree(buf); 640 641 /* Verify configuration by reading the MACE ID. */ 642 { 643 char sig[2]; 644 645 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL); 646 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH); 647 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) { 648 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n", 649 sig[0], sig[1]); 650 } else { 651 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n", 652 sig[0], sig[1]); 653 goto failed; 654 } 655 } 656 657 if(mace_init(lp, ioaddr, dev->dev_addr) == -1) 658 goto failed; 659 660 /* The if_port symbol can be set when the module is loaded */ 661 if (if_port <= 2) 662 dev->if_port = if_port; 663 else 664 pr_notice("invalid if_port requested\n"); 665 666 SET_NETDEV_DEV(dev, &link->dev); 667 668 i = register_netdev(dev); 669 if (i != 0) { 670 pr_notice("register_netdev() failed\n"); 671 goto failed; 672 } 673 674 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n", 675 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr); 676 return 0; 677 678failed: 679 nmclan_release(link); 680 return -ENODEV; 681} /* nmclan_config */ 682 683static void nmclan_release(struct pcmcia_device *link) 684{ 685 dev_dbg(&link->dev, "nmclan_release\n"); 686 pcmcia_disable_device(link); 687} 688 689static int nmclan_suspend(struct pcmcia_device *link) 690{ 691 struct net_device *dev = link->priv; 692 693 if (link->open) 694 netif_device_detach(dev); 695 696 return 0; 697} 698 699static int nmclan_resume(struct pcmcia_device *link) 700{ 701 struct net_device *dev = link->priv; 702 703 if (link->open) { 704 nmclan_reset(dev); 705 netif_device_attach(dev); 706 } 707 708 return 0; 709} 710 711 712/* ---------------------------------------------------------------------------- 713nmclan_reset 714 Reset and restore all of the Xilinx and MACE registers. 715---------------------------------------------------------------------------- */ 716static void nmclan_reset(struct net_device *dev) 717{ 718 mace_private *lp = netdev_priv(dev); 719 720#if RESET_XILINX 721 struct pcmcia_device *link = &lp->link; 722 u8 OrigCorValue; 723 724 /* Save original COR value */ 725 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); 726 727 /* Reset Xilinx */ 728 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", 729 OrigCorValue); 730 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); 731 /* Need to wait for 20 ms for PCMCIA to finish reset. */ 732 733 /* Restore original COR configuration index */ 734 pcmcia_write_config_byte(link, CISREG_COR, 735 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); 736 /* Xilinx is now completely reset along with the MACE chip. */ 737 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 738 739#endif /* #if RESET_XILINX */ 740 741 /* Xilinx is now completely reset along with the MACE chip. */ 742 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 743 744 /* Reinitialize the MACE chip for operation. */ 745 mace_init(lp, dev->base_addr, dev->dev_addr); 746 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); 747 748 /* Restore the multicast list and enable TX and RX. */ 749 restore_multicast_list(dev); 750} /* nmclan_reset */ 751 752/* ---------------------------------------------------------------------------- 753mace_config 754 [Someone tell me what this is supposed to do? Is if_port a defined 755 standard? If so, there should be defines to indicate 1=10Base-T, 756 2=10Base-2, etc. including limited automatic detection.] 757---------------------------------------------------------------------------- */ 758static int mace_config(struct net_device *dev, struct ifmap *map) 759{ 760 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) { 761 if (map->port <= 2) { 762 dev->if_port = map->port; 763 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]); 764 } else 765 return -EINVAL; 766 } 767 return 0; 768} /* mace_config */ 769 770/* ---------------------------------------------------------------------------- 771mace_open 772 Open device driver. 773---------------------------------------------------------------------------- */ 774static int mace_open(struct net_device *dev) 775{ 776 unsigned int ioaddr = dev->base_addr; 777 mace_private *lp = netdev_priv(dev); 778 struct pcmcia_device *link = lp->p_dev; 779 780 if (!pcmcia_dev_present(link)) 781 return -ENODEV; 782 783 link->open++; 784 785 MACEBANK(0); 786 787 netif_start_queue(dev); 788 nmclan_reset(dev); 789 790 return 0; /* Always succeed */ 791} /* mace_open */ 792 793/* ---------------------------------------------------------------------------- 794mace_close 795 Closes device driver. 796---------------------------------------------------------------------------- */ 797static int mace_close(struct net_device *dev) 798{ 799 unsigned int ioaddr = dev->base_addr; 800 mace_private *lp = netdev_priv(dev); 801 struct pcmcia_device *link = lp->p_dev; 802 803 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name); 804 805 /* Mask off all interrupts from the MACE chip. */ 806 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); 807 808 link->open--; 809 netif_stop_queue(dev); 810 811 return 0; 812} /* mace_close */ 813 814static void netdev_get_drvinfo(struct net_device *dev, 815 struct ethtool_drvinfo *info) 816{ 817 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 818 snprintf(info->bus_info, sizeof(info->bus_info), 819 "PCMCIA 0x%lx", dev->base_addr); 820} 821 822static const struct ethtool_ops netdev_ethtool_ops = { 823 .get_drvinfo = netdev_get_drvinfo, 824}; 825 826/* ---------------------------------------------------------------------------- 827mace_start_xmit 828 This routine begins the packet transmit function. When completed, 829 it will generate a transmit interrupt. 830 831 According to /usr/src/linux/net/inet/dev.c, if _start_xmit 832 returns 0, the "packet is now solely the responsibility of the 833 driver." If _start_xmit returns non-zero, the "transmission 834 failed, put skb back into a list." 835---------------------------------------------------------------------------- */ 836 837static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue) 838{ 839 mace_private *lp = netdev_priv(dev); 840 struct pcmcia_device *link = lp->p_dev; 841 842 netdev_notice(dev, "transmit timed out -- "); 843#if RESET_ON_TIMEOUT 844 pr_cont("resetting card\n"); 845 pcmcia_reset_card(link->socket); 846#else /* #if RESET_ON_TIMEOUT */ 847 pr_cont("NOT resetting card\n"); 848#endif /* #if RESET_ON_TIMEOUT */ 849 netif_trans_update(dev); /* prevent tx timeout */ 850 netif_wake_queue(dev); 851} 852 853static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 854 struct net_device *dev) 855{ 856 mace_private *lp = netdev_priv(dev); 857 unsigned int ioaddr = dev->base_addr; 858 859 netif_stop_queue(dev); 860 861 pr_debug("%s: mace_start_xmit(length = %ld) called.\n", 862 dev->name, (long)skb->len); 863 864#if (!TX_INTERRUPTABLE) 865 /* Disable MACE TX interrupts. */ 866 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT, 867 ioaddr + AM2150_MACE_BASE + MACE_IMR); 868 lp->tx_irq_disabled=1; 869#endif /* #if (!TX_INTERRUPTABLE) */ 870 871 { 872 /* This block must not be interrupted by another transmit request! 873 mace_tx_timeout will take care of timer-based retransmissions from 874 the upper layers. The interrupt handler is guaranteed never to 875 service a transmit interrupt while we are in here. 876 */ 877 878 dev->stats.tx_bytes += skb->len; 879 lp->tx_free_frames--; 880 881 /* WARNING: Write the _exact_ number of bytes written in the header! */ 882 /* Put out the word header [must be an outw()] . . . */ 883 outw(skb->len, ioaddr + AM2150_XMT); 884 /* . . . and the packet [may be any combination of outw() and outb()] */ 885 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1); 886 if (skb->len & 1) { 887 /* Odd byte transfer */ 888 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT); 889 } 890 891#if MULTI_TX 892 if (lp->tx_free_frames > 0) 893 netif_start_queue(dev); 894#endif /* #if MULTI_TX */ 895 } 896 897#if (!TX_INTERRUPTABLE) 898 /* Re-enable MACE TX interrupts. */ 899 lp->tx_irq_disabled=0; 900 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); 901#endif /* #if (!TX_INTERRUPTABLE) */ 902 903 dev_kfree_skb(skb); 904 905 return NETDEV_TX_OK; 906} /* mace_start_xmit */ 907 908/* ---------------------------------------------------------------------------- 909mace_interrupt 910 The interrupt handler. 911---------------------------------------------------------------------------- */ 912static irqreturn_t mace_interrupt(int irq, void *dev_id) 913{ 914 struct net_device *dev = (struct net_device *) dev_id; 915 mace_private *lp = netdev_priv(dev); 916 unsigned int ioaddr; 917 int status; 918 int IntrCnt = MACE_MAX_IR_ITERATIONS; 919 920 if (dev == NULL) { 921 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n", 922 irq); 923 return IRQ_NONE; 924 } 925 926 ioaddr = dev->base_addr; 927 928 if (lp->tx_irq_disabled) { 929 const char *msg; 930 if (lp->tx_irq_disabled) 931 msg = "Interrupt with tx_irq_disabled"; 932 else 933 msg = "Re-entering the interrupt handler"; 934 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n", 935 msg, 936 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), 937 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)); 938 /* WARNING: MACE_IR has been read! */ 939 return IRQ_NONE; 940 } 941 942 if (!netif_device_present(dev)) { 943 netdev_dbg(dev, "interrupt from dead card\n"); 944 return IRQ_NONE; 945 } 946 947 do { 948 /* WARNING: MACE_IR is a READ/CLEAR port! */ 949 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); 950 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS) 951 return IRQ_NONE; 952 953 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status); 954 955 if (status & MACE_IR_RCVINT) { 956 mace_rx(dev, MACE_MAX_RX_ITERATIONS); 957 } 958 959 if (status & MACE_IR_XMTINT) { 960 unsigned char fifofc; 961 unsigned char xmtrc; 962 unsigned char xmtfs; 963 964 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); 965 if ((fifofc & MACE_FIFOFC_XMTFC)==0) { 966 dev->stats.tx_errors++; 967 outb(0xFF, ioaddr + AM2150_XMT_SKIP); 968 } 969 970 /* Transmit Retry Count (XMTRC, reg 4) */ 971 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); 972 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++; 973 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC); 974 975 if ( 976 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & 977 MACE_XMTFS_XMTSV /* Transmit Status Valid */ 978 ) { 979 lp->mace_stats.xmtsv++; 980 981 if (xmtfs & ~MACE_XMTFS_XMTSV) { 982 if (xmtfs & MACE_XMTFS_UFLO) { 983 /* Underflow. Indicates that the Transmit FIFO emptied before 984 the end of frame was reached. */ 985 lp->mace_stats.uflo++; 986 } 987 if (xmtfs & MACE_XMTFS_LCOL) { 988 /* Late Collision */ 989 lp->mace_stats.lcol++; 990 } 991 if (xmtfs & MACE_XMTFS_MORE) { 992 /* MORE than one retry was needed */ 993 lp->mace_stats.more++; 994 } 995 if (xmtfs & MACE_XMTFS_ONE) { 996 /* Exactly ONE retry occurred */ 997 lp->mace_stats.one++; 998 } 999 if (xmtfs & MACE_XMTFS_DEFER) { 1000 /* Transmission was defered */ 1001 lp->mace_stats.defer++; 1002 } 1003 if (xmtfs & MACE_XMTFS_LCAR) { 1004 /* Loss of carrier */ 1005 lp->mace_stats.lcar++; 1006 } 1007 if (xmtfs & MACE_XMTFS_RTRY) { 1008 /* Retry error: transmit aborted after 16 attempts */ 1009 lp->mace_stats.rtry++; 1010 } 1011 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */ 1012 1013 } /* if (xmtfs & MACE_XMTFS_XMTSV) */ 1014 1015 dev->stats.tx_packets++; 1016 lp->tx_free_frames++; 1017 netif_wake_queue(dev); 1018 } /* if (status & MACE_IR_XMTINT) */ 1019 1020 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) { 1021 if (status & MACE_IR_JAB) { 1022 /* Jabber Error. Excessive transmit duration (20-150ms). */ 1023 lp->mace_stats.jab++; 1024 } 1025 if (status & MACE_IR_BABL) { 1026 /* Babble Error. >1518 bytes transmitted. */ 1027 lp->mace_stats.babl++; 1028 } 1029 if (status & MACE_IR_CERR) { 1030 /* Collision Error. CERR indicates the absence of the 1031 Signal Quality Error Test message after a packet 1032 transmission. */ 1033 lp->mace_stats.cerr++; 1034 } 1035 if (status & MACE_IR_RCVCCO) { 1036 /* Receive Collision Count Overflow; */ 1037 lp->mace_stats.rcvcco++; 1038 } 1039 if (status & MACE_IR_RNTPCO) { 1040 /* Runt Packet Count Overflow */ 1041 lp->mace_stats.rntpco++; 1042 } 1043 if (status & MACE_IR_MPCO) { 1044 /* Missed Packet Count Overflow */ 1045 lp->mace_stats.mpco++; 1046 } 1047 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */ 1048 1049 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt)); 1050 1051 return IRQ_HANDLED; 1052} /* mace_interrupt */ 1053 1054/* ---------------------------------------------------------------------------- 1055mace_rx 1056 Receives packets. 1057---------------------------------------------------------------------------- */ 1058static int mace_rx(struct net_device *dev, unsigned char RxCnt) 1059{ 1060 mace_private *lp = netdev_priv(dev); 1061 unsigned int ioaddr = dev->base_addr; 1062 unsigned char rx_framecnt; 1063 unsigned short rx_status; 1064 1065 while ( 1066 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) && 1067 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */ 1068 (RxCnt--) 1069 ) { 1070 rx_status = inw(ioaddr + AM2150_RCV); 1071 1072 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status" 1073 " 0x%X.\n", dev->name, rx_framecnt, rx_status); 1074 1075 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */ 1076 dev->stats.rx_errors++; 1077 if (rx_status & MACE_RCVFS_OFLO) { 1078 lp->mace_stats.oflo++; 1079 } 1080 if (rx_status & MACE_RCVFS_CLSN) { 1081 lp->mace_stats.clsn++; 1082 } 1083 if (rx_status & MACE_RCVFS_FRAM) { 1084 lp->mace_stats.fram++; 1085 } 1086 if (rx_status & MACE_RCVFS_FCS) { 1087 lp->mace_stats.fcs++; 1088 } 1089 } else { 1090 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4; 1091 /* Auto Strip is off, always subtract 4 */ 1092 struct sk_buff *skb; 1093 1094 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV); 1095 /* runt packet count */ 1096 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV); 1097 /* rcv collision count */ 1098 1099 pr_debug(" receiving packet size 0x%X rx_status" 1100 " 0x%X.\n", pkt_len, rx_status); 1101 1102 skb = netdev_alloc_skb(dev, pkt_len + 2); 1103 1104 if (skb != NULL) { 1105 skb_reserve(skb, 2); 1106 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1); 1107 if (pkt_len & 1) 1108 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV); 1109 skb->protocol = eth_type_trans(skb, dev); 1110 1111 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */ 1112 1113 dev->stats.rx_packets++; 1114 dev->stats.rx_bytes += pkt_len; 1115 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1116 continue; 1117 } else { 1118 pr_debug("%s: couldn't allocate a sk_buff of size" 1119 " %d.\n", dev->name, pkt_len); 1120 dev->stats.rx_dropped++; 1121 } 1122 } 1123 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1124 } /* while */ 1125 1126 return 0; 1127} /* mace_rx */ 1128 1129/* ---------------------------------------------------------------------------- 1130pr_linux_stats 1131---------------------------------------------------------------------------- */ 1132static void pr_linux_stats(struct net_device_stats *pstats) 1133{ 1134 pr_debug("pr_linux_stats\n"); 1135 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n", 1136 (long)pstats->rx_packets, (long)pstats->tx_packets); 1137 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n", 1138 (long)pstats->rx_errors, (long)pstats->tx_errors); 1139 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n", 1140 (long)pstats->rx_dropped, (long)pstats->tx_dropped); 1141 pr_debug(" multicast=%-7ld collisions=%ld\n", 1142 (long)pstats->multicast, (long)pstats->collisions); 1143 1144 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n", 1145 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors); 1146 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n", 1147 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors); 1148 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n", 1149 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors); 1150 1151 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n", 1152 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors); 1153 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n", 1154 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors); 1155 pr_debug(" tx_window_errors=%ld\n", 1156 (long)pstats->tx_window_errors); 1157} /* pr_linux_stats */ 1158 1159/* ---------------------------------------------------------------------------- 1160pr_mace_stats 1161---------------------------------------------------------------------------- */ 1162static void pr_mace_stats(mace_statistics *pstats) 1163{ 1164 pr_debug("pr_mace_stats\n"); 1165 1166 pr_debug(" xmtsv=%-7d uflo=%d\n", 1167 pstats->xmtsv, pstats->uflo); 1168 pr_debug(" lcol=%-7d more=%d\n", 1169 pstats->lcol, pstats->more); 1170 pr_debug(" one=%-7d defer=%d\n", 1171 pstats->one, pstats->defer); 1172 pr_debug(" lcar=%-7d rtry=%d\n", 1173 pstats->lcar, pstats->rtry); 1174 1175 /* MACE_XMTRC */ 1176 pr_debug(" exdef=%-7d xmtrc=%d\n", 1177 pstats->exdef, pstats->xmtrc); 1178 1179 /* RFS1--Receive Status (RCVSTS) */ 1180 pr_debug(" oflo=%-7d clsn=%d\n", 1181 pstats->oflo, pstats->clsn); 1182 pr_debug(" fram=%-7d fcs=%d\n", 1183 pstats->fram, pstats->fcs); 1184 1185 /* RFS2--Runt Packet Count (RNTPC) */ 1186 /* RFS3--Receive Collision Count (RCVCC) */ 1187 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n", 1188 pstats->rfs_rntpc, pstats->rfs_rcvcc); 1189 1190 /* MACE_IR */ 1191 pr_debug(" jab=%-7d babl=%d\n", 1192 pstats->jab, pstats->babl); 1193 pr_debug(" cerr=%-7d rcvcco=%d\n", 1194 pstats->cerr, pstats->rcvcco); 1195 pr_debug(" rntpco=%-7d mpco=%d\n", 1196 pstats->rntpco, pstats->mpco); 1197 1198 /* MACE_MPC */ 1199 pr_debug(" mpc=%d\n", pstats->mpc); 1200 1201 /* MACE_RNTPC */ 1202 pr_debug(" rntpc=%d\n", pstats->rntpc); 1203 1204 /* MACE_RCVCC */ 1205 pr_debug(" rcvcc=%d\n", pstats->rcvcc); 1206 1207} /* pr_mace_stats */ 1208 1209/* ---------------------------------------------------------------------------- 1210update_stats 1211 Update statistics. We change to register window 1, so this 1212 should be run single-threaded if the device is active. This is 1213 expected to be a rare operation, and it's simpler for the rest 1214 of the driver to assume that window 0 is always valid rather 1215 than use a special window-state variable. 1216 1217 oflo & uflo should _never_ occur since it would mean the Xilinx 1218 was not able to transfer data between the MACE FIFO and the 1219 card's SRAM fast enough. If this happens, something is 1220 seriously wrong with the hardware. 1221---------------------------------------------------------------------------- */ 1222static void update_stats(unsigned int ioaddr, struct net_device *dev) 1223{ 1224 mace_private *lp = netdev_priv(dev); 1225 1226 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC); 1227 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC); 1228 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); 1229 /* At this point, mace_stats is fully updated for this call. 1230 We may now update the netdev stats. */ 1231 1232 /* The MACE has no equivalent for netdev stats field which are commented 1233 out. */ 1234 1235 /* dev->stats.multicast; */ 1236 dev->stats.collisions = 1237 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc; 1238 /* Collision: The MACE may retry sending a packet 15 times 1239 before giving up. The retry count is in XMTRC. 1240 Does each retry constitute a collision? 1241 If so, why doesn't the RCVCC record these collisions? */ 1242 1243 /* detailed rx_errors: */ 1244 dev->stats.rx_length_errors = 1245 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc; 1246 /* dev->stats.rx_over_errors */ 1247 dev->stats.rx_crc_errors = lp->mace_stats.fcs; 1248 dev->stats.rx_frame_errors = lp->mace_stats.fram; 1249 dev->stats.rx_fifo_errors = lp->mace_stats.oflo; 1250 dev->stats.rx_missed_errors = 1251 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; 1252 1253 /* detailed tx_errors */ 1254 dev->stats.tx_aborted_errors = lp->mace_stats.rtry; 1255 dev->stats.tx_carrier_errors = lp->mace_stats.lcar; 1256 /* LCAR usually results from bad cabling. */ 1257 dev->stats.tx_fifo_errors = lp->mace_stats.uflo; 1258 dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr; 1259 /* dev->stats.tx_window_errors; */ 1260} /* update_stats */ 1261 1262/* ---------------------------------------------------------------------------- 1263mace_get_stats 1264 Gathers ethernet statistics from the MACE chip. 1265---------------------------------------------------------------------------- */ 1266static struct net_device_stats *mace_get_stats(struct net_device *dev) 1267{ 1268 mace_private *lp = netdev_priv(dev); 1269 1270 update_stats(dev->base_addr, dev); 1271 1272 pr_debug("%s: updating the statistics.\n", dev->name); 1273 pr_linux_stats(&dev->stats); 1274 pr_mace_stats(&lp->mace_stats); 1275 1276 return &dev->stats; 1277} /* net_device_stats */ 1278 1279/* ---------------------------------------------------------------------------- 1280updateCRC 1281 Modified from Am79C90 data sheet. 1282---------------------------------------------------------------------------- */ 1283 1284#ifdef BROKEN_MULTICAST 1285 1286static void updateCRC(int *CRC, int bit) 1287{ 1288 static const int poly[]={ 1289 1,1,1,0, 1,1,0,1, 1290 1,0,1,1, 1,0,0,0, 1291 1,0,0,0, 0,0,1,1, 1292 0,0,1,0, 0,0,0,0 1293 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the 1294 CRC generator polynomial. */ 1295 1296 int j; 1297 1298 /* shift CRC and control bit (CRC[32]) */ 1299 for (j = 32; j > 0; j--) 1300 CRC[j] = CRC[j-1]; 1301 CRC[0] = 0; 1302 1303 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */ 1304 if (bit ^ CRC[32]) 1305 for (j = 0; j < 32; j++) 1306 CRC[j] ^= poly[j]; 1307} /* updateCRC */ 1308 1309/* ---------------------------------------------------------------------------- 1310BuildLAF 1311 Build logical address filter. 1312 Modified from Am79C90 data sheet. 1313 1314Input 1315 ladrf: logical address filter (contents initialized to 0) 1316 adr: ethernet address 1317---------------------------------------------------------------------------- */ 1318static void BuildLAF(int *ladrf, int *adr) 1319{ 1320 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ 1321 1322 int i, byte; /* temporary array indices */ 1323 int hashcode; /* the output object */ 1324 1325 CRC[32]=0; 1326 1327 for (byte = 0; byte < 6; byte++) 1328 for (i = 0; i < 8; i++) 1329 updateCRC(CRC, (adr[byte] >> i) & 1); 1330 1331 hashcode = 0; 1332 for (i = 0; i < 6; i++) 1333 hashcode = (hashcode << 1) + CRC[i]; 1334 1335 byte = hashcode >> 3; 1336 ladrf[byte] |= (1 << (hashcode & 7)); 1337 1338#ifdef PCMCIA_DEBUG 1339 if (0) 1340 printk(KERN_DEBUG " adr =%pM\n", adr); 1341 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode); 1342 for (i = 0; i < 8; i++) 1343 pr_cont(" %02X", ladrf[i]); 1344 pr_cont("\n"); 1345#endif 1346} /* BuildLAF */ 1347 1348/* ---------------------------------------------------------------------------- 1349restore_multicast_list 1350 Restores the multicast filter for MACE chip to the last 1351 set_multicast_list() call. 1352 1353Input 1354 multicast_num_addrs 1355 multicast_ladrf[] 1356---------------------------------------------------------------------------- */ 1357static void restore_multicast_list(struct net_device *dev) 1358{ 1359 mace_private *lp = netdev_priv(dev); 1360 int num_addrs = lp->multicast_num_addrs; 1361 int *ladrf = lp->multicast_ladrf; 1362 unsigned int ioaddr = dev->base_addr; 1363 int i; 1364 1365 pr_debug("%s: restoring Rx mode to %d addresses.\n", 1366 dev->name, num_addrs); 1367 1368 if (num_addrs > 0) { 1369 1370 pr_debug("Attempt to restore multicast list detected.\n"); 1371 1372 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR); 1373 /* Poll ADDRCHG bit */ 1374 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 1375 ; 1376 /* Set LADRF register */ 1377 for (i = 0; i < MACE_LADRF_LEN; i++) 1378 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]); 1379 1380 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL); 1381 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1382 1383 } else if (num_addrs < 0) { 1384 1385 /* Promiscuous mode: receive all packets */ 1386 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1387 mace_write(lp, ioaddr, MACE_MACCC, 1388 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1389 ); 1390 1391 } else { 1392 1393 /* Normal mode */ 1394 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1395 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1396 1397 } 1398} /* restore_multicast_list */ 1399 1400/* ---------------------------------------------------------------------------- 1401set_multicast_list 1402 Set or clear the multicast filter for this adaptor. 1403 1404Input 1405 num_addrs == -1 Promiscuous mode, receive all packets 1406 num_addrs == 0 Normal mode, clear multicast list 1407 num_addrs > 0 Multicast mode, receive normal and MC packets, and do 1408 best-effort filtering. 1409Output 1410 multicast_num_addrs 1411 multicast_ladrf[] 1412---------------------------------------------------------------------------- */ 1413 1414static void set_multicast_list(struct net_device *dev) 1415{ 1416 mace_private *lp = netdev_priv(dev); 1417 int adr[ETH_ALEN] = {0}; /* Ethernet address */ 1418 struct netdev_hw_addr *ha; 1419 1420#ifdef PCMCIA_DEBUG 1421 { 1422 static int old; 1423 if (netdev_mc_count(dev) != old) { 1424 old = netdev_mc_count(dev); 1425 pr_debug("%s: setting Rx mode to %d addresses.\n", 1426 dev->name, old); 1427 } 1428 } 1429#endif 1430 1431 /* Set multicast_num_addrs. */ 1432 lp->multicast_num_addrs = netdev_mc_count(dev); 1433 1434 /* Set multicast_ladrf. */ 1435 if (num_addrs > 0) { 1436 /* Calculate multicast logical address filter */ 1437 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN); 1438 netdev_for_each_mc_addr(ha, dev) { 1439 memcpy(adr, ha->addr, ETH_ALEN); 1440 BuildLAF(lp->multicast_ladrf, adr); 1441 } 1442 } 1443 1444 restore_multicast_list(dev); 1445 1446} /* set_multicast_list */ 1447 1448#endif /* BROKEN_MULTICAST */ 1449 1450static void restore_multicast_list(struct net_device *dev) 1451{ 1452 unsigned int ioaddr = dev->base_addr; 1453 mace_private *lp = netdev_priv(dev); 1454 1455 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name, 1456 lp->multicast_num_addrs); 1457 1458 if (dev->flags & IFF_PROMISC) { 1459 /* Promiscuous mode: receive all packets */ 1460 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1461 mace_write(lp, ioaddr, MACE_MACCC, 1462 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1463 ); 1464 } else { 1465 /* Normal mode */ 1466 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1467 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1468 } 1469} /* restore_multicast_list */ 1470 1471static void set_multicast_list(struct net_device *dev) 1472{ 1473 mace_private *lp = netdev_priv(dev); 1474 1475#ifdef PCMCIA_DEBUG 1476 { 1477 static int old; 1478 if (netdev_mc_count(dev) != old) { 1479 old = netdev_mc_count(dev); 1480 pr_debug("%s: setting Rx mode to %d addresses.\n", 1481 dev->name, old); 1482 } 1483 } 1484#endif 1485 1486 lp->multicast_num_addrs = netdev_mc_count(dev); 1487 restore_multicast_list(dev); 1488 1489} /* set_multicast_list */ 1490 1491static const struct pcmcia_device_id nmclan_ids[] = { 1492 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941), 1493 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf), 1494 PCMCIA_DEVICE_NULL, 1495}; 1496MODULE_DEVICE_TABLE(pcmcia, nmclan_ids); 1497 1498static struct pcmcia_driver nmclan_cs_driver = { 1499 .owner = THIS_MODULE, 1500 .name = "nmclan_cs", 1501 .probe = nmclan_probe, 1502 .remove = nmclan_detach, 1503 .id_table = nmclan_ids, 1504 .suspend = nmclan_suspend, 1505 .resume = nmclan_resume, 1506}; 1507module_pcmcia_driver(nmclan_cs_driver); 1508