1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef __QCA8K_H 9#define __QCA8K_H 10 11#include <linux/delay.h> 12#include <linux/regmap.h> 13#include <linux/gpio.h> 14 15#define QCA8K_NUM_PORTS 7 16#define QCA8K_MAX_MTU 9000 17 18#define PHY_ID_QCA8337 0x004dd036 19#define QCA8K_ID_QCA8337 0x13 20 21#define QCA8K_NUM_FDB_RECORDS 2048 22 23#define QCA8K_CPU_PORT 0 24 25#define QCA8K_PORT_VID_DEF 1 26 27/* Global control registers */ 28#define QCA8K_REG_MASK_CTRL 0x000 29#define QCA8K_MASK_CTRL_ID_M 0xff 30#define QCA8K_MASK_CTRL_ID_S 8 31#define QCA8K_REG_PORT0_PAD_CTRL 0x004 32#define QCA8K_REG_PORT5_PAD_CTRL 0x008 33#define QCA8K_REG_PORT6_PAD_CTRL 0x00c 34#define QCA8K_PORT_PAD_RGMII_EN BIT(26) 35#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ 36 ((0x8 + (x & 0x3)) << 22) 37#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ 38 ((0x10 + (x & 0x3)) << 20) 39#define QCA8K_MAX_DELAY 3 40#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) 41#define QCA8K_PORT_PAD_SGMII_EN BIT(7) 42#define QCA8K_REG_PWS 0x010 43#define QCA8K_PWS_SERDES_AEN_DIS BIT(7) 44#define QCA8K_REG_MODULE_EN 0x030 45#define QCA8K_MODULE_EN_MIB BIT(0) 46#define QCA8K_REG_MIB 0x034 47#define QCA8K_MIB_FLUSH BIT(24) 48#define QCA8K_MIB_CPU_KEEP BIT(20) 49#define QCA8K_MIB_BUSY BIT(17) 50#define QCA8K_MDIO_MASTER_CTRL 0x3c 51#define QCA8K_MDIO_MASTER_BUSY BIT(31) 52#define QCA8K_MDIO_MASTER_EN BIT(30) 53#define QCA8K_MDIO_MASTER_READ BIT(27) 54#define QCA8K_MDIO_MASTER_WRITE 0 55#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) 56#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21) 57#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16) 58#define QCA8K_MDIO_MASTER_DATA(x) (x) 59#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0) 60#define QCA8K_MDIO_MASTER_MAX_PORTS 5 61#define QCA8K_MDIO_MASTER_MAX_REG 32 62#define QCA8K_GOL_MAC_ADDR0 0x60 63#define QCA8K_GOL_MAC_ADDR1 0x64 64#define QCA8K_MAX_FRAME_SIZE 0x78 65#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 66#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) 67#define QCA8K_PORT_STATUS_SPEED_10 0 68#define QCA8K_PORT_STATUS_SPEED_100 0x1 69#define QCA8K_PORT_STATUS_SPEED_1000 0x2 70#define QCA8K_PORT_STATUS_TXMAC BIT(2) 71#define QCA8K_PORT_STATUS_RXMAC BIT(3) 72#define QCA8K_PORT_STATUS_TXFLOW BIT(4) 73#define QCA8K_PORT_STATUS_RXFLOW BIT(5) 74#define QCA8K_PORT_STATUS_DUPLEX BIT(6) 75#define QCA8K_PORT_STATUS_LINK_UP BIT(8) 76#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9) 77#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10) 78#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12) 79#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) 80#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2) 81#define QCA8K_PORT_HDR_CTRL_RX_S 2 82#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0) 83#define QCA8K_PORT_HDR_CTRL_TX_S 0 84#define QCA8K_PORT_HDR_CTRL_ALL 2 85#define QCA8K_PORT_HDR_CTRL_MGMT 1 86#define QCA8K_PORT_HDR_CTRL_NONE 0 87#define QCA8K_REG_SGMII_CTRL 0x0e0 88#define QCA8K_SGMII_EN_PLL BIT(1) 89#define QCA8K_SGMII_EN_RX BIT(2) 90#define QCA8K_SGMII_EN_TX BIT(3) 91#define QCA8K_SGMII_EN_SD BIT(4) 92#define QCA8K_SGMII_CLK125M_DELAY BIT(7) 93#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23)) 94#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22) 95#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) 96#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) 97 98/* EEE control registers */ 99#define QCA8K_REG_EEE_CTRL 0x100 100#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) 101 102/* ACL registers */ 103#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) 104#define QCA8K_PORT_VLAN_CVID(x) (x << 16) 105#define QCA8K_PORT_VLAN_SVID(x) x 106#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) 107#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470 108#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474 109 110/* Lookup registers */ 111#define QCA8K_REG_ATU_DATA0 0x600 112#define QCA8K_ATU_ADDR2_S 24 113#define QCA8K_ATU_ADDR3_S 16 114#define QCA8K_ATU_ADDR4_S 8 115#define QCA8K_REG_ATU_DATA1 0x604 116#define QCA8K_ATU_PORT_M 0x7f 117#define QCA8K_ATU_PORT_S 16 118#define QCA8K_ATU_ADDR0_S 8 119#define QCA8K_REG_ATU_DATA2 0x608 120#define QCA8K_ATU_VID_M 0xfff 121#define QCA8K_ATU_VID_S 8 122#define QCA8K_ATU_STATUS_M 0xf 123#define QCA8K_ATU_STATUS_STATIC 0xf 124#define QCA8K_REG_ATU_FUNC 0x60c 125#define QCA8K_ATU_FUNC_BUSY BIT(31) 126#define QCA8K_ATU_FUNC_PORT_EN BIT(14) 127#define QCA8K_ATU_FUNC_MULTI_EN BIT(13) 128#define QCA8K_ATU_FUNC_FULL BIT(12) 129#define QCA8K_ATU_FUNC_PORT_M 0xf 130#define QCA8K_ATU_FUNC_PORT_S 8 131#define QCA8K_REG_VTU_FUNC0 0x610 132#define QCA8K_VTU_FUNC0_VALID BIT(20) 133#define QCA8K_VTU_FUNC0_IVL_EN BIT(19) 134#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 135#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3 136#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0 137#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1 138#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2 139#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3 140#define QCA8K_REG_VTU_FUNC1 0x614 141#define QCA8K_VTU_FUNC1_BUSY BIT(31) 142#define QCA8K_VTU_FUNC1_VID_S 16 143#define QCA8K_VTU_FUNC1_FULL BIT(4) 144#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 145#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) 146#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 147#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24 148#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16 149#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8 150#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0 151#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) 152#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0) 153#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8) 154#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8) 155#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8) 156#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8) 157#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8) 158#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16) 159#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16) 160#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16) 161#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16) 162#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16) 163#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16) 164#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) 165#define QCA8K_PORT_LOOKUP_LEARN BIT(20) 166 167/* Pkt edit registers */ 168#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) 169 170/* L3 registers */ 171#define QCA8K_HROUTER_CONTROL 0xe00 172#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16) 173#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16 174#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1 175#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08 176#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c 177#define QCA8K_HNAT_CONTROL 0xe38 178 179/* MIB registers */ 180#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100) 181 182/* QCA specific MII registers */ 183#define MII_ATH_MMD_ADDR 0x0d 184#define MII_ATH_MMD_DATA 0x0e 185 186enum { 187 QCA8K_PORT_SPEED_10M = 0, 188 QCA8K_PORT_SPEED_100M = 1, 189 QCA8K_PORT_SPEED_1000M = 2, 190 QCA8K_PORT_SPEED_ERR = 3, 191}; 192 193enum qca8k_fdb_cmd { 194 QCA8K_FDB_FLUSH = 1, 195 QCA8K_FDB_LOAD = 2, 196 QCA8K_FDB_PURGE = 3, 197 QCA8K_FDB_NEXT = 6, 198 QCA8K_FDB_SEARCH = 7, 199}; 200 201enum qca8k_vlan_cmd { 202 QCA8K_VLAN_FLUSH = 1, 203 QCA8K_VLAN_LOAD = 2, 204 QCA8K_VLAN_PURGE = 3, 205 QCA8K_VLAN_REMOVE_PORT = 4, 206 QCA8K_VLAN_NEXT = 5, 207 QCA8K_VLAN_READ = 6, 208}; 209 210struct ar8xxx_port_status { 211 int enabled; 212}; 213 214struct qca8k_priv { 215 struct regmap *regmap; 216 struct mii_bus *bus; 217 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; 218 struct dsa_switch *ds; 219 struct mutex reg_mutex; 220 struct device *dev; 221 struct dsa_switch_ops ops; 222 struct gpio_desc *reset_gpio; 223 unsigned int port_mtu[QCA8K_NUM_PORTS]; 224}; 225 226struct qca8k_mib_desc { 227 unsigned int size; 228 unsigned int offset; 229 const char *name; 230}; 231 232struct qca8k_fdb { 233 u16 vid; 234 u8 port_mask; 235 u8 aging; 236 u8 mac[6]; 237}; 238 239#endif /* __QCA8K_H */ 240