1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright 2017 Microsemi Corporation
3 * Copyright 2018-2019 NXP Semiconductors
4 */
5#include <linux/fsl/enetc_mdio.h>
6#include <soc/mscc/ocelot_qsys.h>
7#include <soc/mscc/ocelot_vcap.h>
8#include <soc/mscc/ocelot_ptp.h>
9#include <soc/mscc/ocelot_sys.h>
10#include <soc/mscc/ocelot.h>
11#include <linux/packing.h>
12#include <linux/pcs-lynx.h>
13#include <net/pkt_sched.h>
14#include <linux/iopoll.h>
15#include <linux/mdio.h>
16#include <linux/pci.h>
17#include "felix.h"
18
19#define VSC9959_TAS_GCL_ENTRY_MAX	63
20
21static const u32 vsc9959_ana_regmap[] = {
22	REG(ANA_ADVLEARN,			0x0089a0),
23	REG(ANA_VLANMASK,			0x0089a4),
24	REG_RESERVED(ANA_PORT_B_DOMAIN),
25	REG(ANA_ANAGEFIL,			0x0089ac),
26	REG(ANA_ANEVENTS,			0x0089b0),
27	REG(ANA_STORMLIMIT_BURST,		0x0089b4),
28	REG(ANA_STORMLIMIT_CFG,			0x0089b8),
29	REG(ANA_ISOLATED_PORTS,			0x0089c8),
30	REG(ANA_COMMUNITY_PORTS,		0x0089cc),
31	REG(ANA_AUTOAGE,			0x0089d0),
32	REG(ANA_MACTOPTIONS,			0x0089d4),
33	REG(ANA_LEARNDISC,			0x0089d8),
34	REG(ANA_AGENCTRL,			0x0089dc),
35	REG(ANA_MIRRORPORTS,			0x0089e0),
36	REG(ANA_EMIRRORPORTS,			0x0089e4),
37	REG(ANA_FLOODING,			0x0089e8),
38	REG(ANA_FLOODING_IPMC,			0x008a08),
39	REG(ANA_SFLOW_CFG,			0x008a0c),
40	REG(ANA_PORT_MODE,			0x008a28),
41	REG(ANA_CUT_THRU_CFG,			0x008a48),
42	REG(ANA_PGID_PGID,			0x008400),
43	REG(ANA_TABLES_ANMOVED,			0x007f1c),
44	REG(ANA_TABLES_MACHDATA,		0x007f20),
45	REG(ANA_TABLES_MACLDATA,		0x007f24),
46	REG(ANA_TABLES_STREAMDATA,		0x007f28),
47	REG(ANA_TABLES_MACACCESS,		0x007f2c),
48	REG(ANA_TABLES_MACTINDX,		0x007f30),
49	REG(ANA_TABLES_VLANACCESS,		0x007f34),
50	REG(ANA_TABLES_VLANTIDX,		0x007f38),
51	REG(ANA_TABLES_ISDXACCESS,		0x007f3c),
52	REG(ANA_TABLES_ISDXTIDX,		0x007f40),
53	REG(ANA_TABLES_ENTRYLIM,		0x007f00),
54	REG(ANA_TABLES_PTP_ID_HIGH,		0x007f44),
55	REG(ANA_TABLES_PTP_ID_LOW,		0x007f48),
56	REG(ANA_TABLES_STREAMACCESS,		0x007f4c),
57	REG(ANA_TABLES_STREAMTIDX,		0x007f50),
58	REG(ANA_TABLES_SEQ_HISTORY,		0x007f54),
59	REG(ANA_TABLES_SEQ_MASK,		0x007f58),
60	REG(ANA_TABLES_SFID_MASK,		0x007f5c),
61	REG(ANA_TABLES_SFIDACCESS,		0x007f60),
62	REG(ANA_TABLES_SFIDTIDX,		0x007f64),
63	REG(ANA_MSTI_STATE,			0x008600),
64	REG(ANA_OAM_UPM_LM_CNT,			0x008000),
65	REG(ANA_SG_ACCESS_CTRL,			0x008a64),
66	REG(ANA_SG_CONFIG_REG_1,		0x007fb0),
67	REG(ANA_SG_CONFIG_REG_2,		0x007fb4),
68	REG(ANA_SG_CONFIG_REG_3,		0x007fb8),
69	REG(ANA_SG_CONFIG_REG_4,		0x007fbc),
70	REG(ANA_SG_CONFIG_REG_5,		0x007fc0),
71	REG(ANA_SG_GCL_GS_CONFIG,		0x007f80),
72	REG(ANA_SG_GCL_TI_CONFIG,		0x007f90),
73	REG(ANA_SG_STATUS_REG_1,		0x008980),
74	REG(ANA_SG_STATUS_REG_2,		0x008984),
75	REG(ANA_SG_STATUS_REG_3,		0x008988),
76	REG(ANA_PORT_VLAN_CFG,			0x007800),
77	REG(ANA_PORT_DROP_CFG,			0x007804),
78	REG(ANA_PORT_QOS_CFG,			0x007808),
79	REG(ANA_PORT_VCAP_CFG,			0x00780c),
80	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x007810),
81	REG(ANA_PORT_VCAP_S2_CFG,		0x00781c),
82	REG(ANA_PORT_PCP_DEI_MAP,		0x007820),
83	REG(ANA_PORT_CPU_FWD_CFG,		0x007860),
84	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x007864),
85	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x007868),
86	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00786c),
87	REG(ANA_PORT_PORT_CFG,			0x007870),
88	REG(ANA_PORT_POL_CFG,			0x007874),
89	REG(ANA_PORT_PTP_CFG,			0x007878),
90	REG(ANA_PORT_PTP_DLY1_CFG,		0x00787c),
91	REG(ANA_PORT_PTP_DLY2_CFG,		0x007880),
92	REG(ANA_PORT_SFID_CFG,			0x007884),
93	REG(ANA_PFC_PFC_CFG,			0x008800),
94	REG_RESERVED(ANA_PFC_PFC_TIMER),
95	REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
96	REG_RESERVED(ANA_IPT_IPT),
97	REG_RESERVED(ANA_PPT_PPT),
98	REG_RESERVED(ANA_FID_MAP_FID_MAP),
99	REG(ANA_AGGR_CFG,			0x008a68),
100	REG(ANA_CPUQ_CFG,			0x008a6c),
101	REG_RESERVED(ANA_CPUQ_CFG2),
102	REG(ANA_CPUQ_8021_CFG,			0x008a74),
103	REG(ANA_DSCP_CFG,			0x008ab4),
104	REG(ANA_DSCP_REWR_CFG,			0x008bb4),
105	REG(ANA_VCAP_RNG_TYPE_CFG,		0x008bf4),
106	REG(ANA_VCAP_RNG_VAL_CFG,		0x008c14),
107	REG_RESERVED(ANA_VRAP_CFG),
108	REG_RESERVED(ANA_VRAP_HDR_DATA),
109	REG_RESERVED(ANA_VRAP_HDR_MASK),
110	REG(ANA_DISCARD_CFG,			0x008c40),
111	REG(ANA_FID_CFG,			0x008c44),
112	REG(ANA_POL_PIR_CFG,			0x004000),
113	REG(ANA_POL_CIR_CFG,			0x004004),
114	REG(ANA_POL_MODE_CFG,			0x004008),
115	REG(ANA_POL_PIR_STATE,			0x00400c),
116	REG(ANA_POL_CIR_STATE,			0x004010),
117	REG_RESERVED(ANA_POL_STATE),
118	REG(ANA_POL_FLOWC,			0x008c48),
119	REG(ANA_POL_HYST,			0x008cb4),
120	REG_RESERVED(ANA_POL_MISC_CFG),
121};
122
123static const u32 vsc9959_qs_regmap[] = {
124	REG(QS_XTR_GRP_CFG,			0x000000),
125	REG(QS_XTR_RD,				0x000008),
126	REG(QS_XTR_FRM_PRUNING,			0x000010),
127	REG(QS_XTR_FLUSH,			0x000018),
128	REG(QS_XTR_DATA_PRESENT,		0x00001c),
129	REG(QS_XTR_CFG,				0x000020),
130	REG(QS_INJ_GRP_CFG,			0x000024),
131	REG(QS_INJ_WR,				0x00002c),
132	REG(QS_INJ_CTRL,			0x000034),
133	REG(QS_INJ_STATUS,			0x00003c),
134	REG(QS_INJ_ERR,				0x000040),
135	REG_RESERVED(QS_INH_DBG),
136};
137
138static const u32 vsc9959_vcap_regmap[] = {
139	/* VCAP_CORE_CFG */
140	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),
141	REG(VCAP_CORE_MV_CFG,			0x000004),
142	/* VCAP_CORE_CACHE */
143	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),
144	REG(VCAP_CACHE_MASK_DAT,		0x000108),
145	REG(VCAP_CACHE_ACTION_DAT,		0x000208),
146	REG(VCAP_CACHE_CNT_DAT,			0x000308),
147	REG(VCAP_CACHE_TG_DAT,			0x000388),
148	/* VCAP_CONST */
149	REG(VCAP_CONST_VCAP_VER,		0x000398),
150	REG(VCAP_CONST_ENTRY_WIDTH,		0x00039c),
151	REG(VCAP_CONST_ENTRY_CNT,		0x0003a0),
152	REG(VCAP_CONST_ENTRY_SWCNT,		0x0003a4),
153	REG(VCAP_CONST_ENTRY_TG_WIDTH,		0x0003a8),
154	REG(VCAP_CONST_ACTION_DEF_CNT,		0x0003ac),
155	REG(VCAP_CONST_ACTION_WIDTH,		0x0003b0),
156	REG(VCAP_CONST_CNT_WIDTH,		0x0003b4),
157	REG(VCAP_CONST_CORE_CNT,		0x0003b8),
158	REG(VCAP_CONST_IF_CNT,			0x0003bc),
159};
160
161static const u32 vsc9959_qsys_regmap[] = {
162	REG(QSYS_PORT_MODE,			0x00f460),
163	REG(QSYS_SWITCH_PORT_MODE,		0x00f480),
164	REG(QSYS_STAT_CNT_CFG,			0x00f49c),
165	REG(QSYS_EEE_CFG,			0x00f4a0),
166	REG(QSYS_EEE_THRES,			0x00f4b8),
167	REG(QSYS_IGR_NO_SHARING,		0x00f4bc),
168	REG(QSYS_EGR_NO_SHARING,		0x00f4c0),
169	REG(QSYS_SW_STATUS,			0x00f4c4),
170	REG(QSYS_EXT_CPU_CFG,			0x00f4e0),
171	REG_RESERVED(QSYS_PAD_CFG),
172	REG(QSYS_CPU_GROUP_MAP,			0x00f4e8),
173	REG_RESERVED(QSYS_QMAP),
174	REG_RESERVED(QSYS_ISDX_SGRP),
175	REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
176	REG(QSYS_TFRM_MISC,			0x00f50c),
177	REG(QSYS_TFRM_PORT_DLY,			0x00f510),
178	REG(QSYS_TFRM_TIMER_CFG_1,		0x00f514),
179	REG(QSYS_TFRM_TIMER_CFG_2,		0x00f518),
180	REG(QSYS_TFRM_TIMER_CFG_3,		0x00f51c),
181	REG(QSYS_TFRM_TIMER_CFG_4,		0x00f520),
182	REG(QSYS_TFRM_TIMER_CFG_5,		0x00f524),
183	REG(QSYS_TFRM_TIMER_CFG_6,		0x00f528),
184	REG(QSYS_TFRM_TIMER_CFG_7,		0x00f52c),
185	REG(QSYS_TFRM_TIMER_CFG_8,		0x00f530),
186	REG(QSYS_RED_PROFILE,			0x00f534),
187	REG(QSYS_RES_QOS_MODE,			0x00f574),
188	REG(QSYS_RES_CFG,			0x00c000),
189	REG(QSYS_RES_STAT,			0x00c004),
190	REG(QSYS_EGR_DROP_MODE,			0x00f578),
191	REG(QSYS_EQ_CTRL,			0x00f57c),
192	REG_RESERVED(QSYS_EVENTS_CORE),
193	REG(QSYS_QMAXSDU_CFG_0,			0x00f584),
194	REG(QSYS_QMAXSDU_CFG_1,			0x00f5a0),
195	REG(QSYS_QMAXSDU_CFG_2,			0x00f5bc),
196	REG(QSYS_QMAXSDU_CFG_3,			0x00f5d8),
197	REG(QSYS_QMAXSDU_CFG_4,			0x00f5f4),
198	REG(QSYS_QMAXSDU_CFG_5,			0x00f610),
199	REG(QSYS_QMAXSDU_CFG_6,			0x00f62c),
200	REG(QSYS_QMAXSDU_CFG_7,			0x00f648),
201	REG(QSYS_PREEMPTION_CFG,		0x00f664),
202	REG(QSYS_CIR_CFG,			0x000000),
203	REG(QSYS_EIR_CFG,			0x000004),
204	REG(QSYS_SE_CFG,			0x000008),
205	REG(QSYS_SE_DWRR_CFG,			0x00000c),
206	REG_RESERVED(QSYS_SE_CONNECT),
207	REG(QSYS_SE_DLB_SENSE,			0x000040),
208	REG(QSYS_CIR_STATE,			0x000044),
209	REG(QSYS_EIR_STATE,			0x000048),
210	REG_RESERVED(QSYS_SE_STATE),
211	REG(QSYS_HSCH_MISC_CFG,			0x00f67c),
212	REG(QSYS_TAG_CONFIG,			0x00f680),
213	REG(QSYS_TAS_PARAM_CFG_CTRL,		0x00f698),
214	REG(QSYS_PORT_MAX_SDU,			0x00f69c),
215	REG(QSYS_PARAM_CFG_REG_1,		0x00f440),
216	REG(QSYS_PARAM_CFG_REG_2,		0x00f444),
217	REG(QSYS_PARAM_CFG_REG_3,		0x00f448),
218	REG(QSYS_PARAM_CFG_REG_4,		0x00f44c),
219	REG(QSYS_PARAM_CFG_REG_5,		0x00f450),
220	REG(QSYS_GCL_CFG_REG_1,			0x00f454),
221	REG(QSYS_GCL_CFG_REG_2,			0x00f458),
222	REG(QSYS_PARAM_STATUS_REG_1,		0x00f400),
223	REG(QSYS_PARAM_STATUS_REG_2,		0x00f404),
224	REG(QSYS_PARAM_STATUS_REG_3,		0x00f408),
225	REG(QSYS_PARAM_STATUS_REG_4,		0x00f40c),
226	REG(QSYS_PARAM_STATUS_REG_5,		0x00f410),
227	REG(QSYS_PARAM_STATUS_REG_6,		0x00f414),
228	REG(QSYS_PARAM_STATUS_REG_7,		0x00f418),
229	REG(QSYS_PARAM_STATUS_REG_8,		0x00f41c),
230	REG(QSYS_PARAM_STATUS_REG_9,		0x00f420),
231	REG(QSYS_GCL_STATUS_REG_1,		0x00f424),
232	REG(QSYS_GCL_STATUS_REG_2,		0x00f428),
233};
234
235static const u32 vsc9959_rew_regmap[] = {
236	REG(REW_PORT_VLAN_CFG,			0x000000),
237	REG(REW_TAG_CFG,			0x000004),
238	REG(REW_PORT_CFG,			0x000008),
239	REG(REW_DSCP_CFG,			0x00000c),
240	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
241	REG(REW_PTP_CFG,			0x000050),
242	REG(REW_PTP_DLY1_CFG,			0x000054),
243	REG(REW_RED_TAG_CFG,			0x000058),
244	REG(REW_DSCP_REMAP_DP1_CFG,		0x000410),
245	REG(REW_DSCP_REMAP_CFG,			0x000510),
246	REG_RESERVED(REW_STAT_CFG),
247	REG_RESERVED(REW_REW_STICKY),
248	REG_RESERVED(REW_PPT),
249};
250
251static const u32 vsc9959_sys_regmap[] = {
252	REG(SYS_COUNT_RX_OCTETS,		0x000000),
253	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
254	REG(SYS_COUNT_RX_SHORTS,		0x000010),
255	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
256	REG(SYS_COUNT_RX_JABBERS,		0x000018),
257	REG(SYS_COUNT_RX_64,			0x000024),
258	REG(SYS_COUNT_RX_65_127,		0x000028),
259	REG(SYS_COUNT_RX_128_255,		0x00002c),
260	REG(SYS_COUNT_RX_256_1023,		0x000030),
261	REG(SYS_COUNT_RX_1024_1526,		0x000034),
262	REG(SYS_COUNT_RX_1527_MAX,		0x000038),
263	REG(SYS_COUNT_RX_LONGS,			0x000044),
264	REG(SYS_COUNT_TX_OCTETS,		0x000200),
265	REG(SYS_COUNT_TX_COLLISION,		0x000210),
266	REG(SYS_COUNT_TX_DROPS,			0x000214),
267	REG(SYS_COUNT_TX_64,			0x00021c),
268	REG(SYS_COUNT_TX_65_127,		0x000220),
269	REG(SYS_COUNT_TX_128_511,		0x000224),
270	REG(SYS_COUNT_TX_512_1023,		0x000228),
271	REG(SYS_COUNT_TX_1024_1526,		0x00022c),
272	REG(SYS_COUNT_TX_1527_MAX,		0x000230),
273	REG(SYS_COUNT_TX_AGING,			0x000278),
274	REG(SYS_RESET_CFG,			0x000e00),
275	REG(SYS_SR_ETYPE_CFG,			0x000e04),
276	REG(SYS_VLAN_ETYPE_CFG,			0x000e08),
277	REG(SYS_PORT_MODE,			0x000e0c),
278	REG(SYS_FRONT_PORT_MODE,		0x000e2c),
279	REG(SYS_FRM_AGING,			0x000e44),
280	REG(SYS_STAT_CFG,			0x000e48),
281	REG(SYS_SW_STATUS,			0x000e4c),
282	REG_RESERVED(SYS_MISC_CFG),
283	REG(SYS_REW_MAC_HIGH_CFG,		0x000e6c),
284	REG(SYS_REW_MAC_LOW_CFG,		0x000e84),
285	REG(SYS_TIMESTAMP_OFFSET,		0x000e9c),
286	REG(SYS_PAUSE_CFG,			0x000ea0),
287	REG(SYS_PAUSE_TOT_CFG,			0x000ebc),
288	REG(SYS_ATOP,				0x000ec0),
289	REG(SYS_ATOP_TOT_CFG,			0x000edc),
290	REG(SYS_MAC_FC_CFG,			0x000ee0),
291	REG(SYS_MMGT,				0x000ef8),
292	REG_RESERVED(SYS_MMGT_FAST),
293	REG_RESERVED(SYS_EVENTS_DIF),
294	REG_RESERVED(SYS_EVENTS_CORE),
295	REG_RESERVED(SYS_CNT),
296	REG(SYS_PTP_STATUS,			0x000f14),
297	REG(SYS_PTP_TXSTAMP,			0x000f18),
298	REG(SYS_PTP_NXT,			0x000f1c),
299	REG(SYS_PTP_CFG,			0x000f20),
300	REG(SYS_RAM_INIT,			0x000f24),
301	REG_RESERVED(SYS_CM_ADDR),
302	REG_RESERVED(SYS_CM_DATA_WR),
303	REG_RESERVED(SYS_CM_DATA_RD),
304	REG_RESERVED(SYS_CM_OP),
305	REG_RESERVED(SYS_CM_DATA),
306};
307
308static const u32 vsc9959_ptp_regmap[] = {
309	REG(PTP_PIN_CFG,			0x000000),
310	REG(PTP_PIN_TOD_SEC_MSB,		0x000004),
311	REG(PTP_PIN_TOD_SEC_LSB,		0x000008),
312	REG(PTP_PIN_TOD_NSEC,			0x00000c),
313	REG(PTP_PIN_WF_HIGH_PERIOD,		0x000014),
314	REG(PTP_PIN_WF_LOW_PERIOD,		0x000018),
315	REG(PTP_CFG_MISC,			0x0000a0),
316	REG(PTP_CLK_CFG_ADJ_CFG,		0x0000a4),
317	REG(PTP_CLK_CFG_ADJ_FREQ,		0x0000a8),
318};
319
320static const u32 vsc9959_gcb_regmap[] = {
321	REG(GCB_SOFT_RST,			0x000004),
322};
323
324static const u32 vsc9959_dev_gmii_regmap[] = {
325	REG(DEV_CLOCK_CFG,			0x0),
326	REG(DEV_PORT_MISC,			0x4),
327	REG(DEV_EVENTS,				0x8),
328	REG(DEV_EEE_CFG,			0xc),
329	REG(DEV_RX_PATH_DELAY,			0x10),
330	REG(DEV_TX_PATH_DELAY,			0x14),
331	REG(DEV_PTP_PREDICT_CFG,		0x18),
332	REG(DEV_MAC_ENA_CFG,			0x1c),
333	REG(DEV_MAC_MODE_CFG,			0x20),
334	REG(DEV_MAC_MAXLEN_CFG,			0x24),
335	REG(DEV_MAC_TAGS_CFG,			0x28),
336	REG(DEV_MAC_ADV_CHK_CFG,		0x2c),
337	REG(DEV_MAC_IFG_CFG,			0x30),
338	REG(DEV_MAC_HDX_CFG,			0x34),
339	REG(DEV_MAC_DBG_CFG,			0x38),
340	REG(DEV_MAC_FC_MAC_LOW_CFG,		0x3c),
341	REG(DEV_MAC_FC_MAC_HIGH_CFG,		0x40),
342	REG(DEV_MAC_STICKY,			0x44),
343	REG_RESERVED(PCS1G_CFG),
344	REG_RESERVED(PCS1G_MODE_CFG),
345	REG_RESERVED(PCS1G_SD_CFG),
346	REG_RESERVED(PCS1G_ANEG_CFG),
347	REG_RESERVED(PCS1G_ANEG_NP_CFG),
348	REG_RESERVED(PCS1G_LB_CFG),
349	REG_RESERVED(PCS1G_DBG_CFG),
350	REG_RESERVED(PCS1G_CDET_CFG),
351	REG_RESERVED(PCS1G_ANEG_STATUS),
352	REG_RESERVED(PCS1G_ANEG_NP_STATUS),
353	REG_RESERVED(PCS1G_LINK_STATUS),
354	REG_RESERVED(PCS1G_LINK_DOWN_CNT),
355	REG_RESERVED(PCS1G_STICKY),
356	REG_RESERVED(PCS1G_DEBUG_STATUS),
357	REG_RESERVED(PCS1G_LPI_CFG),
358	REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
359	REG_RESERVED(PCS1G_LPI_STATUS),
360	REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
361	REG_RESERVED(PCS1G_TSTPAT_STATUS),
362	REG_RESERVED(DEV_PCS_FX100_CFG),
363	REG_RESERVED(DEV_PCS_FX100_STATUS),
364};
365
366static const u32 *vsc9959_regmap[TARGET_MAX] = {
367	[ANA]	= vsc9959_ana_regmap,
368	[QS]	= vsc9959_qs_regmap,
369	[QSYS]	= vsc9959_qsys_regmap,
370	[REW]	= vsc9959_rew_regmap,
371	[SYS]	= vsc9959_sys_regmap,
372	[S0]	= vsc9959_vcap_regmap,
373	[S1]	= vsc9959_vcap_regmap,
374	[S2]	= vsc9959_vcap_regmap,
375	[PTP]	= vsc9959_ptp_regmap,
376	[GCB]	= vsc9959_gcb_regmap,
377	[DEV_GMII] = vsc9959_dev_gmii_regmap,
378};
379
380/* Addresses are relative to the PCI device's base address */
381static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
382	[ANA] = {
383		.start	= 0x0280000,
384		.end	= 0x028ffff,
385		.name	= "ana",
386	},
387	[QS] = {
388		.start	= 0x0080000,
389		.end	= 0x00800ff,
390		.name	= "qs",
391	},
392	[QSYS] = {
393		.start	= 0x0200000,
394		.end	= 0x021ffff,
395		.name	= "qsys",
396	},
397	[REW] = {
398		.start	= 0x0030000,
399		.end	= 0x003ffff,
400		.name	= "rew",
401	},
402	[SYS] = {
403		.start	= 0x0010000,
404		.end	= 0x001ffff,
405		.name	= "sys",
406	},
407	[S0] = {
408		.start	= 0x0040000,
409		.end	= 0x00403ff,
410		.name	= "s0",
411	},
412	[S1] = {
413		.start	= 0x0050000,
414		.end	= 0x00503ff,
415		.name	= "s1",
416	},
417	[S2] = {
418		.start	= 0x0060000,
419		.end	= 0x00603ff,
420		.name	= "s2",
421	},
422	[PTP] = {
423		.start	= 0x0090000,
424		.end	= 0x00900cb,
425		.name	= "ptp",
426	},
427	[GCB] = {
428		.start	= 0x0070000,
429		.end	= 0x00701ff,
430		.name	= "devcpu_gcb",
431	},
432};
433
434static const struct resource vsc9959_port_io_res[] = {
435	{
436		.start	= 0x0100000,
437		.end	= 0x010ffff,
438		.name	= "port0",
439	},
440	{
441		.start	= 0x0110000,
442		.end	= 0x011ffff,
443		.name	= "port1",
444	},
445	{
446		.start	= 0x0120000,
447		.end	= 0x012ffff,
448		.name	= "port2",
449	},
450	{
451		.start	= 0x0130000,
452		.end	= 0x013ffff,
453		.name	= "port3",
454	},
455	{
456		.start	= 0x0140000,
457		.end	= 0x014ffff,
458		.name	= "port4",
459	},
460	{
461		.start	= 0x0150000,
462		.end	= 0x015ffff,
463		.name	= "port5",
464	},
465};
466
467/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
468 * SGMII/QSGMII MAC PCS can be found.
469 */
470static const struct resource vsc9959_imdio_res = {
471	.start		= 0x8030,
472	.end		= 0x8040,
473	.name		= "imdio",
474};
475
476static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
477	[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
478	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
479	[ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
480	[ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
481	[ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
482	[ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
483	[ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
484	[ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
485	[ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
486	[ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
487	[ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
488	[ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
489	[ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
490	[ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
491	[ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
492	[ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
493	[ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
494	[ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
495	[ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
496	[ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
497	[ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
498	[ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
499	[ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
500	[ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
501	[ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
502	[ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
503	[ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
504	[ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
505	[ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
506	[ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
507	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
508	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
509	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
510	/* Replicated per number of ports (7), register size 4 per port */
511	[QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
512	[QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
513	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
514	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
515	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
516	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
517	[SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
518	[SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
519	[SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
520	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
521	[SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
522	[SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
523	[SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
524};
525
526static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
527	{ .offset = 0x00,	.name = "rx_octets", },
528	{ .offset = 0x01,	.name = "rx_unicast", },
529	{ .offset = 0x02,	.name = "rx_multicast", },
530	{ .offset = 0x03,	.name = "rx_broadcast", },
531	{ .offset = 0x04,	.name = "rx_shorts", },
532	{ .offset = 0x05,	.name = "rx_fragments", },
533	{ .offset = 0x06,	.name = "rx_jabbers", },
534	{ .offset = 0x07,	.name = "rx_crc_align_errs", },
535	{ .offset = 0x08,	.name = "rx_sym_errs", },
536	{ .offset = 0x09,	.name = "rx_frames_below_65_octets", },
537	{ .offset = 0x0A,	.name = "rx_frames_65_to_127_octets", },
538	{ .offset = 0x0B,	.name = "rx_frames_128_to_255_octets", },
539	{ .offset = 0x0C,	.name = "rx_frames_256_to_511_octets", },
540	{ .offset = 0x0D,	.name = "rx_frames_512_to_1023_octets", },
541	{ .offset = 0x0E,	.name = "rx_frames_1024_to_1526_octets", },
542	{ .offset = 0x0F,	.name = "rx_frames_over_1526_octets", },
543	{ .offset = 0x10,	.name = "rx_pause", },
544	{ .offset = 0x11,	.name = "rx_control", },
545	{ .offset = 0x12,	.name = "rx_longs", },
546	{ .offset = 0x13,	.name = "rx_classified_drops", },
547	{ .offset = 0x14,	.name = "rx_red_prio_0", },
548	{ .offset = 0x15,	.name = "rx_red_prio_1", },
549	{ .offset = 0x16,	.name = "rx_red_prio_2", },
550	{ .offset = 0x17,	.name = "rx_red_prio_3", },
551	{ .offset = 0x18,	.name = "rx_red_prio_4", },
552	{ .offset = 0x19,	.name = "rx_red_prio_5", },
553	{ .offset = 0x1A,	.name = "rx_red_prio_6", },
554	{ .offset = 0x1B,	.name = "rx_red_prio_7", },
555	{ .offset = 0x1C,	.name = "rx_yellow_prio_0", },
556	{ .offset = 0x1D,	.name = "rx_yellow_prio_1", },
557	{ .offset = 0x1E,	.name = "rx_yellow_prio_2", },
558	{ .offset = 0x1F,	.name = "rx_yellow_prio_3", },
559	{ .offset = 0x20,	.name = "rx_yellow_prio_4", },
560	{ .offset = 0x21,	.name = "rx_yellow_prio_5", },
561	{ .offset = 0x22,	.name = "rx_yellow_prio_6", },
562	{ .offset = 0x23,	.name = "rx_yellow_prio_7", },
563	{ .offset = 0x24,	.name = "rx_green_prio_0", },
564	{ .offset = 0x25,	.name = "rx_green_prio_1", },
565	{ .offset = 0x26,	.name = "rx_green_prio_2", },
566	{ .offset = 0x27,	.name = "rx_green_prio_3", },
567	{ .offset = 0x28,	.name = "rx_green_prio_4", },
568	{ .offset = 0x29,	.name = "rx_green_prio_5", },
569	{ .offset = 0x2A,	.name = "rx_green_prio_6", },
570	{ .offset = 0x2B,	.name = "rx_green_prio_7", },
571	{ .offset = 0x80,	.name = "tx_octets", },
572	{ .offset = 0x81,	.name = "tx_unicast", },
573	{ .offset = 0x82,	.name = "tx_multicast", },
574	{ .offset = 0x83,	.name = "tx_broadcast", },
575	{ .offset = 0x84,	.name = "tx_collision", },
576	{ .offset = 0x85,	.name = "tx_drops", },
577	{ .offset = 0x86,	.name = "tx_pause", },
578	{ .offset = 0x87,	.name = "tx_frames_below_65_octets", },
579	{ .offset = 0x88,	.name = "tx_frames_65_to_127_octets", },
580	{ .offset = 0x89,	.name = "tx_frames_128_255_octets", },
581	{ .offset = 0x8A,	.name = "tx_frames_256_511_octets", },
582	{ .offset = 0x8B,	.name = "tx_frames_512_1023_octets", },
583	{ .offset = 0x8C,	.name = "tx_frames_1024_1526_octets", },
584	{ .offset = 0x8D,	.name = "tx_frames_over_1526_octets", },
585	{ .offset = 0x8E,	.name = "tx_yellow_prio_0", },
586	{ .offset = 0x8F,	.name = "tx_yellow_prio_1", },
587	{ .offset = 0x90,	.name = "tx_yellow_prio_2", },
588	{ .offset = 0x91,	.name = "tx_yellow_prio_3", },
589	{ .offset = 0x92,	.name = "tx_yellow_prio_4", },
590	{ .offset = 0x93,	.name = "tx_yellow_prio_5", },
591	{ .offset = 0x94,	.name = "tx_yellow_prio_6", },
592	{ .offset = 0x95,	.name = "tx_yellow_prio_7", },
593	{ .offset = 0x96,	.name = "tx_green_prio_0", },
594	{ .offset = 0x97,	.name = "tx_green_prio_1", },
595	{ .offset = 0x98,	.name = "tx_green_prio_2", },
596	{ .offset = 0x99,	.name = "tx_green_prio_3", },
597	{ .offset = 0x9A,	.name = "tx_green_prio_4", },
598	{ .offset = 0x9B,	.name = "tx_green_prio_5", },
599	{ .offset = 0x9C,	.name = "tx_green_prio_6", },
600	{ .offset = 0x9D,	.name = "tx_green_prio_7", },
601	{ .offset = 0x9E,	.name = "tx_aged", },
602	{ .offset = 0x100,	.name = "drop_local", },
603	{ .offset = 0x101,	.name = "drop_tail", },
604	{ .offset = 0x102,	.name = "drop_yellow_prio_0", },
605	{ .offset = 0x103,	.name = "drop_yellow_prio_1", },
606	{ .offset = 0x104,	.name = "drop_yellow_prio_2", },
607	{ .offset = 0x105,	.name = "drop_yellow_prio_3", },
608	{ .offset = 0x106,	.name = "drop_yellow_prio_4", },
609	{ .offset = 0x107,	.name = "drop_yellow_prio_5", },
610	{ .offset = 0x108,	.name = "drop_yellow_prio_6", },
611	{ .offset = 0x109,	.name = "drop_yellow_prio_7", },
612	{ .offset = 0x10A,	.name = "drop_green_prio_0", },
613	{ .offset = 0x10B,	.name = "drop_green_prio_1", },
614	{ .offset = 0x10C,	.name = "drop_green_prio_2", },
615	{ .offset = 0x10D,	.name = "drop_green_prio_3", },
616	{ .offset = 0x10E,	.name = "drop_green_prio_4", },
617	{ .offset = 0x10F,	.name = "drop_green_prio_5", },
618	{ .offset = 0x110,	.name = "drop_green_prio_6", },
619	{ .offset = 0x111,	.name = "drop_green_prio_7", },
620};
621
622static const struct vcap_field vsc9959_vcap_es0_keys[] = {
623	[VCAP_ES0_EGR_PORT]			= {  0,  3},
624	[VCAP_ES0_IGR_PORT]			= {  3,  3},
625	[VCAP_ES0_RSV]				= {  6,  2},
626	[VCAP_ES0_L2_MC]			= {  8,  1},
627	[VCAP_ES0_L2_BC]			= {  9,  1},
628	[VCAP_ES0_VID]				= { 10, 12},
629	[VCAP_ES0_DP]				= { 22,  1},
630	[VCAP_ES0_PCP]				= { 23,  3},
631};
632
633static const struct vcap_field vsc9959_vcap_es0_actions[] = {
634	[VCAP_ES0_ACT_PUSH_OUTER_TAG]		= {  0,  2},
635	[VCAP_ES0_ACT_PUSH_INNER_TAG]		= {  2,  1},
636	[VCAP_ES0_ACT_TAG_A_TPID_SEL]		= {  3,  2},
637	[VCAP_ES0_ACT_TAG_A_VID_SEL]		= {  5,  1},
638	[VCAP_ES0_ACT_TAG_A_PCP_SEL]		= {  6,  2},
639	[VCAP_ES0_ACT_TAG_A_DEI_SEL]		= {  8,  2},
640	[VCAP_ES0_ACT_TAG_B_TPID_SEL]		= { 10,  2},
641	[VCAP_ES0_ACT_TAG_B_VID_SEL]		= { 12,  1},
642	[VCAP_ES0_ACT_TAG_B_PCP_SEL]		= { 13,  2},
643	[VCAP_ES0_ACT_TAG_B_DEI_SEL]		= { 15,  2},
644	[VCAP_ES0_ACT_VID_A_VAL]		= { 17, 12},
645	[VCAP_ES0_ACT_PCP_A_VAL]		= { 29,  3},
646	[VCAP_ES0_ACT_DEI_A_VAL]		= { 32,  1},
647	[VCAP_ES0_ACT_VID_B_VAL]		= { 33, 12},
648	[VCAP_ES0_ACT_PCP_B_VAL]		= { 45,  3},
649	[VCAP_ES0_ACT_DEI_B_VAL]		= { 48,  1},
650	[VCAP_ES0_ACT_RSV]			= { 49, 23},
651	[VCAP_ES0_ACT_HIT_STICKY]		= { 72,  1},
652};
653
654static const struct vcap_field vsc9959_vcap_is1_keys[] = {
655	[VCAP_IS1_HK_TYPE]			= {  0,   1},
656	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},
657	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,   7},
658	[VCAP_IS1_HK_RSV]			= { 10,   9},
659	[VCAP_IS1_HK_OAM_Y1731]			= { 19,   1},
660	[VCAP_IS1_HK_L2_MC]			= { 20,   1},
661	[VCAP_IS1_HK_L2_BC]			= { 21,   1},
662	[VCAP_IS1_HK_IP_MC]			= { 22,   1},
663	[VCAP_IS1_HK_VLAN_TAGGED]		= { 23,   1},
664	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 24,   1},
665	[VCAP_IS1_HK_TPID]			= { 25,   1},
666	[VCAP_IS1_HK_VID]			= { 26,  12},
667	[VCAP_IS1_HK_DEI]			= { 38,   1},
668	[VCAP_IS1_HK_PCP]			= { 39,   3},
669	/* Specific Fields for IS1 Half Key S1_NORMAL */
670	[VCAP_IS1_HK_L2_SMAC]			= { 42,  48},
671	[VCAP_IS1_HK_ETYPE_LEN]			= { 90,   1},
672	[VCAP_IS1_HK_ETYPE]			= { 91,  16},
673	[VCAP_IS1_HK_IP_SNAP]			= {107,   1},
674	[VCAP_IS1_HK_IP4]			= {108,   1},
675	/* Layer-3 Information */
676	[VCAP_IS1_HK_L3_FRAGMENT]		= {109,   1},
677	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {110,   1},
678	[VCAP_IS1_HK_L3_OPTIONS]		= {111,   1},
679	[VCAP_IS1_HK_L3_DSCP]			= {112,   6},
680	[VCAP_IS1_HK_L3_IP4_SIP]		= {118,  32},
681	/* Layer-4 Information */
682	[VCAP_IS1_HK_TCP_UDP]			= {150,   1},
683	[VCAP_IS1_HK_TCP]			= {151,   1},
684	[VCAP_IS1_HK_L4_SPORT]			= {152,  16},
685	[VCAP_IS1_HK_L4_RNG]			= {168,   8},
686	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
687	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
688	[VCAP_IS1_HK_IP4_INNER_VID]		= { 43,  12},
689	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 55,   1},
690	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 56,   3},
691	[VCAP_IS1_HK_IP4_IP4]			= { 59,   1},
692	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 60,   1},
693	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 61,   1},
694	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 62,   1},
695	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 63,   6},
696	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 69,  32},
697	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {101,  32},
698	[VCAP_IS1_HK_IP4_L3_PROTO]		= {133,   8},
699	[VCAP_IS1_HK_IP4_TCP_UDP]		= {141,   1},
700	[VCAP_IS1_HK_IP4_TCP]			= {142,   1},
701	[VCAP_IS1_HK_IP4_L4_RNG]		= {143,   8},
702	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {151,  32},
703};
704
705static const struct vcap_field vsc9959_vcap_is1_actions[] = {
706	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},
707	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},
708	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},
709	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},
710	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},
711	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},
712	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},
713	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},
714	[VCAP_IS1_ACT_RSV]			= { 29,  9},
715	/* The fields below are incorrectly shifted by 2 in the manual */
716	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 38,  1},
717	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 39, 12},
718	[VCAP_IS1_ACT_FID_SEL]			= { 51,  2},
719	[VCAP_IS1_ACT_FID_VAL]			= { 53, 13},
720	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 66,  1},
721	[VCAP_IS1_ACT_PCP_VAL]			= { 67,  3},
722	[VCAP_IS1_ACT_DEI_VAL]			= { 70,  1},
723	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 71,  1},
724	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 72,  2},
725	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 74,  4},
726	[VCAP_IS1_ACT_HIT_STICKY]		= { 78,  1},
727};
728
729static struct vcap_field vsc9959_vcap_is2_keys[] = {
730	/* Common: 41 bits */
731	[VCAP_IS2_TYPE]				= {  0,   4},
732	[VCAP_IS2_HK_FIRST]			= {  4,   1},
733	[VCAP_IS2_HK_PAG]			= {  5,   8},
734	[VCAP_IS2_HK_IGR_PORT_MASK]		= { 13,   7},
735	[VCAP_IS2_HK_RSV2]			= { 20,   1},
736	[VCAP_IS2_HK_HOST_MATCH]		= { 21,   1},
737	[VCAP_IS2_HK_L2_MC]			= { 22,   1},
738	[VCAP_IS2_HK_L2_BC]			= { 23,   1},
739	[VCAP_IS2_HK_VLAN_TAGGED]		= { 24,   1},
740	[VCAP_IS2_HK_VID]			= { 25,  12},
741	[VCAP_IS2_HK_DEI]			= { 37,   1},
742	[VCAP_IS2_HK_PCP]			= { 38,   3},
743	/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
744	[VCAP_IS2_HK_L2_DMAC]			= { 41,  48},
745	[VCAP_IS2_HK_L2_SMAC]			= { 89,  48},
746	/* MAC_ETYPE (TYPE=000) */
747	[VCAP_IS2_HK_MAC_ETYPE_ETYPE]		= {137,  16},
748	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]	= {153,  16},
749	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]	= {169,   8},
750	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]	= {177,   3},
751	/* MAC_LLC (TYPE=001) */
752	[VCAP_IS2_HK_MAC_LLC_L2_LLC]		= {137,  40},
753	/* MAC_SNAP (TYPE=010) */
754	[VCAP_IS2_HK_MAC_SNAP_L2_SNAP]		= {137,  40},
755	/* MAC_ARP (TYPE=011) */
756	[VCAP_IS2_HK_MAC_ARP_SMAC]		= { 41,  48},
757	[VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]	= { 89,   1},
758	[VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]	= { 90,   1},
759	[VCAP_IS2_HK_MAC_ARP_LEN_OK]		= { 91,   1},
760	[VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]	= { 92,   1},
761	[VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]	= { 93,   1},
762	[VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]	= { 94,   1},
763	[VCAP_IS2_HK_MAC_ARP_OPCODE]		= { 95,   2},
764	[VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]	= { 97,  32},
765	[VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]	= {129,  32},
766	[VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]	= {161,   1},
767	/* IP4_TCP_UDP / IP4_OTHER common */
768	[VCAP_IS2_HK_IP4]			= { 41,   1},
769	[VCAP_IS2_HK_L3_FRAGMENT]		= { 42,   1},
770	[VCAP_IS2_HK_L3_FRAG_OFS_GT0]		= { 43,   1},
771	[VCAP_IS2_HK_L3_OPTIONS]		= { 44,   1},
772	[VCAP_IS2_HK_IP4_L3_TTL_GT0]		= { 45,   1},
773	[VCAP_IS2_HK_L3_TOS]			= { 46,   8},
774	[VCAP_IS2_HK_L3_IP4_DIP]		= { 54,  32},
775	[VCAP_IS2_HK_L3_IP4_SIP]		= { 86,  32},
776	[VCAP_IS2_HK_DIP_EQ_SIP]		= {118,   1},
777	/* IP4_TCP_UDP (TYPE=100) */
778	[VCAP_IS2_HK_TCP]			= {119,   1},
779	[VCAP_IS2_HK_L4_DPORT]			= {120,  16},
780	[VCAP_IS2_HK_L4_SPORT]			= {136,  16},
781	[VCAP_IS2_HK_L4_RNG]			= {152,   8},
782	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {160,   1},
783	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {161,   1},
784	[VCAP_IS2_HK_L4_FIN]			= {162,   1},
785	[VCAP_IS2_HK_L4_SYN]			= {163,   1},
786	[VCAP_IS2_HK_L4_RST]			= {164,   1},
787	[VCAP_IS2_HK_L4_PSH]			= {165,   1},
788	[VCAP_IS2_HK_L4_ACK]			= {166,   1},
789	[VCAP_IS2_HK_L4_URG]			= {167,   1},
790	[VCAP_IS2_HK_L4_1588_DOM]		= {168,   8},
791	[VCAP_IS2_HK_L4_1588_VER]		= {176,   4},
792	/* IP4_OTHER (TYPE=101) */
793	[VCAP_IS2_HK_IP4_L3_PROTO]		= {119,   8},
794	[VCAP_IS2_HK_L3_PAYLOAD]		= {127,  56},
795	/* IP6_STD (TYPE=110) */
796	[VCAP_IS2_HK_IP6_L3_TTL_GT0]		= { 41,   1},
797	[VCAP_IS2_HK_L3_IP6_SIP]		= { 42, 128},
798	[VCAP_IS2_HK_IP6_L3_PROTO]		= {170,   8},
799	/* OAM (TYPE=111) */
800	[VCAP_IS2_HK_OAM_MEL_FLAGS]		= {137,   7},
801	[VCAP_IS2_HK_OAM_VER]			= {144,   5},
802	[VCAP_IS2_HK_OAM_OPCODE]		= {149,   8},
803	[VCAP_IS2_HK_OAM_FLAGS]			= {157,   8},
804	[VCAP_IS2_HK_OAM_MEPID]			= {165,  16},
805	[VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]		= {181,   1},
806	[VCAP_IS2_HK_OAM_IS_Y1731]		= {182,   1},
807};
808
809static struct vcap_field vsc9959_vcap_is2_actions[] = {
810	[VCAP_IS2_ACT_HIT_ME_ONCE]		= {  0,  1},
811	[VCAP_IS2_ACT_CPU_COPY_ENA]		= {  1,  1},
812	[VCAP_IS2_ACT_CPU_QU_NUM]		= {  2,  3},
813	[VCAP_IS2_ACT_MASK_MODE]		= {  5,  2},
814	[VCAP_IS2_ACT_MIRROR_ENA]		= {  7,  1},
815	[VCAP_IS2_ACT_LRN_DIS]			= {  8,  1},
816	[VCAP_IS2_ACT_POLICE_ENA]		= {  9,  1},
817	[VCAP_IS2_ACT_POLICE_IDX]		= { 10,  9},
818	[VCAP_IS2_ACT_POLICE_VCAP_ONLY]		= { 19,  1},
819	[VCAP_IS2_ACT_PORT_MASK]		= { 20,  6},
820	[VCAP_IS2_ACT_REW_OP]			= { 26,  9},
821	[VCAP_IS2_ACT_SMAC_REPLACE_ENA]		= { 35,  1},
822	[VCAP_IS2_ACT_RSV]			= { 36,  2},
823	[VCAP_IS2_ACT_ACL_ID]			= { 38,  6},
824	[VCAP_IS2_ACT_HIT_CNT]			= { 44, 32},
825};
826
827static struct vcap_props vsc9959_vcap_props[] = {
828	[VCAP_ES0] = {
829		.action_type_width = 0,
830		.action_table = {
831			[ES0_ACTION_TYPE_NORMAL] = {
832				.width = 72, /* HIT_STICKY not included */
833				.count = 1,
834			},
835		},
836		.target = S0,
837		.keys = vsc9959_vcap_es0_keys,
838		.actions = vsc9959_vcap_es0_actions,
839	},
840	[VCAP_IS1] = {
841		.action_type_width = 0,
842		.action_table = {
843			[IS1_ACTION_TYPE_NORMAL] = {
844				.width = 78, /* HIT_STICKY not included */
845				.count = 4,
846			},
847		},
848		.target = S1,
849		.keys = vsc9959_vcap_is1_keys,
850		.actions = vsc9959_vcap_is1_actions,
851	},
852	[VCAP_IS2] = {
853		.action_type_width = 1,
854		.action_table = {
855			[IS2_ACTION_TYPE_NORMAL] = {
856				.width = 44,
857				.count = 2
858			},
859			[IS2_ACTION_TYPE_SMAC_SIP] = {
860				.width = 6,
861				.count = 4
862			},
863		},
864		.target = S2,
865		.keys = vsc9959_vcap_is2_keys,
866		.actions = vsc9959_vcap_is2_actions,
867	},
868};
869
870static const struct ptp_clock_info vsc9959_ptp_caps = {
871	.owner		= THIS_MODULE,
872	.name		= "felix ptp",
873	.max_adj	= 0x7fffffff,
874	.n_alarm	= 0,
875	.n_ext_ts	= 0,
876	.n_per_out	= OCELOT_PTP_PINS_NUM,
877	.n_pins		= OCELOT_PTP_PINS_NUM,
878	.pps		= 0,
879	.gettime64	= ocelot_ptp_gettime64,
880	.settime64	= ocelot_ptp_settime64,
881	.adjtime	= ocelot_ptp_adjtime,
882	.adjfine	= ocelot_ptp_adjfine,
883	.verify		= ocelot_ptp_verify,
884	.enable		= ocelot_ptp_enable,
885};
886
887#define VSC9959_INIT_TIMEOUT			50000
888#define VSC9959_GCB_RST_SLEEP			100
889#define VSC9959_SYS_RAMINIT_SLEEP		80
890
891static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
892{
893	int val;
894
895	ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
896
897	return val;
898}
899
900static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
901{
902	return ocelot_read(ocelot, SYS_RAM_INIT);
903}
904
905/* CORE_ENA is in SYS:SYSTEM:RESET_CFG
906 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
907 */
908static int vsc9959_reset(struct ocelot *ocelot)
909{
910	int val, err;
911
912	/* soft-reset the switch core */
913	ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
914
915	err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
916				 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
917	if (err) {
918		dev_err(ocelot->dev, "timeout: switch core reset\n");
919		return err;
920	}
921
922	/* initialize switch mem ~40us */
923	ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
924	err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
925				 VSC9959_SYS_RAMINIT_SLEEP,
926				 VSC9959_INIT_TIMEOUT);
927	if (err) {
928		dev_err(ocelot->dev, "timeout: switch sram init\n");
929		return err;
930	}
931
932	/* enable switch core */
933	ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
934
935	return 0;
936}
937
938static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
939				     unsigned long *supported,
940				     struct phylink_link_state *state)
941{
942	struct ocelot_port *ocelot_port = ocelot->ports[port];
943	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
944
945	if (state->interface != PHY_INTERFACE_MODE_NA &&
946	    state->interface != ocelot_port->phy_mode) {
947		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
948		return;
949	}
950
951	phylink_set_port_modes(mask);
952	phylink_set(mask, Autoneg);
953	phylink_set(mask, Pause);
954	phylink_set(mask, Asym_Pause);
955	phylink_set(mask, 10baseT_Half);
956	phylink_set(mask, 10baseT_Full);
957	phylink_set(mask, 100baseT_Half);
958	phylink_set(mask, 100baseT_Full);
959	phylink_set(mask, 1000baseT_Half);
960	phylink_set(mask, 1000baseT_Full);
961
962	if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
963	    state->interface == PHY_INTERFACE_MODE_2500BASEX ||
964	    state->interface == PHY_INTERFACE_MODE_USXGMII) {
965		phylink_set(mask, 2500baseT_Full);
966		phylink_set(mask, 2500baseX_Full);
967	}
968
969	bitmap_and(supported, supported, mask,
970		   __ETHTOOL_LINK_MODE_MASK_NBITS);
971	bitmap_and(state->advertising, state->advertising, mask,
972		   __ETHTOOL_LINK_MODE_MASK_NBITS);
973}
974
975static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
976					phy_interface_t phy_mode)
977{
978	switch (phy_mode) {
979	case PHY_INTERFACE_MODE_INTERNAL:
980		if (port != 4 && port != 5)
981			return -ENOTSUPP;
982		return 0;
983	case PHY_INTERFACE_MODE_SGMII:
984	case PHY_INTERFACE_MODE_QSGMII:
985	case PHY_INTERFACE_MODE_USXGMII:
986	case PHY_INTERFACE_MODE_2500BASEX:
987		/* Not supported on internal to-CPU ports */
988		if (port == 4 || port == 5)
989			return -ENOTSUPP;
990		return 0;
991	default:
992		return -ENOTSUPP;
993	}
994}
995
996/* Watermark encode
997 * Bit 8:   Unit; 0:1, 1:16
998 * Bit 7-0: Value to be multiplied with unit
999 */
1000static u16 vsc9959_wm_enc(u16 value)
1001{
1002	WARN_ON(value >= 16 * BIT(8));
1003
1004	if (value >= BIT(8))
1005		return BIT(8) | (value / 16);
1006
1007	return value;
1008}
1009
1010static const struct ocelot_ops vsc9959_ops = {
1011	.reset			= vsc9959_reset,
1012	.wm_enc			= vsc9959_wm_enc,
1013	.port_to_netdev		= felix_port_to_netdev,
1014	.netdev_to_port		= felix_netdev_to_port,
1015};
1016
1017static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1018{
1019	struct felix *felix = ocelot_to_felix(ocelot);
1020	struct enetc_mdio_priv *mdio_priv;
1021	struct device *dev = ocelot->dev;
1022	void __iomem *imdio_regs;
1023	struct resource res;
1024	struct enetc_hw *hw;
1025	struct mii_bus *bus;
1026	int port;
1027	int rc;
1028
1029	felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1030				  sizeof(struct lynx_pcs *),
1031				  GFP_KERNEL);
1032	if (!felix->pcs) {
1033		dev_err(dev, "failed to allocate array for PCS PHYs\n");
1034		return -ENOMEM;
1035	}
1036
1037	memcpy(&res, felix->info->imdio_res, sizeof(res));
1038	res.flags = IORESOURCE_MEM;
1039	res.start += felix->imdio_base;
1040	res.end += felix->imdio_base;
1041
1042	imdio_regs = devm_ioremap_resource(dev, &res);
1043	if (IS_ERR(imdio_regs)) {
1044		dev_err(dev, "failed to map internal MDIO registers\n");
1045		return PTR_ERR(imdio_regs);
1046	}
1047
1048	hw = enetc_hw_alloc(dev, imdio_regs);
1049	if (IS_ERR(hw)) {
1050		dev_err(dev, "failed to allocate ENETC HW structure\n");
1051		return PTR_ERR(hw);
1052	}
1053
1054	bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
1055	if (!bus)
1056		return -ENOMEM;
1057
1058	bus->name = "VSC9959 internal MDIO bus";
1059	bus->read = enetc_mdio_read;
1060	bus->write = enetc_mdio_write;
1061	bus->parent = dev;
1062	mdio_priv = bus->priv;
1063	mdio_priv->hw = hw;
1064	/* This gets added to imdio_regs, which already maps addresses
1065	 * starting with the proper offset.
1066	 */
1067	mdio_priv->mdio_base = 0;
1068	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1069
1070	/* Needed in order to initialize the bus mutex lock */
1071	rc = mdiobus_register(bus);
1072	if (rc < 0) {
1073		dev_err(dev, "failed to register MDIO bus\n");
1074		return rc;
1075	}
1076
1077	felix->imdio = bus;
1078
1079	for (port = 0; port < felix->info->num_ports; port++) {
1080		struct ocelot_port *ocelot_port = ocelot->ports[port];
1081		struct mdio_device *pcs;
1082		struct lynx_pcs *lynx;
1083
1084		if (dsa_is_unused_port(felix->ds, port))
1085			continue;
1086
1087		if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1088			continue;
1089
1090		pcs = mdio_device_create(felix->imdio, port);
1091		if (IS_ERR(pcs))
1092			continue;
1093
1094		lynx = lynx_pcs_create(pcs);
1095		if (!lynx) {
1096			mdio_device_free(pcs);
1097			continue;
1098		}
1099
1100		felix->pcs[port] = lynx;
1101
1102		dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1103	}
1104
1105	return 0;
1106}
1107
1108static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1109{
1110	struct felix *felix = ocelot_to_felix(ocelot);
1111	int port;
1112
1113	for (port = 0; port < ocelot->num_phys_ports; port++) {
1114		struct lynx_pcs *pcs = felix->pcs[port];
1115
1116		if (!pcs)
1117			continue;
1118
1119		mdio_device_free(pcs->mdio);
1120		lynx_pcs_destroy(pcs);
1121	}
1122	mdiobus_unregister(felix->imdio);
1123}
1124
1125static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1126				    u32 speed)
1127{
1128	u8 tas_speed;
1129
1130	switch (speed) {
1131	case SPEED_10:
1132		tas_speed = OCELOT_SPEED_10;
1133		break;
1134	case SPEED_100:
1135		tas_speed = OCELOT_SPEED_100;
1136		break;
1137	case SPEED_1000:
1138		tas_speed = OCELOT_SPEED_1000;
1139		break;
1140	case SPEED_2500:
1141		tas_speed = OCELOT_SPEED_2500;
1142		break;
1143	default:
1144		tas_speed = OCELOT_SPEED_1000;
1145		break;
1146	}
1147
1148	ocelot_rmw_rix(ocelot,
1149		       QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1150		       QSYS_TAG_CONFIG_LINK_SPEED_M,
1151		       QSYS_TAG_CONFIG, port);
1152}
1153
1154static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1155				  u64 cycle_time,
1156				  struct timespec64 *new_base_ts)
1157{
1158	struct timespec64 ts;
1159	ktime_t new_base_time;
1160	ktime_t current_time;
1161
1162	ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1163	current_time = timespec64_to_ktime(ts);
1164	new_base_time = base_time;
1165
1166	if (base_time < current_time) {
1167		u64 nr_of_cycles = current_time - base_time;
1168
1169		do_div(nr_of_cycles, cycle_time);
1170		new_base_time += cycle_time * (nr_of_cycles + 1);
1171	}
1172
1173	*new_base_ts = ktime_to_timespec64(new_base_time);
1174}
1175
1176static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1177{
1178	return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1179}
1180
1181static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1182				struct tc_taprio_sched_entry *entry)
1183{
1184	ocelot_write(ocelot,
1185		     QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1186		     QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1187		     QSYS_GCL_CFG_REG_1);
1188	ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1189}
1190
1191static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1192				    struct tc_taprio_qopt_offload *taprio)
1193{
1194	struct timespec64 base_ts;
1195	int ret, i;
1196	u32 val;
1197
1198	if (!taprio->enable) {
1199		ocelot_rmw_rix(ocelot,
1200			       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1201			       QSYS_TAG_CONFIG_ENABLE |
1202			       QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1203			       QSYS_TAG_CONFIG, port);
1204
1205		return 0;
1206	}
1207
1208	if (taprio->cycle_time > NSEC_PER_SEC ||
1209	    taprio->cycle_time_extension >= NSEC_PER_SEC)
1210		return -EINVAL;
1211
1212	if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1213		return -ERANGE;
1214
1215	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1216		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1217		   QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1218		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1219		   QSYS_TAS_PARAM_CFG_CTRL);
1220
1221	/* Hardware errata -  Admin config could not be overwritten if
1222	 * config is pending, need reset the TAS module
1223	 */
1224	val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1225	if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1226		return  -EBUSY;
1227
1228	ocelot_rmw_rix(ocelot,
1229		       QSYS_TAG_CONFIG_ENABLE |
1230		       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1231		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1232		       QSYS_TAG_CONFIG_ENABLE |
1233		       QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1234		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1235		       QSYS_TAG_CONFIG, port);
1236
1237	vsc9959_new_base_time(ocelot, taprio->base_time,
1238			      taprio->cycle_time, &base_ts);
1239	ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1240	ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1241	val = upper_32_bits(base_ts.tv_sec);
1242	ocelot_write(ocelot,
1243		     QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1244		     QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1245		     QSYS_PARAM_CFG_REG_3);
1246	ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1247	ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1248
1249	for (i = 0; i < taprio->num_entries; i++)
1250		vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1251
1252	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1253		   QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1254		   QSYS_TAS_PARAM_CFG_CTRL);
1255
1256	ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1257				 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1258				 10, 100000);
1259
1260	return ret;
1261}
1262
1263static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1264				    struct tc_cbs_qopt_offload *cbs_qopt)
1265{
1266	struct ocelot *ocelot = ds->priv;
1267	int port_ix = port * 8 + cbs_qopt->queue;
1268	u32 rate, burst;
1269
1270	if (cbs_qopt->queue >= ds->num_tx_queues)
1271		return -EINVAL;
1272
1273	if (!cbs_qopt->enable) {
1274		ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1275				 QSYS_CIR_CFG_CIR_BURST(0),
1276				 QSYS_CIR_CFG, port_ix);
1277
1278		ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1279			       QSYS_SE_CFG, port_ix);
1280
1281		return 0;
1282	}
1283
1284	/* Rate unit is 100 kbps */
1285	rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1286	/* Avoid using zero rate */
1287	rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1288	/* Burst unit is 4kB */
1289	burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1290	/* Avoid using zero burst size */
1291	burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1292	ocelot_write_gix(ocelot,
1293			 QSYS_CIR_CFG_CIR_RATE(rate) |
1294			 QSYS_CIR_CFG_CIR_BURST(burst),
1295			 QSYS_CIR_CFG,
1296			 port_ix);
1297
1298	ocelot_rmw_gix(ocelot,
1299		       QSYS_SE_CFG_SE_FRM_MODE(0) |
1300		       QSYS_SE_CFG_SE_AVB_ENA,
1301		       QSYS_SE_CFG_SE_AVB_ENA |
1302		       QSYS_SE_CFG_SE_FRM_MODE_M,
1303		       QSYS_SE_CFG,
1304		       port_ix);
1305
1306	return 0;
1307}
1308
1309static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1310				 enum tc_setup_type type,
1311				 void *type_data)
1312{
1313	struct ocelot *ocelot = ds->priv;
1314
1315	switch (type) {
1316	case TC_SETUP_QDISC_TAPRIO:
1317		return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1318	case TC_SETUP_QDISC_CBS:
1319		return vsc9959_qos_port_cbs_set(ds, port, type_data);
1320	default:
1321		return -EOPNOTSUPP;
1322	}
1323}
1324
1325static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port)
1326{
1327	struct ocelot_port *ocelot_port = ocelot->ports[port];
1328	u8 *template = ocelot_port->xmit_template;
1329	u64 bypass, dest, src;
1330	__be32 *prefix;
1331	u8 *injection;
1332
1333	/* Set the source port as the CPU port module and not the
1334	 * NPI port
1335	 */
1336	src = ocelot->num_phys_ports;
1337	dest = BIT(port);
1338	bypass = true;
1339
1340	injection = template + OCELOT_SHORT_PREFIX_LEN;
1341	prefix = (__be32 *)template;
1342
1343	packing(injection, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
1344	packing(injection, &dest,    68,  56, OCELOT_TAG_LEN, PACK, 0);
1345	packing(injection, &src,     46,  43, OCELOT_TAG_LEN, PACK, 0);
1346
1347	*prefix = cpu_to_be32(0x8880000a);
1348}
1349
1350static const struct felix_info felix_info_vsc9959 = {
1351	.target_io_res		= vsc9959_target_io_res,
1352	.port_io_res		= vsc9959_port_io_res,
1353	.imdio_res		= &vsc9959_imdio_res,
1354	.regfields		= vsc9959_regfields,
1355	.map			= vsc9959_regmap,
1356	.ops			= &vsc9959_ops,
1357	.stats_layout		= vsc9959_stats_layout,
1358	.num_stats		= ARRAY_SIZE(vsc9959_stats_layout),
1359	.vcap			= vsc9959_vcap_props,
1360	.shared_queue_sz	= 128 * 1024,
1361	.num_mact_rows		= 2048,
1362	.num_ports		= 6,
1363	.num_tx_queues		= FELIX_NUM_TC,
1364	.switch_pci_bar		= 4,
1365	.imdio_pci_bar		= 0,
1366	.ptp_caps		= &vsc9959_ptp_caps,
1367	.mdio_bus_alloc		= vsc9959_mdio_bus_alloc,
1368	.mdio_bus_free		= vsc9959_mdio_bus_free,
1369	.phylink_validate	= vsc9959_phylink_validate,
1370	.prevalidate_phy_mode	= vsc9959_prevalidate_phy_mode,
1371	.port_setup_tc		= vsc9959_port_setup_tc,
1372	.port_sched_speed_set	= vsc9959_sched_speed_set,
1373	.xmit_template_populate	= vsc9959_xmit_template_populate,
1374};
1375
1376static irqreturn_t felix_irq_handler(int irq, void *data)
1377{
1378	struct ocelot *ocelot = (struct ocelot *)data;
1379
1380	/* The INTB interrupt is used for both PTP TX timestamp interrupt
1381	 * and preemption status change interrupt on each port.
1382	 *
1383	 * - Get txtstamp if have
1384	 * - TODO: handle preemption. Without handling it, driver may get
1385	 *   interrupt storm.
1386	 */
1387
1388	ocelot_get_txtstamp(ocelot);
1389
1390	return IRQ_HANDLED;
1391}
1392
1393static int felix_pci_probe(struct pci_dev *pdev,
1394			   const struct pci_device_id *id)
1395{
1396	struct dsa_switch *ds;
1397	struct ocelot *ocelot;
1398	struct felix *felix;
1399	int err;
1400
1401	if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
1402		dev_info(&pdev->dev, "device is disabled, skipping\n");
1403		return -ENODEV;
1404	}
1405
1406	err = pci_enable_device(pdev);
1407	if (err) {
1408		dev_err(&pdev->dev, "device enable failed\n");
1409		goto err_pci_enable;
1410	}
1411
1412	/* set up for high or low dma */
1413	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1414	if (err) {
1415		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1416		if (err) {
1417			dev_err(&pdev->dev,
1418				"DMA configuration failed: 0x%x\n", err);
1419			goto err_dma;
1420		}
1421	}
1422
1423	felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1424	if (!felix) {
1425		err = -ENOMEM;
1426		dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1427		goto err_alloc_felix;
1428	}
1429
1430	pci_set_drvdata(pdev, felix);
1431	ocelot = &felix->ocelot;
1432	ocelot->dev = &pdev->dev;
1433	ocelot->num_flooding_pgids = FELIX_NUM_TC;
1434	felix->info = &felix_info_vsc9959;
1435	felix->switch_base = pci_resource_start(pdev,
1436						felix->info->switch_pci_bar);
1437	felix->imdio_base = pci_resource_start(pdev,
1438					       felix->info->imdio_pci_bar);
1439
1440	pci_set_master(pdev);
1441
1442	err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
1443					&felix_irq_handler, IRQF_ONESHOT,
1444					"felix-intb", ocelot);
1445	if (err) {
1446		dev_err(&pdev->dev, "Failed to request irq\n");
1447		goto err_alloc_irq;
1448	}
1449
1450	ocelot->ptp = 1;
1451
1452	ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1453	if (!ds) {
1454		err = -ENOMEM;
1455		dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1456		goto err_alloc_ds;
1457	}
1458
1459	ds->dev = &pdev->dev;
1460	ds->num_ports = felix->info->num_ports;
1461	ds->num_tx_queues = felix->info->num_tx_queues;
1462	ds->ops = &felix_switch_ops;
1463	ds->priv = ocelot;
1464	felix->ds = ds;
1465
1466	err = dsa_register_switch(ds);
1467	if (err) {
1468		dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n");
1469		goto err_register_ds;
1470	}
1471
1472	return 0;
1473
1474err_register_ds:
1475	kfree(ds);
1476err_alloc_ds:
1477err_alloc_irq:
1478err_alloc_felix:
1479	kfree(felix);
1480err_dma:
1481	pci_disable_device(pdev);
1482err_pci_enable:
1483	return err;
1484}
1485
1486static void felix_pci_remove(struct pci_dev *pdev)
1487{
1488	struct felix *felix;
1489
1490	felix = pci_get_drvdata(pdev);
1491
1492	dsa_unregister_switch(felix->ds);
1493
1494	kfree(felix->ds);
1495	kfree(felix);
1496
1497	pci_disable_device(pdev);
1498}
1499
1500static struct pci_device_id felix_ids[] = {
1501	{
1502		/* NXP LS1028A */
1503		PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
1504	},
1505	{ 0, }
1506};
1507MODULE_DEVICE_TABLE(pci, felix_ids);
1508
1509static struct pci_driver felix_vsc9959_pci_driver = {
1510	.name		= "mscc_felix",
1511	.id_table	= felix_ids,
1512	.probe		= felix_pci_probe,
1513	.remove		= felix_pci_remove,
1514};
1515module_pci_driver(felix_vsc9959_pci_driver);
1516
1517MODULE_DESCRIPTION("Felix Switch driver");
1518MODULE_LICENSE("GPL v2");
1519