1// SPDX-License-Identifier: GPL-2.0 2/* Copyright 2019 NXP Semiconductors 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8#include <uapi/linux/if_bridge.h> 9#include <soc/mscc/ocelot_vcap.h> 10#include <soc/mscc/ocelot_qsys.h> 11#include <soc/mscc/ocelot_sys.h> 12#include <soc/mscc/ocelot_dev.h> 13#include <soc/mscc/ocelot_ana.h> 14#include <soc/mscc/ocelot_ptp.h> 15#include <soc/mscc/ocelot.h> 16#include <linux/platform_device.h> 17#include <linux/packing.h> 18#include <linux/module.h> 19#include <linux/of_net.h> 20#include <linux/pci.h> 21#include <linux/of.h> 22#include <linux/pcs-lynx.h> 23#include <net/pkt_sched.h> 24#include <net/dsa.h> 25#include "felix.h" 26 27static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 28 int port, 29 enum dsa_tag_protocol mp) 30{ 31 return DSA_TAG_PROTO_OCELOT; 32} 33 34static int felix_set_ageing_time(struct dsa_switch *ds, 35 unsigned int ageing_time) 36{ 37 struct ocelot *ocelot = ds->priv; 38 39 ocelot_set_ageing_time(ocelot, ageing_time); 40 41 return 0; 42} 43 44static int felix_fdb_dump(struct dsa_switch *ds, int port, 45 dsa_fdb_dump_cb_t *cb, void *data) 46{ 47 struct ocelot *ocelot = ds->priv; 48 49 return ocelot_fdb_dump(ocelot, port, cb, data); 50} 51 52static int felix_fdb_add(struct dsa_switch *ds, int port, 53 const unsigned char *addr, u16 vid) 54{ 55 struct ocelot *ocelot = ds->priv; 56 57 return ocelot_fdb_add(ocelot, port, addr, vid); 58} 59 60static int felix_fdb_del(struct dsa_switch *ds, int port, 61 const unsigned char *addr, u16 vid) 62{ 63 struct ocelot *ocelot = ds->priv; 64 65 return ocelot_fdb_del(ocelot, port, addr, vid); 66} 67 68/* This callback needs to be present */ 69static int felix_mdb_prepare(struct dsa_switch *ds, int port, 70 const struct switchdev_obj_port_mdb *mdb) 71{ 72 return 0; 73} 74 75static void felix_mdb_add(struct dsa_switch *ds, int port, 76 const struct switchdev_obj_port_mdb *mdb) 77{ 78 struct ocelot *ocelot = ds->priv; 79 80 ocelot_port_mdb_add(ocelot, port, mdb); 81} 82 83static int felix_mdb_del(struct dsa_switch *ds, int port, 84 const struct switchdev_obj_port_mdb *mdb) 85{ 86 struct ocelot *ocelot = ds->priv; 87 88 return ocelot_port_mdb_del(ocelot, port, mdb); 89} 90 91static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 92 u8 state) 93{ 94 struct ocelot *ocelot = ds->priv; 95 96 return ocelot_bridge_stp_state_set(ocelot, port, state); 97} 98 99static int felix_bridge_join(struct dsa_switch *ds, int port, 100 struct net_device *br) 101{ 102 struct ocelot *ocelot = ds->priv; 103 104 return ocelot_port_bridge_join(ocelot, port, br); 105} 106 107static void felix_bridge_leave(struct dsa_switch *ds, int port, 108 struct net_device *br) 109{ 110 struct ocelot *ocelot = ds->priv; 111 112 ocelot_port_bridge_leave(ocelot, port, br); 113} 114 115/* This callback needs to be present */ 116static int felix_vlan_prepare(struct dsa_switch *ds, int port, 117 const struct switchdev_obj_port_vlan *vlan) 118{ 119 return 0; 120} 121 122static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 123 struct switchdev_trans *trans) 124{ 125 struct ocelot *ocelot = ds->priv; 126 127 return ocelot_port_vlan_filtering(ocelot, port, enabled, trans); 128} 129 130static void felix_vlan_add(struct dsa_switch *ds, int port, 131 const struct switchdev_obj_port_vlan *vlan) 132{ 133 struct ocelot *ocelot = ds->priv; 134 u16 flags = vlan->flags; 135 u16 vid; 136 int err; 137 138 if (dsa_is_cpu_port(ds, port)) 139 flags &= ~BRIDGE_VLAN_INFO_UNTAGGED; 140 141 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 142 err = ocelot_vlan_add(ocelot, port, vid, 143 flags & BRIDGE_VLAN_INFO_PVID, 144 flags & BRIDGE_VLAN_INFO_UNTAGGED); 145 if (err) { 146 dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n", 147 vid, port, err); 148 return; 149 } 150 } 151} 152 153static int felix_vlan_del(struct dsa_switch *ds, int port, 154 const struct switchdev_obj_port_vlan *vlan) 155{ 156 struct ocelot *ocelot = ds->priv; 157 u16 vid; 158 int err; 159 160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 161 err = ocelot_vlan_del(ocelot, port, vid); 162 if (err) { 163 dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n", 164 vid, port, err); 165 return err; 166 } 167 } 168 return 0; 169} 170 171static int felix_port_enable(struct dsa_switch *ds, int port, 172 struct phy_device *phy) 173{ 174 struct ocelot *ocelot = ds->priv; 175 176 ocelot_port_enable(ocelot, port, phy); 177 178 return 0; 179} 180 181static void felix_port_disable(struct dsa_switch *ds, int port) 182{ 183 struct ocelot *ocelot = ds->priv; 184 185 return ocelot_port_disable(ocelot, port); 186} 187 188static void felix_phylink_validate(struct dsa_switch *ds, int port, 189 unsigned long *supported, 190 struct phylink_link_state *state) 191{ 192 struct ocelot *ocelot = ds->priv; 193 struct felix *felix = ocelot_to_felix(ocelot); 194 195 if (felix->info->phylink_validate) 196 felix->info->phylink_validate(ocelot, port, supported, state); 197} 198 199static void felix_phylink_mac_config(struct dsa_switch *ds, int port, 200 unsigned int link_an_mode, 201 const struct phylink_link_state *state) 202{ 203 struct ocelot *ocelot = ds->priv; 204 struct felix *felix = ocelot_to_felix(ocelot); 205 struct dsa_port *dp = dsa_to_port(ds, port); 206 207 if (felix->pcs[port]) 208 phylink_set_pcs(dp->pl, &felix->pcs[port]->pcs); 209} 210 211static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 212 unsigned int link_an_mode, 213 phy_interface_t interface) 214{ 215 struct ocelot *ocelot = ds->priv; 216 struct ocelot_port *ocelot_port = ocelot->ports[port]; 217 int err; 218 219 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 220 DEV_MAC_ENA_CFG); 221 222 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 223 224 err = ocelot_port_flush(ocelot, port); 225 if (err) 226 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 227 port, err); 228 229 /* Put the port in reset. */ 230 ocelot_port_writel(ocelot_port, 231 DEV_CLOCK_CFG_MAC_TX_RST | 232 DEV_CLOCK_CFG_MAC_RX_RST | 233 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), 234 DEV_CLOCK_CFG); 235} 236 237static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 238 unsigned int link_an_mode, 239 phy_interface_t interface, 240 struct phy_device *phydev, 241 int speed, int duplex, 242 bool tx_pause, bool rx_pause) 243{ 244 struct ocelot *ocelot = ds->priv; 245 struct ocelot_port *ocelot_port = ocelot->ports[port]; 246 struct felix *felix = ocelot_to_felix(ocelot); 247 u32 mac_fc_cfg; 248 249 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 250 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is 251 * integrated is that the MAC speed is fixed and it's the PCS who is 252 * performing the rate adaptation, so we have to write "1000Mbps" into 253 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default 254 * value). 255 */ 256 ocelot_port_writel(ocelot_port, 257 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), 258 DEV_CLOCK_CFG); 259 260 switch (speed) { 261 case SPEED_10: 262 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3); 263 break; 264 case SPEED_100: 265 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2); 266 break; 267 case SPEED_1000: 268 case SPEED_2500: 269 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1); 270 break; 271 default: 272 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 273 port, speed); 274 return; 275 } 276 277 /* handle Rx pause in all cases, with 2500base-X this is used for rate 278 * adaptation. 279 */ 280 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 281 282 if (tx_pause) 283 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 284 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 285 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 286 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 287 288 /* Flow control. Link speed is only used here to evaluate the time 289 * specification in incoming pause frames. 290 */ 291 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 292 293 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 294 295 /* Undo the effects of felix_phylink_mac_link_down: 296 * enable MAC module 297 */ 298 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 299 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 300 301 /* Enable receiving frames on the port, and activate auto-learning of 302 * MAC addresses. 303 */ 304 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 305 ANA_PORT_PORT_CFG_RECV_ENA | 306 ANA_PORT_PORT_CFG_PORTID_VAL(port), 307 ANA_PORT_PORT_CFG, port); 308 309 /* Core: Enable port for frame transfer */ 310 ocelot_fields_write(ocelot, port, 311 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 312 313 if (felix->info->port_sched_speed_set) 314 felix->info->port_sched_speed_set(ocelot, port, speed); 315} 316 317static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 318{ 319 int i; 320 321 ocelot_rmw_gix(ocelot, 322 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 323 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 324 ANA_PORT_QOS_CFG, 325 port); 326 327 for (i = 0; i < FELIX_NUM_TC * 2; i++) { 328 ocelot_rmw_ix(ocelot, 329 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 330 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 331 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 332 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 333 ANA_PORT_PCP_DEI_MAP, 334 port, i); 335 } 336} 337 338static void felix_get_strings(struct dsa_switch *ds, int port, 339 u32 stringset, u8 *data) 340{ 341 struct ocelot *ocelot = ds->priv; 342 343 return ocelot_get_strings(ocelot, port, stringset, data); 344} 345 346static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 347{ 348 struct ocelot *ocelot = ds->priv; 349 350 ocelot_get_ethtool_stats(ocelot, port, data); 351} 352 353static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 354{ 355 struct ocelot *ocelot = ds->priv; 356 357 return ocelot_get_sset_count(ocelot, port, sset); 358} 359 360static int felix_get_ts_info(struct dsa_switch *ds, int port, 361 struct ethtool_ts_info *info) 362{ 363 struct ocelot *ocelot = ds->priv; 364 365 return ocelot_get_ts_info(ocelot, port, info); 366} 367 368static int felix_parse_ports_node(struct felix *felix, 369 struct device_node *ports_node, 370 phy_interface_t *port_phy_modes) 371{ 372 struct ocelot *ocelot = &felix->ocelot; 373 struct device *dev = felix->ocelot.dev; 374 struct device_node *child; 375 376 for_each_available_child_of_node(ports_node, child) { 377 phy_interface_t phy_mode; 378 u32 port; 379 int err; 380 381 /* Get switch port number from DT */ 382 if (of_property_read_u32(child, "reg", &port) < 0) { 383 dev_err(dev, "Port number not defined in device tree " 384 "(property \"reg\")\n"); 385 of_node_put(child); 386 return -ENODEV; 387 } 388 389 /* Get PHY mode from DT */ 390 err = of_get_phy_mode(child, &phy_mode); 391 if (err) { 392 dev_err(dev, "Failed to read phy-mode or " 393 "phy-interface-type property for port %d\n", 394 port); 395 of_node_put(child); 396 return -ENODEV; 397 } 398 399 err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode); 400 if (err < 0) { 401 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 402 phy_modes(phy_mode), port); 403 of_node_put(child); 404 return err; 405 } 406 407 port_phy_modes[port] = phy_mode; 408 } 409 410 return 0; 411} 412 413static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 414{ 415 struct device *dev = felix->ocelot.dev; 416 struct device_node *switch_node; 417 struct device_node *ports_node; 418 int err; 419 420 switch_node = dev->of_node; 421 422 ports_node = of_get_child_by_name(switch_node, "ports"); 423 if (!ports_node) { 424 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); 425 return -ENODEV; 426 } 427 428 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 429 of_node_put(ports_node); 430 431 return err; 432} 433 434static int felix_init_structs(struct felix *felix, int num_phys_ports) 435{ 436 struct ocelot *ocelot = &felix->ocelot; 437 phy_interface_t *port_phy_modes; 438 struct resource res; 439 int port, i, err; 440 441 ocelot->num_phys_ports = num_phys_ports; 442 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 443 sizeof(struct ocelot_port *), GFP_KERNEL); 444 if (!ocelot->ports) 445 return -ENOMEM; 446 447 ocelot->map = felix->info->map; 448 ocelot->stats_layout = felix->info->stats_layout; 449 ocelot->num_stats = felix->info->num_stats; 450 ocelot->shared_queue_sz = felix->info->shared_queue_sz; 451 ocelot->num_mact_rows = felix->info->num_mact_rows; 452 ocelot->vcap = felix->info->vcap; 453 ocelot->ops = felix->info->ops; 454 ocelot->inj_prefix = OCELOT_TAG_PREFIX_SHORT; 455 ocelot->xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 456 457 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 458 GFP_KERNEL); 459 if (!port_phy_modes) 460 return -ENOMEM; 461 462 err = felix_parse_dt(felix, port_phy_modes); 463 if (err) { 464 kfree(port_phy_modes); 465 return err; 466 } 467 468 for (i = 0; i < TARGET_MAX; i++) { 469 struct regmap *target; 470 471 if (!felix->info->target_io_res[i].name) 472 continue; 473 474 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 475 res.flags = IORESOURCE_MEM; 476 res.start += felix->switch_base; 477 res.end += felix->switch_base; 478 479 target = ocelot_regmap_init(ocelot, &res); 480 if (IS_ERR(target)) { 481 dev_err(ocelot->dev, 482 "Failed to map device memory space\n"); 483 kfree(port_phy_modes); 484 return PTR_ERR(target); 485 } 486 487 ocelot->targets[i] = target; 488 } 489 490 err = ocelot_regfields_init(ocelot, felix->info->regfields); 491 if (err) { 492 dev_err(ocelot->dev, "failed to init reg fields map\n"); 493 kfree(port_phy_modes); 494 return err; 495 } 496 497 for (port = 0; port < num_phys_ports; port++) { 498 struct ocelot_port *ocelot_port; 499 struct regmap *target; 500 u8 *template; 501 502 ocelot_port = devm_kzalloc(ocelot->dev, 503 sizeof(struct ocelot_port), 504 GFP_KERNEL); 505 if (!ocelot_port) { 506 dev_err(ocelot->dev, 507 "failed to allocate port memory\n"); 508 kfree(port_phy_modes); 509 return -ENOMEM; 510 } 511 512 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 513 res.flags = IORESOURCE_MEM; 514 res.start += felix->switch_base; 515 res.end += felix->switch_base; 516 517 target = ocelot_regmap_init(ocelot, &res); 518 if (IS_ERR(target)) { 519 dev_err(ocelot->dev, 520 "Failed to map memory space for port %d\n", 521 port); 522 kfree(port_phy_modes); 523 return PTR_ERR(target); 524 } 525 526 template = devm_kzalloc(ocelot->dev, OCELOT_TOTAL_TAG_LEN, 527 GFP_KERNEL); 528 if (!template) { 529 dev_err(ocelot->dev, 530 "Failed to allocate memory for DSA tag\n"); 531 kfree(port_phy_modes); 532 return -ENOMEM; 533 } 534 535 ocelot_port->phy_mode = port_phy_modes[port]; 536 ocelot_port->ocelot = ocelot; 537 ocelot_port->target = target; 538 ocelot_port->xmit_template = template; 539 ocelot->ports[port] = ocelot_port; 540 541 felix->info->xmit_template_populate(ocelot, port); 542 } 543 544 kfree(port_phy_modes); 545 546 if (felix->info->mdio_bus_alloc) { 547 err = felix->info->mdio_bus_alloc(ocelot); 548 if (err < 0) 549 return err; 550 } 551 552 return 0; 553} 554 555/* The CPU port module is connected to the Node Processor Interface (NPI). This 556 * is the mode through which frames can be injected from and extracted to an 557 * external CPU, over Ethernet. 558 */ 559static void felix_npi_port_init(struct ocelot *ocelot, int port) 560{ 561 ocelot->npi = port; 562 563 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 564 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 565 QSYS_EXT_CPU_CFG); 566 567 /* NPI port Injection/Extraction configuration */ 568 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 569 ocelot->xtr_prefix); 570 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 571 ocelot->inj_prefix); 572 573 /* Disable transmission of pause frames */ 574 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 575} 576 577/* Hardware initialization done here so that we can allocate structures with 578 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 579 * us to allocate structures twice (leak memory) and map PCI memory twice 580 * (which will not work). 581 */ 582static int felix_setup(struct dsa_switch *ds) 583{ 584 struct ocelot *ocelot = ds->priv; 585 struct felix *felix = ocelot_to_felix(ocelot); 586 int port, err; 587 588 err = felix_init_structs(felix, ds->num_ports); 589 if (err) 590 return err; 591 592 err = ocelot_init(ocelot); 593 if (err) 594 return err; 595 596 if (ocelot->ptp) { 597 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 598 if (err) { 599 dev_err(ocelot->dev, 600 "Timestamp initialization failed\n"); 601 ocelot->ptp = 0; 602 } 603 } 604 605 for (port = 0; port < ds->num_ports; port++) { 606 ocelot_init_port(ocelot, port); 607 608 if (dsa_is_cpu_port(ds, port)) 609 felix_npi_port_init(ocelot, port); 610 611 /* Set the default QoS Classification based on PCP and DEI 612 * bits of vlan tag. 613 */ 614 felix_port_qos_map_init(ocelot, port); 615 } 616 617 /* Include the CPU port module in the forwarding mask for unknown 618 * unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST 619 * excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since 620 * Ocelot relies on whitelisting MAC addresses towards PGID_CPU. 621 */ 622 ocelot_write_rix(ocelot, 623 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 624 ANA_PGID_PGID, PGID_UC); 625 626 ds->mtu_enforcement_ingress = true; 627 ds->configure_vlan_while_not_filtering = true; 628 629 return 0; 630} 631 632static void felix_teardown(struct dsa_switch *ds) 633{ 634 struct ocelot *ocelot = ds->priv; 635 struct felix *felix = ocelot_to_felix(ocelot); 636 int port; 637 638 ocelot_deinit_timestamp(ocelot); 639 ocelot_deinit(ocelot); 640 641 for (port = 0; port < ocelot->num_phys_ports; port++) { 642 if (dsa_is_unused_port(ds, port)) 643 continue; 644 645 ocelot_deinit_port(ocelot, port); 646 } 647 648 if (felix->info->mdio_bus_free) 649 felix->info->mdio_bus_free(ocelot); 650} 651 652static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 653 struct ifreq *ifr) 654{ 655 struct ocelot *ocelot = ds->priv; 656 657 return ocelot_hwstamp_get(ocelot, port, ifr); 658} 659 660static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 661 struct ifreq *ifr) 662{ 663 struct ocelot *ocelot = ds->priv; 664 665 return ocelot_hwstamp_set(ocelot, port, ifr); 666} 667 668static bool felix_rxtstamp(struct dsa_switch *ds, int port, 669 struct sk_buff *skb, unsigned int type) 670{ 671 struct skb_shared_hwtstamps *shhwtstamps; 672 struct ocelot *ocelot = ds->priv; 673 u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN; 674 u32 tstamp_lo, tstamp_hi; 675 struct timespec64 ts; 676 u64 tstamp, val; 677 678 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 679 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 680 681 packing(extraction, &val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0); 682 tstamp_lo = (u32)val; 683 684 tstamp_hi = tstamp >> 32; 685 if ((tstamp & 0xffffffff) < tstamp_lo) 686 tstamp_hi--; 687 688 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 689 690 shhwtstamps = skb_hwtstamps(skb); 691 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 692 shhwtstamps->hwtstamp = tstamp; 693 return false; 694} 695 696static bool felix_txtstamp(struct dsa_switch *ds, int port, 697 struct sk_buff *clone, unsigned int type) 698{ 699 struct ocelot *ocelot = ds->priv; 700 struct ocelot_port *ocelot_port = ocelot->ports[port]; 701 702 if (ocelot->ptp && (skb_shinfo(clone)->tx_flags & SKBTX_HW_TSTAMP) && 703 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 704 ocelot_port_add_txtstamp_skb(ocelot, port, clone); 705 return true; 706 } 707 708 return false; 709} 710 711static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 712{ 713 struct ocelot *ocelot = ds->priv; 714 715 ocelot_port_set_maxlen(ocelot, port, new_mtu); 716 717 return 0; 718} 719 720static int felix_get_max_mtu(struct dsa_switch *ds, int port) 721{ 722 struct ocelot *ocelot = ds->priv; 723 724 return ocelot_get_max_mtu(ocelot, port); 725} 726 727static int felix_cls_flower_add(struct dsa_switch *ds, int port, 728 struct flow_cls_offload *cls, bool ingress) 729{ 730 struct ocelot *ocelot = ds->priv; 731 732 return ocelot_cls_flower_replace(ocelot, port, cls, ingress); 733} 734 735static int felix_cls_flower_del(struct dsa_switch *ds, int port, 736 struct flow_cls_offload *cls, bool ingress) 737{ 738 struct ocelot *ocelot = ds->priv; 739 740 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 741} 742 743static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 744 struct flow_cls_offload *cls, bool ingress) 745{ 746 struct ocelot *ocelot = ds->priv; 747 748 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 749} 750 751static int felix_port_policer_add(struct dsa_switch *ds, int port, 752 struct dsa_mall_policer_tc_entry *policer) 753{ 754 struct ocelot *ocelot = ds->priv; 755 struct ocelot_policer pol = { 756 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 757 .burst = policer->burst, 758 }; 759 760 return ocelot_port_policer_add(ocelot, port, &pol); 761} 762 763static void felix_port_policer_del(struct dsa_switch *ds, int port) 764{ 765 struct ocelot *ocelot = ds->priv; 766 767 ocelot_port_policer_del(ocelot, port); 768} 769 770static int felix_port_setup_tc(struct dsa_switch *ds, int port, 771 enum tc_setup_type type, 772 void *type_data) 773{ 774 struct ocelot *ocelot = ds->priv; 775 struct felix *felix = ocelot_to_felix(ocelot); 776 777 if (felix->info->port_setup_tc) 778 return felix->info->port_setup_tc(ds, port, type, type_data); 779 else 780 return -EOPNOTSUPP; 781} 782 783const struct dsa_switch_ops felix_switch_ops = { 784 .get_tag_protocol = felix_get_tag_protocol, 785 .setup = felix_setup, 786 .teardown = felix_teardown, 787 .set_ageing_time = felix_set_ageing_time, 788 .get_strings = felix_get_strings, 789 .get_ethtool_stats = felix_get_ethtool_stats, 790 .get_sset_count = felix_get_sset_count, 791 .get_ts_info = felix_get_ts_info, 792 .phylink_validate = felix_phylink_validate, 793 .phylink_mac_config = felix_phylink_mac_config, 794 .phylink_mac_link_down = felix_phylink_mac_link_down, 795 .phylink_mac_link_up = felix_phylink_mac_link_up, 796 .port_enable = felix_port_enable, 797 .port_disable = felix_port_disable, 798 .port_fdb_dump = felix_fdb_dump, 799 .port_fdb_add = felix_fdb_add, 800 .port_fdb_del = felix_fdb_del, 801 .port_mdb_prepare = felix_mdb_prepare, 802 .port_mdb_add = felix_mdb_add, 803 .port_mdb_del = felix_mdb_del, 804 .port_bridge_join = felix_bridge_join, 805 .port_bridge_leave = felix_bridge_leave, 806 .port_stp_state_set = felix_bridge_stp_state_set, 807 .port_vlan_prepare = felix_vlan_prepare, 808 .port_vlan_filtering = felix_vlan_filtering, 809 .port_vlan_add = felix_vlan_add, 810 .port_vlan_del = felix_vlan_del, 811 .port_hwtstamp_get = felix_hwtstamp_get, 812 .port_hwtstamp_set = felix_hwtstamp_set, 813 .port_rxtstamp = felix_rxtstamp, 814 .port_txtstamp = felix_txtstamp, 815 .port_change_mtu = felix_change_mtu, 816 .port_max_mtu = felix_get_max_mtu, 817 .port_policer_add = felix_port_policer_add, 818 .port_policer_del = felix_port_policer_del, 819 .cls_flower_add = felix_cls_flower_add, 820 .cls_flower_del = felix_cls_flower_del, 821 .cls_flower_stats = felix_cls_flower_stats, 822 .port_setup_tc = felix_port_setup_tc, 823}; 824 825struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 826{ 827 struct felix *felix = ocelot_to_felix(ocelot); 828 struct dsa_switch *ds = felix->ds; 829 830 if (!dsa_is_user_port(ds, port)) 831 return NULL; 832 833 return dsa_to_port(ds, port)->slave; 834} 835 836int felix_netdev_to_port(struct net_device *dev) 837{ 838 struct dsa_port *dp; 839 840 dp = dsa_port_from_netdev(dev); 841 if (IS_ERR(dp)) 842 return -EINVAL; 843 844 return dp->index; 845} 846