1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11#include <linux/bitfield.h> 12 13#include "chip.h" 14#include "global1.h" 15 16int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17{ 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21} 22 23int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24{ 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28} 29 30int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 31 bit, int val) 32{ 33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 34 bit, val); 35} 36 37int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38 u16 mask, u16 val) 39{ 40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41 mask, val); 42} 43 44/* Offset 0x00: Switch Global Status Register */ 45 46static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47{ 48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49 MV88E6185_G1_STS_PPU_STATE_MASK, 50 MV88E6185_G1_STS_PPU_STATE_DISABLED); 51} 52 53static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 54{ 55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56 MV88E6185_G1_STS_PPU_STATE_MASK, 57 MV88E6185_G1_STS_PPU_STATE_POLLING); 58} 59 60static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 61{ 62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 63 64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 65} 66 67static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 68{ 69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 70 71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 72 * is set to a one when all units inside the device (ATU, VTU, etc.) 73 * have finished their initialization and are ready to accept frames. 74 */ 75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 76} 77 78/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 79 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 80 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 81 */ 82int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 83{ 84 u16 reg; 85 int err; 86 87 reg = (addr[0] << 8) | addr[1]; 88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 89 if (err) 90 return err; 91 92 reg = (addr[2] << 8) | addr[3]; 93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 94 if (err) 95 return err; 96 97 reg = (addr[4] << 8) | addr[5]; 98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 99 if (err) 100 return err; 101 102 return 0; 103} 104 105/* Offset 0x04: Switch Global Control Register */ 106 107int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 108{ 109 u16 val; 110 int err; 111 112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 113 * the PPU, including re-doing PHY detection and initialization 114 */ 115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 116 if (err) 117 return err; 118 119 val |= MV88E6XXX_G1_CTL1_SW_RESET; 120 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 121 122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 123 if (err) 124 return err; 125 126 err = mv88e6xxx_g1_wait_init_ready(chip); 127 if (err) 128 return err; 129 130 return mv88e6185_g1_wait_ppu_polling(chip); 131} 132 133int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 134{ 135 u16 val; 136 int err; 137 138 /* Set the SWReset bit 15 */ 139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 140 if (err) 141 return err; 142 143 val |= MV88E6XXX_G1_CTL1_SW_RESET; 144 145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 146 if (err) 147 return err; 148 149 return mv88e6xxx_g1_wait_init_ready(chip); 150} 151 152int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 153{ 154 int err; 155 156 err = mv88e6250_g1_reset(chip); 157 if (err) 158 return err; 159 160 return mv88e6352_g1_wait_ppu_polling(chip); 161} 162 163int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 164{ 165 u16 val; 166 int err; 167 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 169 if (err) 170 return err; 171 172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175 if (err) 176 return err; 177 178 return mv88e6185_g1_wait_ppu_polling(chip); 179} 180 181int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 182{ 183 u16 val; 184 int err; 185 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 187 if (err) 188 return err; 189 190 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 191 192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 193 if (err) 194 return err; 195 196 return mv88e6185_g1_wait_ppu_disabled(chip); 197} 198 199int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) 200{ 201 u16 val; 202 int err; 203 204 mtu += ETH_HLEN + ETH_FCS_LEN; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 207 if (err) 208 return err; 209 210 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; 211 212 if (mtu > 1518) 213 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; 214 215 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 216} 217 218/* Offset 0x10: IP-PRI Mapping Register 0 219 * Offset 0x11: IP-PRI Mapping Register 1 220 * Offset 0x12: IP-PRI Mapping Register 2 221 * Offset 0x13: IP-PRI Mapping Register 3 222 * Offset 0x14: IP-PRI Mapping Register 4 223 * Offset 0x15: IP-PRI Mapping Register 5 224 * Offset 0x16: IP-PRI Mapping Register 6 225 * Offset 0x17: IP-PRI Mapping Register 7 226 */ 227 228int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 229{ 230 int err; 231 232 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 233 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 234 if (err) 235 return err; 236 237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 238 if (err) 239 return err; 240 241 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 242 if (err) 243 return err; 244 245 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 246 if (err) 247 return err; 248 249 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 250 if (err) 251 return err; 252 253 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 254 if (err) 255 return err; 256 257 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 258 if (err) 259 return err; 260 261 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 262 if (err) 263 return err; 264 265 return 0; 266} 267 268/* Offset 0x18: IEEE-PRI Register */ 269 270int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 271{ 272 /* Reset the IEEE Tag priorities to defaults */ 273 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 274} 275 276int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 277{ 278 /* Reset the IEEE Tag priorities to defaults */ 279 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 280} 281 282/* Offset 0x1a: Monitor Control */ 283/* Offset 0x1a: Monitor & MGMT Control on some devices */ 284 285int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 286 enum mv88e6xxx_egress_direction direction, 287 int port) 288{ 289 int *dest_port_chip; 290 u16 reg; 291 int err; 292 293 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 294 if (err) 295 return err; 296 297 switch (direction) { 298 case MV88E6XXX_EGRESS_DIR_INGRESS: 299 dest_port_chip = &chip->ingress_dest_port; 300 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 301 reg |= port << 302 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 303 break; 304 case MV88E6XXX_EGRESS_DIR_EGRESS: 305 dest_port_chip = &chip->egress_dest_port; 306 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 307 reg |= port << 308 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 309 break; 310 default: 311 return -EINVAL; 312 } 313 314 err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 315 if (!err) 316 *dest_port_chip = port; 317 318 return err; 319} 320 321/* Older generations also call this the ARP destination. It has been 322 * generalized in more modern devices such that more than ARP can 323 * egress it 324 */ 325int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 326{ 327 u16 reg; 328 int err; 329 330 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 331 if (err) 332 return err; 333 334 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 335 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 336 337 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 338} 339 340static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 341 u16 pointer, u8 data) 342{ 343 u16 reg; 344 345 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 346 347 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 348} 349 350int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 351 enum mv88e6xxx_egress_direction direction, 352 int port) 353{ 354 int *dest_port_chip; 355 u16 ptr; 356 int err; 357 358 switch (direction) { 359 case MV88E6XXX_EGRESS_DIR_INGRESS: 360 dest_port_chip = &chip->ingress_dest_port; 361 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 362 break; 363 case MV88E6XXX_EGRESS_DIR_EGRESS: 364 dest_port_chip = &chip->egress_dest_port; 365 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 err = mv88e6390_g1_monitor_write(chip, ptr, port); 372 if (!err) 373 *dest_port_chip = port; 374 375 return err; 376} 377 378int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 379{ 380 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 381 382 /* Use the default high priority for management frames sent to 383 * the CPU. 384 */ 385 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 386 387 return mv88e6390_g1_monitor_write(chip, ptr, port); 388} 389 390int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 391{ 392 u16 ptr; 393 int err; 394 395 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 396 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 397 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 398 if (err) 399 return err; 400 401 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 402 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 403 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 404 if (err) 405 return err; 406 407 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 408 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 409 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 410 if (err) 411 return err; 412 413 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 414 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 415 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 416 if (err) 417 return err; 418 419 return 0; 420} 421 422/* Offset 0x1c: Global Control 2 */ 423 424static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 425 u16 val) 426{ 427 u16 reg; 428 int err; 429 430 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 431 if (err) 432 return err; 433 434 reg &= ~mask; 435 reg |= val & mask; 436 437 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 438} 439 440int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 441{ 442 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 443 444 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 445} 446 447int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 448{ 449 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 450 MV88E6085_G1_CTL2_RM_ENABLE, 0); 451} 452 453int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 454{ 455 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 456 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 457} 458 459int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 460{ 461 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 462 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 463} 464 465int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 466{ 467 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 468 MV88E6390_G1_CTL2_HIST_MODE_RX | 469 MV88E6390_G1_CTL2_HIST_MODE_TX); 470} 471 472int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 473{ 474 return mv88e6xxx_g1_ctl2_mask(chip, 475 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 476 index); 477} 478 479/* Offset 0x1d: Statistics Operation 2 */ 480 481static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 482{ 483 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 484 485 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 486} 487 488int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 489{ 490 u16 val; 491 int err; 492 493 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 494 if (err) 495 return err; 496 497 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 498 499 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 500 501 return err; 502} 503 504int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 505{ 506 int err; 507 508 /* Snapshot the hardware statistics counters for this port. */ 509 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 510 MV88E6XXX_G1_STATS_OP_BUSY | 511 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 512 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 513 if (err) 514 return err; 515 516 /* Wait for the snapshotting to complete. */ 517 return mv88e6xxx_g1_stats_wait(chip); 518} 519 520int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 521{ 522 port = (port + 1) << 5; 523 524 return mv88e6xxx_g1_stats_snapshot(chip, port); 525} 526 527int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 528{ 529 int err; 530 531 port = (port + 1) << 5; 532 533 /* Snapshot the hardware statistics counters for this port. */ 534 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 535 MV88E6XXX_G1_STATS_OP_BUSY | 536 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 537 if (err) 538 return err; 539 540 /* Wait for the snapshotting to complete. */ 541 return mv88e6xxx_g1_stats_wait(chip); 542} 543 544void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 545{ 546 u32 value; 547 u16 reg; 548 int err; 549 550 *val = 0; 551 552 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 553 MV88E6XXX_G1_STATS_OP_BUSY | 554 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 555 if (err) 556 return; 557 558 err = mv88e6xxx_g1_stats_wait(chip); 559 if (err) 560 return; 561 562 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 563 if (err) 564 return; 565 566 value = reg << 16; 567 568 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 569 if (err) 570 return; 571 572 *val = value | reg; 573} 574 575int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 576{ 577 int err; 578 u16 val; 579 580 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 581 if (err) 582 return err; 583 584 /* Keep the histogram mode bits */ 585 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 586 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 587 588 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 589 if (err) 590 return err; 591 592 /* Wait for the flush to complete. */ 593 return mv88e6xxx_g1_stats_wait(chip); 594} 595