1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6#include <linux/etherdevice.h> 7#include <linux/if_bridge.h> 8#include <linux/iopoll.h> 9#include <linux/mdio.h> 10#include <linux/mfd/syscon.h> 11#include <linux/module.h> 12#include <linux/netdevice.h> 13#include <linux/of_mdio.h> 14#include <linux/of_net.h> 15#include <linux/of_platform.h> 16#include <linux/phylink.h> 17#include <linux/regmap.h> 18#include <linux/regulator/consumer.h> 19#include <linux/reset.h> 20#include <linux/gpio/consumer.h> 21#include <net/dsa.h> 22 23#include "mt7530.h" 24 25/* String, offset, and register size in bytes if different from 4 bytes */ 26static const struct mt7530_mib_desc mt7530_mib[] = { 27 MIB_DESC(1, 0x00, "TxDrop"), 28 MIB_DESC(1, 0x04, "TxCrcErr"), 29 MIB_DESC(1, 0x08, "TxUnicast"), 30 MIB_DESC(1, 0x0c, "TxMulticast"), 31 MIB_DESC(1, 0x10, "TxBroadcast"), 32 MIB_DESC(1, 0x14, "TxCollision"), 33 MIB_DESC(1, 0x18, "TxSingleCollision"), 34 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 35 MIB_DESC(1, 0x20, "TxDeferred"), 36 MIB_DESC(1, 0x24, "TxLateCollision"), 37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 38 MIB_DESC(1, 0x2c, "TxPause"), 39 MIB_DESC(1, 0x30, "TxPktSz64"), 40 MIB_DESC(1, 0x34, "TxPktSz65To127"), 41 MIB_DESC(1, 0x38, "TxPktSz128To255"), 42 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 43 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 44 MIB_DESC(1, 0x44, "Tx1024ToMax"), 45 MIB_DESC(2, 0x48, "TxBytes"), 46 MIB_DESC(1, 0x60, "RxDrop"), 47 MIB_DESC(1, 0x64, "RxFiltering"), 48 MIB_DESC(1, 0x68, "RxUnicast"), 49 MIB_DESC(1, 0x6c, "RxMulticast"), 50 MIB_DESC(1, 0x70, "RxBroadcast"), 51 MIB_DESC(1, 0x74, "RxAlignErr"), 52 MIB_DESC(1, 0x78, "RxCrcErr"), 53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 54 MIB_DESC(1, 0x80, "RxFragErr"), 55 MIB_DESC(1, 0x84, "RxOverSzErr"), 56 MIB_DESC(1, 0x88, "RxJabberErr"), 57 MIB_DESC(1, 0x8c, "RxPause"), 58 MIB_DESC(1, 0x90, "RxPktSz64"), 59 MIB_DESC(1, 0x94, "RxPktSz65To127"), 60 MIB_DESC(1, 0x98, "RxPktSz128To255"), 61 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 64 MIB_DESC(2, 0xa8, "RxBytes"), 65 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 66 MIB_DESC(1, 0xb4, "RxIngressDrop"), 67 MIB_DESC(1, 0xb8, "RxArlDrop"), 68}; 69 70static int 71core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 72{ 73 struct mii_bus *bus = priv->bus; 74 int value, ret; 75 76 /* Write the desired MMD Devad */ 77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 78 if (ret < 0) 79 goto err; 80 81 /* Write the desired MMD register address */ 82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 83 if (ret < 0) 84 goto err; 85 86 /* Select the Function : DATA with no post increment */ 87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 88 if (ret < 0) 89 goto err; 90 91 /* Read the content of the MMD's selected register */ 92 value = bus->read(bus, 0, MII_MMD_DATA); 93 94 return value; 95err: 96 dev_err(&bus->dev, "failed to read mmd register\n"); 97 98 return ret; 99} 100 101static int 102core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 103 int devad, u32 data) 104{ 105 struct mii_bus *bus = priv->bus; 106 int ret; 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 110 if (ret < 0) 111 goto err; 112 113 /* Write the desired MMD register address */ 114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 115 if (ret < 0) 116 goto err; 117 118 /* Select the Function : DATA with no post increment */ 119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 120 if (ret < 0) 121 goto err; 122 123 /* Write the data into MMD's selected register */ 124 ret = bus->write(bus, 0, MII_MMD_DATA, data); 125err: 126 if (ret < 0) 127 dev_err(&bus->dev, 128 "failed to write mmd register\n"); 129 return ret; 130} 131 132static void 133core_write(struct mt7530_priv *priv, u32 reg, u32 val) 134{ 135 struct mii_bus *bus = priv->bus; 136 137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 138 139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 140 141 mutex_unlock(&bus->mdio_lock); 142} 143 144static void 145core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 146{ 147 struct mii_bus *bus = priv->bus; 148 u32 val; 149 150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 151 152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 153 val &= ~mask; 154 val |= set; 155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 156 157 mutex_unlock(&bus->mdio_lock); 158} 159 160static void 161core_set(struct mt7530_priv *priv, u32 reg, u32 val) 162{ 163 core_rmw(priv, reg, 0, val); 164} 165 166static void 167core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 168{ 169 core_rmw(priv, reg, val, 0); 170} 171 172static int 173mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 174{ 175 struct mii_bus *bus = priv->bus; 176 u16 page, r, lo, hi; 177 int ret; 178 179 page = (reg >> 6) & 0x3ff; 180 r = (reg >> 2) & 0xf; 181 lo = val & 0xffff; 182 hi = val >> 16; 183 184 /* MT7530 uses 31 as the pseudo port */ 185 ret = bus->write(bus, 0x1f, 0x1f, page); 186 if (ret < 0) 187 goto err; 188 189 ret = bus->write(bus, 0x1f, r, lo); 190 if (ret < 0) 191 goto err; 192 193 ret = bus->write(bus, 0x1f, 0x10, hi); 194err: 195 if (ret < 0) 196 dev_err(&bus->dev, 197 "failed to write mt7530 register\n"); 198 return ret; 199} 200 201static u32 202mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 203{ 204 struct mii_bus *bus = priv->bus; 205 u16 page, r, lo, hi; 206 int ret; 207 208 page = (reg >> 6) & 0x3ff; 209 r = (reg >> 2) & 0xf; 210 211 /* MT7530 uses 31 as the pseudo port */ 212 ret = bus->write(bus, 0x1f, 0x1f, page); 213 if (ret < 0) { 214 dev_err(&bus->dev, 215 "failed to read mt7530 register\n"); 216 return ret; 217 } 218 219 lo = bus->read(bus, 0x1f, r); 220 hi = bus->read(bus, 0x1f, 0x10); 221 222 return (hi << 16) | (lo & 0xffff); 223} 224 225static void 226mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 227{ 228 struct mii_bus *bus = priv->bus; 229 230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 231 232 mt7530_mii_write(priv, reg, val); 233 234 mutex_unlock(&bus->mdio_lock); 235} 236 237static u32 238_mt7530_unlocked_read(struct mt7530_dummy_poll *p) 239{ 240 return mt7530_mii_read(p->priv, p->reg); 241} 242 243static u32 244_mt7530_read(struct mt7530_dummy_poll *p) 245{ 246 struct mii_bus *bus = p->priv->bus; 247 u32 val; 248 249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 250 251 val = mt7530_mii_read(p->priv, p->reg); 252 253 mutex_unlock(&bus->mdio_lock); 254 255 return val; 256} 257 258static u32 259mt7530_read(struct mt7530_priv *priv, u32 reg) 260{ 261 struct mt7530_dummy_poll p; 262 263 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 264 return _mt7530_read(&p); 265} 266 267static void 268mt7530_rmw(struct mt7530_priv *priv, u32 reg, 269 u32 mask, u32 set) 270{ 271 struct mii_bus *bus = priv->bus; 272 u32 val; 273 274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 275 276 val = mt7530_mii_read(priv, reg); 277 val &= ~mask; 278 val |= set; 279 mt7530_mii_write(priv, reg, val); 280 281 mutex_unlock(&bus->mdio_lock); 282} 283 284static void 285mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 286{ 287 mt7530_rmw(priv, reg, 0, val); 288} 289 290static void 291mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 292{ 293 mt7530_rmw(priv, reg, val, 0); 294} 295 296static int 297mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 298{ 299 u32 val; 300 int ret; 301 struct mt7530_dummy_poll p; 302 303 /* Set the command operating upon the MAC address entries */ 304 val = ATC_BUSY | ATC_MAT(0) | cmd; 305 mt7530_write(priv, MT7530_ATC, val); 306 307 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 308 ret = readx_poll_timeout(_mt7530_read, &p, val, 309 !(val & ATC_BUSY), 20, 20000); 310 if (ret < 0) { 311 dev_err(priv->dev, "reset timeout\n"); 312 return ret; 313 } 314 315 /* Additional sanity for read command if the specified 316 * entry is invalid 317 */ 318 val = mt7530_read(priv, MT7530_ATC); 319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 320 return -EINVAL; 321 322 if (rsp) 323 *rsp = val; 324 325 return 0; 326} 327 328static void 329mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 330{ 331 u32 reg[3]; 332 int i; 333 334 /* Read from ARL table into an array */ 335 for (i = 0; i < 3; i++) { 336 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 337 338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 339 __func__, __LINE__, i, reg[i]); 340 } 341 342 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 352} 353 354static void 355mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 356 u8 port_mask, const u8 *mac, 357 u8 aging, u8 type) 358{ 359 u32 reg[3] = { 0 }; 360 int i; 361 362 reg[1] |= vid & CVID_MASK; 363 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 364 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 365 /* STATIC_ENT indicate that entry is static wouldn't 366 * be aged out and STATIC_EMP specified as erasing an 367 * entry 368 */ 369 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 370 reg[1] |= mac[5] << MAC_BYTE_5; 371 reg[1] |= mac[4] << MAC_BYTE_4; 372 reg[0] |= mac[3] << MAC_BYTE_3; 373 reg[0] |= mac[2] << MAC_BYTE_2; 374 reg[0] |= mac[1] << MAC_BYTE_1; 375 reg[0] |= mac[0] << MAC_BYTE_0; 376 377 /* Write array into the ARL table */ 378 for (i = 0; i < 3; i++) 379 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 380} 381 382/* Setup TX circuit including relevant PAD and driving */ 383static int 384mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 385{ 386 struct mt7530_priv *priv = ds->priv; 387 u32 ncpo1, ssc_delta, trgint, i, xtal; 388 389 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 390 391 if (xtal == HWTRAP_XTAL_20MHZ) { 392 dev_err(priv->dev, 393 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 394 __func__); 395 return -EINVAL; 396 } 397 398 switch (interface) { 399 case PHY_INTERFACE_MODE_RGMII: 400 trgint = 0; 401 /* PLL frequency: 125MHz */ 402 ncpo1 = 0x0c80; 403 break; 404 case PHY_INTERFACE_MODE_TRGMII: 405 trgint = 1; 406 if (priv->id == ID_MT7621) { 407 /* PLL frequency: 125MHz: 1.0GBit */ 408 if (xtal == HWTRAP_XTAL_40MHZ) 409 ncpo1 = 0x0640; 410 if (xtal == HWTRAP_XTAL_25MHZ) 411 ncpo1 = 0x0a00; 412 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 413 if (xtal == HWTRAP_XTAL_40MHZ) 414 ncpo1 = 0x0c80; 415 if (xtal == HWTRAP_XTAL_25MHZ) 416 ncpo1 = 0x1400; 417 } 418 break; 419 default: 420 dev_err(priv->dev, "xMII interface %d not supported\n", 421 interface); 422 return -EINVAL; 423 } 424 425 if (xtal == HWTRAP_XTAL_25MHZ) 426 ssc_delta = 0x57; 427 else 428 ssc_delta = 0x87; 429 430 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 431 P6_INTF_MODE(trgint)); 432 433 /* Lower Tx Driving for TRGMII path */ 434 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 435 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 436 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 437 438 /* Setup core clock for MT7530 */ 439 if (!trgint) { 440 /* Disable MT7530 core clock */ 441 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 442 443 /* Disable PLL, since phy_device has not yet been created 444 * provided for phy_[read,write]_mmd_indirect is called, we 445 * provide our own core_write_mmd_indirect to complete this 446 * function. 447 */ 448 core_write_mmd_indirect(priv, 449 CORE_GSWPLL_GRP1, 450 MDIO_MMD_VEND2, 451 0); 452 453 /* Set core clock into 500Mhz */ 454 core_write(priv, CORE_GSWPLL_GRP2, 455 RG_GSWPLL_POSDIV_500M(1) | 456 RG_GSWPLL_FBKDIV_500M(25)); 457 458 /* Enable PLL */ 459 core_write(priv, CORE_GSWPLL_GRP1, 460 RG_GSWPLL_EN_PRE | 461 RG_GSWPLL_POSDIV_200M(2) | 462 RG_GSWPLL_FBKDIV_200M(32)); 463 464 /* Enable MT7530 core clock */ 465 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 466 } 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 470 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 471 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 472 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 474 core_write(priv, CORE_PLL_GROUP4, 475 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 476 RG_SYSPLL_BIAS_LPF_EN); 477 core_write(priv, CORE_PLL_GROUP2, 478 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 479 RG_SYSPLL_POSDIV(1)); 480 core_write(priv, CORE_PLL_GROUP7, 481 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 482 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 483 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 484 REG_GSWCK_EN | REG_TRGMIICK_EN); 485 486 if (!trgint) 487 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 488 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 489 RD_TAP_MASK, RD_TAP(16)); 490 return 0; 491} 492 493static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 494{ 495 u32 val; 496 497 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 498 499 return (val & PAD_DUAL_SGMII_EN) != 0; 500} 501 502static int 503mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 504{ 505 return 0; 506} 507 508static void 509mt7531_pll_setup(struct mt7530_priv *priv) 510{ 511 u32 top_sig; 512 u32 hwstrap; 513 u32 xtal; 514 u32 val; 515 516 if (mt7531_dual_sgmii_supported(priv)) 517 return; 518 519 val = mt7530_read(priv, MT7531_CREV); 520 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 521 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 522 if ((val & CHIP_REV_M) > 0) 523 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 524 HWTRAP_XTAL_FSEL_25MHZ; 525 else 526 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 527 528 /* Step 1 : Disable MT7531 COREPLL */ 529 val = mt7530_read(priv, MT7531_PLLGP_EN); 530 val &= ~EN_COREPLL; 531 mt7530_write(priv, MT7531_PLLGP_EN, val); 532 533 /* Step 2: switch to XTAL output */ 534 val = mt7530_read(priv, MT7531_PLLGP_EN); 535 val |= SW_CLKSW; 536 mt7530_write(priv, MT7531_PLLGP_EN, val); 537 538 val = mt7530_read(priv, MT7531_PLLGP_CR0); 539 val &= ~RG_COREPLL_EN; 540 mt7530_write(priv, MT7531_PLLGP_CR0, val); 541 542 /* Step 3: disable PLLGP and enable program PLLGP */ 543 val = mt7530_read(priv, MT7531_PLLGP_EN); 544 val |= SW_PLLGP; 545 mt7530_write(priv, MT7531_PLLGP_EN, val); 546 547 /* Step 4: program COREPLL output frequency to 500MHz */ 548 val = mt7530_read(priv, MT7531_PLLGP_CR0); 549 val &= ~RG_COREPLL_POSDIV_M; 550 val |= 2 << RG_COREPLL_POSDIV_S; 551 mt7530_write(priv, MT7531_PLLGP_CR0, val); 552 usleep_range(25, 35); 553 554 switch (xtal) { 555 case HWTRAP_XTAL_FSEL_25MHZ: 556 val = mt7530_read(priv, MT7531_PLLGP_CR0); 557 val &= ~RG_COREPLL_SDM_PCW_M; 558 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 559 mt7530_write(priv, MT7531_PLLGP_CR0, val); 560 break; 561 case HWTRAP_XTAL_FSEL_40MHZ: 562 val = mt7530_read(priv, MT7531_PLLGP_CR0); 563 val &= ~RG_COREPLL_SDM_PCW_M; 564 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 565 mt7530_write(priv, MT7531_PLLGP_CR0, val); 566 break; 567 }; 568 569 /* Set feedback divide ratio update signal to high */ 570 val = mt7530_read(priv, MT7531_PLLGP_CR0); 571 val |= RG_COREPLL_SDM_PCW_CHG; 572 mt7530_write(priv, MT7531_PLLGP_CR0, val); 573 /* Wait for at least 16 XTAL clocks */ 574 usleep_range(10, 20); 575 576 /* Step 5: set feedback divide ratio update signal to low */ 577 val = mt7530_read(priv, MT7531_PLLGP_CR0); 578 val &= ~RG_COREPLL_SDM_PCW_CHG; 579 mt7530_write(priv, MT7531_PLLGP_CR0, val); 580 581 /* Enable 325M clock for SGMII */ 582 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 583 584 /* Enable 250SSC clock for RGMII */ 585 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 586 587 /* Step 6: Enable MT7531 PLL */ 588 val = mt7530_read(priv, MT7531_PLLGP_CR0); 589 val |= RG_COREPLL_EN; 590 mt7530_write(priv, MT7531_PLLGP_CR0, val); 591 592 val = mt7530_read(priv, MT7531_PLLGP_EN); 593 val |= EN_COREPLL; 594 mt7530_write(priv, MT7531_PLLGP_EN, val); 595 usleep_range(25, 35); 596} 597 598static void 599mt7530_mib_reset(struct dsa_switch *ds) 600{ 601 struct mt7530_priv *priv = ds->priv; 602 603 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 604 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 605} 606 607static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 608{ 609 struct mt7530_priv *priv = ds->priv; 610 611 return mdiobus_read_nested(priv->bus, port, regnum); 612} 613 614static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 615 u16 val) 616{ 617 struct mt7530_priv *priv = ds->priv; 618 619 return mdiobus_write_nested(priv->bus, port, regnum, val); 620} 621 622static int 623mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 624 int regnum) 625{ 626 struct mii_bus *bus = priv->bus; 627 struct mt7530_dummy_poll p; 628 u32 reg, val; 629 int ret; 630 631 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 632 633 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 634 635 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 636 !(val & MT7531_PHY_ACS_ST), 20, 100000); 637 if (ret < 0) { 638 dev_err(priv->dev, "poll timeout\n"); 639 goto out; 640 } 641 642 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 643 MT7531_MDIO_DEV_ADDR(devad) | regnum; 644 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 645 646 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 647 !(val & MT7531_PHY_ACS_ST), 20, 100000); 648 if (ret < 0) { 649 dev_err(priv->dev, "poll timeout\n"); 650 goto out; 651 } 652 653 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 654 MT7531_MDIO_DEV_ADDR(devad); 655 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 656 657 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 658 !(val & MT7531_PHY_ACS_ST), 20, 100000); 659 if (ret < 0) { 660 dev_err(priv->dev, "poll timeout\n"); 661 goto out; 662 } 663 664 ret = val & MT7531_MDIO_RW_DATA_MASK; 665out: 666 mutex_unlock(&bus->mdio_lock); 667 668 return ret; 669} 670 671static int 672mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 673 int regnum, u32 data) 674{ 675 struct mii_bus *bus = priv->bus; 676 struct mt7530_dummy_poll p; 677 u32 val, reg; 678 int ret; 679 680 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 681 682 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 683 684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 685 !(val & MT7531_PHY_ACS_ST), 20, 100000); 686 if (ret < 0) { 687 dev_err(priv->dev, "poll timeout\n"); 688 goto out; 689 } 690 691 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 692 MT7531_MDIO_DEV_ADDR(devad) | regnum; 693 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 703 MT7531_MDIO_DEV_ADDR(devad) | data; 704 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 705 706 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 707 !(val & MT7531_PHY_ACS_ST), 20, 100000); 708 if (ret < 0) { 709 dev_err(priv->dev, "poll timeout\n"); 710 goto out; 711 } 712 713out: 714 mutex_unlock(&bus->mdio_lock); 715 716 return ret; 717} 718 719static int 720mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 721{ 722 struct mii_bus *bus = priv->bus; 723 struct mt7530_dummy_poll p; 724 int ret; 725 u32 val; 726 727 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 728 729 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 730 731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 732 !(val & MT7531_PHY_ACS_ST), 20, 100000); 733 if (ret < 0) { 734 dev_err(priv->dev, "poll timeout\n"); 735 goto out; 736 } 737 738 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 739 MT7531_MDIO_REG_ADDR(regnum); 740 741 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 742 743 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 744 !(val & MT7531_PHY_ACS_ST), 20, 100000); 745 if (ret < 0) { 746 dev_err(priv->dev, "poll timeout\n"); 747 goto out; 748 } 749 750 ret = val & MT7531_MDIO_RW_DATA_MASK; 751out: 752 mutex_unlock(&bus->mdio_lock); 753 754 return ret; 755} 756 757static int 758mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 759 u16 data) 760{ 761 struct mii_bus *bus = priv->bus; 762 struct mt7530_dummy_poll p; 763 int ret; 764 u32 reg; 765 766 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 767 768 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 769 770 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 771 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 772 if (ret < 0) { 773 dev_err(priv->dev, "poll timeout\n"); 774 goto out; 775 } 776 777 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 778 MT7531_MDIO_REG_ADDR(regnum) | data; 779 780 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 781 782 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 783 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 784 if (ret < 0) { 785 dev_err(priv->dev, "poll timeout\n"); 786 goto out; 787 } 788 789out: 790 mutex_unlock(&bus->mdio_lock); 791 792 return ret; 793} 794 795static int 796mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) 797{ 798 struct mt7530_priv *priv = ds->priv; 799 int devad; 800 int ret; 801 802 if (regnum & MII_ADDR_C45) { 803 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 804 ret = mt7531_ind_c45_phy_read(priv, port, devad, 805 regnum & MII_REGADDR_C45_MASK); 806 } else { 807 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 808 } 809 810 return ret; 811} 812 813static int 814mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, 815 u16 data) 816{ 817 struct mt7530_priv *priv = ds->priv; 818 int devad; 819 int ret; 820 821 if (regnum & MII_ADDR_C45) { 822 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 823 ret = mt7531_ind_c45_phy_write(priv, port, devad, 824 regnum & MII_REGADDR_C45_MASK, 825 data); 826 } else { 827 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 828 } 829 830 return ret; 831} 832 833static void 834mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 835 uint8_t *data) 836{ 837 int i; 838 839 if (stringset != ETH_SS_STATS) 840 return; 841 842 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 843 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 844 ETH_GSTRING_LEN); 845} 846 847static void 848mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 849 uint64_t *data) 850{ 851 struct mt7530_priv *priv = ds->priv; 852 const struct mt7530_mib_desc *mib; 853 u32 reg, i; 854 u64 hi; 855 856 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 857 mib = &mt7530_mib[i]; 858 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 859 860 data[i] = mt7530_read(priv, reg); 861 if (mib->size == 2) { 862 hi = mt7530_read(priv, reg + 4); 863 data[i] |= hi << 32; 864 } 865 } 866} 867 868static int 869mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 870{ 871 if (sset != ETH_SS_STATS) 872 return 0; 873 874 return ARRAY_SIZE(mt7530_mib); 875} 876 877static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 878{ 879 struct mt7530_priv *priv = ds->priv; 880 u8 tx_delay = 0; 881 int val; 882 883 mutex_lock(&priv->reg_mutex); 884 885 val = mt7530_read(priv, MT7530_MHWTRAP); 886 887 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 888 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 889 890 switch (priv->p5_intf_sel) { 891 case P5_INTF_SEL_PHY_P0: 892 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 893 val |= MHWTRAP_PHY0_SEL; 894 fallthrough; 895 case P5_INTF_SEL_PHY_P4: 896 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 897 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 898 899 /* Setup the MAC by default for the cpu port */ 900 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 901 break; 902 case P5_INTF_SEL_GMAC5: 903 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 904 val &= ~MHWTRAP_P5_DIS; 905 break; 906 case P5_DISABLED: 907 interface = PHY_INTERFACE_MODE_NA; 908 break; 909 default: 910 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 911 priv->p5_intf_sel); 912 goto unlock_exit; 913 } 914 915 /* Setup RGMII settings */ 916 if (phy_interface_mode_is_rgmii(interface)) { 917 val |= MHWTRAP_P5_RGMII_MODE; 918 919 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 920 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 921 922 /* Don't set delay in DSA mode */ 923 if (!dsa_is_dsa_port(priv->ds, 5) && 924 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 925 interface == PHY_INTERFACE_MODE_RGMII_ID)) 926 tx_delay = 4; /* n * 0.5 ns */ 927 928 /* P5 RGMII TX Clock Control: delay x */ 929 mt7530_write(priv, MT7530_P5RGMIITXCR, 930 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 931 932 /* reduce P5 RGMII Tx driving, 8mA */ 933 mt7530_write(priv, MT7530_IO_DRV_CR, 934 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 935 } 936 937 mt7530_write(priv, MT7530_MHWTRAP, val); 938 939 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 940 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 941 942 priv->p5_interface = interface; 943 944unlock_exit: 945 mutex_unlock(&priv->reg_mutex); 946} 947 948static int 949mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 950{ 951 struct mt7530_priv *priv = ds->priv; 952 int ret; 953 954 /* Setup max capability of CPU port at first */ 955 if (priv->info->cpu_port_config) { 956 ret = priv->info->cpu_port_config(ds, port); 957 if (ret) 958 return ret; 959 } 960 961 /* Enable Mediatek header mode on the cpu port */ 962 mt7530_write(priv, MT7530_PVC_P(port), 963 PORT_SPEC_TAG); 964 965 /* Unknown multicast frame forwarding to the cpu port */ 966 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); 967 968 /* Set CPU port number */ 969 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 970 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 971 972 /* CPU port gets connected to all user ports of 973 * the switch. 974 */ 975 mt7530_write(priv, MT7530_PCR_P(port), 976 PCR_MATRIX(dsa_user_ports(priv->ds))); 977 978 return 0; 979} 980 981static int 982mt7530_port_enable(struct dsa_switch *ds, int port, 983 struct phy_device *phy) 984{ 985 struct mt7530_priv *priv = ds->priv; 986 987 mutex_lock(&priv->reg_mutex); 988 989 /* Allow the user port gets connected to the cpu port and also 990 * restore the port matrix if the port is the member of a certain 991 * bridge. 992 */ 993 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 994 priv->ports[port].enable = true; 995 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 996 priv->ports[port].pm); 997 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 998 999 mutex_unlock(&priv->reg_mutex); 1000 1001 return 0; 1002} 1003 1004static void 1005mt7530_port_disable(struct dsa_switch *ds, int port) 1006{ 1007 struct mt7530_priv *priv = ds->priv; 1008 1009 mutex_lock(&priv->reg_mutex); 1010 1011 /* Clear up all port matrix which could be restored in the next 1012 * enablement for the port. 1013 */ 1014 priv->ports[port].enable = false; 1015 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1016 PCR_MATRIX_CLR); 1017 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1018 1019 mutex_unlock(&priv->reg_mutex); 1020} 1021 1022static void 1023mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1024{ 1025 struct mt7530_priv *priv = ds->priv; 1026 u32 stp_state; 1027 1028 switch (state) { 1029 case BR_STATE_DISABLED: 1030 stp_state = MT7530_STP_DISABLED; 1031 break; 1032 case BR_STATE_BLOCKING: 1033 stp_state = MT7530_STP_BLOCKING; 1034 break; 1035 case BR_STATE_LISTENING: 1036 stp_state = MT7530_STP_LISTENING; 1037 break; 1038 case BR_STATE_LEARNING: 1039 stp_state = MT7530_STP_LEARNING; 1040 break; 1041 case BR_STATE_FORWARDING: 1042 default: 1043 stp_state = MT7530_STP_FORWARDING; 1044 break; 1045 } 1046 1047 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1048} 1049 1050static int 1051mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1052 struct net_device *bridge) 1053{ 1054 struct mt7530_priv *priv = ds->priv; 1055 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1056 int i; 1057 1058 mutex_lock(&priv->reg_mutex); 1059 1060 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1061 /* Add this port to the port matrix of the other ports in the 1062 * same bridge. If the port is disabled, port matrix is kept 1063 * and not being setup until the port becomes enabled. 1064 */ 1065 if (dsa_is_user_port(ds, i) && i != port) { 1066 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1067 continue; 1068 if (priv->ports[i].enable) 1069 mt7530_set(priv, MT7530_PCR_P(i), 1070 PCR_MATRIX(BIT(port))); 1071 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1072 1073 port_bitmap |= BIT(i); 1074 } 1075 } 1076 1077 /* Add the all other ports to this port matrix. */ 1078 if (priv->ports[port].enable) 1079 mt7530_rmw(priv, MT7530_PCR_P(port), 1080 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1081 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1082 1083 mutex_unlock(&priv->reg_mutex); 1084 1085 return 0; 1086} 1087 1088static void 1089mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1090{ 1091 struct mt7530_priv *priv = ds->priv; 1092 bool all_user_ports_removed = true; 1093 int i; 1094 1095 /* When a port is removed from the bridge, the port would be set up 1096 * back to the default as is at initial boot which is a VLAN-unaware 1097 * port. 1098 */ 1099 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1100 MT7530_PORT_MATRIX_MODE); 1101 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1102 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1103 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1104 1105 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1106 if (dsa_is_user_port(ds, i) && 1107 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1108 all_user_ports_removed = false; 1109 break; 1110 } 1111 } 1112 1113 /* CPU port also does the same thing until all user ports belonging to 1114 * the CPU port get out of VLAN filtering mode. 1115 */ 1116 if (all_user_ports_removed) { 1117 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1118 PCR_MATRIX(dsa_user_ports(priv->ds))); 1119 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1120 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1121 } 1122} 1123 1124static void 1125mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1126{ 1127 struct mt7530_priv *priv = ds->priv; 1128 1129 /* Trapped into security mode allows packet forwarding through VLAN 1130 * table lookup. CPU port is set to fallback mode to let untagged 1131 * frames pass through. 1132 */ 1133 if (dsa_is_cpu_port(ds, port)) 1134 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1135 MT7530_PORT_FALLBACK_MODE); 1136 else 1137 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1138 MT7530_PORT_SECURITY_MODE); 1139 1140 /* Set the port as a user port which is to be able to recognize VID 1141 * from incoming packets before fetching entry within the VLAN table. 1142 */ 1143 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1144 VLAN_ATTR(MT7530_VLAN_USER) | 1145 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1146} 1147 1148static void 1149mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1150 struct net_device *bridge) 1151{ 1152 struct mt7530_priv *priv = ds->priv; 1153 int i; 1154 1155 mutex_lock(&priv->reg_mutex); 1156 1157 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1158 /* Remove this port from the port matrix of the other ports 1159 * in the same bridge. If the port is disabled, port matrix 1160 * is kept and not being setup until the port becomes enabled. 1161 */ 1162 if (dsa_is_user_port(ds, i) && i != port) { 1163 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1164 continue; 1165 if (priv->ports[i].enable) 1166 mt7530_clear(priv, MT7530_PCR_P(i), 1167 PCR_MATRIX(BIT(port))); 1168 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1169 } 1170 } 1171 1172 /* Set the cpu port to be the only one in the port matrix of 1173 * this port. 1174 */ 1175 if (priv->ports[port].enable) 1176 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1177 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1178 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1179 1180 mutex_unlock(&priv->reg_mutex); 1181} 1182 1183static int 1184mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1185 const unsigned char *addr, u16 vid) 1186{ 1187 struct mt7530_priv *priv = ds->priv; 1188 int ret; 1189 u8 port_mask = BIT(port); 1190 1191 mutex_lock(&priv->reg_mutex); 1192 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1193 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1194 mutex_unlock(&priv->reg_mutex); 1195 1196 return ret; 1197} 1198 1199static int 1200mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1201 const unsigned char *addr, u16 vid) 1202{ 1203 struct mt7530_priv *priv = ds->priv; 1204 int ret; 1205 u8 port_mask = BIT(port); 1206 1207 mutex_lock(&priv->reg_mutex); 1208 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1209 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1210 mutex_unlock(&priv->reg_mutex); 1211 1212 return ret; 1213} 1214 1215static int 1216mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1217 dsa_fdb_dump_cb_t *cb, void *data) 1218{ 1219 struct mt7530_priv *priv = ds->priv; 1220 struct mt7530_fdb _fdb = { 0 }; 1221 int cnt = MT7530_NUM_FDB_RECORDS; 1222 int ret = 0; 1223 u32 rsp = 0; 1224 1225 mutex_lock(&priv->reg_mutex); 1226 1227 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1228 if (ret < 0) 1229 goto err; 1230 1231 do { 1232 if (rsp & ATC_SRCH_HIT) { 1233 mt7530_fdb_read(priv, &_fdb); 1234 if (_fdb.port_mask & BIT(port)) { 1235 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1236 data); 1237 if (ret < 0) 1238 break; 1239 } 1240 } 1241 } while (--cnt && 1242 !(rsp & ATC_SRCH_END) && 1243 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1244err: 1245 mutex_unlock(&priv->reg_mutex); 1246 1247 return 0; 1248} 1249 1250static int 1251mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1252{ 1253 struct mt7530_dummy_poll p; 1254 u32 val; 1255 int ret; 1256 1257 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1258 mt7530_write(priv, MT7530_VTCR, val); 1259 1260 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1261 ret = readx_poll_timeout(_mt7530_read, &p, val, 1262 !(val & VTCR_BUSY), 20, 20000); 1263 if (ret < 0) { 1264 dev_err(priv->dev, "poll timeout\n"); 1265 return ret; 1266 } 1267 1268 val = mt7530_read(priv, MT7530_VTCR); 1269 if (val & VTCR_INVALID) { 1270 dev_err(priv->dev, "read VTCR invalid\n"); 1271 return -EINVAL; 1272 } 1273 1274 return 0; 1275} 1276 1277static int 1278mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1279 bool vlan_filtering, 1280 struct switchdev_trans *trans) 1281{ 1282 if (switchdev_trans_ph_prepare(trans)) 1283 return 0; 1284 1285 if (vlan_filtering) { 1286 /* The port is being kept as VLAN-unaware port when bridge is 1287 * set up with vlan_filtering not being set, Otherwise, the 1288 * port and the corresponding CPU port is required the setup 1289 * for becoming a VLAN-aware port. 1290 */ 1291 mt7530_port_set_vlan_aware(ds, port); 1292 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1293 } else { 1294 mt7530_port_set_vlan_unaware(ds, port); 1295 } 1296 1297 return 0; 1298} 1299 1300static int 1301mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1302 const struct switchdev_obj_port_vlan *vlan) 1303{ 1304 /* nothing needed */ 1305 1306 return 0; 1307} 1308 1309static void 1310mt7530_hw_vlan_add(struct mt7530_priv *priv, 1311 struct mt7530_hw_vlan_entry *entry) 1312{ 1313 u8 new_members; 1314 u32 val; 1315 1316 new_members = entry->old_members | BIT(entry->port) | 1317 BIT(MT7530_CPU_PORT); 1318 1319 /* Validate the entry with independent learning, create egress tag per 1320 * VLAN and joining the port as one of the port members. 1321 */ 1322 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1323 mt7530_write(priv, MT7530_VAWD1, val); 1324 1325 /* Decide whether adding tag or not for those outgoing packets from the 1326 * port inside the VLAN. 1327 */ 1328 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1329 MT7530_VLAN_EGRESS_TAG; 1330 mt7530_rmw(priv, MT7530_VAWD2, 1331 ETAG_CTRL_P_MASK(entry->port), 1332 ETAG_CTRL_P(entry->port, val)); 1333 1334 /* CPU port is always taken as a tagged port for serving more than one 1335 * VLANs across and also being applied with egress type stack mode for 1336 * that VLAN tags would be appended after hardware special tag used as 1337 * DSA tag. 1338 */ 1339 mt7530_rmw(priv, MT7530_VAWD2, 1340 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1341 ETAG_CTRL_P(MT7530_CPU_PORT, 1342 MT7530_VLAN_EGRESS_STACK)); 1343} 1344 1345static void 1346mt7530_hw_vlan_del(struct mt7530_priv *priv, 1347 struct mt7530_hw_vlan_entry *entry) 1348{ 1349 u8 new_members; 1350 u32 val; 1351 1352 new_members = entry->old_members & ~BIT(entry->port); 1353 1354 val = mt7530_read(priv, MT7530_VAWD1); 1355 if (!(val & VLAN_VALID)) { 1356 dev_err(priv->dev, 1357 "Cannot be deleted due to invalid entry\n"); 1358 return; 1359 } 1360 1361 /* If certain member apart from CPU port is still alive in the VLAN, 1362 * the entry would be kept valid. Otherwise, the entry is got to be 1363 * disabled. 1364 */ 1365 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1366 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1367 VLAN_VALID; 1368 mt7530_write(priv, MT7530_VAWD1, val); 1369 } else { 1370 mt7530_write(priv, MT7530_VAWD1, 0); 1371 mt7530_write(priv, MT7530_VAWD2, 0); 1372 } 1373} 1374 1375static void 1376mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1377 struct mt7530_hw_vlan_entry *entry, 1378 mt7530_vlan_op vlan_op) 1379{ 1380 u32 val; 1381 1382 /* Fetch entry */ 1383 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1384 1385 val = mt7530_read(priv, MT7530_VAWD1); 1386 1387 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1388 1389 /* Manipulate entry */ 1390 vlan_op(priv, entry); 1391 1392 /* Flush result to hardware */ 1393 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1394} 1395 1396static void 1397mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1398 const struct switchdev_obj_port_vlan *vlan) 1399{ 1400 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1401 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1402 struct mt7530_hw_vlan_entry new_entry; 1403 struct mt7530_priv *priv = ds->priv; 1404 u16 vid; 1405 1406 mutex_lock(&priv->reg_mutex); 1407 1408 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1409 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1410 mt7530_hw_vlan_update(priv, vid, &new_entry, 1411 mt7530_hw_vlan_add); 1412 } 1413 1414 if (pvid) { 1415 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1416 G0_PORT_VID(vlan->vid_end)); 1417 priv->ports[port].pvid = vlan->vid_end; 1418 } 1419 1420 mutex_unlock(&priv->reg_mutex); 1421} 1422 1423static int 1424mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1425 const struct switchdev_obj_port_vlan *vlan) 1426{ 1427 struct mt7530_hw_vlan_entry target_entry; 1428 struct mt7530_priv *priv = ds->priv; 1429 u16 vid, pvid; 1430 1431 mutex_lock(&priv->reg_mutex); 1432 1433 pvid = priv->ports[port].pvid; 1434 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1435 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1436 mt7530_hw_vlan_update(priv, vid, &target_entry, 1437 mt7530_hw_vlan_del); 1438 1439 /* PVID is being restored to the default whenever the PVID port 1440 * is being removed from the VLAN. 1441 */ 1442 if (pvid == vid) 1443 pvid = G0_PORT_VID_DEF; 1444 } 1445 1446 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1447 priv->ports[port].pvid = pvid; 1448 1449 mutex_unlock(&priv->reg_mutex); 1450 1451 return 0; 1452} 1453 1454static int mt753x_mirror_port_get(unsigned int id, u32 val) 1455{ 1456 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1457 MIRROR_PORT(val); 1458} 1459 1460static int mt753x_mirror_port_set(unsigned int id, u32 val) 1461{ 1462 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1463 MIRROR_PORT(val); 1464} 1465 1466static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1467 struct dsa_mall_mirror_tc_entry *mirror, 1468 bool ingress) 1469{ 1470 struct mt7530_priv *priv = ds->priv; 1471 int monitor_port; 1472 u32 val; 1473 1474 /* Check for existent entry */ 1475 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1476 return -EEXIST; 1477 1478 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1479 1480 /* MT7530 only supports one monitor port */ 1481 monitor_port = mt753x_mirror_port_get(priv->id, val); 1482 if (val & MT753X_MIRROR_EN(priv->id) && 1483 monitor_port != mirror->to_local_port) 1484 return -EEXIST; 1485 1486 val |= MT753X_MIRROR_EN(priv->id); 1487 val &= ~MT753X_MIRROR_MASK(priv->id); 1488 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1489 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1490 1491 val = mt7530_read(priv, MT7530_PCR_P(port)); 1492 if (ingress) { 1493 val |= PORT_RX_MIR; 1494 priv->mirror_rx |= BIT(port); 1495 } else { 1496 val |= PORT_TX_MIR; 1497 priv->mirror_tx |= BIT(port); 1498 } 1499 mt7530_write(priv, MT7530_PCR_P(port), val); 1500 1501 return 0; 1502} 1503 1504static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1505 struct dsa_mall_mirror_tc_entry *mirror) 1506{ 1507 struct mt7530_priv *priv = ds->priv; 1508 u32 val; 1509 1510 val = mt7530_read(priv, MT7530_PCR_P(port)); 1511 if (mirror->ingress) { 1512 val &= ~PORT_RX_MIR; 1513 priv->mirror_rx &= ~BIT(port); 1514 } else { 1515 val &= ~PORT_TX_MIR; 1516 priv->mirror_tx &= ~BIT(port); 1517 } 1518 mt7530_write(priv, MT7530_PCR_P(port), val); 1519 1520 if (!priv->mirror_rx && !priv->mirror_tx) { 1521 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1522 val &= ~MT753X_MIRROR_EN(priv->id); 1523 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1524 } 1525} 1526 1527static enum dsa_tag_protocol 1528mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1529 enum dsa_tag_protocol mp) 1530{ 1531 struct mt7530_priv *priv = ds->priv; 1532 1533 if (port != MT7530_CPU_PORT) { 1534 dev_warn(priv->dev, 1535 "port not matched with tagging CPU port\n"); 1536 return DSA_TAG_PROTO_NONE; 1537 } else { 1538 return DSA_TAG_PROTO_MTK; 1539 } 1540} 1541 1542static int 1543mt7530_setup(struct dsa_switch *ds) 1544{ 1545 struct mt7530_priv *priv = ds->priv; 1546 struct device_node *phy_node; 1547 struct device_node *mac_np; 1548 struct mt7530_dummy_poll p; 1549 phy_interface_t interface; 1550 struct device_node *dn; 1551 u32 id, val; 1552 int ret, i; 1553 1554 /* The parent node of master netdev which holds the common system 1555 * controller also is the container for two GMACs nodes representing 1556 * as two netdev instances. 1557 */ 1558 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 1559 ds->configure_vlan_while_not_filtering = true; 1560 1561 if (priv->id == ID_MT7530) { 1562 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1563 ret = regulator_enable(priv->core_pwr); 1564 if (ret < 0) { 1565 dev_err(priv->dev, 1566 "Failed to enable core power: %d\n", ret); 1567 return ret; 1568 } 1569 1570 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1571 ret = regulator_enable(priv->io_pwr); 1572 if (ret < 0) { 1573 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1574 ret); 1575 return ret; 1576 } 1577 } 1578 1579 /* Reset whole chip through gpio pin or memory-mapped registers for 1580 * different type of hardware 1581 */ 1582 if (priv->mcm) { 1583 reset_control_assert(priv->rstc); 1584 usleep_range(1000, 1100); 1585 reset_control_deassert(priv->rstc); 1586 } else { 1587 gpiod_set_value_cansleep(priv->reset, 0); 1588 usleep_range(1000, 1100); 1589 gpiod_set_value_cansleep(priv->reset, 1); 1590 } 1591 1592 /* Waiting for MT7530 got to stable */ 1593 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1594 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1595 20, 1000000); 1596 if (ret < 0) { 1597 dev_err(priv->dev, "reset timeout\n"); 1598 return ret; 1599 } 1600 1601 id = mt7530_read(priv, MT7530_CREV); 1602 id >>= CHIP_NAME_SHIFT; 1603 if (id != MT7530_ID) { 1604 dev_err(priv->dev, "chip %x can't be supported\n", id); 1605 return -ENODEV; 1606 } 1607 1608 /* Reset the switch through internal reset */ 1609 mt7530_write(priv, MT7530_SYS_CTRL, 1610 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1611 SYS_CTRL_REG_RST); 1612 1613 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1614 val = mt7530_read(priv, MT7530_MHWTRAP); 1615 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1616 val |= MHWTRAP_MANUAL; 1617 mt7530_write(priv, MT7530_MHWTRAP, val); 1618 1619 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1620 1621 /* Enable and reset MIB counters */ 1622 mt7530_mib_reset(ds); 1623 1624 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1625 /* Disable forwarding by default on all ports */ 1626 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1627 PCR_MATRIX_CLR); 1628 1629 if (dsa_is_cpu_port(ds, i)) { 1630 ret = mt753x_cpu_port_enable(ds, i); 1631 if (ret) 1632 return ret; 1633 } else 1634 mt7530_port_disable(ds, i); 1635 1636 /* Enable consistent egress tag */ 1637 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1638 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1639 } 1640 1641 /* Setup port 5 */ 1642 priv->p5_intf_sel = P5_DISABLED; 1643 interface = PHY_INTERFACE_MODE_NA; 1644 1645 if (!dsa_is_unused_port(ds, 5)) { 1646 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1647 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 1648 if (ret && ret != -ENODEV) 1649 return ret; 1650 } else { 1651 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 1652 for_each_child_of_node(dn, mac_np) { 1653 if (!of_device_is_compatible(mac_np, 1654 "mediatek,eth-mac")) 1655 continue; 1656 1657 ret = of_property_read_u32(mac_np, "reg", &id); 1658 if (ret < 0 || id != 1) 1659 continue; 1660 1661 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 1662 if (!phy_node) 1663 continue; 1664 1665 if (phy_node->parent == priv->dev->of_node->parent) { 1666 ret = of_get_phy_mode(mac_np, &interface); 1667 if (ret && ret != -ENODEV) { 1668 of_node_put(mac_np); 1669 of_node_put(phy_node); 1670 return ret; 1671 } 1672 id = of_mdio_parse_addr(ds->dev, phy_node); 1673 if (id == 0) 1674 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 1675 if (id == 4) 1676 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 1677 } 1678 of_node_put(mac_np); 1679 of_node_put(phy_node); 1680 break; 1681 } 1682 } 1683 1684 mt7530_setup_port5(ds, interface); 1685 1686 /* Flush the FDB table */ 1687 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1688 if (ret < 0) 1689 return ret; 1690 1691 return 0; 1692} 1693 1694static int 1695mt7531_setup(struct dsa_switch *ds) 1696{ 1697 struct mt7530_priv *priv = ds->priv; 1698 struct mt7530_dummy_poll p; 1699 u32 val, id; 1700 int ret, i; 1701 1702 /* Reset whole chip through gpio pin or memory-mapped registers for 1703 * different type of hardware 1704 */ 1705 if (priv->mcm) { 1706 reset_control_assert(priv->rstc); 1707 usleep_range(1000, 1100); 1708 reset_control_deassert(priv->rstc); 1709 } else { 1710 gpiod_set_value_cansleep(priv->reset, 0); 1711 usleep_range(1000, 1100); 1712 gpiod_set_value_cansleep(priv->reset, 1); 1713 } 1714 1715 /* Waiting for MT7530 got to stable */ 1716 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1717 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1718 20, 1000000); 1719 if (ret < 0) { 1720 dev_err(priv->dev, "reset timeout\n"); 1721 return ret; 1722 } 1723 1724 id = mt7530_read(priv, MT7531_CREV); 1725 id >>= CHIP_NAME_SHIFT; 1726 1727 if (id != MT7531_ID) { 1728 dev_err(priv->dev, "chip %x can't be supported\n", id); 1729 return -ENODEV; 1730 } 1731 1732 /* Reset the switch through internal reset */ 1733 mt7530_write(priv, MT7530_SYS_CTRL, 1734 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1735 SYS_CTRL_REG_RST); 1736 1737 mt7531_pll_setup(priv); 1738 1739 if (mt7531_dual_sgmii_supported(priv)) { 1740 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 1741 1742 /* Let ds->slave_mii_bus be able to access external phy. */ 1743 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 1744 MT7531_EXT_P_MDC_11); 1745 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 1746 MT7531_EXT_P_MDIO_12); 1747 } else { 1748 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1749 } 1750 dev_dbg(ds->dev, "P5 support %s interface\n", 1751 p5_intf_modes(priv->p5_intf_sel)); 1752 1753 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 1754 MT7531_GPIO0_INTERRUPT); 1755 1756 /* Let phylink decide the interface later. */ 1757 priv->p5_interface = PHY_INTERFACE_MODE_NA; 1758 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1759 1760 /* Enable PHY core PLL, since phy_device has not yet been created 1761 * provided for phy_[read,write]_mmd_indirect is called, we provide 1762 * our own mt7531_ind_mmd_phy_[read,write] to complete this 1763 * function. 1764 */ 1765 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 1766 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 1767 val |= MT7531_PHY_PLL_BYPASS_MODE; 1768 val &= ~MT7531_PHY_PLL_OFF; 1769 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 1770 CORE_PLL_GROUP4, val); 1771 1772 /* BPDU to CPU port */ 1773 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 1774 BIT(MT7530_CPU_PORT)); 1775 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 1776 MT753X_BPDU_CPU_ONLY); 1777 1778 /* Enable and reset MIB counters */ 1779 mt7530_mib_reset(ds); 1780 1781 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1782 /* Disable forwarding by default on all ports */ 1783 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1784 PCR_MATRIX_CLR); 1785 1786 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 1787 1788 if (dsa_is_cpu_port(ds, i)) { 1789 ret = mt753x_cpu_port_enable(ds, i); 1790 if (ret) 1791 return ret; 1792 } else 1793 mt7530_port_disable(ds, i); 1794 1795 /* Enable consistent egress tag */ 1796 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1797 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1798 } 1799 1800 ds->configure_vlan_while_not_filtering = true; 1801 1802 /* Flush the FDB table */ 1803 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1804 if (ret < 0) 1805 return ret; 1806 1807 return 0; 1808} 1809 1810static bool 1811mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 1812 const struct phylink_link_state *state) 1813{ 1814 struct mt7530_priv *priv = ds->priv; 1815 1816 switch (port) { 1817 case 0 ... 4: /* Internal phy */ 1818 if (state->interface != PHY_INTERFACE_MODE_GMII) 1819 return false; 1820 break; 1821 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 1822 if (!phy_interface_mode_is_rgmii(state->interface) && 1823 state->interface != PHY_INTERFACE_MODE_MII && 1824 state->interface != PHY_INTERFACE_MODE_GMII) 1825 return false; 1826 break; 1827 case 6: /* 1st cpu port */ 1828 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1829 state->interface != PHY_INTERFACE_MODE_TRGMII) 1830 return false; 1831 break; 1832 default: 1833 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 1834 port); 1835 return false; 1836 } 1837 1838 return true; 1839} 1840 1841static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 1842{ 1843 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 1844} 1845 1846static bool 1847mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 1848 const struct phylink_link_state *state) 1849{ 1850 struct mt7530_priv *priv = ds->priv; 1851 1852 switch (port) { 1853 case 0 ... 4: /* Internal phy */ 1854 if (state->interface != PHY_INTERFACE_MODE_GMII) 1855 return false; 1856 break; 1857 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 1858 if (mt7531_is_rgmii_port(priv, port)) 1859 return phy_interface_mode_is_rgmii(state->interface); 1860 fallthrough; 1861 case 6: /* 1st cpu port supports sgmii/8023z only */ 1862 if (state->interface != PHY_INTERFACE_MODE_SGMII && 1863 !phy_interface_mode_is_8023z(state->interface)) 1864 return false; 1865 break; 1866 default: 1867 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 1868 port); 1869 return false; 1870 } 1871 1872 return true; 1873} 1874 1875static bool 1876mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 1877 const struct phylink_link_state *state) 1878{ 1879 struct mt7530_priv *priv = ds->priv; 1880 1881 return priv->info->phy_mode_supported(ds, port, state); 1882} 1883 1884static int 1885mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 1886{ 1887 struct mt7530_priv *priv = ds->priv; 1888 1889 return priv->info->pad_setup(ds, state->interface); 1890} 1891 1892static int 1893mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 1894 phy_interface_t interface) 1895{ 1896 struct mt7530_priv *priv = ds->priv; 1897 1898 /* Only need to setup port5. */ 1899 if (port != 5) 1900 return 0; 1901 1902 mt7530_setup_port5(priv->ds, interface); 1903 1904 return 0; 1905} 1906 1907static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 1908 phy_interface_t interface, 1909 struct phy_device *phydev) 1910{ 1911 u32 val; 1912 1913 if (!mt7531_is_rgmii_port(priv, port)) { 1914 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 1915 port); 1916 return -EINVAL; 1917 } 1918 1919 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 1920 val |= GP_CLK_EN; 1921 val &= ~GP_MODE_MASK; 1922 val |= GP_MODE(MT7531_GP_MODE_RGMII); 1923 val &= ~CLK_SKEW_IN_MASK; 1924 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 1925 val &= ~CLK_SKEW_OUT_MASK; 1926 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 1927 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 1928 1929 /* Do not adjust rgmii delay when vendor phy driver presents. */ 1930 if (!phydev || phy_driver_is_genphy(phydev)) { 1931 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 1932 switch (interface) { 1933 case PHY_INTERFACE_MODE_RGMII: 1934 val |= TXCLK_NO_REVERSE; 1935 val |= RXCLK_NO_DELAY; 1936 break; 1937 case PHY_INTERFACE_MODE_RGMII_RXID: 1938 val |= TXCLK_NO_REVERSE; 1939 break; 1940 case PHY_INTERFACE_MODE_RGMII_TXID: 1941 val |= RXCLK_NO_DELAY; 1942 break; 1943 case PHY_INTERFACE_MODE_RGMII_ID: 1944 break; 1945 default: 1946 return -EINVAL; 1947 } 1948 } 1949 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 1950 1951 return 0; 1952} 1953 1954static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 1955 unsigned long *supported) 1956{ 1957 /* Port5 supports ethier RGMII or SGMII. 1958 * Port6 supports SGMII only. 1959 */ 1960 if (port == 6) { 1961 phylink_set(supported, 2500baseX_Full); 1962 phylink_set(supported, 2500baseT_Full); 1963 } 1964} 1965 1966static void 1967mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 1968 unsigned int mode, phy_interface_t interface, 1969 int speed, int duplex) 1970{ 1971 struct mt7530_priv *priv = ds->priv; 1972 unsigned int val; 1973 1974 /* For adjusting speed and duplex of SGMII force mode. */ 1975 if (interface != PHY_INTERFACE_MODE_SGMII || 1976 phylink_autoneg_inband(mode)) 1977 return; 1978 1979 /* SGMII force mode setting */ 1980 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 1981 val &= ~MT7531_SGMII_IF_MODE_MASK; 1982 1983 switch (speed) { 1984 case SPEED_10: 1985 val |= MT7531_SGMII_FORCE_SPEED_10; 1986 break; 1987 case SPEED_100: 1988 val |= MT7531_SGMII_FORCE_SPEED_100; 1989 break; 1990 case SPEED_1000: 1991 val |= MT7531_SGMII_FORCE_SPEED_1000; 1992 break; 1993 } 1994 1995 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 1996 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 1997 */ 1998 if ((speed == SPEED_10 || speed == SPEED_100) && 1999 duplex != DUPLEX_FULL) 2000 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2001 2002 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2003} 2004 2005static bool mt753x_is_mac_port(u32 port) 2006{ 2007 return (port == 5 || port == 6); 2008} 2009 2010static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2011 phy_interface_t interface) 2012{ 2013 u32 val; 2014 2015 if (!mt753x_is_mac_port(port)) 2016 return -EINVAL; 2017 2018 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2019 MT7531_SGMII_PHYA_PWD); 2020 2021 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2022 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2023 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2024 * encoding. 2025 */ 2026 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2027 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2028 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2029 2030 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2031 2032 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2033 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2034 */ 2035 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2036 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2037 MT7531_SGMII_FORCE_SPEED_1000); 2038 2039 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2040 2041 return 0; 2042} 2043 2044static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2045 phy_interface_t interface) 2046{ 2047 if (!mt753x_is_mac_port(port)) 2048 return -EINVAL; 2049 2050 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2051 MT7531_SGMII_PHYA_PWD); 2052 2053 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2054 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2055 2056 mt7530_set(priv, MT7531_SGMII_MODE(port), 2057 MT7531_SGMII_REMOTE_FAULT_DIS | 2058 MT7531_SGMII_SPEED_DUPLEX_AN); 2059 2060 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2061 MT7531_SGMII_TX_CONFIG_MASK, 1); 2062 2063 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2064 2065 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2066 2067 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2068 2069 return 0; 2070} 2071 2072static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2073{ 2074 struct mt7530_priv *priv = ds->priv; 2075 u32 val; 2076 2077 /* Only restart AN when AN is enabled */ 2078 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2079 if (val & MT7531_SGMII_AN_ENABLE) { 2080 val |= MT7531_SGMII_AN_RESTART; 2081 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2082 } 2083} 2084 2085static int 2086mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2087 phy_interface_t interface) 2088{ 2089 struct mt7530_priv *priv = ds->priv; 2090 struct phy_device *phydev; 2091 struct dsa_port *dp; 2092 2093 if (!mt753x_is_mac_port(port)) { 2094 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2095 return -EINVAL; 2096 } 2097 2098 switch (interface) { 2099 case PHY_INTERFACE_MODE_RGMII: 2100 case PHY_INTERFACE_MODE_RGMII_ID: 2101 case PHY_INTERFACE_MODE_RGMII_RXID: 2102 case PHY_INTERFACE_MODE_RGMII_TXID: 2103 dp = dsa_to_port(ds, port); 2104 phydev = dp->slave->phydev; 2105 return mt7531_rgmii_setup(priv, port, interface, phydev); 2106 case PHY_INTERFACE_MODE_SGMII: 2107 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2108 case PHY_INTERFACE_MODE_NA: 2109 case PHY_INTERFACE_MODE_1000BASEX: 2110 case PHY_INTERFACE_MODE_2500BASEX: 2111 if (phylink_autoneg_inband(mode)) 2112 return -EINVAL; 2113 2114 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2115 default: 2116 return -EINVAL; 2117 } 2118 2119 return -EINVAL; 2120} 2121 2122static int 2123mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2124 const struct phylink_link_state *state) 2125{ 2126 struct mt7530_priv *priv = ds->priv; 2127 2128 return priv->info->mac_port_config(ds, port, mode, state->interface); 2129} 2130 2131static void 2132mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2133 const struct phylink_link_state *state) 2134{ 2135 struct mt7530_priv *priv = ds->priv; 2136 u32 mcr_cur, mcr_new; 2137 2138 if (!mt753x_phy_mode_supported(ds, port, state)) 2139 goto unsupported; 2140 2141 switch (port) { 2142 case 0 ... 4: /* Internal phy */ 2143 if (state->interface != PHY_INTERFACE_MODE_GMII) 2144 goto unsupported; 2145 break; 2146 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2147 if (priv->p5_interface == state->interface) 2148 break; 2149 2150 if (mt753x_mac_config(ds, port, mode, state) < 0) 2151 goto unsupported; 2152 2153 if (priv->p5_intf_sel != P5_DISABLED) 2154 priv->p5_interface = state->interface; 2155 break; 2156 case 6: /* 1st cpu port */ 2157 if (priv->p6_interface == state->interface) 2158 break; 2159 2160 mt753x_pad_setup(ds, state); 2161 2162 if (mt753x_mac_config(ds, port, mode, state) < 0) 2163 goto unsupported; 2164 2165 priv->p6_interface = state->interface; 2166 break; 2167 default: 2168unsupported: 2169 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2170 __func__, phy_modes(state->interface), port); 2171 return; 2172 } 2173 2174 if (phylink_autoneg_inband(mode) && 2175 state->interface != PHY_INTERFACE_MODE_SGMII) { 2176 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2177 __func__); 2178 return; 2179 } 2180 2181 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2182 mcr_new = mcr_cur; 2183 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2184 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2185 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2186 2187 /* Are we connected to external phy */ 2188 if (port == 5 && dsa_is_user_port(ds, 5)) 2189 mcr_new |= PMCR_EXT_PHY; 2190 2191 if (mcr_new != mcr_cur) 2192 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2193} 2194 2195static void 2196mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2197{ 2198 struct mt7530_priv *priv = ds->priv; 2199 2200 if (!priv->info->mac_pcs_an_restart) 2201 return; 2202 2203 priv->info->mac_pcs_an_restart(ds, port); 2204} 2205 2206static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2207 unsigned int mode, 2208 phy_interface_t interface) 2209{ 2210 struct mt7530_priv *priv = ds->priv; 2211 2212 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2213} 2214 2215static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2216 unsigned int mode, phy_interface_t interface, 2217 int speed, int duplex) 2218{ 2219 struct mt7530_priv *priv = ds->priv; 2220 2221 if (!priv->info->mac_pcs_link_up) 2222 return; 2223 2224 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2225} 2226 2227static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2228 unsigned int mode, 2229 phy_interface_t interface, 2230 struct phy_device *phydev, 2231 int speed, int duplex, 2232 bool tx_pause, bool rx_pause) 2233{ 2234 struct mt7530_priv *priv = ds->priv; 2235 u32 mcr; 2236 2237 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2238 2239 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2240 2241 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2242 * variants. 2243 */ 2244 if (interface == PHY_INTERFACE_MODE_TRGMII || 2245 (phy_interface_mode_is_8023z(interface))) { 2246 speed = SPEED_1000; 2247 duplex = DUPLEX_FULL; 2248 } 2249 2250 switch (speed) { 2251 case SPEED_1000: 2252 mcr |= PMCR_FORCE_SPEED_1000; 2253 break; 2254 case SPEED_100: 2255 mcr |= PMCR_FORCE_SPEED_100; 2256 break; 2257 } 2258 if (duplex == DUPLEX_FULL) { 2259 mcr |= PMCR_FORCE_FDX; 2260 if (tx_pause) 2261 mcr |= PMCR_TX_FC_EN; 2262 if (rx_pause) 2263 mcr |= PMCR_RX_FC_EN; 2264 } 2265 2266 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2267} 2268 2269static int 2270mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2271{ 2272 struct mt7530_priv *priv = ds->priv; 2273 phy_interface_t interface; 2274 int speed; 2275 int ret; 2276 2277 switch (port) { 2278 case 5: 2279 if (mt7531_is_rgmii_port(priv, port)) 2280 interface = PHY_INTERFACE_MODE_RGMII; 2281 else 2282 interface = PHY_INTERFACE_MODE_2500BASEX; 2283 2284 priv->p5_interface = interface; 2285 break; 2286 case 6: 2287 interface = PHY_INTERFACE_MODE_2500BASEX; 2288 2289 priv->p6_interface = interface; 2290 break; 2291 default: 2292 return -EINVAL; 2293 } 2294 2295 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2296 speed = SPEED_2500; 2297 else 2298 speed = SPEED_1000; 2299 2300 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2301 if (ret) 2302 return ret; 2303 mt7530_write(priv, MT7530_PMCR_P(port), 2304 PMCR_CPU_PORT_SETTING(priv->id)); 2305 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2306 speed, DUPLEX_FULL, true, true); 2307 2308 return 0; 2309} 2310 2311static void 2312mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2313 unsigned long *supported) 2314{ 2315} 2316 2317static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2318 unsigned long *supported) 2319{ 2320 struct mt7530_priv *priv = ds->priv; 2321 2322 mt7531_sgmii_validate(priv, port, supported); 2323} 2324 2325static void 2326mt753x_phylink_validate(struct dsa_switch *ds, int port, 2327 unsigned long *supported, 2328 struct phylink_link_state *state) 2329{ 2330 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2331 struct mt7530_priv *priv = ds->priv; 2332 2333 if (state->interface != PHY_INTERFACE_MODE_NA && 2334 !mt753x_phy_mode_supported(ds, port, state)) { 2335 linkmode_zero(supported); 2336 return; 2337 } 2338 2339 phylink_set_port_modes(mask); 2340 2341 if (state->interface != PHY_INTERFACE_MODE_TRGMII && 2342 !phy_interface_mode_is_8023z(state->interface)) { 2343 phylink_set(mask, 10baseT_Half); 2344 phylink_set(mask, 10baseT_Full); 2345 phylink_set(mask, 100baseT_Half); 2346 phylink_set(mask, 100baseT_Full); 2347 phylink_set(mask, Autoneg); 2348 } 2349 2350 /* This switch only supports 1G full-duplex. */ 2351 if (state->interface != PHY_INTERFACE_MODE_MII) { 2352 phylink_set(mask, 1000baseT_Full); 2353 phylink_set(mask, 1000baseX_Full); 2354 } 2355 2356 priv->info->mac_port_validate(ds, port, mask); 2357 2358 phylink_set(mask, Pause); 2359 phylink_set(mask, Asym_Pause); 2360 2361 linkmode_and(supported, supported, mask); 2362 linkmode_and(state->advertising, state->advertising, mask); 2363 2364 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2365 * to advertise both, only report advertising at 2500BaseX. 2366 */ 2367 phylink_helper_basex_speed(state); 2368} 2369 2370static int 2371mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2372 struct phylink_link_state *state) 2373{ 2374 struct mt7530_priv *priv = ds->priv; 2375 u32 pmsr; 2376 2377 if (port < 0 || port >= MT7530_NUM_PORTS) 2378 return -EINVAL; 2379 2380 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2381 2382 state->link = (pmsr & PMSR_LINK); 2383 state->an_complete = state->link; 2384 state->duplex = !!(pmsr & PMSR_DPX); 2385 2386 switch (pmsr & PMSR_SPEED_MASK) { 2387 case PMSR_SPEED_10: 2388 state->speed = SPEED_10; 2389 break; 2390 case PMSR_SPEED_100: 2391 state->speed = SPEED_100; 2392 break; 2393 case PMSR_SPEED_1000: 2394 state->speed = SPEED_1000; 2395 break; 2396 default: 2397 state->speed = SPEED_UNKNOWN; 2398 break; 2399 } 2400 2401 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2402 if (pmsr & PMSR_RX_FC) 2403 state->pause |= MLO_PAUSE_RX; 2404 if (pmsr & PMSR_TX_FC) 2405 state->pause |= MLO_PAUSE_TX; 2406 2407 return 1; 2408} 2409 2410static int 2411mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2412 struct phylink_link_state *state) 2413{ 2414 u32 status, val; 2415 u16 config_reg; 2416 2417 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2418 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2419 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2420 (status & MT7531_SGMII_AN_ENABLE)) { 2421 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2422 config_reg = val >> 16; 2423 2424 switch (config_reg & LPA_SGMII_SPD_MASK) { 2425 case LPA_SGMII_1000: 2426 state->speed = SPEED_1000; 2427 break; 2428 case LPA_SGMII_100: 2429 state->speed = SPEED_100; 2430 break; 2431 case LPA_SGMII_10: 2432 state->speed = SPEED_10; 2433 break; 2434 default: 2435 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2436 state->link = false; 2437 return -EINVAL; 2438 } 2439 2440 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2441 state->duplex = DUPLEX_FULL; 2442 else 2443 state->duplex = DUPLEX_HALF; 2444 } 2445 2446 return 0; 2447} 2448 2449static int 2450mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2451 struct phylink_link_state *state) 2452{ 2453 struct mt7530_priv *priv = ds->priv; 2454 2455 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2456 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2457 2458 return -EOPNOTSUPP; 2459} 2460 2461static int 2462mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2463 struct phylink_link_state *state) 2464{ 2465 struct mt7530_priv *priv = ds->priv; 2466 2467 return priv->info->mac_port_get_state(ds, port, state); 2468} 2469 2470static int 2471mt753x_setup(struct dsa_switch *ds) 2472{ 2473 struct mt7530_priv *priv = ds->priv; 2474 2475 return priv->info->sw_setup(ds); 2476} 2477 2478static int 2479mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) 2480{ 2481 struct mt7530_priv *priv = ds->priv; 2482 2483 return priv->info->phy_read(ds, port, regnum); 2484} 2485 2486static int 2487mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 2488{ 2489 struct mt7530_priv *priv = ds->priv; 2490 2491 return priv->info->phy_write(ds, port, regnum, val); 2492} 2493 2494static const struct dsa_switch_ops mt7530_switch_ops = { 2495 .get_tag_protocol = mtk_get_tag_protocol, 2496 .setup = mt753x_setup, 2497 .get_strings = mt7530_get_strings, 2498 .phy_read = mt753x_phy_read, 2499 .phy_write = mt753x_phy_write, 2500 .get_ethtool_stats = mt7530_get_ethtool_stats, 2501 .get_sset_count = mt7530_get_sset_count, 2502 .port_enable = mt7530_port_enable, 2503 .port_disable = mt7530_port_disable, 2504 .port_stp_state_set = mt7530_stp_state_set, 2505 .port_bridge_join = mt7530_port_bridge_join, 2506 .port_bridge_leave = mt7530_port_bridge_leave, 2507 .port_fdb_add = mt7530_port_fdb_add, 2508 .port_fdb_del = mt7530_port_fdb_del, 2509 .port_fdb_dump = mt7530_port_fdb_dump, 2510 .port_vlan_filtering = mt7530_port_vlan_filtering, 2511 .port_vlan_prepare = mt7530_port_vlan_prepare, 2512 .port_vlan_add = mt7530_port_vlan_add, 2513 .port_vlan_del = mt7530_port_vlan_del, 2514 .port_mirror_add = mt753x_port_mirror_add, 2515 .port_mirror_del = mt753x_port_mirror_del, 2516 .phylink_validate = mt753x_phylink_validate, 2517 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 2518 .phylink_mac_config = mt753x_phylink_mac_config, 2519 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 2520 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2521 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2522}; 2523 2524static const struct mt753x_info mt753x_table[] = { 2525 [ID_MT7621] = { 2526 .id = ID_MT7621, 2527 .sw_setup = mt7530_setup, 2528 .phy_read = mt7530_phy_read, 2529 .phy_write = mt7530_phy_write, 2530 .pad_setup = mt7530_pad_clk_setup, 2531 .phy_mode_supported = mt7530_phy_mode_supported, 2532 .mac_port_validate = mt7530_mac_port_validate, 2533 .mac_port_get_state = mt7530_phylink_mac_link_state, 2534 .mac_port_config = mt7530_mac_config, 2535 }, 2536 [ID_MT7530] = { 2537 .id = ID_MT7530, 2538 .sw_setup = mt7530_setup, 2539 .phy_read = mt7530_phy_read, 2540 .phy_write = mt7530_phy_write, 2541 .pad_setup = mt7530_pad_clk_setup, 2542 .phy_mode_supported = mt7530_phy_mode_supported, 2543 .mac_port_validate = mt7530_mac_port_validate, 2544 .mac_port_get_state = mt7530_phylink_mac_link_state, 2545 .mac_port_config = mt7530_mac_config, 2546 }, 2547 [ID_MT7531] = { 2548 .id = ID_MT7531, 2549 .sw_setup = mt7531_setup, 2550 .phy_read = mt7531_ind_phy_read, 2551 .phy_write = mt7531_ind_phy_write, 2552 .pad_setup = mt7531_pad_setup, 2553 .cpu_port_config = mt7531_cpu_port_config, 2554 .phy_mode_supported = mt7531_phy_mode_supported, 2555 .mac_port_validate = mt7531_mac_port_validate, 2556 .mac_port_get_state = mt7531_phylink_mac_link_state, 2557 .mac_port_config = mt7531_mac_config, 2558 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 2559 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 2560 }, 2561}; 2562 2563static const struct of_device_id mt7530_of_match[] = { 2564 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 2565 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 2566 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 2567 { /* sentinel */ }, 2568}; 2569MODULE_DEVICE_TABLE(of, mt7530_of_match); 2570 2571static int 2572mt7530_probe(struct mdio_device *mdiodev) 2573{ 2574 struct mt7530_priv *priv; 2575 struct device_node *dn; 2576 2577 dn = mdiodev->dev.of_node; 2578 2579 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2580 if (!priv) 2581 return -ENOMEM; 2582 2583 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2584 if (!priv->ds) 2585 return -ENOMEM; 2586 2587 priv->ds->dev = &mdiodev->dev; 2588 priv->ds->num_ports = MT7530_NUM_PORTS; 2589 2590 /* Use medatek,mcm property to distinguish hardware type that would 2591 * casues a little bit differences on power-on sequence. 2592 */ 2593 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 2594 if (priv->mcm) { 2595 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 2596 2597 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 2598 if (IS_ERR(priv->rstc)) { 2599 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2600 return PTR_ERR(priv->rstc); 2601 } 2602 } 2603 2604 /* Get the hardware identifier from the devicetree node. 2605 * We will need it for some of the clock and regulator setup. 2606 */ 2607 priv->info = of_device_get_match_data(&mdiodev->dev); 2608 if (!priv->info) 2609 return -EINVAL; 2610 2611 /* Sanity check if these required device operations are filled 2612 * properly. 2613 */ 2614 if (!priv->info->sw_setup || !priv->info->pad_setup || 2615 !priv->info->phy_read || !priv->info->phy_write || 2616 !priv->info->phy_mode_supported || 2617 !priv->info->mac_port_validate || 2618 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 2619 return -EINVAL; 2620 2621 priv->id = priv->info->id; 2622 2623 if (priv->id == ID_MT7530) { 2624 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 2625 if (IS_ERR(priv->core_pwr)) 2626 return PTR_ERR(priv->core_pwr); 2627 2628 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 2629 if (IS_ERR(priv->io_pwr)) 2630 return PTR_ERR(priv->io_pwr); 2631 } 2632 2633 /* Not MCM that indicates switch works as the remote standalone 2634 * integrated circuit so the GPIO pin would be used to complete 2635 * the reset, otherwise memory-mapped register accessing used 2636 * through syscon provides in the case of MCM. 2637 */ 2638 if (!priv->mcm) { 2639 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 2640 GPIOD_OUT_LOW); 2641 if (IS_ERR(priv->reset)) { 2642 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2643 return PTR_ERR(priv->reset); 2644 } 2645 } 2646 2647 priv->bus = mdiodev->bus; 2648 priv->dev = &mdiodev->dev; 2649 priv->ds->priv = priv; 2650 priv->ds->ops = &mt7530_switch_ops; 2651 mutex_init(&priv->reg_mutex); 2652 dev_set_drvdata(&mdiodev->dev, priv); 2653 2654 return dsa_register_switch(priv->ds); 2655} 2656 2657static void 2658mt7530_remove(struct mdio_device *mdiodev) 2659{ 2660 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 2661 int ret = 0; 2662 2663 ret = regulator_disable(priv->core_pwr); 2664 if (ret < 0) 2665 dev_err(priv->dev, 2666 "Failed to disable core power: %d\n", ret); 2667 2668 ret = regulator_disable(priv->io_pwr); 2669 if (ret < 0) 2670 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 2671 ret); 2672 2673 dsa_unregister_switch(priv->ds); 2674 mutex_destroy(&priv->reg_mutex); 2675} 2676 2677static struct mdio_driver mt7530_mdio_driver = { 2678 .probe = mt7530_probe, 2679 .remove = mt7530_remove, 2680 .mdiodrv.driver = { 2681 .name = "mt7530", 2682 .of_match_table = mt7530_of_match, 2683 }, 2684}; 2685 2686mdio_module_driver(mt7530_mdio_driver); 2687 2688MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 2689MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 2690MODULE_LICENSE("GPL"); 2691