1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8#include <linux/kernel.h> 9#include <linux/module.h> 10#include <linux/iopoll.h> 11#include <linux/platform_data/microchip-ksz.h> 12#include <linux/phy.h> 13#include <linux/if_bridge.h> 14#include <net/dsa.h> 15#include <net/switchdev.h> 16 17#include "ksz9477_reg.h" 18#include "ksz_common.h" 19 20/* Used with variable features to indicate capabilities. */ 21#define GBIT_SUPPORT BIT(0) 22#define NEW_XMII BIT(1) 23#define IS_9893 BIT(2) 24 25static const struct { 26 int index; 27 char string[ETH_GSTRING_LEN]; 28} ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 29 { 0x00, "rx_hi" }, 30 { 0x01, "rx_undersize" }, 31 { 0x02, "rx_fragments" }, 32 { 0x03, "rx_oversize" }, 33 { 0x04, "rx_jabbers" }, 34 { 0x05, "rx_symbol_err" }, 35 { 0x06, "rx_crc_err" }, 36 { 0x07, "rx_align_err" }, 37 { 0x08, "rx_mac_ctrl" }, 38 { 0x09, "rx_pause" }, 39 { 0x0A, "rx_bcast" }, 40 { 0x0B, "rx_mcast" }, 41 { 0x0C, "rx_ucast" }, 42 { 0x0D, "rx_64_or_less" }, 43 { 0x0E, "rx_65_127" }, 44 { 0x0F, "rx_128_255" }, 45 { 0x10, "rx_256_511" }, 46 { 0x11, "rx_512_1023" }, 47 { 0x12, "rx_1024_1522" }, 48 { 0x13, "rx_1523_2000" }, 49 { 0x14, "rx_2001" }, 50 { 0x15, "tx_hi" }, 51 { 0x16, "tx_late_col" }, 52 { 0x17, "tx_pause" }, 53 { 0x18, "tx_bcast" }, 54 { 0x19, "tx_mcast" }, 55 { 0x1A, "tx_ucast" }, 56 { 0x1B, "tx_deferred" }, 57 { 0x1C, "tx_total_col" }, 58 { 0x1D, "tx_exc_col" }, 59 { 0x1E, "tx_single_col" }, 60 { 0x1F, "tx_mult_col" }, 61 { 0x80, "rx_total" }, 62 { 0x81, "tx_total" }, 63 { 0x82, "rx_discards" }, 64 { 0x83, "tx_discards" }, 65}; 66 67static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 68{ 69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 70} 71 72static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 73 bool set) 74{ 75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 76 bits, set ? bits : 0); 77} 78 79static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 80{ 81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 82} 83 84static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 85 u32 bits, bool set) 86{ 87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 88 bits, set ? bits : 0); 89} 90 91static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 92{ 93 unsigned int val; 94 95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 96 val, !(val & VLAN_START), 10, 1000); 97} 98 99static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 100 u32 *vlan_table) 101{ 102 int ret; 103 104 mutex_lock(&dev->vlan_mutex); 105 106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 108 109 /* wait to be cleared */ 110 ret = ksz9477_wait_vlan_ctrl_ready(dev); 111 if (ret) { 112 dev_dbg(dev->dev, "Failed to read vlan table\n"); 113 goto exit; 114 } 115 116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 119 120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 121 122exit: 123 mutex_unlock(&dev->vlan_mutex); 124 125 return ret; 126} 127 128static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 129 u32 *vlan_table) 130{ 131 int ret; 132 133 mutex_lock(&dev->vlan_mutex); 134 135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 138 139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 141 142 /* wait to be cleared */ 143 ret = ksz9477_wait_vlan_ctrl_ready(dev); 144 if (ret) { 145 dev_dbg(dev->dev, "Failed to write vlan table\n"); 146 goto exit; 147 } 148 149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 150 151 /* update vlan cache table */ 152 dev->vlan_cache[vid].table[0] = vlan_table[0]; 153 dev->vlan_cache[vid].table[1] = vlan_table[1]; 154 dev->vlan_cache[vid].table[2] = vlan_table[2]; 155 156exit: 157 mutex_unlock(&dev->vlan_mutex); 158 159 return ret; 160} 161 162static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 163{ 164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 168} 169 170static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 171{ 172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 176} 177 178static int ksz9477_wait_alu_ready(struct ksz_device *dev) 179{ 180 unsigned int val; 181 182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 183 val, !(val & ALU_START), 10, 1000); 184} 185 186static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 187{ 188 unsigned int val; 189 190 return regmap_read_poll_timeout(dev->regmap[2], 191 REG_SW_ALU_STAT_CTRL__4, 192 val, !(val & ALU_STAT_START), 193 10, 1000); 194} 195 196static int ksz9477_reset_switch(struct ksz_device *dev) 197{ 198 u8 data8; 199 u32 data32; 200 201 /* reset switch */ 202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 203 204 /* turn off SPI DO Edge select */ 205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 206 SPI_AUTO_EDGE_DETECTION, 0); 207 208 /* default configuration */ 209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 210 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 211 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 213 214 /* disable interrupts */ 215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 218 219 /* set broadcast storm protection 10% rate */ 220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 221 BROADCAST_STORM_RATE, 222 (BROADCAST_STORM_VALUE * 223 BROADCAST_STORM_PROT_RATE) / 100); 224 225 if (dev->synclko_125) 226 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 227 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ); 228 229 return 0; 230} 231 232static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 233 u64 *cnt) 234{ 235 struct ksz_port *p = &dev->ports[port]; 236 unsigned int val; 237 u32 data; 238 int ret; 239 240 /* retain the flush/freeze bit */ 241 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 242 data |= MIB_COUNTER_READ; 243 data |= (addr << MIB_COUNTER_INDEX_S); 244 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 245 246 ret = regmap_read_poll_timeout(dev->regmap[2], 247 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 248 val, !(val & MIB_COUNTER_READ), 10, 1000); 249 /* failed to read MIB. get out of loop */ 250 if (ret) { 251 dev_dbg(dev->dev, "Failed to get MIB\n"); 252 return; 253 } 254 255 /* count resets upon read */ 256 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 257 *cnt += data; 258} 259 260static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 261 u64 *dropped, u64 *cnt) 262{ 263 addr = ksz9477_mib_names[addr].index; 264 ksz9477_r_mib_cnt(dev, port, addr, cnt); 265} 266 267static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 268{ 269 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 270 struct ksz_port *p = &dev->ports[port]; 271 272 /* enable/disable the port for flush/freeze function */ 273 mutex_lock(&p->mib.cnt_mutex); 274 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 275 276 /* used by MIB counter reading code to know freeze is enabled */ 277 p->freeze = freeze; 278 mutex_unlock(&p->mib.cnt_mutex); 279} 280 281static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 282{ 283 struct ksz_port_mib *mib = &dev->ports[port].mib; 284 285 /* flush all enabled port MIB counters */ 286 mutex_lock(&mib->cnt_mutex); 287 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 288 MIB_COUNTER_FLUSH_FREEZE); 289 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 291 mutex_unlock(&mib->cnt_mutex); 292 293 mib->cnt_ptr = 0; 294 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 295} 296 297static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 298 int port, 299 enum dsa_tag_protocol mp) 300{ 301 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 302 struct ksz_device *dev = ds->priv; 303 304 if (dev->features & IS_9893) 305 proto = DSA_TAG_PROTO_KSZ9893; 306 return proto; 307} 308 309static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 310{ 311 struct ksz_device *dev = ds->priv; 312 u16 val = 0xffff; 313 314 /* No real PHY after this. Simulate the PHY. 315 * A fixed PHY can be setup in the device tree, but this function is 316 * still called for that port during initialization. 317 * For RGMII PHY there is no way to access it so the fixed PHY should 318 * be used. For SGMII PHY the supporting code will be added later. 319 */ 320 if (addr >= dev->phy_port_cnt) { 321 struct ksz_port *p = &dev->ports[addr]; 322 323 switch (reg) { 324 case MII_BMCR: 325 val = 0x1140; 326 break; 327 case MII_BMSR: 328 val = 0x796d; 329 break; 330 case MII_PHYSID1: 331 val = 0x0022; 332 break; 333 case MII_PHYSID2: 334 val = 0x1631; 335 break; 336 case MII_ADVERTISE: 337 val = 0x05e1; 338 break; 339 case MII_LPA: 340 val = 0xc5e1; 341 break; 342 case MII_CTRL1000: 343 val = 0x0700; 344 break; 345 case MII_STAT1000: 346 if (p->phydev.speed == SPEED_1000) 347 val = 0x3800; 348 else 349 val = 0; 350 break; 351 } 352 } else { 353 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 354 } 355 356 return val; 357} 358 359static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 360 u16 val) 361{ 362 struct ksz_device *dev = ds->priv; 363 364 /* No real PHY after this. */ 365 if (addr >= dev->phy_port_cnt) 366 return 0; 367 368 /* No gigabit support. Do not write to this register. */ 369 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 370 return 0; 371 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 372 373 return 0; 374} 375 376static void ksz9477_get_strings(struct dsa_switch *ds, int port, 377 u32 stringset, uint8_t *buf) 378{ 379 int i; 380 381 if (stringset != ETH_SS_STATS) 382 return; 383 384 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 385 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 386 ETH_GSTRING_LEN); 387 } 388} 389 390static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 391 u8 member) 392{ 393 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 394 dev->ports[port].member = member; 395} 396 397static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 398 u8 state) 399{ 400 struct ksz_device *dev = ds->priv; 401 struct ksz_port *p = &dev->ports[port]; 402 u8 data; 403 int member = -1; 404 int forward = dev->member; 405 406 ksz_pread8(dev, port, P_STP_CTRL, &data); 407 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 408 409 switch (state) { 410 case BR_STATE_DISABLED: 411 data |= PORT_LEARN_DISABLE; 412 if (port != dev->cpu_port) 413 member = 0; 414 break; 415 case BR_STATE_LISTENING: 416 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 417 if (port != dev->cpu_port && 418 p->stp_state == BR_STATE_DISABLED) 419 member = dev->host_mask | p->vid_member; 420 break; 421 case BR_STATE_LEARNING: 422 data |= PORT_RX_ENABLE; 423 break; 424 case BR_STATE_FORWARDING: 425 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 426 427 /* This function is also used internally. */ 428 if (port == dev->cpu_port) 429 break; 430 431 member = dev->host_mask | p->vid_member; 432 mutex_lock(&dev->dev_mutex); 433 434 /* Port is a member of a bridge. */ 435 if (dev->br_member & (1 << port)) { 436 dev->member |= (1 << port); 437 member = dev->member; 438 } 439 mutex_unlock(&dev->dev_mutex); 440 break; 441 case BR_STATE_BLOCKING: 442 data |= PORT_LEARN_DISABLE; 443 if (port != dev->cpu_port && 444 p->stp_state == BR_STATE_DISABLED) 445 member = dev->host_mask | p->vid_member; 446 break; 447 default: 448 dev_err(ds->dev, "invalid STP state: %d\n", state); 449 return; 450 } 451 452 ksz_pwrite8(dev, port, P_STP_CTRL, data); 453 p->stp_state = state; 454 mutex_lock(&dev->dev_mutex); 455 /* Port membership may share register with STP state. */ 456 if (member >= 0 && member != p->member) 457 ksz9477_cfg_port_member(dev, port, (u8)member); 458 459 /* Check if forwarding needs to be updated. */ 460 if (state != BR_STATE_FORWARDING) { 461 if (dev->br_member & (1 << port)) 462 dev->member &= ~(1 << port); 463 } 464 465 /* When topology has changed the function ksz_update_port_member 466 * should be called to modify port forwarding behavior. 467 */ 468 if (forward != dev->member) 469 ksz_update_port_member(dev, port); 470 mutex_unlock(&dev->dev_mutex); 471} 472 473static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 474{ 475 u8 data; 476 477 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 478 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 479 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 480 481 if (port < dev->mib_port_cnt) { 482 /* flush individual port */ 483 ksz_pread8(dev, port, P_STP_CTRL, &data); 484 if (!(data & PORT_LEARN_DISABLE)) 485 ksz_pwrite8(dev, port, P_STP_CTRL, 486 data | PORT_LEARN_DISABLE); 487 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 488 ksz_pwrite8(dev, port, P_STP_CTRL, data); 489 } else { 490 /* flush all */ 491 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 492 } 493} 494 495static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 496 bool flag, 497 struct switchdev_trans *trans) 498{ 499 struct ksz_device *dev = ds->priv; 500 501 if (switchdev_trans_ph_prepare(trans)) 502 return 0; 503 504 if (flag) { 505 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 506 PORT_VLAN_LOOKUP_VID_0, true); 507 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 508 } else { 509 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 510 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 511 PORT_VLAN_LOOKUP_VID_0, false); 512 } 513 514 return 0; 515} 516 517static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 518 const struct switchdev_obj_port_vlan *vlan) 519{ 520 struct ksz_device *dev = ds->priv; 521 u32 vlan_table[3]; 522 u16 vid; 523 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 524 525 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 526 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 527 dev_dbg(dev->dev, "Failed to get vlan table\n"); 528 return; 529 } 530 531 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 532 if (untagged) 533 vlan_table[1] |= BIT(port); 534 else 535 vlan_table[1] &= ~BIT(port); 536 vlan_table[1] &= ~(BIT(dev->cpu_port)); 537 538 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 539 540 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 541 dev_dbg(dev->dev, "Failed to set vlan table\n"); 542 return; 543 } 544 545 /* change PVID */ 546 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 547 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 548 } 549} 550 551static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 552 const struct switchdev_obj_port_vlan *vlan) 553{ 554 struct ksz_device *dev = ds->priv; 555 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 556 u32 vlan_table[3]; 557 u16 vid; 558 u16 pvid; 559 560 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 561 pvid = pvid & 0xFFF; 562 563 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 564 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 565 dev_dbg(dev->dev, "Failed to get vlan table\n"); 566 return -ETIMEDOUT; 567 } 568 569 vlan_table[2] &= ~BIT(port); 570 571 if (pvid == vid) 572 pvid = 1; 573 574 if (untagged) 575 vlan_table[1] &= ~BIT(port); 576 577 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 578 dev_dbg(dev->dev, "Failed to set vlan table\n"); 579 return -ETIMEDOUT; 580 } 581 } 582 583 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 584 585 return 0; 586} 587 588static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 589 const unsigned char *addr, u16 vid) 590{ 591 struct ksz_device *dev = ds->priv; 592 u32 alu_table[4]; 593 u32 data; 594 int ret = 0; 595 596 mutex_lock(&dev->alu_mutex); 597 598 /* find any entry with mac & vid */ 599 data = vid << ALU_FID_INDEX_S; 600 data |= ((addr[0] << 8) | addr[1]); 601 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 602 603 data = ((addr[2] << 24) | (addr[3] << 16)); 604 data |= ((addr[4] << 8) | addr[5]); 605 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 606 607 /* start read operation */ 608 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 609 610 /* wait to be finished */ 611 ret = ksz9477_wait_alu_ready(dev); 612 if (ret) { 613 dev_dbg(dev->dev, "Failed to read ALU\n"); 614 goto exit; 615 } 616 617 /* read ALU entry */ 618 ksz9477_read_table(dev, alu_table); 619 620 /* update ALU entry */ 621 alu_table[0] = ALU_V_STATIC_VALID; 622 alu_table[1] |= BIT(port); 623 if (vid) 624 alu_table[1] |= ALU_V_USE_FID; 625 alu_table[2] = (vid << ALU_V_FID_S); 626 alu_table[2] |= ((addr[0] << 8) | addr[1]); 627 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 628 alu_table[3] |= ((addr[4] << 8) | addr[5]); 629 630 ksz9477_write_table(dev, alu_table); 631 632 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 633 634 /* wait to be finished */ 635 ret = ksz9477_wait_alu_ready(dev); 636 if (ret) 637 dev_dbg(dev->dev, "Failed to write ALU\n"); 638 639exit: 640 mutex_unlock(&dev->alu_mutex); 641 642 return ret; 643} 644 645static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 646 const unsigned char *addr, u16 vid) 647{ 648 struct ksz_device *dev = ds->priv; 649 u32 alu_table[4]; 650 u32 data; 651 int ret = 0; 652 653 mutex_lock(&dev->alu_mutex); 654 655 /* read any entry with mac & vid */ 656 data = vid << ALU_FID_INDEX_S; 657 data |= ((addr[0] << 8) | addr[1]); 658 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 659 660 data = ((addr[2] << 24) | (addr[3] << 16)); 661 data |= ((addr[4] << 8) | addr[5]); 662 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 663 664 /* start read operation */ 665 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 666 667 /* wait to be finished */ 668 ret = ksz9477_wait_alu_ready(dev); 669 if (ret) { 670 dev_dbg(dev->dev, "Failed to read ALU\n"); 671 goto exit; 672 } 673 674 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 675 if (alu_table[0] & ALU_V_STATIC_VALID) { 676 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 677 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 678 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 679 680 /* clear forwarding port */ 681 alu_table[1] &= ~BIT(port); 682 683 /* if there is no port to forward, clear table */ 684 if ((alu_table[1] & ALU_V_PORT_MAP) == 0) { 685 alu_table[0] = 0; 686 alu_table[1] = 0; 687 alu_table[2] = 0; 688 alu_table[3] = 0; 689 } 690 } else { 691 alu_table[0] = 0; 692 alu_table[1] = 0; 693 alu_table[2] = 0; 694 alu_table[3] = 0; 695 } 696 697 ksz9477_write_table(dev, alu_table); 698 699 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 700 701 /* wait to be finished */ 702 ret = ksz9477_wait_alu_ready(dev); 703 if (ret) 704 dev_dbg(dev->dev, "Failed to write ALU\n"); 705 706exit: 707 mutex_unlock(&dev->alu_mutex); 708 709 return ret; 710} 711 712static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 713{ 714 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 715 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 716 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 717 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 718 ALU_V_PRIO_AGE_CNT_M; 719 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 720 721 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 722 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 723 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 724 725 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 726 727 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 728 alu->mac[1] = alu_table[2] & 0xFF; 729 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 730 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 731 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 732 alu->mac[5] = alu_table[3] & 0xFF; 733} 734 735static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 736 dsa_fdb_dump_cb_t *cb, void *data) 737{ 738 struct ksz_device *dev = ds->priv; 739 int ret = 0; 740 u32 ksz_data; 741 u32 alu_table[4]; 742 struct alu_struct alu; 743 int timeout; 744 745 mutex_lock(&dev->alu_mutex); 746 747 /* start ALU search */ 748 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 749 750 do { 751 timeout = 1000; 752 do { 753 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 754 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 755 break; 756 usleep_range(1, 10); 757 } while (timeout-- > 0); 758 759 if (!timeout) { 760 dev_dbg(dev->dev, "Failed to search ALU\n"); 761 ret = -ETIMEDOUT; 762 goto exit; 763 } 764 765 if (!(ksz_data & ALU_VALID)) 766 continue; 767 768 /* read ALU table */ 769 ksz9477_read_table(dev, alu_table); 770 771 ksz9477_convert_alu(&alu, alu_table); 772 773 if (alu.port_forward & BIT(port)) { 774 ret = cb(alu.mac, alu.fid, alu.is_static, data); 775 if (ret) 776 goto exit; 777 } 778 } while (ksz_data & ALU_START); 779 780exit: 781 782 /* stop ALU search */ 783 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 784 785 mutex_unlock(&dev->alu_mutex); 786 787 return ret; 788} 789 790static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 791 const struct switchdev_obj_port_mdb *mdb) 792{ 793 struct ksz_device *dev = ds->priv; 794 u32 static_table[4]; 795 u32 data; 796 int index; 797 u32 mac_hi, mac_lo; 798 799 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 800 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 801 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 802 803 mutex_lock(&dev->alu_mutex); 804 805 for (index = 0; index < dev->num_statics; index++) { 806 /* find empty slot first */ 807 data = (index << ALU_STAT_INDEX_S) | 808 ALU_STAT_READ | ALU_STAT_START; 809 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 810 811 /* wait to be finished */ 812 if (ksz9477_wait_alu_sta_ready(dev)) { 813 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 814 goto exit; 815 } 816 817 /* read ALU static table */ 818 ksz9477_read_table(dev, static_table); 819 820 if (static_table[0] & ALU_V_STATIC_VALID) { 821 /* check this has same vid & mac address */ 822 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 823 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 824 static_table[3] == mac_lo) { 825 /* found matching one */ 826 break; 827 } 828 } else { 829 /* found empty one */ 830 break; 831 } 832 } 833 834 /* no available entry */ 835 if (index == dev->num_statics) 836 goto exit; 837 838 /* add entry */ 839 static_table[0] = ALU_V_STATIC_VALID; 840 static_table[1] |= BIT(port); 841 if (mdb->vid) 842 static_table[1] |= ALU_V_USE_FID; 843 static_table[2] = (mdb->vid << ALU_V_FID_S); 844 static_table[2] |= mac_hi; 845 static_table[3] = mac_lo; 846 847 ksz9477_write_table(dev, static_table); 848 849 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 850 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 851 852 /* wait to be finished */ 853 if (ksz9477_wait_alu_sta_ready(dev)) 854 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 855 856exit: 857 mutex_unlock(&dev->alu_mutex); 858} 859 860static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 861 const struct switchdev_obj_port_mdb *mdb) 862{ 863 struct ksz_device *dev = ds->priv; 864 u32 static_table[4]; 865 u32 data; 866 int index; 867 int ret = 0; 868 u32 mac_hi, mac_lo; 869 870 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 871 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 872 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 873 874 mutex_lock(&dev->alu_mutex); 875 876 for (index = 0; index < dev->num_statics; index++) { 877 /* find empty slot first */ 878 data = (index << ALU_STAT_INDEX_S) | 879 ALU_STAT_READ | ALU_STAT_START; 880 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 881 882 /* wait to be finished */ 883 ret = ksz9477_wait_alu_sta_ready(dev); 884 if (ret) { 885 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 886 goto exit; 887 } 888 889 /* read ALU static table */ 890 ksz9477_read_table(dev, static_table); 891 892 if (static_table[0] & ALU_V_STATIC_VALID) { 893 /* check this has same vid & mac address */ 894 895 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 896 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 897 static_table[3] == mac_lo) { 898 /* found matching one */ 899 break; 900 } 901 } 902 } 903 904 /* no available entry */ 905 if (index == dev->num_statics) 906 goto exit; 907 908 /* clear port */ 909 static_table[1] &= ~BIT(port); 910 911 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 912 /* delete entry */ 913 static_table[0] = 0; 914 static_table[1] = 0; 915 static_table[2] = 0; 916 static_table[3] = 0; 917 } 918 919 ksz9477_write_table(dev, static_table); 920 921 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 922 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 923 924 /* wait to be finished */ 925 ret = ksz9477_wait_alu_sta_ready(dev); 926 if (ret) 927 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 928 929exit: 930 mutex_unlock(&dev->alu_mutex); 931 932 return ret; 933} 934 935static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 936 struct dsa_mall_mirror_tc_entry *mirror, 937 bool ingress) 938{ 939 struct ksz_device *dev = ds->priv; 940 941 if (ingress) 942 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 943 else 944 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 945 946 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 947 948 /* configure mirror port */ 949 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 950 PORT_MIRROR_SNIFFER, true); 951 952 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 953 954 return 0; 955} 956 957static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 958 struct dsa_mall_mirror_tc_entry *mirror) 959{ 960 struct ksz_device *dev = ds->priv; 961 u8 data; 962 963 if (mirror->ingress) 964 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 965 else 966 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 967 968 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 969 970 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 971 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 972 PORT_MIRROR_SNIFFER, false); 973} 974 975static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 976{ 977 bool gbit; 978 979 if (dev->features & NEW_XMII) 980 gbit = !(data & PORT_MII_NOT_1GBIT); 981 else 982 gbit = !!(data & PORT_MII_1000MBIT_S1); 983 return gbit; 984} 985 986static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 987{ 988 if (dev->features & NEW_XMII) { 989 if (gbit) 990 *data &= ~PORT_MII_NOT_1GBIT; 991 else 992 *data |= PORT_MII_NOT_1GBIT; 993 } else { 994 if (gbit) 995 *data |= PORT_MII_1000MBIT_S1; 996 else 997 *data &= ~PORT_MII_1000MBIT_S1; 998 } 999} 1000 1001static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1002{ 1003 int mode; 1004 1005 if (dev->features & NEW_XMII) { 1006 switch (data & PORT_MII_SEL_M) { 1007 case PORT_MII_SEL: 1008 mode = 0; 1009 break; 1010 case PORT_RMII_SEL: 1011 mode = 1; 1012 break; 1013 case PORT_GMII_SEL: 1014 mode = 2; 1015 break; 1016 default: 1017 mode = 3; 1018 } 1019 } else { 1020 switch (data & PORT_MII_SEL_M) { 1021 case PORT_MII_SEL_S1: 1022 mode = 0; 1023 break; 1024 case PORT_RMII_SEL_S1: 1025 mode = 1; 1026 break; 1027 case PORT_GMII_SEL_S1: 1028 mode = 2; 1029 break; 1030 default: 1031 mode = 3; 1032 } 1033 } 1034 return mode; 1035} 1036 1037static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1038{ 1039 u8 xmii; 1040 1041 if (dev->features & NEW_XMII) { 1042 switch (mode) { 1043 case 0: 1044 xmii = PORT_MII_SEL; 1045 break; 1046 case 1: 1047 xmii = PORT_RMII_SEL; 1048 break; 1049 case 2: 1050 xmii = PORT_GMII_SEL; 1051 break; 1052 default: 1053 xmii = PORT_RGMII_SEL; 1054 break; 1055 } 1056 } else { 1057 switch (mode) { 1058 case 0: 1059 xmii = PORT_MII_SEL_S1; 1060 break; 1061 case 1: 1062 xmii = PORT_RMII_SEL_S1; 1063 break; 1064 case 2: 1065 xmii = PORT_GMII_SEL_S1; 1066 break; 1067 default: 1068 xmii = PORT_RGMII_SEL_S1; 1069 break; 1070 } 1071 } 1072 *data &= ~PORT_MII_SEL_M; 1073 *data |= xmii; 1074} 1075 1076static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1077{ 1078 phy_interface_t interface; 1079 bool gbit; 1080 int mode; 1081 u8 data8; 1082 1083 if (port < dev->phy_port_cnt) 1084 return PHY_INTERFACE_MODE_NA; 1085 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1086 gbit = ksz9477_get_gbit(dev, data8); 1087 mode = ksz9477_get_xmii(dev, data8); 1088 switch (mode) { 1089 case 2: 1090 interface = PHY_INTERFACE_MODE_GMII; 1091 if (gbit) 1092 break; 1093 fallthrough; 1094 case 0: 1095 interface = PHY_INTERFACE_MODE_MII; 1096 break; 1097 case 1: 1098 interface = PHY_INTERFACE_MODE_RMII; 1099 break; 1100 default: 1101 interface = PHY_INTERFACE_MODE_RGMII; 1102 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1103 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1104 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1105 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1106 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1107 interface = PHY_INTERFACE_MODE_RGMII_ID; 1108 } 1109 break; 1110 } 1111 return interface; 1112} 1113 1114static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1115 u8 dev_addr, u16 reg_addr, u16 val) 1116{ 1117 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1118 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1119 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1120 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1121 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1122 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1123} 1124 1125static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1126{ 1127 /* Apply PHY settings to address errata listed in 1128 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1129 * Silicon Errata and Data Sheet Clarification documents: 1130 * 1131 * Register settings are needed to improve PHY receive performance 1132 */ 1133 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1134 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1135 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1136 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1137 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1138 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1139 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1140 1141 /* Transmit waveform amplitude can be improved 1142 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1143 */ 1144 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1145 1146 /* Energy Efficient Ethernet (EEE) feature select must 1147 * be manually disabled (except on KSZ8565 which is 100Mbit) 1148 */ 1149 if (dev->features & GBIT_SUPPORT) 1150 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1151 1152 /* Register settings are required to meet data sheet 1153 * supply current specifications 1154 */ 1155 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1156 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1157 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1158 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1159 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1160 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1161 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1162 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1163 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1164 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1165 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1166 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1167 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1168} 1169 1170static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1171{ 1172 u8 data8; 1173 u8 member; 1174 u16 data16; 1175 struct ksz_port *p = &dev->ports[port]; 1176 1177 /* enable tag tail for host port */ 1178 if (cpu_port) 1179 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1180 true); 1181 1182 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1183 1184 /* set back pressure */ 1185 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1186 1187 /* enable broadcast storm limit */ 1188 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1189 1190 /* disable DiffServ priority */ 1191 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1192 1193 /* replace priority */ 1194 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1195 false); 1196 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1197 MTI_PVID_REPLACE, false); 1198 1199 /* enable 802.1p priority */ 1200 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1201 1202 if (port < dev->phy_port_cnt) { 1203 /* do not force flow control */ 1204 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1205 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1206 false); 1207 1208 if (dev->phy_errata_9477) 1209 ksz9477_phy_errata_setup(dev, port); 1210 } else { 1211 /* force flow control */ 1212 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1213 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1214 true); 1215 1216 /* configure MAC to 1G & RGMII mode */ 1217 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1218 switch (p->interface) { 1219 case PHY_INTERFACE_MODE_MII: 1220 ksz9477_set_xmii(dev, 0, &data8); 1221 ksz9477_set_gbit(dev, false, &data8); 1222 p->phydev.speed = SPEED_100; 1223 break; 1224 case PHY_INTERFACE_MODE_RMII: 1225 ksz9477_set_xmii(dev, 1, &data8); 1226 ksz9477_set_gbit(dev, false, &data8); 1227 p->phydev.speed = SPEED_100; 1228 break; 1229 case PHY_INTERFACE_MODE_GMII: 1230 ksz9477_set_xmii(dev, 2, &data8); 1231 ksz9477_set_gbit(dev, true, &data8); 1232 p->phydev.speed = SPEED_1000; 1233 break; 1234 default: 1235 ksz9477_set_xmii(dev, 3, &data8); 1236 ksz9477_set_gbit(dev, true, &data8); 1237 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1238 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1239 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1240 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1241 data8 |= PORT_RGMII_ID_IG_ENABLE; 1242 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1243 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1244 data8 |= PORT_RGMII_ID_EG_ENABLE; 1245 /* On KSZ9893, disable RGMII in-band status support */ 1246 if (dev->features & IS_9893) 1247 data8 &= ~PORT_MII_MAC_MODE; 1248 p->phydev.speed = SPEED_1000; 1249 break; 1250 } 1251 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1252 p->phydev.duplex = 1; 1253 } 1254 mutex_lock(&dev->dev_mutex); 1255 if (cpu_port) 1256 member = dev->port_mask; 1257 else 1258 member = dev->host_mask | p->vid_member; 1259 mutex_unlock(&dev->dev_mutex); 1260 ksz9477_cfg_port_member(dev, port, member); 1261 1262 /* clear pending interrupts */ 1263 if (port < dev->phy_port_cnt) 1264 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1265} 1266 1267static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1268{ 1269 struct ksz_device *dev = ds->priv; 1270 struct ksz_port *p; 1271 int i; 1272 1273 ds->num_ports = dev->port_cnt; 1274 1275 for (i = 0; i < dev->port_cnt; i++) { 1276 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1277 phy_interface_t interface; 1278 const char *prev_msg; 1279 const char *prev_mode; 1280 1281 dev->cpu_port = i; 1282 dev->host_mask = (1 << dev->cpu_port); 1283 dev->port_mask |= dev->host_mask; 1284 p = &dev->ports[i]; 1285 1286 /* Read from XMII register to determine host port 1287 * interface. If set specifically in device tree 1288 * note the difference to help debugging. 1289 */ 1290 interface = ksz9477_get_interface(dev, i); 1291 if (!p->interface) { 1292 if (dev->compat_interface) { 1293 dev_warn(dev->dev, 1294 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1295 "Please update your device tree.\n", 1296 i); 1297 p->interface = dev->compat_interface; 1298 } else { 1299 p->interface = interface; 1300 } 1301 } 1302 if (interface && interface != p->interface) { 1303 prev_msg = " instead of "; 1304 prev_mode = phy_modes(interface); 1305 } else { 1306 prev_msg = ""; 1307 prev_mode = ""; 1308 } 1309 dev_info(dev->dev, 1310 "Port%d: using phy mode %s%s%s\n", 1311 i, 1312 phy_modes(p->interface), 1313 prev_msg, 1314 prev_mode); 1315 1316 /* enable cpu port */ 1317 ksz9477_port_setup(dev, i, true); 1318 p->vid_member = dev->port_mask; 1319 p->on = 1; 1320 } 1321 } 1322 1323 dev->member = dev->host_mask; 1324 1325 for (i = 0; i < dev->mib_port_cnt; i++) { 1326 if (i == dev->cpu_port) 1327 continue; 1328 p = &dev->ports[i]; 1329 1330 /* Initialize to non-zero so that ksz_cfg_port_member() will 1331 * be called. 1332 */ 1333 p->vid_member = (1 << i); 1334 p->member = dev->port_mask; 1335 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1336 p->on = 1; 1337 if (i < dev->phy_port_cnt) 1338 p->phy = 1; 1339 if (dev->chip_id == 0x00947700 && i == 6) { 1340 p->sgmii = 1; 1341 1342 /* SGMII PHY detection code is not implemented yet. */ 1343 p->phy = 0; 1344 } 1345 } 1346} 1347 1348static int ksz9477_setup(struct dsa_switch *ds) 1349{ 1350 struct ksz_device *dev = ds->priv; 1351 int ret = 0; 1352 1353 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1354 dev->num_vlans, GFP_KERNEL); 1355 if (!dev->vlan_cache) 1356 return -ENOMEM; 1357 1358 ret = ksz9477_reset_switch(dev); 1359 if (ret) { 1360 dev_err(ds->dev, "failed to reset switch\n"); 1361 return ret; 1362 } 1363 1364 /* Required for port partitioning. */ 1365 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1366 true); 1367 1368 /* Do not work correctly with tail tagging. */ 1369 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1370 1371 /* accept packet up to 2000bytes */ 1372 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1373 1374 ksz9477_config_cpu_port(ds); 1375 1376 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1377 1378 /* queue based egress rate limit */ 1379 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1380 1381 /* enable global MIB counter freeze function */ 1382 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1383 1384 /* start switch */ 1385 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1386 1387 ksz_init_mib_timer(dev); 1388 1389 return 0; 1390} 1391 1392static const struct dsa_switch_ops ksz9477_switch_ops = { 1393 .get_tag_protocol = ksz9477_get_tag_protocol, 1394 .setup = ksz9477_setup, 1395 .phy_read = ksz9477_phy_read16, 1396 .phy_write = ksz9477_phy_write16, 1397 .phylink_mac_link_down = ksz_mac_link_down, 1398 .port_enable = ksz_enable_port, 1399 .get_strings = ksz9477_get_strings, 1400 .get_ethtool_stats = ksz_get_ethtool_stats, 1401 .get_sset_count = ksz_sset_count, 1402 .port_bridge_join = ksz_port_bridge_join, 1403 .port_bridge_leave = ksz_port_bridge_leave, 1404 .port_stp_state_set = ksz9477_port_stp_state_set, 1405 .port_fast_age = ksz_port_fast_age, 1406 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1407 .port_vlan_prepare = ksz_port_vlan_prepare, 1408 .port_vlan_add = ksz9477_port_vlan_add, 1409 .port_vlan_del = ksz9477_port_vlan_del, 1410 .port_fdb_dump = ksz9477_port_fdb_dump, 1411 .port_fdb_add = ksz9477_port_fdb_add, 1412 .port_fdb_del = ksz9477_port_fdb_del, 1413 .port_mdb_prepare = ksz_port_mdb_prepare, 1414 .port_mdb_add = ksz9477_port_mdb_add, 1415 .port_mdb_del = ksz9477_port_mdb_del, 1416 .port_mirror_add = ksz9477_port_mirror_add, 1417 .port_mirror_del = ksz9477_port_mirror_del, 1418}; 1419 1420static u32 ksz9477_get_port_addr(int port, int offset) 1421{ 1422 return PORT_CTRL_ADDR(port, offset); 1423} 1424 1425static int ksz9477_switch_detect(struct ksz_device *dev) 1426{ 1427 u8 data8; 1428 u8 id_hi; 1429 u8 id_lo; 1430 u32 id32; 1431 int ret; 1432 1433 /* turn off SPI DO Edge select */ 1434 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1435 if (ret) 1436 return ret; 1437 1438 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1439 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1440 if (ret) 1441 return ret; 1442 1443 /* read chip id */ 1444 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1445 if (ret) 1446 return ret; 1447 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1448 if (ret) 1449 return ret; 1450 1451 /* Number of ports can be reduced depending on chip. */ 1452 dev->mib_port_cnt = TOTAL_PORT_NUM; 1453 dev->phy_port_cnt = 5; 1454 1455 /* Default capability is gigabit capable. */ 1456 dev->features = GBIT_SUPPORT; 1457 1458 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1459 id_hi = (u8)(id32 >> 16); 1460 id_lo = (u8)(id32 >> 8); 1461 if ((id_lo & 0xf) == 3) { 1462 /* Chip is from KSZ9893 design. */ 1463 dev_info(dev->dev, "Found KSZ9893\n"); 1464 dev->features |= IS_9893; 1465 1466 /* Chip does not support gigabit. */ 1467 if (data8 & SW_QW_ABLE) 1468 dev->features &= ~GBIT_SUPPORT; 1469 dev->mib_port_cnt = 3; 1470 dev->phy_port_cnt = 2; 1471 } else { 1472 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1473 /* Chip uses new XMII register definitions. */ 1474 dev->features |= NEW_XMII; 1475 1476 /* Chip does not support gigabit. */ 1477 if (!(data8 & SW_GIGABIT_ABLE)) 1478 dev->features &= ~GBIT_SUPPORT; 1479 } 1480 1481 /* Change chip id to known ones so it can be matched against them. */ 1482 id32 = (id_hi << 16) | (id_lo << 8); 1483 1484 dev->chip_id = id32; 1485 1486 return 0; 1487} 1488 1489struct ksz_chip_data { 1490 u32 chip_id; 1491 const char *dev_name; 1492 int num_vlans; 1493 int num_alus; 1494 int num_statics; 1495 int cpu_ports; 1496 int port_cnt; 1497 bool phy_errata_9477; 1498}; 1499 1500static const struct ksz_chip_data ksz9477_switch_chips[] = { 1501 { 1502 .chip_id = 0x00947700, 1503 .dev_name = "KSZ9477", 1504 .num_vlans = 4096, 1505 .num_alus = 4096, 1506 .num_statics = 16, 1507 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1508 .port_cnt = 7, /* total physical port count */ 1509 .phy_errata_9477 = true, 1510 }, 1511 { 1512 .chip_id = 0x00989700, 1513 .dev_name = "KSZ9897", 1514 .num_vlans = 4096, 1515 .num_alus = 4096, 1516 .num_statics = 16, 1517 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1518 .port_cnt = 7, /* total physical port count */ 1519 .phy_errata_9477 = true, 1520 }, 1521 { 1522 .chip_id = 0x00989300, 1523 .dev_name = "KSZ9893", 1524 .num_vlans = 4096, 1525 .num_alus = 4096, 1526 .num_statics = 16, 1527 .cpu_ports = 0x07, /* can be configured as cpu port */ 1528 .port_cnt = 3, /* total port count */ 1529 }, 1530 { 1531 .chip_id = 0x00956700, 1532 .dev_name = "KSZ9567", 1533 .num_vlans = 4096, 1534 .num_alus = 4096, 1535 .num_statics = 16, 1536 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1537 .port_cnt = 7, /* total physical port count */ 1538 .phy_errata_9477 = true, 1539 }, 1540}; 1541 1542static int ksz9477_switch_init(struct ksz_device *dev) 1543{ 1544 int i; 1545 1546 dev->ds->ops = &ksz9477_switch_ops; 1547 1548 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1549 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1550 1551 if (dev->chip_id == chip->chip_id) { 1552 dev->name = chip->dev_name; 1553 dev->num_vlans = chip->num_vlans; 1554 dev->num_alus = chip->num_alus; 1555 dev->num_statics = chip->num_statics; 1556 dev->port_cnt = chip->port_cnt; 1557 dev->cpu_ports = chip->cpu_ports; 1558 dev->phy_errata_9477 = chip->phy_errata_9477; 1559 1560 break; 1561 } 1562 } 1563 1564 /* no switch found */ 1565 if (!dev->port_cnt) 1566 return -ENODEV; 1567 1568 dev->port_mask = (1 << dev->port_cnt) - 1; 1569 1570 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1571 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1572 1573 i = dev->mib_port_cnt; 1574 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1575 GFP_KERNEL); 1576 if (!dev->ports) 1577 return -ENOMEM; 1578 for (i = 0; i < dev->mib_port_cnt; i++) { 1579 mutex_init(&dev->ports[i].mib.cnt_mutex); 1580 dev->ports[i].mib.counters = 1581 devm_kzalloc(dev->dev, 1582 sizeof(u64) * 1583 (TOTAL_SWITCH_COUNTER_NUM + 1), 1584 GFP_KERNEL); 1585 if (!dev->ports[i].mib.counters) 1586 return -ENOMEM; 1587 } 1588 1589 /* set the real number of ports */ 1590 dev->ds->num_ports = dev->port_cnt; 1591 1592 return 0; 1593} 1594 1595static void ksz9477_switch_exit(struct ksz_device *dev) 1596{ 1597 ksz9477_reset_switch(dev); 1598} 1599 1600static const struct ksz_dev_ops ksz9477_dev_ops = { 1601 .get_port_addr = ksz9477_get_port_addr, 1602 .cfg_port_member = ksz9477_cfg_port_member, 1603 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1604 .port_setup = ksz9477_port_setup, 1605 .r_mib_cnt = ksz9477_r_mib_cnt, 1606 .r_mib_pkt = ksz9477_r_mib_pkt, 1607 .freeze_mib = ksz9477_freeze_mib, 1608 .port_init_cnt = ksz9477_port_init_cnt, 1609 .shutdown = ksz9477_reset_switch, 1610 .detect = ksz9477_switch_detect, 1611 .init = ksz9477_switch_init, 1612 .exit = ksz9477_switch_exit, 1613}; 1614 1615int ksz9477_switch_register(struct ksz_device *dev) 1616{ 1617 int ret, i; 1618 struct phy_device *phydev; 1619 1620 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1621 if (ret) 1622 return ret; 1623 1624 for (i = 0; i < dev->phy_port_cnt; ++i) { 1625 if (!dsa_is_user_port(dev->ds, i)) 1626 continue; 1627 1628 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1629 1630 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1631 phy_remove_link_mode(phydev, 1632 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1633 1634 /* PHY does not support gigabit. */ 1635 if (!(dev->features & GBIT_SUPPORT)) 1636 phy_remove_link_mode(phydev, 1637 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1638 } 1639 return ret; 1640} 1641EXPORT_SYMBOL(ksz9477_switch_register); 1642 1643MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1644MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1645MODULE_LICENSE("GPL"); 1646