1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Broadcom Starfighter 2 switch register defines 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7#ifndef __BCM_SF2_REGS_H 8#define __BCM_SF2_REGS_H 9 10/* Register set relative to 'REG' */ 11 12enum bcm_sf2_reg_offs { 13 REG_SWITCH_CNTRL = 0, 14 REG_SWITCH_STATUS, 15 REG_DIR_DATA_WRITE, 16 REG_DIR_DATA_READ, 17 REG_SWITCH_REVISION, 18 REG_PHY_REVISION, 19 REG_SPHY_CNTRL, 20 REG_RGMII_0_CNTRL, 21 REG_RGMII_1_CNTRL, 22 REG_RGMII_2_CNTRL, 23 REG_LED_0_CNTRL, 24 REG_LED_1_CNTRL, 25 REG_LED_2_CNTRL, 26 REG_SWITCH_REG_MAX, 27}; 28 29/* Relative to REG_SWITCH_CNTRL */ 30#define MDIO_MASTER_SEL (1 << 0) 31 32/* Relative to REG_SWITCH_REVISION */ 33#define SF2_REV_MASK 0xffff 34#define SWITCH_TOP_REV_SHIFT 16 35#define SWITCH_TOP_REV_MASK 0xffff 36 37/* Relative to REG_PHY_REVISION */ 38#define PHY_REVISION_MASK 0xffff 39 40/* Relative to REG_SPHY_CNTRL */ 41#define IDDQ_BIAS (1 << 0) 42#define EXT_PWR_DOWN (1 << 1) 43#define FORCE_DLL_EN (1 << 2) 44#define IDDQ_GLOBAL_PWR (1 << 3) 45#define CK25_DIS (1 << 4) 46#define PHY_RESET (1 << 5) 47#define PHY_PHYAD_SHIFT 8 48#define PHY_PHYAD_MASK 0x1F 49 50#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x)) 51 52/* Relative to REG_RGMII_CNTRL */ 53#define RGMII_MODE_EN (1 << 0) 54#define ID_MODE_DIS (1 << 1) 55#define PORT_MODE_SHIFT 2 56#define INT_EPHY (0 << PORT_MODE_SHIFT) 57#define INT_GPHY (1 << PORT_MODE_SHIFT) 58#define EXT_EPHY (2 << PORT_MODE_SHIFT) 59#define EXT_GPHY (3 << PORT_MODE_SHIFT) 60#define EXT_REVMII (4 << PORT_MODE_SHIFT) 61#define PORT_MODE_MASK 0x7 62#define RVMII_REF_SEL (1 << 5) 63#define RX_PAUSE_EN (1 << 6) 64#define TX_PAUSE_EN (1 << 7) 65#define TX_CLK_STOP_EN (1 << 8) 66#define LPI_COUNT_SHIFT 9 67#define LPI_COUNT_MASK 0x3F 68 69#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x)) 70 71#define SPDLNK_SRC_SEL (1 << 24) 72 73/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ 74#define INTRL2_CPU_STATUS 0x00 75#define INTRL2_CPU_SET 0x04 76#define INTRL2_CPU_CLEAR 0x08 77#define INTRL2_CPU_MASK_STATUS 0x0c 78#define INTRL2_CPU_MASK_SET 0x10 79#define INTRL2_CPU_MASK_CLEAR 0x14 80 81/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */ 82#define P_LINK_UP_IRQ(x) (1 << (0 + (x))) 83#define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) 84#define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) 85#define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) 86#define P_GPHY_IRQ(x) (1 << (4 + (x))) 87#define P_NUM_IRQ 5 88#define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ 89 P_LINK_DOWN_IRQ((x)) | \ 90 P_ENERGY_ON_IRQ((x)) | \ 91 P_ENERGY_OFF_IRQ((x)) | \ 92 P_GPHY_IRQ((x))) 93 94/* INTRL2_0 interrupt sources */ 95#define P0_IRQ_OFF 0 96#define MEM_DOUBLE_IRQ (1 << 5) 97#define EEE_LPI_IRQ (1 << 6) 98#define P5_CPU_WAKE_IRQ (1 << 7) 99#define P8_CPU_WAKE_IRQ (1 << 8) 100#define P7_CPU_WAKE_IRQ (1 << 9) 101#define IEEE1588_IRQ (1 << 10) 102#define MDIO_ERR_IRQ (1 << 11) 103#define MDIO_DONE_IRQ (1 << 12) 104#define GISB_ERR_IRQ (1 << 13) 105#define UBUS_ERR_IRQ (1 << 14) 106#define FAILOVER_ON_IRQ (1 << 15) 107#define FAILOVER_OFF_IRQ (1 << 16) 108#define TCAM_SOFT_ERR_IRQ (1 << 17) 109 110/* INTRL2_1 interrupt sources */ 111#define P7_IRQ_OFF 0 112#define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) 113 114/* Register set relative to 'ACB' */ 115#define ACB_CONTROL 0x00 116#define ACB_EN (1 << 0) 117#define ACB_ALGORITHM (1 << 1) 118#define ACB_FLUSH_SHIFT 2 119#define ACB_FLUSH_MASK 0x3 120 121#define ACB_QUEUE_0_CFG 0x08 122#define XOFF_THRESHOLD_MASK 0x7ff 123#define XON_EN (1 << 11) 124#define TOTAL_XOFF_THRESHOLD_SHIFT 12 125#define TOTAL_XOFF_THRESHOLD_MASK 0x7ff 126#define TOTAL_XOFF_EN (1 << 23) 127#define TOTAL_XON_EN (1 << 24) 128#define PKTLEN_SHIFT 25 129#define PKTLEN_MASK 0x3f 130#define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4)) 131 132/* Register set relative to 'CORE' */ 133#define CORE_G_PCTL_PORT0 0x00000 134#define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) 135#define CORE_IMP_CTL 0x00020 136#define RX_DIS (1 << 0) 137#define TX_DIS (1 << 1) 138#define RX_BCST_EN (1 << 2) 139#define RX_MCST_EN (1 << 3) 140#define RX_UCST_EN (1 << 4) 141 142#define CORE_SWMODE 0x0002c 143#define SW_FWDG_MODE (1 << 0) 144#define SW_FWDG_EN (1 << 1) 145#define RTRY_LMT_DIS (1 << 2) 146 147#define CORE_STS_OVERRIDE_IMP 0x00038 148#define GMII_SPEED_UP_2G (1 << 6) 149#define MII_SW_OR (1 << 7) 150 151/* Alternate layout for e.g: 7278 */ 152#define CORE_STS_OVERRIDE_IMP2 0x39040 153 154#define CORE_NEW_CTRL 0x00084 155#define IP_MC (1 << 0) 156#define OUTRANGEERR_DISCARD (1 << 1) 157#define INRANGEERR_DISCARD (1 << 2) 158#define CABLE_DIAG_LEN (1 << 3) 159#define OVERRIDE_AUTO_PD_WAR (1 << 4) 160#define EN_AUTO_PD_WAR (1 << 5) 161#define UC_FWD_EN (1 << 6) 162#define MC_FWD_EN (1 << 7) 163 164#define CORE_SWITCH_CTRL 0x00088 165#define MII_DUMB_FWDG_EN (1 << 6) 166 167#define CORE_DIS_LEARN 0x000f0 168 169#define CORE_SFT_LRN_CTRL 0x000f8 170#define SW_LEARN_CNTL(x) (1 << (x)) 171 172#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) 173#define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8) 174#define LINK_STS (1 << 0) 175#define DUPLX_MODE (1 << 1) 176#define SPEED_SHIFT 2 177#define SPEED_MASK 0x3 178#define RXFLOW_CNTL (1 << 4) 179#define TXFLOW_CNTL (1 << 5) 180#define SW_OVERRIDE (1 << 6) 181 182#define CORE_WATCHDOG_CTRL 0x001e4 183#define SOFTWARE_RESET (1 << 7) 184#define EN_CHIP_RST (1 << 6) 185#define EN_SW_RESET (1 << 4) 186 187#define CORE_FAST_AGE_CTRL 0x00220 188#define EN_FAST_AGE_STATIC (1 << 0) 189#define EN_AGE_DYNAMIC (1 << 1) 190#define EN_AGE_PORT (1 << 2) 191#define EN_AGE_VLAN (1 << 3) 192#define EN_AGE_SPT (1 << 4) 193#define EN_AGE_MCAST (1 << 5) 194#define FAST_AGE_STR_DONE (1 << 7) 195 196#define CORE_FAST_AGE_PORT 0x00224 197#define AGE_PORT_MASK 0xf 198 199#define CORE_FAST_AGE_VID 0x00228 200#define AGE_VID_MASK 0x3fff 201 202#define CORE_LNKSTS 0x00400 203#define LNK_STS_MASK 0x1ff 204 205#define CORE_SPDSTS 0x00410 206#define SPDSTS_10 0 207#define SPDSTS_100 1 208#define SPDSTS_1000 2 209#define SPDSTS_SHIFT 2 210#define SPDSTS_MASK 0x3 211 212#define CORE_DUPSTS 0x00420 213#define CORE_DUPSTS_MASK 0x1ff 214 215#define CORE_PAUSESTS 0x00428 216#define PAUSESTS_TX_PAUSE_SHIFT 9 217 218#define CORE_GMNCFGCFG 0x0800 219#define RST_MIB_CNT (1 << 0) 220#define RXBPDU_EN (1 << 1) 221 222#define CORE_IMP0_PRT_ID 0x0804 223 224#define CORE_RST_MIB_CNT_EN 0x0950 225 226#define CORE_ARLA_VTBL_RWCTRL 0x1600 227#define ARLA_VTBL_CMD_WRITE 0 228#define ARLA_VTBL_CMD_READ 1 229#define ARLA_VTBL_CMD_CLEAR 2 230#define ARLA_VTBL_STDN (1 << 7) 231 232#define CORE_ARLA_VTBL_ADDR 0x1604 233#define VTBL_ADDR_INDEX_MASK 0xfff 234 235#define CORE_ARLA_VTBL_ENTRY 0x160c 236#define FWD_MAP_MASK 0x1ff 237#define UNTAG_MAP_MASK 0x1ff 238#define UNTAG_MAP_SHIFT 9 239#define MSTP_INDEX_MASK 0x7 240#define MSTP_INDEX_SHIFT 18 241#define FWD_MODE (1 << 21) 242 243#define CORE_MEM_PSM_VDD_CTRL 0x2380 244#define P_TXQ_PSM_VDD_SHIFT 2 245#define P_TXQ_PSM_VDD_MASK 0x3 246#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ 247 ((x) * P_TXQ_PSM_VDD_SHIFT)) 248 249#define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10)) 250#define PRT_TO_QID_MASK 0x3 251#define PRT_TO_QID_SHIFT 3 252 253#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) 254#define PORT_VLAN_CTRL_MASK 0x1ff 255 256#define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80 257#define TXQ_PAUSE_THD_MASK 0x7ff 258#define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \ 259 (x) * 0x8) 260 261#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) 262#define CFI_SHIFT 12 263#define PRI_SHIFT 13 264#define PRI_MASK 0x7 265 266#define CORE_JOIN_ALL_VLAN_EN 0xd140 267 268#define CORE_CFP_ACC 0x28000 269#define OP_STR_DONE (1 << 0) 270#define OP_SEL_SHIFT 1 271#define OP_SEL_READ (1 << OP_SEL_SHIFT) 272#define OP_SEL_WRITE (2 << OP_SEL_SHIFT) 273#define OP_SEL_SEARCH (4 << OP_SEL_SHIFT) 274#define OP_SEL_MASK (7 << OP_SEL_SHIFT) 275#define CFP_RAM_CLEAR (1 << 4) 276#define RAM_SEL_SHIFT 10 277#define TCAM_SEL (1 << RAM_SEL_SHIFT) 278#define ACT_POL_RAM (2 << RAM_SEL_SHIFT) 279#define RATE_METER_RAM (4 << RAM_SEL_SHIFT) 280#define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT) 281#define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT) 282#define RED_STAT_RAM (24 << RAM_SEL_SHIFT) 283#define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT) 284#define TCAM_RESET (1 << 15) 285#define XCESS_ADDR_SHIFT 16 286#define XCESS_ADDR_MASK 0xff 287#define SEARCH_STS (1 << 27) 288#define RD_STS_SHIFT 28 289#define RD_STS_TCAM (1 << RD_STS_SHIFT) 290#define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT) 291#define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT) 292#define RD_STS_STAT_RAM (8 << RD_STS_SHIFT) 293 294#define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010 295 296#define CORE_CFP_DATA_PORT_0 0x28040 297#define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \ 298 (x) * 0x10) 299 300/* UDF_DATA7 */ 301#define L3_FRAMING_SHIFT 24 302#define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT) 303#define IPTOS_SHIFT 16 304#define IPTOS_MASK 0xff 305#define IPPROTO_SHIFT 8 306#define IPPROTO_MASK (0xff << IPPROTO_SHIFT) 307#define IP_FRAG_SHIFT 7 308#define IP_FRAG (1 << IP_FRAG_SHIFT) 309 310/* UDF_DATA0 */ 311#define SLICE_VALID 3 312#define SLICE_NUM_SHIFT 2 313#define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT) 314#define SLICE_NUM_MASK 0x3 315 316#define CORE_CFP_MASK_PORT_0 0x280c0 317 318#define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \ 319 (x) * 0x10) 320 321#define CORE_ACT_POL_DATA0 0x28140 322#define VLAN_BYP (1 << 0) 323#define EAP_BYP (1 << 1) 324#define STP_BYP (1 << 2) 325#define REASON_CODE_SHIFT 3 326#define REASON_CODE_MASK 0x3f 327#define LOOP_BK_EN (1 << 9) 328#define NEW_TC_SHIFT 10 329#define NEW_TC_MASK 0x7 330#define CHANGE_TC (1 << 13) 331#define DST_MAP_IB_SHIFT 14 332#define DST_MAP_IB_MASK 0x1ff 333#define CHANGE_FWRD_MAP_IB_SHIFT 24 334#define CHANGE_FWRD_MAP_IB_MASK 0x3 335#define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT) 336#define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT) 337#define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT) 338#define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT) 339#define NEW_DSCP_IB_SHIFT 26 340#define NEW_DSCP_IB_MASK 0x3f 341 342#define CORE_ACT_POL_DATA1 0x28150 343#define CHANGE_DSCP_IB (1 << 0) 344#define DST_MAP_OB_SHIFT 1 345#define DST_MAP_OB_MASK 0x3ff 346#define CHANGE_FWRD_MAP_OB_SHIT 11 347#define CHANGE_FWRD_MAP_OB_MASK 0x3 348#define NEW_DSCP_OB_SHIFT 13 349#define NEW_DSCP_OB_MASK 0x3f 350#define CHANGE_DSCP_OB (1 << 19) 351#define CHAIN_ID_SHIFT 20 352#define CHAIN_ID_MASK 0xff 353#define CHANGE_COLOR (1 << 28) 354#define NEW_COLOR_SHIFT 29 355#define NEW_COLOR_MASK 0x3 356#define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT) 357#define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT) 358#define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT) 359#define RED_DEFAULT (1 << 31) 360 361#define CORE_ACT_POL_DATA2 0x28160 362#define MAC_LIMIT_BYPASS (1 << 0) 363#define CHANGE_TC_O (1 << 1) 364#define NEW_TC_O_SHIFT 2 365#define NEW_TC_O_MASK 0x7 366#define SPCP_RMK_DISABLE (1 << 5) 367#define CPCP_RMK_DISABLE (1 << 6) 368#define DEI_RMK_DISABLE (1 << 7) 369 370#define CORE_RATE_METER0 0x28180 371#define COLOR_MODE (1 << 0) 372#define POLICER_ACTION (1 << 1) 373#define COUPLING_FLAG (1 << 2) 374#define POLICER_MODE_SHIFT 3 375#define POLICER_MODE_MASK 0x3 376#define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT) 377#define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT) 378#define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT) 379#define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT) 380 381#define CORE_RATE_METER1 0x28190 382#define EIR_TK_BKT_MASK 0x7fffff 383 384#define CORE_RATE_METER2 0x281a0 385#define EIR_BKT_SIZE_MASK 0xfffff 386 387#define CORE_RATE_METER3 0x281b0 388#define EIR_REF_CNT_MASK 0x7ffff 389 390#define CORE_RATE_METER4 0x281c0 391#define CIR_TK_BKT_MASK 0x7fffff 392 393#define CORE_RATE_METER5 0x281d0 394#define CIR_BKT_SIZE_MASK 0xfffff 395 396#define CORE_RATE_METER6 0x281e0 397#define CIR_REF_CNT_MASK 0x7ffff 398 399#define CORE_STAT_GREEN_CNTR 0x28200 400#define CORE_STAT_YELLOW_CNTR 0x28210 401#define CORE_STAT_RED_CNTR 0x28220 402 403#define CORE_CFP_CTL_REG 0x28400 404#define CFP_EN_MAP_MASK 0x1ff 405 406/* IPv4 slices, 3 of them */ 407#define CORE_UDF_0_A_0_8_PORT_0 0x28440 408#define CFG_UDF_OFFSET_MASK 0x1f 409#define CFG_UDF_OFFSET_BASE_SHIFT 5 410#define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT) 411#define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT) 412#define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT) 413 414/* IPv6 slices */ 415#define CORE_UDF_0_B_0_8_PORT_0 0x28500 416 417/* IPv6 chained slices */ 418#define CORE_UDF_0_D_0_11_PORT_0 0x28680 419 420/* Number of slices for IPv4, IPv6 and non-IP */ 421#define UDF_NUM_SLICES 4 422#define UDFS_PER_SLICE 9 423 424/* Spacing between different slices */ 425#define UDF_SLICE_OFFSET 0x40 426 427#define CFP_NUM_RULES 256 428 429/* Number of egress queues per port */ 430#define SF2_NUM_EGRESS_QUEUES 8 431 432#endif /* __BCM_SF2_REGS_H */ 433