18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Northstar Plus switch SerDes/SGMII PHY definitions
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#include <linux/phy.h>
98c2ecf20Sopenharmony_ci#include <linux/types.h>
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci/* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
128c2ecf20Sopenharmony_ci#define B53_SERDES_PAGE			0x16
138c2ecf20Sopenharmony_ci#define B53_SERDES_BLKADDR		0x3e
148c2ecf20Sopenharmony_ci#define B53_SERDES_LANE			0x3c
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci#define B53_SERDES_ID0			0x20
178c2ecf20Sopenharmony_ci#define  SERDES_ID0_MODEL_MASK		0x3f
188c2ecf20Sopenharmony_ci#define  SERDES_ID0_REV_NUM_SHIFT	11
198c2ecf20Sopenharmony_ci#define  SERDES_ID0_REV_NUM_MASK	0x7
208c2ecf20Sopenharmony_ci#define  SERDES_ID0_REV_LETTER_SHIFT	14
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci#define B53_SERDES_MII_REG(x)		(0x20 + (x) * 2)
238c2ecf20Sopenharmony_ci#define B53_SERDES_DIGITAL_CONTROL(x)	(0x1e + (x) * 2)
248c2ecf20Sopenharmony_ci#define B53_SERDES_DIGITAL_STATUS	0x28
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci/* SERDES_DIGITAL_CONTROL1 */
278c2ecf20Sopenharmony_ci#define  FIBER_MODE_1000X		BIT(0)
288c2ecf20Sopenharmony_ci#define  TBI_INTERFACE			BIT(1)
298c2ecf20Sopenharmony_ci#define  SIGNAL_DETECT_EN		BIT(2)
308c2ecf20Sopenharmony_ci#define  INVERT_SIGNAL_DETECT		BIT(3)
318c2ecf20Sopenharmony_ci#define  AUTODET_EN			BIT(4)
328c2ecf20Sopenharmony_ci#define  SGMII_MASTER_MODE		BIT(5)
338c2ecf20Sopenharmony_ci#define  DISABLE_DLL_PWRDOWN		BIT(6)
348c2ecf20Sopenharmony_ci#define  CRC_CHECKER_DIS		BIT(7)
358c2ecf20Sopenharmony_ci#define  COMMA_DET_EN			BIT(8)
368c2ecf20Sopenharmony_ci#define  ZERO_COMMA_DET_EN		BIT(9)
378c2ecf20Sopenharmony_ci#define  REMOTE_LOOPBACK		BIT(10)
388c2ecf20Sopenharmony_ci#define  SEL_RX_PKTS_FOR_CNTR		BIT(11)
398c2ecf20Sopenharmony_ci#define  MASTER_MDIO_PHY_SEL		BIT(13)
408c2ecf20Sopenharmony_ci#define  DISABLE_SIGNAL_DETECT_FLT	BIT(14)
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci/* SERDES_DIGITAL_CONTROL2 */
438c2ecf20Sopenharmony_ci#define  EN_PARALLEL_DET		BIT(0)
448c2ecf20Sopenharmony_ci#define  DIS_FALSE_LINK			BIT(1)
458c2ecf20Sopenharmony_ci#define  FLT_FORCE_LINK			BIT(2)
468c2ecf20Sopenharmony_ci#define  EN_AUTONEG_ERR_TIMER		BIT(3)
478c2ecf20Sopenharmony_ci#define  DIS_REMOTE_FAULT_SENSING	BIT(4)
488c2ecf20Sopenharmony_ci#define  FORCE_XMIT_DATA		BIT(5)
498c2ecf20Sopenharmony_ci#define  AUTONEG_FAST_TIMERS		BIT(6)
508c2ecf20Sopenharmony_ci#define  DIS_CARRIER_EXTEND		BIT(7)
518c2ecf20Sopenharmony_ci#define  DIS_TRRR_GENERATION		BIT(8)
528c2ecf20Sopenharmony_ci#define  BYPASS_PCS_RX			BIT(9)
538c2ecf20Sopenharmony_ci#define  BYPASS_PCS_TX			BIT(10)
548c2ecf20Sopenharmony_ci#define  TEST_CNTR_EN			BIT(11)
558c2ecf20Sopenharmony_ci#define  TX_PACKET_SEQ_TEST		BIT(12)
568c2ecf20Sopenharmony_ci#define  TX_IDLE_JAM_SEQ_TEST		BIT(13)
578c2ecf20Sopenharmony_ci#define  CLR_BER_CNTR			BIT(14)
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci/* SERDES_DIGITAL_CONTROL3 */
608c2ecf20Sopenharmony_ci#define  TX_FIFO_RST			BIT(0)
618c2ecf20Sopenharmony_ci#define  FIFO_ELAST_TX_RX_SHIFT		1
628c2ecf20Sopenharmony_ci#define  FIFO_ELAST_TX_RX_5K		0
638c2ecf20Sopenharmony_ci#define  FIFO_ELAST_TX_RX_10K		1
648c2ecf20Sopenharmony_ci#define  FIFO_ELAST_TX_RX_13_5K		2
658c2ecf20Sopenharmony_ci#define  FIFO_ELAST_TX_RX_18_5K		3
668c2ecf20Sopenharmony_ci#define  BLOCK_TXEN_MODE		BIT(9)
678c2ecf20Sopenharmony_ci#define  JAM_FALSE_CARRIER_MODE		BIT(10)
688c2ecf20Sopenharmony_ci#define  EXT_PHY_CRS_MODE		BIT(11)
698c2ecf20Sopenharmony_ci#define  INVERT_EXT_PHY_CRS		BIT(12)
708c2ecf20Sopenharmony_ci#define  DISABLE_TX_CRS			BIT(13)
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ci/* SERDES_DIGITAL_STATUS */
738c2ecf20Sopenharmony_ci#define  SGMII_MODE			BIT(0)
748c2ecf20Sopenharmony_ci#define  LINK_STATUS			BIT(1)
758c2ecf20Sopenharmony_ci#define  DUPLEX_STATUS			BIT(2)
768c2ecf20Sopenharmony_ci#define  SPEED_STATUS_SHIFT		3
778c2ecf20Sopenharmony_ci#define  SPEED_STATUS_10		0
788c2ecf20Sopenharmony_ci#define  SPEED_STATUS_100		1
798c2ecf20Sopenharmony_ci#define  SPEED_STATUS_1000		2
808c2ecf20Sopenharmony_ci#define  SPEED_STATUS_2500		3
818c2ecf20Sopenharmony_ci#define  SPEED_STATUS_MASK		SPEED_STATUS_2500
828c2ecf20Sopenharmony_ci#define  PAUSE_RESOLUTION_TX_SIDE	BIT(5)
838c2ecf20Sopenharmony_ci#define  PAUSE_RESOLUTION_RX_SIDE	BIT(6)
848c2ecf20Sopenharmony_ci#define  LINK_STATUS_CHANGE		BIT(7)
858c2ecf20Sopenharmony_ci#define  EARLY_END_EXT_DET		BIT(8)
868c2ecf20Sopenharmony_ci#define  CARRIER_EXT_ERR_DET		BIT(9)
878c2ecf20Sopenharmony_ci#define  RX_ERR_DET			BIT(10)
888c2ecf20Sopenharmony_ci#define  TX_ERR_DET			BIT(11)
898c2ecf20Sopenharmony_ci#define  CRC_ERR_DET			BIT(12)
908c2ecf20Sopenharmony_ci#define  FALSE_CARRIER_ERR_DET		BIT(13)
918c2ecf20Sopenharmony_ci#define  RXFIFO_ERR_DET			BIT(14)
928c2ecf20Sopenharmony_ci#define  TXFIFO_ERR_DET			BIT(15)
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ci/* Block offsets */
958c2ecf20Sopenharmony_ci#define SERDES_DIGITAL_BLK		0x8300
968c2ecf20Sopenharmony_ci#define SERDES_ID0			0x8310
978c2ecf20Sopenharmony_ci#define SERDES_MII_BLK			0xffe0
988c2ecf20Sopenharmony_ci#define SERDES_XGXSBLK0_BLOCKADDRESS	0xffd0
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_cistruct phylink_link_state;
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_cistatic inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
1038c2ecf20Sopenharmony_ci{
1048c2ecf20Sopenharmony_ci	if (!dev->ops->serdes_map_lane)
1058c2ecf20Sopenharmony_ci		return B53_INVALID_LANE;
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ci	return dev->ops->serdes_map_lane(dev, port);
1088c2ecf20Sopenharmony_ci}
1098c2ecf20Sopenharmony_ci
1108c2ecf20Sopenharmony_ciint b53_serdes_get_link(struct b53_device *dev, int port);
1118c2ecf20Sopenharmony_ciint b53_serdes_link_state(struct b53_device *dev, int port,
1128c2ecf20Sopenharmony_ci			  struct phylink_link_state *state);
1138c2ecf20Sopenharmony_civoid b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
1148c2ecf20Sopenharmony_ci		       const struct phylink_link_state *state);
1158c2ecf20Sopenharmony_civoid b53_serdes_an_restart(struct b53_device *dev, int port);
1168c2ecf20Sopenharmony_civoid b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
1178c2ecf20Sopenharmony_ci			 phy_interface_t interface, bool link_up);
1188c2ecf20Sopenharmony_civoid b53_serdes_phylink_validate(struct b53_device *dev, int port,
1198c2ecf20Sopenharmony_ci				unsigned long *supported,
1208c2ecf20Sopenharmony_ci				struct phylink_link_state *state);
1218c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_B53_SERDES)
1228c2ecf20Sopenharmony_ciint b53_serdes_init(struct b53_device *dev, int port);
1238c2ecf20Sopenharmony_ci#else
1248c2ecf20Sopenharmony_cistatic inline int b53_serdes_init(struct b53_device *dev, int port)
1258c2ecf20Sopenharmony_ci{
1268c2ecf20Sopenharmony_ci	return -ENODEV;
1278c2ecf20Sopenharmony_ci}
1288c2ecf20Sopenharmony_ci#endif
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