1// SPDX-License-Identifier: GPL-2.0-only 2/* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface 3 * 4 * MCP2510 support and bug fixes by Christian Pellegrin 5 * <chripell@evolware.org> 6 * 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * 9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 10 * Written under contract by: 11 * Chris Elston, Katalix Systems, Ltd. 12 * 13 * Based on Microchip MCP251x CAN controller driver written by 14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. 15 * 16 * Based on CAN bus driver for the CCAN controller written by 17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 18 * - Simon Kallweit, intefo AG 19 * Copyright 2007 20 */ 21 22#include <linux/bitfield.h> 23#include <linux/can/core.h> 24#include <linux/can/dev.h> 25#include <linux/can/led.h> 26#include <linux/clk.h> 27#include <linux/completion.h> 28#include <linux/delay.h> 29#include <linux/device.h> 30#include <linux/freezer.h> 31#include <linux/gpio.h> 32#include <linux/gpio/driver.h> 33#include <linux/interrupt.h> 34#include <linux/io.h> 35#include <linux/iopoll.h> 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/netdevice.h> 39#include <linux/platform_device.h> 40#include <linux/property.h> 41#include <linux/regulator/consumer.h> 42#include <linux/slab.h> 43#include <linux/spi/spi.h> 44#include <linux/uaccess.h> 45 46/* SPI interface instruction set */ 47#define INSTRUCTION_WRITE 0x02 48#define INSTRUCTION_READ 0x03 49#define INSTRUCTION_BIT_MODIFY 0x05 50#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) 51#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) 52#define INSTRUCTION_RESET 0xC0 53#define RTS_TXB0 0x01 54#define RTS_TXB1 0x02 55#define RTS_TXB2 0x04 56#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) 57 58/* MPC251x registers */ 59#define BFPCTRL 0x0c 60# define BFPCTRL_B0BFM BIT(0) 61# define BFPCTRL_B1BFM BIT(1) 62# define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n)) 63# define BFPCTRL_BFM_MASK GENMASK(1, 0) 64# define BFPCTRL_B0BFE BIT(2) 65# define BFPCTRL_B1BFE BIT(3) 66# define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n)) 67# define BFPCTRL_BFE_MASK GENMASK(3, 2) 68# define BFPCTRL_B0BFS BIT(4) 69# define BFPCTRL_B1BFS BIT(5) 70# define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n)) 71# define BFPCTRL_BFS_MASK GENMASK(5, 4) 72#define TXRTSCTRL 0x0d 73# define TXRTSCTRL_B0RTSM BIT(0) 74# define TXRTSCTRL_B1RTSM BIT(1) 75# define TXRTSCTRL_B2RTSM BIT(2) 76# define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n)) 77# define TXRTSCTRL_RTSM_MASK GENMASK(2, 0) 78# define TXRTSCTRL_B0RTS BIT(3) 79# define TXRTSCTRL_B1RTS BIT(4) 80# define TXRTSCTRL_B2RTS BIT(5) 81# define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n)) 82# define TXRTSCTRL_RTS_MASK GENMASK(5, 3) 83#define CANSTAT 0x0e 84#define CANCTRL 0x0f 85# define CANCTRL_REQOP_MASK 0xe0 86# define CANCTRL_REQOP_CONF 0x80 87# define CANCTRL_REQOP_LISTEN_ONLY 0x60 88# define CANCTRL_REQOP_LOOPBACK 0x40 89# define CANCTRL_REQOP_SLEEP 0x20 90# define CANCTRL_REQOP_NORMAL 0x00 91# define CANCTRL_OSM 0x08 92# define CANCTRL_ABAT 0x10 93#define TEC 0x1c 94#define REC 0x1d 95#define CNF1 0x2a 96# define CNF1_SJW_SHIFT 6 97#define CNF2 0x29 98# define CNF2_BTLMODE 0x80 99# define CNF2_SAM 0x40 100# define CNF2_PS1_SHIFT 3 101#define CNF3 0x28 102# define CNF3_SOF 0x08 103# define CNF3_WAKFIL 0x04 104# define CNF3_PHSEG2_MASK 0x07 105#define CANINTE 0x2b 106# define CANINTE_MERRE 0x80 107# define CANINTE_WAKIE 0x40 108# define CANINTE_ERRIE 0x20 109# define CANINTE_TX2IE 0x10 110# define CANINTE_TX1IE 0x08 111# define CANINTE_TX0IE 0x04 112# define CANINTE_RX1IE 0x02 113# define CANINTE_RX0IE 0x01 114#define CANINTF 0x2c 115# define CANINTF_MERRF 0x80 116# define CANINTF_WAKIF 0x40 117# define CANINTF_ERRIF 0x20 118# define CANINTF_TX2IF 0x10 119# define CANINTF_TX1IF 0x08 120# define CANINTF_TX0IF 0x04 121# define CANINTF_RX1IF 0x02 122# define CANINTF_RX0IF 0x01 123# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) 124# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) 125# define CANINTF_ERR (CANINTF_ERRIF) 126#define EFLG 0x2d 127# define EFLG_EWARN 0x01 128# define EFLG_RXWAR 0x02 129# define EFLG_TXWAR 0x04 130# define EFLG_RXEP 0x08 131# define EFLG_TXEP 0x10 132# define EFLG_TXBO 0x20 133# define EFLG_RX0OVR 0x40 134# define EFLG_RX1OVR 0x80 135#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) 136# define TXBCTRL_ABTF 0x40 137# define TXBCTRL_MLOA 0x20 138# define TXBCTRL_TXERR 0x10 139# define TXBCTRL_TXREQ 0x08 140#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) 141# define SIDH_SHIFT 3 142#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) 143# define SIDL_SID_MASK 7 144# define SIDL_SID_SHIFT 5 145# define SIDL_EXIDE_SHIFT 3 146# define SIDL_EID_SHIFT 16 147# define SIDL_EID_MASK 3 148#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) 149#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) 150#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) 151# define DLC_RTR_SHIFT 6 152#define TXBCTRL_OFF 0 153#define TXBSIDH_OFF 1 154#define TXBSIDL_OFF 2 155#define TXBEID8_OFF 3 156#define TXBEID0_OFF 4 157#define TXBDLC_OFF 5 158#define TXBDAT_OFF 6 159#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) 160# define RXBCTRL_BUKT 0x04 161# define RXBCTRL_RXM0 0x20 162# define RXBCTRL_RXM1 0x40 163#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) 164# define RXBSIDH_SHIFT 3 165#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) 166# define RXBSIDL_IDE 0x08 167# define RXBSIDL_SRR 0x10 168# define RXBSIDL_EID 3 169# define RXBSIDL_SHIFT 5 170#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) 171#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) 172#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) 173# define RXBDLC_LEN_MASK 0x0f 174# define RXBDLC_RTR 0x40 175#define RXBCTRL_OFF 0 176#define RXBSIDH_OFF 1 177#define RXBSIDL_OFF 2 178#define RXBEID8_OFF 3 179#define RXBEID0_OFF 4 180#define RXBDLC_OFF 5 181#define RXBDAT_OFF 6 182#define RXFSID(n) ((n < 3) ? 0 : 4) 183#define RXFSIDH(n) ((n) * 4 + RXFSID(n)) 184#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n)) 185#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n)) 186#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n)) 187#define RXMSIDH(n) ((n) * 4 + 0x20) 188#define RXMSIDL(n) ((n) * 4 + 0x21) 189#define RXMEID8(n) ((n) * 4 + 0x22) 190#define RXMEID0(n) ((n) * 4 + 0x23) 191 192#define GET_BYTE(val, byte) \ 193 (((val) >> ((byte) * 8)) & 0xff) 194#define SET_BYTE(val, byte) \ 195 (((val) & 0xff) << ((byte) * 8)) 196 197/* Buffer size required for the largest SPI transfer (i.e., reading a 198 * frame) 199 */ 200#define CAN_FRAME_MAX_DATA_LEN 8 201#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) 202#define CAN_FRAME_MAX_BITS 128 203 204#define TX_ECHO_SKB_MAX 1 205 206#define MCP251X_OST_DELAY_MS (5) 207 208#define DEVICE_NAME "mcp251x" 209 210static const struct can_bittiming_const mcp251x_bittiming_const = { 211 .name = DEVICE_NAME, 212 .tseg1_min = 3, 213 .tseg1_max = 16, 214 .tseg2_min = 2, 215 .tseg2_max = 8, 216 .sjw_max = 4, 217 .brp_min = 1, 218 .brp_max = 64, 219 .brp_inc = 1, 220}; 221 222enum mcp251x_model { 223 CAN_MCP251X_MCP2510 = 0x2510, 224 CAN_MCP251X_MCP2515 = 0x2515, 225 CAN_MCP251X_MCP25625 = 0x25625, 226}; 227 228struct mcp251x_priv { 229 struct can_priv can; 230 struct net_device *net; 231 struct spi_device *spi; 232 enum mcp251x_model model; 233 234 struct mutex mcp_lock; /* SPI device lock */ 235 236 u8 *spi_tx_buf; 237 u8 *spi_rx_buf; 238 239 struct sk_buff *tx_skb; 240 int tx_len; 241 242 struct workqueue_struct *wq; 243 struct work_struct tx_work; 244 struct work_struct restart_work; 245 246 int force_quit; 247 int after_suspend; 248#define AFTER_SUSPEND_UP 1 249#define AFTER_SUSPEND_DOWN 2 250#define AFTER_SUSPEND_POWER 4 251#define AFTER_SUSPEND_RESTART 8 252 int restart_tx; 253 struct regulator *power; 254 struct regulator *transceiver; 255 struct clk *clk; 256#ifdef CONFIG_GPIOLIB 257 struct gpio_chip gpio; 258 u8 reg_bfpctrl; 259#endif 260}; 261 262#define MCP251X_IS(_model) \ 263static inline int mcp251x_is_##_model(struct spi_device *spi) \ 264{ \ 265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \ 266 return priv->model == CAN_MCP251X_MCP##_model; \ 267} 268 269MCP251X_IS(2510); 270 271static void mcp251x_clean(struct net_device *net) 272{ 273 struct mcp251x_priv *priv = netdev_priv(net); 274 275 if (priv->tx_skb || priv->tx_len) 276 net->stats.tx_errors++; 277 dev_kfree_skb(priv->tx_skb); 278 if (priv->tx_len) 279 can_free_echo_skb(priv->net, 0); 280 priv->tx_skb = NULL; 281 priv->tx_len = 0; 282} 283 284/* Note about handling of error return of mcp251x_spi_trans: accessing 285 * registers via SPI is not really different conceptually than using 286 * normal I/O assembler instructions, although it's much more 287 * complicated from a practical POV. So it's not advisable to always 288 * check the return value of this function. Imagine that every 289 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 290 * error();", it would be a great mess (well there are some situation 291 * when exception handling C++ like could be useful after all). So we 292 * just check that transfers are OK at the beginning of our 293 * conversation with the chip and to avoid doing really nasty things 294 * (like injecting bogus packets in the network stack). 295 */ 296static int mcp251x_spi_trans(struct spi_device *spi, int len) 297{ 298 struct mcp251x_priv *priv = spi_get_drvdata(spi); 299 struct spi_transfer t = { 300 .tx_buf = priv->spi_tx_buf, 301 .rx_buf = priv->spi_rx_buf, 302 .len = len, 303 .cs_change = 0, 304 }; 305 struct spi_message m; 306 int ret; 307 308 spi_message_init(&m); 309 spi_message_add_tail(&t, &m); 310 311 ret = spi_sync(spi, &m); 312 if (ret) 313 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 314 return ret; 315} 316 317static int mcp251x_spi_write(struct spi_device *spi, int len) 318{ 319 struct mcp251x_priv *priv = spi_get_drvdata(spi); 320 int ret; 321 322 ret = spi_write(spi, priv->spi_tx_buf, len); 323 if (ret) 324 dev_err(&spi->dev, "spi write failed: ret = %d\n", ret); 325 326 return ret; 327} 328 329static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg) 330{ 331 struct mcp251x_priv *priv = spi_get_drvdata(spi); 332 u8 val = 0; 333 334 priv->spi_tx_buf[0] = INSTRUCTION_READ; 335 priv->spi_tx_buf[1] = reg; 336 337 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) { 338 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1); 339 } else { 340 mcp251x_spi_trans(spi, 3); 341 val = priv->spi_rx_buf[2]; 342 } 343 344 return val; 345} 346 347static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2) 348{ 349 struct mcp251x_priv *priv = spi_get_drvdata(spi); 350 351 priv->spi_tx_buf[0] = INSTRUCTION_READ; 352 priv->spi_tx_buf[1] = reg; 353 354 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) { 355 u8 val[2] = { 0 }; 356 357 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2); 358 *v1 = val[0]; 359 *v2 = val[1]; 360 } else { 361 mcp251x_spi_trans(spi, 4); 362 363 *v1 = priv->spi_rx_buf[2]; 364 *v2 = priv->spi_rx_buf[3]; 365 } 366} 367 368static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val) 369{ 370 struct mcp251x_priv *priv = spi_get_drvdata(spi); 371 372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 373 priv->spi_tx_buf[1] = reg; 374 priv->spi_tx_buf[2] = val; 375 376 mcp251x_spi_write(spi, 3); 377} 378 379static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2) 380{ 381 struct mcp251x_priv *priv = spi_get_drvdata(spi); 382 383 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 384 priv->spi_tx_buf[1] = reg; 385 priv->spi_tx_buf[2] = v1; 386 priv->spi_tx_buf[3] = v2; 387 388 mcp251x_spi_write(spi, 4); 389} 390 391static void mcp251x_write_bits(struct spi_device *spi, u8 reg, 392 u8 mask, u8 val) 393{ 394 struct mcp251x_priv *priv = spi_get_drvdata(spi); 395 396 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; 397 priv->spi_tx_buf[1] = reg; 398 priv->spi_tx_buf[2] = mask; 399 priv->spi_tx_buf[3] = val; 400 401 mcp251x_spi_write(spi, 4); 402} 403 404static u8 mcp251x_read_stat(struct spi_device *spi) 405{ 406 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK; 407} 408 409#define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \ 410 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \ 411 delay_us, timeout_us) 412 413#ifdef CONFIG_GPIOLIB 414enum { 415 MCP251X_GPIO_TX0RTS = 0, /* inputs */ 416 MCP251X_GPIO_TX1RTS, 417 MCP251X_GPIO_TX2RTS, 418 MCP251X_GPIO_RX0BF, /* outputs */ 419 MCP251X_GPIO_RX1BF, 420}; 421 422#define MCP251X_GPIO_INPUT_MASK \ 423 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS) 424#define MCP251X_GPIO_OUTPUT_MASK \ 425 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF) 426 427static const char * const mcp251x_gpio_names[] = { 428 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */ 429 [MCP251X_GPIO_TX1RTS] = "TX1RTS", 430 [MCP251X_GPIO_TX2RTS] = "TX2RTS", 431 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */ 432 [MCP251X_GPIO_RX1BF] = "RX1BF", 433}; 434 435static inline bool mcp251x_gpio_is_input(unsigned int offset) 436{ 437 return offset <= MCP251X_GPIO_TX2RTS; 438} 439 440static int mcp251x_gpio_request(struct gpio_chip *chip, 441 unsigned int offset) 442{ 443 struct mcp251x_priv *priv = gpiochip_get_data(chip); 444 u8 val; 445 446 /* nothing to be done for inputs */ 447 if (mcp251x_gpio_is_input(offset)) 448 return 0; 449 450 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF); 451 452 mutex_lock(&priv->mcp_lock); 453 mcp251x_write_bits(priv->spi, BFPCTRL, val, val); 454 mutex_unlock(&priv->mcp_lock); 455 456 priv->reg_bfpctrl |= val; 457 458 return 0; 459} 460 461static void mcp251x_gpio_free(struct gpio_chip *chip, 462 unsigned int offset) 463{ 464 struct mcp251x_priv *priv = gpiochip_get_data(chip); 465 u8 val; 466 467 /* nothing to be done for inputs */ 468 if (mcp251x_gpio_is_input(offset)) 469 return; 470 471 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF); 472 473 mutex_lock(&priv->mcp_lock); 474 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0); 475 mutex_unlock(&priv->mcp_lock); 476 477 priv->reg_bfpctrl &= ~val; 478} 479 480static int mcp251x_gpio_get_direction(struct gpio_chip *chip, 481 unsigned int offset) 482{ 483 if (mcp251x_gpio_is_input(offset)) 484 return GPIOF_DIR_IN; 485 486 return GPIOF_DIR_OUT; 487} 488 489static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset) 490{ 491 struct mcp251x_priv *priv = gpiochip_get_data(chip); 492 u8 reg, mask, val; 493 494 if (mcp251x_gpio_is_input(offset)) { 495 reg = TXRTSCTRL; 496 mask = TXRTSCTRL_RTS(offset); 497 } else { 498 reg = BFPCTRL; 499 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF); 500 } 501 502 mutex_lock(&priv->mcp_lock); 503 val = mcp251x_read_reg(priv->spi, reg); 504 mutex_unlock(&priv->mcp_lock); 505 506 return !!(val & mask); 507} 508 509static int mcp251x_gpio_get_multiple(struct gpio_chip *chip, 510 unsigned long *maskp, unsigned long *bitsp) 511{ 512 struct mcp251x_priv *priv = gpiochip_get_data(chip); 513 unsigned long bits = 0; 514 u8 val; 515 516 mutex_lock(&priv->mcp_lock); 517 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) { 518 val = mcp251x_read_reg(priv->spi, TXRTSCTRL); 519 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val); 520 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val); 521 } 522 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) { 523 val = mcp251x_read_reg(priv->spi, BFPCTRL); 524 val = FIELD_GET(BFPCTRL_BFS_MASK, val); 525 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val); 526 } 527 mutex_unlock(&priv->mcp_lock); 528 529 bitsp[0] = bits; 530 return 0; 531} 532 533static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset, 534 int value) 535{ 536 struct mcp251x_priv *priv = gpiochip_get_data(chip); 537 u8 mask, val; 538 539 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF); 540 val = value ? mask : 0; 541 542 mutex_lock(&priv->mcp_lock); 543 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val); 544 mutex_unlock(&priv->mcp_lock); 545 546 priv->reg_bfpctrl &= ~mask; 547 priv->reg_bfpctrl |= val; 548} 549 550static void 551mcp251x_gpio_set_multiple(struct gpio_chip *chip, 552 unsigned long *maskp, unsigned long *bitsp) 553{ 554 struct mcp251x_priv *priv = gpiochip_get_data(chip); 555 u8 mask, val; 556 557 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]); 558 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask); 559 560 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]); 561 val = FIELD_PREP(BFPCTRL_BFS_MASK, val); 562 563 if (!mask) 564 return; 565 566 mutex_lock(&priv->mcp_lock); 567 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val); 568 mutex_unlock(&priv->mcp_lock); 569 570 priv->reg_bfpctrl &= ~mask; 571 priv->reg_bfpctrl |= val; 572} 573 574static void mcp251x_gpio_restore(struct spi_device *spi) 575{ 576 struct mcp251x_priv *priv = spi_get_drvdata(spi); 577 578 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl); 579} 580 581static int mcp251x_gpio_setup(struct mcp251x_priv *priv) 582{ 583 struct gpio_chip *gpio = &priv->gpio; 584 585 if (!device_property_present(&priv->spi->dev, "gpio-controller")) 586 return 0; 587 588 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */ 589 gpio->label = priv->spi->modalias; 590 gpio->parent = &priv->spi->dev; 591 gpio->owner = THIS_MODULE; 592 gpio->request = mcp251x_gpio_request; 593 gpio->free = mcp251x_gpio_free; 594 gpio->get_direction = mcp251x_gpio_get_direction; 595 gpio->get = mcp251x_gpio_get; 596 gpio->get_multiple = mcp251x_gpio_get_multiple; 597 gpio->set = mcp251x_gpio_set; 598 gpio->set_multiple = mcp251x_gpio_set_multiple; 599 gpio->base = -1; 600 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names); 601 gpio->names = mcp251x_gpio_names; 602 gpio->can_sleep = true; 603#ifdef CONFIG_OF_GPIO 604 gpio->of_node = priv->spi->dev.of_node; 605#endif 606 607 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv); 608} 609#else 610static inline void mcp251x_gpio_restore(struct spi_device *spi) 611{ 612} 613 614static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv) 615{ 616 return 0; 617} 618#endif 619 620static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, 621 int len, int tx_buf_idx) 622{ 623 struct mcp251x_priv *priv = spi_get_drvdata(spi); 624 625 if (mcp251x_is_2510(spi)) { 626 int i; 627 628 for (i = 1; i < TXBDAT_OFF + len; i++) 629 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, 630 buf[i]); 631 } else { 632 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); 633 mcp251x_spi_write(spi, TXBDAT_OFF + len); 634 } 635} 636 637static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, 638 int tx_buf_idx) 639{ 640 struct mcp251x_priv *priv = spi_get_drvdata(spi); 641 u32 sid, eid, exide, rtr; 642 u8 buf[SPI_TRANSFER_BUF_LEN]; 643 644 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ 645 if (exide) 646 sid = (frame->can_id & CAN_EFF_MASK) >> 18; 647 else 648 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ 649 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ 650 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ 651 652 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); 653 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; 654 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | 655 (exide << SIDL_EXIDE_SHIFT) | 656 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); 657 buf[TXBEID8_OFF] = GET_BYTE(eid, 1); 658 buf[TXBEID0_OFF] = GET_BYTE(eid, 0); 659 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; 660 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); 661 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); 662 663 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ 664 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); 665 mcp251x_spi_write(priv->spi, 1); 666} 667 668static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, 669 int buf_idx) 670{ 671 struct mcp251x_priv *priv = spi_get_drvdata(spi); 672 673 if (mcp251x_is_2510(spi)) { 674 int i, len; 675 676 for (i = 1; i < RXBDAT_OFF; i++) 677 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 678 679 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 680 for (; i < (RXBDAT_OFF + len); i++) 681 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 682 } else { 683 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); 684 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) { 685 spi_write_then_read(spi, priv->spi_tx_buf, 1, 686 priv->spi_rx_buf, 687 SPI_TRANSFER_BUF_LEN); 688 memcpy(buf + 1, priv->spi_rx_buf, 689 SPI_TRANSFER_BUF_LEN - 1); 690 } else { 691 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); 692 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); 693 } 694 } 695} 696 697static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) 698{ 699 struct mcp251x_priv *priv = spi_get_drvdata(spi); 700 struct sk_buff *skb; 701 struct can_frame *frame; 702 u8 buf[SPI_TRANSFER_BUF_LEN]; 703 704 skb = alloc_can_skb(priv->net, &frame); 705 if (!skb) { 706 dev_err(&spi->dev, "cannot allocate RX skb\n"); 707 priv->net->stats.rx_dropped++; 708 return; 709 } 710 711 mcp251x_hw_rx_frame(spi, buf, buf_idx); 712 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { 713 /* Extended ID format */ 714 frame->can_id = CAN_EFF_FLAG; 715 frame->can_id |= 716 /* Extended ID part */ 717 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | 718 SET_BYTE(buf[RXBEID8_OFF], 1) | 719 SET_BYTE(buf[RXBEID0_OFF], 0) | 720 /* Standard ID part */ 721 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 722 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); 723 /* Remote transmission request */ 724 if (buf[RXBDLC_OFF] & RXBDLC_RTR) 725 frame->can_id |= CAN_RTR_FLAG; 726 } else { 727 /* Standard ID format */ 728 frame->can_id = 729 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 730 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); 731 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) 732 frame->can_id |= CAN_RTR_FLAG; 733 } 734 /* Data length */ 735 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 736 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); 737 738 priv->net->stats.rx_packets++; 739 priv->net->stats.rx_bytes += frame->can_dlc; 740 741 can_led_event(priv->net, CAN_LED_EVENT_RX); 742 743 netif_rx_ni(skb); 744} 745 746static void mcp251x_hw_sleep(struct spi_device *spi) 747{ 748 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); 749} 750 751/* May only be called when device is sleeping! */ 752static int mcp251x_hw_wake(struct spi_device *spi) 753{ 754 u8 value; 755 int ret; 756 757 /* Force wakeup interrupt to wake device, but don't execute IST */ 758 disable_irq_nosync(spi->irq); 759 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF); 760 761 /* Wait for oscillator startup timer after wake up */ 762 mdelay(MCP251X_OST_DELAY_MS); 763 764 /* Put device into config mode */ 765 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF); 766 767 /* Wait for the device to enter config mode */ 768 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF, 769 MCP251X_OST_DELAY_MS * 1000, 770 USEC_PER_SEC); 771 if (ret) { 772 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n"); 773 return ret; 774 } 775 776 /* Disable and clear pending interrupts */ 777 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00); 778 enable_irq(spi->irq); 779 780 return 0; 781} 782 783static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, 784 struct net_device *net) 785{ 786 struct mcp251x_priv *priv = netdev_priv(net); 787 struct spi_device *spi = priv->spi; 788 789 if (priv->tx_skb || priv->tx_len) { 790 dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); 791 return NETDEV_TX_BUSY; 792 } 793 794 if (can_dropped_invalid_skb(net, skb)) 795 return NETDEV_TX_OK; 796 797 netif_stop_queue(net); 798 priv->tx_skb = skb; 799 queue_work(priv->wq, &priv->tx_work); 800 801 return NETDEV_TX_OK; 802} 803 804static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) 805{ 806 struct mcp251x_priv *priv = netdev_priv(net); 807 808 switch (mode) { 809 case CAN_MODE_START: 810 mcp251x_clean(net); 811 /* We have to delay work since SPI I/O may sleep */ 812 priv->can.state = CAN_STATE_ERROR_ACTIVE; 813 priv->restart_tx = 1; 814 if (priv->can.restart_ms == 0) 815 priv->after_suspend = AFTER_SUSPEND_RESTART; 816 queue_work(priv->wq, &priv->restart_work); 817 break; 818 default: 819 return -EOPNOTSUPP; 820 } 821 822 return 0; 823} 824 825static int mcp251x_set_normal_mode(struct spi_device *spi) 826{ 827 struct mcp251x_priv *priv = spi_get_drvdata(spi); 828 u8 value; 829 int ret; 830 831 /* Enable interrupts */ 832 mcp251x_write_reg(spi, CANINTE, 833 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | 834 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); 835 836 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 837 /* Put device into loopback mode */ 838 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); 839 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 840 /* Put device into listen-only mode */ 841 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); 842 } else { 843 /* Put device into normal mode */ 844 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); 845 846 /* Wait for the device to enter normal mode */ 847 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0, 848 MCP251X_OST_DELAY_MS * 1000, 849 USEC_PER_SEC); 850 if (ret) { 851 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n"); 852 return ret; 853 } 854 } 855 priv->can.state = CAN_STATE_ERROR_ACTIVE; 856 return 0; 857} 858 859static int mcp251x_do_set_bittiming(struct net_device *net) 860{ 861 struct mcp251x_priv *priv = netdev_priv(net); 862 struct can_bittiming *bt = &priv->can.bittiming; 863 struct spi_device *spi = priv->spi; 864 865 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | 866 (bt->brp - 1)); 867 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | 868 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 869 CNF2_SAM : 0) | 870 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | 871 (bt->prop_seg - 1)); 872 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, 873 (bt->phase_seg2 - 1)); 874 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", 875 mcp251x_read_reg(spi, CNF1), 876 mcp251x_read_reg(spi, CNF2), 877 mcp251x_read_reg(spi, CNF3)); 878 879 return 0; 880} 881 882static int mcp251x_setup(struct net_device *net, struct spi_device *spi) 883{ 884 mcp251x_do_set_bittiming(net); 885 886 mcp251x_write_reg(spi, RXBCTRL(0), 887 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); 888 mcp251x_write_reg(spi, RXBCTRL(1), 889 RXBCTRL_RXM0 | RXBCTRL_RXM1); 890 return 0; 891} 892 893static int mcp251x_hw_reset(struct spi_device *spi) 894{ 895 struct mcp251x_priv *priv = spi_get_drvdata(spi); 896 u8 value; 897 int ret; 898 899 /* Wait for oscillator startup timer after power up */ 900 mdelay(MCP251X_OST_DELAY_MS); 901 902 priv->spi_tx_buf[0] = INSTRUCTION_RESET; 903 ret = mcp251x_spi_write(spi, 1); 904 if (ret) 905 return ret; 906 907 /* Wait for oscillator startup timer after reset */ 908 mdelay(MCP251X_OST_DELAY_MS); 909 910 /* Wait for reset to finish */ 911 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF, 912 MCP251X_OST_DELAY_MS * 1000, 913 USEC_PER_SEC); 914 if (ret) 915 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n"); 916 return ret; 917} 918 919static int mcp251x_hw_probe(struct spi_device *spi) 920{ 921 u8 ctrl; 922 int ret; 923 924 ret = mcp251x_hw_reset(spi); 925 if (ret) 926 return ret; 927 928 ctrl = mcp251x_read_reg(spi, CANCTRL); 929 930 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl); 931 932 /* Check for power up default value */ 933 if ((ctrl & 0x17) != 0x07) 934 return -ENODEV; 935 936 return 0; 937} 938 939static int mcp251x_power_enable(struct regulator *reg, int enable) 940{ 941 if (IS_ERR_OR_NULL(reg)) 942 return 0; 943 944 if (enable) 945 return regulator_enable(reg); 946 else 947 return regulator_disable(reg); 948} 949 950static int mcp251x_stop(struct net_device *net) 951{ 952 struct mcp251x_priv *priv = netdev_priv(net); 953 struct spi_device *spi = priv->spi; 954 955 close_candev(net); 956 957 priv->force_quit = 1; 958 free_irq(spi->irq, priv); 959 960 mutex_lock(&priv->mcp_lock); 961 962 /* Disable and clear pending interrupts */ 963 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00); 964 965 mcp251x_write_reg(spi, TXBCTRL(0), 0); 966 mcp251x_clean(net); 967 968 mcp251x_hw_sleep(spi); 969 970 mcp251x_power_enable(priv->transceiver, 0); 971 972 priv->can.state = CAN_STATE_STOPPED; 973 974 mutex_unlock(&priv->mcp_lock); 975 976 can_led_event(net, CAN_LED_EVENT_STOP); 977 978 return 0; 979} 980 981static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) 982{ 983 struct sk_buff *skb; 984 struct can_frame *frame; 985 986 skb = alloc_can_err_skb(net, &frame); 987 if (skb) { 988 frame->can_id |= can_id; 989 frame->data[1] = data1; 990 netif_rx_ni(skb); 991 } else { 992 netdev_err(net, "cannot allocate error skb\n"); 993 } 994} 995 996static void mcp251x_tx_work_handler(struct work_struct *ws) 997{ 998 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 999 tx_work); 1000 struct spi_device *spi = priv->spi; 1001 struct net_device *net = priv->net; 1002 struct can_frame *frame; 1003 1004 mutex_lock(&priv->mcp_lock); 1005 if (priv->tx_skb) { 1006 if (priv->can.state == CAN_STATE_BUS_OFF) { 1007 mcp251x_clean(net); 1008 } else { 1009 frame = (struct can_frame *)priv->tx_skb->data; 1010 1011 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) 1012 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; 1013 mcp251x_hw_tx(spi, frame, 0); 1014 priv->tx_len = 1 + frame->can_dlc; 1015 can_put_echo_skb(priv->tx_skb, net, 0); 1016 priv->tx_skb = NULL; 1017 } 1018 } 1019 mutex_unlock(&priv->mcp_lock); 1020} 1021 1022static void mcp251x_restart_work_handler(struct work_struct *ws) 1023{ 1024 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 1025 restart_work); 1026 struct spi_device *spi = priv->spi; 1027 struct net_device *net = priv->net; 1028 1029 mutex_lock(&priv->mcp_lock); 1030 if (priv->after_suspend) { 1031 if (priv->after_suspend & AFTER_SUSPEND_POWER) { 1032 mcp251x_hw_reset(spi); 1033 mcp251x_setup(net, spi); 1034 mcp251x_gpio_restore(spi); 1035 } else { 1036 mcp251x_hw_wake(spi); 1037 } 1038 priv->force_quit = 0; 1039 if (priv->after_suspend & AFTER_SUSPEND_RESTART) { 1040 mcp251x_set_normal_mode(spi); 1041 } else if (priv->after_suspend & AFTER_SUSPEND_UP) { 1042 netif_device_attach(net); 1043 mcp251x_clean(net); 1044 mcp251x_set_normal_mode(spi); 1045 netif_wake_queue(net); 1046 } else { 1047 mcp251x_hw_sleep(spi); 1048 } 1049 priv->after_suspend = 0; 1050 } 1051 1052 if (priv->restart_tx) { 1053 priv->restart_tx = 0; 1054 mcp251x_write_reg(spi, TXBCTRL(0), 0); 1055 mcp251x_clean(net); 1056 netif_wake_queue(net); 1057 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); 1058 } 1059 mutex_unlock(&priv->mcp_lock); 1060} 1061 1062static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) 1063{ 1064 struct mcp251x_priv *priv = dev_id; 1065 struct spi_device *spi = priv->spi; 1066 struct net_device *net = priv->net; 1067 1068 mutex_lock(&priv->mcp_lock); 1069 while (!priv->force_quit) { 1070 enum can_state new_state; 1071 u8 intf, eflag; 1072 u8 clear_intf = 0; 1073 int can_id = 0, data1 = 0; 1074 1075 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); 1076 1077 /* receive buffer 0 */ 1078 if (intf & CANINTF_RX0IF) { 1079 mcp251x_hw_rx(spi, 0); 1080 /* Free one buffer ASAP 1081 * (The MCP2515/25625 does this automatically.) 1082 */ 1083 if (mcp251x_is_2510(spi)) 1084 mcp251x_write_bits(spi, CANINTF, 1085 CANINTF_RX0IF, 0x00); 1086 1087 /* check if buffer 1 is already known to be full, no need to re-read */ 1088 if (!(intf & CANINTF_RX1IF)) { 1089 u8 intf1, eflag1; 1090 1091 /* intf needs to be read again to avoid a race condition */ 1092 mcp251x_read_2regs(spi, CANINTF, &intf1, &eflag1); 1093 1094 /* combine flags from both operations for error handling */ 1095 intf |= intf1; 1096 eflag |= eflag1; 1097 } 1098 } 1099 1100 /* receive buffer 1 */ 1101 if (intf & CANINTF_RX1IF) { 1102 mcp251x_hw_rx(spi, 1); 1103 /* The MCP2515/25625 does this automatically. */ 1104 if (mcp251x_is_2510(spi)) 1105 clear_intf |= CANINTF_RX1IF; 1106 } 1107 1108 /* mask out flags we don't care about */ 1109 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; 1110 1111 /* any error or tx interrupt we need to clear? */ 1112 if (intf & (CANINTF_ERR | CANINTF_TX)) 1113 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); 1114 if (clear_intf) 1115 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); 1116 1117 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) 1118 mcp251x_write_bits(spi, EFLG, eflag, 0x00); 1119 1120 /* Update can state */ 1121 if (eflag & EFLG_TXBO) { 1122 new_state = CAN_STATE_BUS_OFF; 1123 can_id |= CAN_ERR_BUSOFF; 1124 } else if (eflag & EFLG_TXEP) { 1125 new_state = CAN_STATE_ERROR_PASSIVE; 1126 can_id |= CAN_ERR_CRTL; 1127 data1 |= CAN_ERR_CRTL_TX_PASSIVE; 1128 } else if (eflag & EFLG_RXEP) { 1129 new_state = CAN_STATE_ERROR_PASSIVE; 1130 can_id |= CAN_ERR_CRTL; 1131 data1 |= CAN_ERR_CRTL_RX_PASSIVE; 1132 } else if (eflag & EFLG_TXWAR) { 1133 new_state = CAN_STATE_ERROR_WARNING; 1134 can_id |= CAN_ERR_CRTL; 1135 data1 |= CAN_ERR_CRTL_TX_WARNING; 1136 } else if (eflag & EFLG_RXWAR) { 1137 new_state = CAN_STATE_ERROR_WARNING; 1138 can_id |= CAN_ERR_CRTL; 1139 data1 |= CAN_ERR_CRTL_RX_WARNING; 1140 } else { 1141 new_state = CAN_STATE_ERROR_ACTIVE; 1142 } 1143 1144 /* Update can state statistics */ 1145 switch (priv->can.state) { 1146 case CAN_STATE_ERROR_ACTIVE: 1147 if (new_state >= CAN_STATE_ERROR_WARNING && 1148 new_state <= CAN_STATE_BUS_OFF) 1149 priv->can.can_stats.error_warning++; 1150 fallthrough; 1151 case CAN_STATE_ERROR_WARNING: 1152 if (new_state >= CAN_STATE_ERROR_PASSIVE && 1153 new_state <= CAN_STATE_BUS_OFF) 1154 priv->can.can_stats.error_passive++; 1155 break; 1156 default: 1157 break; 1158 } 1159 priv->can.state = new_state; 1160 1161 if (intf & CANINTF_ERRIF) { 1162 /* Handle overflow counters */ 1163 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { 1164 if (eflag & EFLG_RX0OVR) { 1165 net->stats.rx_over_errors++; 1166 net->stats.rx_errors++; 1167 } 1168 if (eflag & EFLG_RX1OVR) { 1169 net->stats.rx_over_errors++; 1170 net->stats.rx_errors++; 1171 } 1172 can_id |= CAN_ERR_CRTL; 1173 data1 |= CAN_ERR_CRTL_RX_OVERFLOW; 1174 } 1175 mcp251x_error_skb(net, can_id, data1); 1176 } 1177 1178 if (priv->can.state == CAN_STATE_BUS_OFF) { 1179 if (priv->can.restart_ms == 0) { 1180 priv->force_quit = 1; 1181 priv->can.can_stats.bus_off++; 1182 can_bus_off(net); 1183 mcp251x_hw_sleep(spi); 1184 break; 1185 } 1186 } 1187 1188 if (intf == 0) 1189 break; 1190 1191 if (intf & CANINTF_TX) { 1192 net->stats.tx_packets++; 1193 net->stats.tx_bytes += priv->tx_len - 1; 1194 can_led_event(net, CAN_LED_EVENT_TX); 1195 if (priv->tx_len) { 1196 can_get_echo_skb(net, 0); 1197 priv->tx_len = 0; 1198 } 1199 netif_wake_queue(net); 1200 } 1201 } 1202 mutex_unlock(&priv->mcp_lock); 1203 return IRQ_HANDLED; 1204} 1205 1206static int mcp251x_open(struct net_device *net) 1207{ 1208 struct mcp251x_priv *priv = netdev_priv(net); 1209 struct spi_device *spi = priv->spi; 1210 unsigned long flags = 0; 1211 int ret; 1212 1213 ret = open_candev(net); 1214 if (ret) { 1215 dev_err(&spi->dev, "unable to set initial baudrate!\n"); 1216 return ret; 1217 } 1218 1219 mutex_lock(&priv->mcp_lock); 1220 mcp251x_power_enable(priv->transceiver, 1); 1221 1222 priv->force_quit = 0; 1223 priv->tx_skb = NULL; 1224 priv->tx_len = 0; 1225 1226 if (!dev_fwnode(&spi->dev)) 1227 flags = IRQF_TRIGGER_FALLING; 1228 1229 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, 1230 flags | IRQF_ONESHOT, dev_name(&spi->dev), 1231 priv); 1232 if (ret) { 1233 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 1234 goto out_close; 1235 } 1236 1237 ret = mcp251x_hw_wake(spi); 1238 if (ret) 1239 goto out_free_irq; 1240 ret = mcp251x_setup(net, spi); 1241 if (ret) 1242 goto out_free_irq; 1243 ret = mcp251x_set_normal_mode(spi); 1244 if (ret) 1245 goto out_free_irq; 1246 1247 can_led_event(net, CAN_LED_EVENT_OPEN); 1248 1249 netif_wake_queue(net); 1250 mutex_unlock(&priv->mcp_lock); 1251 1252 return 0; 1253 1254out_free_irq: 1255 free_irq(spi->irq, priv); 1256 mcp251x_hw_sleep(spi); 1257out_close: 1258 mcp251x_power_enable(priv->transceiver, 0); 1259 close_candev(net); 1260 mutex_unlock(&priv->mcp_lock); 1261 return ret; 1262} 1263 1264static const struct net_device_ops mcp251x_netdev_ops = { 1265 .ndo_open = mcp251x_open, 1266 .ndo_stop = mcp251x_stop, 1267 .ndo_start_xmit = mcp251x_hard_start_xmit, 1268 .ndo_change_mtu = can_change_mtu, 1269}; 1270 1271static const struct of_device_id mcp251x_of_match[] = { 1272 { 1273 .compatible = "microchip,mcp2510", 1274 .data = (void *)CAN_MCP251X_MCP2510, 1275 }, 1276 { 1277 .compatible = "microchip,mcp2515", 1278 .data = (void *)CAN_MCP251X_MCP2515, 1279 }, 1280 { 1281 .compatible = "microchip,mcp25625", 1282 .data = (void *)CAN_MCP251X_MCP25625, 1283 }, 1284 { } 1285}; 1286MODULE_DEVICE_TABLE(of, mcp251x_of_match); 1287 1288static const struct spi_device_id mcp251x_id_table[] = { 1289 { 1290 .name = "mcp2510", 1291 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510, 1292 }, 1293 { 1294 .name = "mcp2515", 1295 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515, 1296 }, 1297 { 1298 .name = "mcp25625", 1299 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625, 1300 }, 1301 { } 1302}; 1303MODULE_DEVICE_TABLE(spi, mcp251x_id_table); 1304 1305static int mcp251x_can_probe(struct spi_device *spi) 1306{ 1307 const void *match = device_get_match_data(&spi->dev); 1308 struct net_device *net; 1309 struct mcp251x_priv *priv; 1310 struct clk *clk; 1311 u32 freq; 1312 int ret; 1313 1314 clk = devm_clk_get_optional(&spi->dev, NULL); 1315 if (IS_ERR(clk)) 1316 return PTR_ERR(clk); 1317 1318 freq = clk_get_rate(clk); 1319 if (freq == 0) 1320 device_property_read_u32(&spi->dev, "clock-frequency", &freq); 1321 1322 /* Sanity check */ 1323 if (freq < 1000000 || freq > 25000000) 1324 return -ERANGE; 1325 1326 /* Allocate can/net device */ 1327 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); 1328 if (!net) 1329 return -ENOMEM; 1330 1331 ret = clk_prepare_enable(clk); 1332 if (ret) 1333 goto out_free; 1334 1335 net->netdev_ops = &mcp251x_netdev_ops; 1336 net->flags |= IFF_ECHO; 1337 1338 priv = netdev_priv(net); 1339 priv->can.bittiming_const = &mcp251x_bittiming_const; 1340 priv->can.do_set_mode = mcp251x_do_set_mode; 1341 priv->can.clock.freq = freq / 2; 1342 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1343 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; 1344 if (match) 1345 priv->model = (enum mcp251x_model)match; 1346 else 1347 priv->model = spi_get_device_id(spi)->driver_data; 1348 priv->net = net; 1349 priv->clk = clk; 1350 1351 spi_set_drvdata(spi, priv); 1352 1353 /* Configure the SPI bus */ 1354 spi->bits_per_word = 8; 1355 if (mcp251x_is_2510(spi)) 1356 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000; 1357 else 1358 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000; 1359 ret = spi_setup(spi); 1360 if (ret) 1361 goto out_clk; 1362 1363 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 1364 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1365 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 1366 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 1367 ret = -EPROBE_DEFER; 1368 goto out_clk; 1369 } 1370 1371 ret = mcp251x_power_enable(priv->power, 1); 1372 if (ret) 1373 goto out_clk; 1374 1375 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 1376 0); 1377 if (!priv->wq) { 1378 ret = -ENOMEM; 1379 goto out_clk; 1380 } 1381 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); 1382 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); 1383 1384 priv->spi = spi; 1385 mutex_init(&priv->mcp_lock); 1386 1387 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1388 GFP_KERNEL); 1389 if (!priv->spi_tx_buf) { 1390 ret = -ENOMEM; 1391 goto error_probe; 1392 } 1393 1394 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1395 GFP_KERNEL); 1396 if (!priv->spi_rx_buf) { 1397 ret = -ENOMEM; 1398 goto error_probe; 1399 } 1400 1401 SET_NETDEV_DEV(net, &spi->dev); 1402 1403 /* Here is OK to not lock the MCP, no one knows about it yet */ 1404 ret = mcp251x_hw_probe(spi); 1405 if (ret) { 1406 if (ret == -ENODEV) 1407 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", 1408 priv->model); 1409 goto error_probe; 1410 } 1411 1412 mcp251x_hw_sleep(spi); 1413 1414 ret = register_candev(net); 1415 if (ret) 1416 goto error_probe; 1417 1418 devm_can_led_init(net); 1419 1420 ret = mcp251x_gpio_setup(priv); 1421 if (ret) 1422 goto out_unregister_candev; 1423 1424 netdev_info(net, "MCP%x successfully initialized.\n", priv->model); 1425 return 0; 1426 1427out_unregister_candev: 1428 unregister_candev(net); 1429 1430error_probe: 1431 destroy_workqueue(priv->wq); 1432 priv->wq = NULL; 1433 mcp251x_power_enable(priv->power, 0); 1434 1435out_clk: 1436 clk_disable_unprepare(clk); 1437 1438out_free: 1439 free_candev(net); 1440 1441 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 1442 return ret; 1443} 1444 1445static int mcp251x_can_remove(struct spi_device *spi) 1446{ 1447 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1448 struct net_device *net = priv->net; 1449 1450 unregister_candev(net); 1451 1452 mcp251x_power_enable(priv->power, 0); 1453 1454 destroy_workqueue(priv->wq); 1455 priv->wq = NULL; 1456 1457 clk_disable_unprepare(priv->clk); 1458 1459 free_candev(net); 1460 1461 return 0; 1462} 1463 1464static int __maybe_unused mcp251x_can_suspend(struct device *dev) 1465{ 1466 struct spi_device *spi = to_spi_device(dev); 1467 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1468 struct net_device *net = priv->net; 1469 1470 priv->force_quit = 1; 1471 disable_irq(spi->irq); 1472 /* Note: at this point neither IST nor workqueues are running. 1473 * open/stop cannot be called anyway so locking is not needed 1474 */ 1475 if (netif_running(net)) { 1476 netif_device_detach(net); 1477 1478 mcp251x_hw_sleep(spi); 1479 mcp251x_power_enable(priv->transceiver, 0); 1480 priv->after_suspend = AFTER_SUSPEND_UP; 1481 } else { 1482 priv->after_suspend = AFTER_SUSPEND_DOWN; 1483 } 1484 1485 mcp251x_power_enable(priv->power, 0); 1486 priv->after_suspend |= AFTER_SUSPEND_POWER; 1487 1488 return 0; 1489} 1490 1491static int __maybe_unused mcp251x_can_resume(struct device *dev) 1492{ 1493 struct spi_device *spi = to_spi_device(dev); 1494 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1495 1496 if (priv->after_suspend & AFTER_SUSPEND_POWER) 1497 mcp251x_power_enable(priv->power, 1); 1498 if (priv->after_suspend & AFTER_SUSPEND_UP) 1499 mcp251x_power_enable(priv->transceiver, 1); 1500 1501 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP)) 1502 queue_work(priv->wq, &priv->restart_work); 1503 else 1504 priv->after_suspend = 0; 1505 1506 priv->force_quit = 0; 1507 enable_irq(spi->irq); 1508 return 0; 1509} 1510 1511static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, 1512 mcp251x_can_resume); 1513 1514static struct spi_driver mcp251x_can_driver = { 1515 .driver = { 1516 .name = DEVICE_NAME, 1517 .of_match_table = mcp251x_of_match, 1518 .pm = &mcp251x_can_pm_ops, 1519 }, 1520 .id_table = mcp251x_id_table, 1521 .probe = mcp251x_can_probe, 1522 .remove = mcp251x_can_remove, 1523}; 1524module_spi_driver(mcp251x_can_driver); 1525 1526MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " 1527 "Christian Pellegrin <chripell@evolware.org>"); 1528MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver"); 1529MODULE_LICENSE("GPL v2"); 1530