1// SPDX-License-Identifier: GPL-2.0-only 2/* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 3 * 4 * Copyright(C) Timesys Corporation 2016 5 * 6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 9 * Copyright 2006 Arcom Control Systems Ltd. 10 * 11 * Based on CAN bus driver for the CCAN controller written by 12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 13 * - Simon Kallweit, intefo AG 14 * Copyright 2007 15 */ 16 17#include <linux/can/core.h> 18#include <linux/can/dev.h> 19#include <linux/can/led.h> 20#include <linux/clk.h> 21#include <linux/completion.h> 22#include <linux/delay.h> 23#include <linux/device.h> 24#include <linux/freezer.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/kernel.h> 28#include <linux/module.h> 29#include <linux/netdevice.h> 30#include <linux/of.h> 31#include <linux/of_device.h> 32#include <linux/platform_device.h> 33#include <linux/regulator/consumer.h> 34#include <linux/slab.h> 35#include <linux/spi/spi.h> 36#include <linux/uaccess.h> 37 38#define HI3110_MASTER_RESET 0x56 39#define HI3110_READ_CTRL0 0xD2 40#define HI3110_READ_CTRL1 0xD4 41#define HI3110_READ_STATF 0xE2 42#define HI3110_WRITE_CTRL0 0x14 43#define HI3110_WRITE_CTRL1 0x16 44#define HI3110_WRITE_INTE 0x1C 45#define HI3110_WRITE_BTR0 0x18 46#define HI3110_WRITE_BTR1 0x1A 47#define HI3110_READ_BTR0 0xD6 48#define HI3110_READ_BTR1 0xD8 49#define HI3110_READ_INTF 0xDE 50#define HI3110_READ_ERR 0xDC 51#define HI3110_READ_FIFO_WOTIME 0x48 52#define HI3110_WRITE_FIFO 0x12 53#define HI3110_READ_MESSTAT 0xDA 54#define HI3110_READ_REC 0xEA 55#define HI3110_READ_TEC 0xEC 56 57#define HI3110_CTRL0_MODE_MASK (7 << 5) 58#define HI3110_CTRL0_NORMAL_MODE (0 << 5) 59#define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 60#define HI3110_CTRL0_MONITOR_MODE (2 << 5) 61#define HI3110_CTRL0_SLEEP_MODE (3 << 5) 62#define HI3110_CTRL0_INIT_MODE (4 << 5) 63 64#define HI3110_CTRL1_TXEN BIT(7) 65 66#define HI3110_INT_RXTMP BIT(7) 67#define HI3110_INT_RXFIFO BIT(6) 68#define HI3110_INT_TXCPLT BIT(5) 69#define HI3110_INT_BUSERR BIT(4) 70#define HI3110_INT_MCHG BIT(3) 71#define HI3110_INT_WAKEUP BIT(2) 72#define HI3110_INT_F1MESS BIT(1) 73#define HI3110_INT_F0MESS BIT(0) 74 75#define HI3110_ERR_BUSOFF BIT(7) 76#define HI3110_ERR_TXERRP BIT(6) 77#define HI3110_ERR_RXERRP BIT(5) 78#define HI3110_ERR_BITERR BIT(4) 79#define HI3110_ERR_FRMERR BIT(3) 80#define HI3110_ERR_CRCERR BIT(2) 81#define HI3110_ERR_ACKERR BIT(1) 82#define HI3110_ERR_STUFERR BIT(0) 83#define HI3110_ERR_PROTOCOL_MASK (0x1F) 84#define HI3110_ERR_PASSIVE_MASK (0x60) 85 86#define HI3110_STAT_RXFMTY BIT(1) 87#define HI3110_STAT_BUSOFF BIT(2) 88#define HI3110_STAT_ERRP BIT(3) 89#define HI3110_STAT_ERRW BIT(4) 90#define HI3110_STAT_TXMTY BIT(7) 91 92#define HI3110_BTR0_SJW_SHIFT 6 93#define HI3110_BTR0_BRP_SHIFT 0 94 95#define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 96#define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 97#define HI3110_BTR1_TSEG2_SHIFT 4 98#define HI3110_BTR1_TSEG1_SHIFT 0 99 100#define HI3110_FIFO_WOTIME_TAG_OFF 0 101#define HI3110_FIFO_WOTIME_ID_OFF 1 102#define HI3110_FIFO_WOTIME_DLC_OFF 5 103#define HI3110_FIFO_WOTIME_DAT_OFF 6 104 105#define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 106#define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 107 108#define HI3110_FIFO_TAG_OFF 0 109#define HI3110_FIFO_ID_OFF 1 110#define HI3110_FIFO_STD_DLC_OFF 3 111#define HI3110_FIFO_STD_DATA_OFF 4 112#define HI3110_FIFO_EXT_DLC_OFF 5 113#define HI3110_FIFO_EXT_DATA_OFF 6 114 115#define HI3110_CAN_MAX_DATA_LEN 8 116#define HI3110_RX_BUF_LEN 15 117#define HI3110_TX_STD_BUF_LEN 12 118#define HI3110_TX_EXT_BUF_LEN 14 119#define HI3110_CAN_FRAME_MAX_BITS 128 120#define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 121 122#define HI3110_TX_ECHO_SKB_MAX 1 123 124#define HI3110_OST_DELAY_MS (10) 125 126#define DEVICE_NAME "hi3110" 127 128static const struct can_bittiming_const hi3110_bittiming_const = { 129 .name = DEVICE_NAME, 130 .tseg1_min = 2, 131 .tseg1_max = 16, 132 .tseg2_min = 2, 133 .tseg2_max = 8, 134 .sjw_max = 4, 135 .brp_min = 1, 136 .brp_max = 64, 137 .brp_inc = 1, 138}; 139 140enum hi3110_model { 141 CAN_HI3110_HI3110 = 0x3110, 142}; 143 144struct hi3110_priv { 145 struct can_priv can; 146 struct net_device *net; 147 struct spi_device *spi; 148 enum hi3110_model model; 149 150 struct mutex hi3110_lock; /* SPI device lock */ 151 152 u8 *spi_tx_buf; 153 u8 *spi_rx_buf; 154 155 struct sk_buff *tx_skb; 156 int tx_len; 157 158 struct workqueue_struct *wq; 159 struct work_struct tx_work; 160 struct work_struct restart_work; 161 162 int force_quit; 163 int after_suspend; 164#define HI3110_AFTER_SUSPEND_UP 1 165#define HI3110_AFTER_SUSPEND_DOWN 2 166#define HI3110_AFTER_SUSPEND_POWER 4 167#define HI3110_AFTER_SUSPEND_RESTART 8 168 int restart_tx; 169 struct regulator *power; 170 struct regulator *transceiver; 171 struct clk *clk; 172}; 173 174static void hi3110_clean(struct net_device *net) 175{ 176 struct hi3110_priv *priv = netdev_priv(net); 177 178 if (priv->tx_skb || priv->tx_len) 179 net->stats.tx_errors++; 180 dev_kfree_skb(priv->tx_skb); 181 if (priv->tx_len) 182 can_free_echo_skb(priv->net, 0); 183 priv->tx_skb = NULL; 184 priv->tx_len = 0; 185} 186 187/* Note about handling of error return of hi3110_spi_trans: accessing 188 * registers via SPI is not really different conceptually than using 189 * normal I/O assembler instructions, although it's much more 190 * complicated from a practical POV. So it's not advisable to always 191 * check the return value of this function. Imagine that every 192 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 193 * error();", it would be a great mess (well there are some situation 194 * when exception handling C++ like could be useful after all). So we 195 * just check that transfers are OK at the beginning of our 196 * conversation with the chip and to avoid doing really nasty things 197 * (like injecting bogus packets in the network stack). 198 */ 199static int hi3110_spi_trans(struct spi_device *spi, int len) 200{ 201 struct hi3110_priv *priv = spi_get_drvdata(spi); 202 struct spi_transfer t = { 203 .tx_buf = priv->spi_tx_buf, 204 .rx_buf = priv->spi_rx_buf, 205 .len = len, 206 .cs_change = 0, 207 }; 208 struct spi_message m; 209 int ret; 210 211 spi_message_init(&m); 212 spi_message_add_tail(&t, &m); 213 214 ret = spi_sync(spi, &m); 215 216 if (ret) 217 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 218 return ret; 219} 220 221static int hi3110_cmd(struct spi_device *spi, u8 command) 222{ 223 struct hi3110_priv *priv = spi_get_drvdata(spi); 224 225 priv->spi_tx_buf[0] = command; 226 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 227 228 return hi3110_spi_trans(spi, 1); 229} 230 231static u8 hi3110_read(struct spi_device *spi, u8 command) 232{ 233 struct hi3110_priv *priv = spi_get_drvdata(spi); 234 u8 val = 0; 235 236 priv->spi_tx_buf[0] = command; 237 hi3110_spi_trans(spi, 2); 238 val = priv->spi_rx_buf[1]; 239 240 return val; 241} 242 243static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 244{ 245 struct hi3110_priv *priv = spi_get_drvdata(spi); 246 247 priv->spi_tx_buf[0] = reg; 248 priv->spi_tx_buf[1] = val; 249 hi3110_spi_trans(spi, 2); 250} 251 252static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 253{ 254 struct hi3110_priv *priv = spi_get_drvdata(spi); 255 256 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 257 memcpy(priv->spi_tx_buf + 1, buf, len); 258 hi3110_spi_trans(spi, len + 1); 259} 260 261static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 262{ 263 u8 buf[HI3110_TX_EXT_BUF_LEN]; 264 265 buf[HI3110_FIFO_TAG_OFF] = 0; 266 267 if (frame->can_id & CAN_EFF_FLAG) { 268 /* Extended frame */ 269 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 270 buf[HI3110_FIFO_ID_OFF + 1] = 271 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 272 HI3110_EFF_FLAGS | 273 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 274 buf[HI3110_FIFO_ID_OFF + 2] = 275 (frame->can_id & CAN_EFF_MASK) >> 7; 276 buf[HI3110_FIFO_ID_OFF + 3] = 277 ((frame->can_id & CAN_EFF_MASK) << 1) | 278 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 279 280 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc; 281 282 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 283 frame->data, frame->can_dlc); 284 285 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 286 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 287 } else { 288 /* Standard frame */ 289 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 290 buf[HI3110_FIFO_ID_OFF + 1] = 291 ((frame->can_id & CAN_SFF_MASK) << 5) | 292 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 293 294 buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc; 295 296 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 297 frame->data, frame->can_dlc); 298 299 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 300 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 301 } 302} 303 304static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 305{ 306 struct hi3110_priv *priv = spi_get_drvdata(spi); 307 308 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 309 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 310 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 311} 312 313static void hi3110_hw_rx(struct spi_device *spi) 314{ 315 struct hi3110_priv *priv = spi_get_drvdata(spi); 316 struct sk_buff *skb; 317 struct can_frame *frame; 318 u8 buf[HI3110_RX_BUF_LEN - 1]; 319 320 skb = alloc_can_skb(priv->net, &frame); 321 if (!skb) { 322 priv->net->stats.rx_dropped++; 323 return; 324 } 325 326 hi3110_hw_rx_frame(spi, buf); 327 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 328 /* IDE is recessive (1), indicating extended 29-bit frame */ 329 frame->can_id = CAN_EFF_FLAG; 330 frame->can_id |= 331 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 332 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 333 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 334 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 335 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 336 } else { 337 /* IDE is dominant (0), frame indicating standard 11-bit */ 338 frame->can_id = 339 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 340 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 341 } 342 343 /* Data length */ 344 frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 345 346 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) 347 frame->can_id |= CAN_RTR_FLAG; 348 else 349 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 350 frame->can_dlc); 351 352 priv->net->stats.rx_packets++; 353 priv->net->stats.rx_bytes += frame->can_dlc; 354 355 can_led_event(priv->net, CAN_LED_EVENT_RX); 356 357 netif_rx_ni(skb); 358} 359 360static void hi3110_hw_sleep(struct spi_device *spi) 361{ 362 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 363} 364 365static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 366 struct net_device *net) 367{ 368 struct hi3110_priv *priv = netdev_priv(net); 369 struct spi_device *spi = priv->spi; 370 371 if (priv->tx_skb || priv->tx_len) { 372 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 373 return NETDEV_TX_BUSY; 374 } 375 376 if (can_dropped_invalid_skb(net, skb)) 377 return NETDEV_TX_OK; 378 379 netif_stop_queue(net); 380 priv->tx_skb = skb; 381 queue_work(priv->wq, &priv->tx_work); 382 383 return NETDEV_TX_OK; 384} 385 386static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 387{ 388 struct hi3110_priv *priv = netdev_priv(net); 389 390 switch (mode) { 391 case CAN_MODE_START: 392 hi3110_clean(net); 393 /* We have to delay work since SPI I/O may sleep */ 394 priv->can.state = CAN_STATE_ERROR_ACTIVE; 395 priv->restart_tx = 1; 396 if (priv->can.restart_ms == 0) 397 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 398 queue_work(priv->wq, &priv->restart_work); 399 break; 400 default: 401 return -EOPNOTSUPP; 402 } 403 404 return 0; 405} 406 407static int hi3110_get_berr_counter(const struct net_device *net, 408 struct can_berr_counter *bec) 409{ 410 struct hi3110_priv *priv = netdev_priv(net); 411 struct spi_device *spi = priv->spi; 412 413 mutex_lock(&priv->hi3110_lock); 414 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 415 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 416 mutex_unlock(&priv->hi3110_lock); 417 418 return 0; 419} 420 421static int hi3110_set_normal_mode(struct spi_device *spi) 422{ 423 struct hi3110_priv *priv = spi_get_drvdata(spi); 424 u8 reg = 0; 425 426 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 427 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 428 429 /* Enable TX */ 430 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 431 432 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 433 reg = HI3110_CTRL0_LOOPBACK_MODE; 434 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 435 reg = HI3110_CTRL0_MONITOR_MODE; 436 else 437 reg = HI3110_CTRL0_NORMAL_MODE; 438 439 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 440 441 /* Wait for the device to enter the mode */ 442 mdelay(HI3110_OST_DELAY_MS); 443 reg = hi3110_read(spi, HI3110_READ_CTRL0); 444 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 445 return -EBUSY; 446 447 priv->can.state = CAN_STATE_ERROR_ACTIVE; 448 return 0; 449} 450 451static int hi3110_do_set_bittiming(struct net_device *net) 452{ 453 struct hi3110_priv *priv = netdev_priv(net); 454 struct can_bittiming *bt = &priv->can.bittiming; 455 struct spi_device *spi = priv->spi; 456 457 hi3110_write(spi, HI3110_WRITE_BTR0, 458 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 459 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 460 461 hi3110_write(spi, HI3110_WRITE_BTR1, 462 (priv->can.ctrlmode & 463 CAN_CTRLMODE_3_SAMPLES ? 464 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 465 ((bt->phase_seg1 + bt->prop_seg - 1) 466 << HI3110_BTR1_TSEG1_SHIFT) | 467 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 468 469 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 470 hi3110_read(spi, HI3110_READ_BTR0), 471 hi3110_read(spi, HI3110_READ_BTR1)); 472 473 return 0; 474} 475 476static int hi3110_setup(struct net_device *net) 477{ 478 hi3110_do_set_bittiming(net); 479 return 0; 480} 481 482static int hi3110_hw_reset(struct spi_device *spi) 483{ 484 u8 reg; 485 int ret; 486 487 /* Wait for oscillator startup timer after power up */ 488 mdelay(HI3110_OST_DELAY_MS); 489 490 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 491 if (ret) 492 return ret; 493 494 /* Wait for oscillator startup timer after reset */ 495 mdelay(HI3110_OST_DELAY_MS); 496 497 reg = hi3110_read(spi, HI3110_READ_CTRL0); 498 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 499 return -ENODEV; 500 501 /* As per the datasheet it appears the error flags are 502 * not cleared on reset. Explicitly clear them by performing a read 503 */ 504 hi3110_read(spi, HI3110_READ_ERR); 505 506 return 0; 507} 508 509static int hi3110_hw_probe(struct spi_device *spi) 510{ 511 u8 statf; 512 513 hi3110_hw_reset(spi); 514 515 /* Confirm correct operation by checking against reset values 516 * in datasheet 517 */ 518 statf = hi3110_read(spi, HI3110_READ_STATF); 519 520 dev_dbg(&spi->dev, "statf: %02X\n", statf); 521 522 if (statf != 0x82) 523 return -ENODEV; 524 525 return 0; 526} 527 528static int hi3110_power_enable(struct regulator *reg, int enable) 529{ 530 if (IS_ERR_OR_NULL(reg)) 531 return 0; 532 533 if (enable) 534 return regulator_enable(reg); 535 else 536 return regulator_disable(reg); 537} 538 539static int hi3110_stop(struct net_device *net) 540{ 541 struct hi3110_priv *priv = netdev_priv(net); 542 struct spi_device *spi = priv->spi; 543 544 close_candev(net); 545 546 priv->force_quit = 1; 547 free_irq(spi->irq, priv); 548 destroy_workqueue(priv->wq); 549 priv->wq = NULL; 550 551 mutex_lock(&priv->hi3110_lock); 552 553 /* Disable transmit, interrupts and clear flags */ 554 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 555 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 556 hi3110_read(spi, HI3110_READ_INTF); 557 558 hi3110_clean(net); 559 560 hi3110_hw_sleep(spi); 561 562 hi3110_power_enable(priv->transceiver, 0); 563 564 priv->can.state = CAN_STATE_STOPPED; 565 566 mutex_unlock(&priv->hi3110_lock); 567 568 can_led_event(net, CAN_LED_EVENT_STOP); 569 570 return 0; 571} 572 573static void hi3110_tx_work_handler(struct work_struct *ws) 574{ 575 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 576 tx_work); 577 struct spi_device *spi = priv->spi; 578 struct net_device *net = priv->net; 579 struct can_frame *frame; 580 581 mutex_lock(&priv->hi3110_lock); 582 if (priv->tx_skb) { 583 if (priv->can.state == CAN_STATE_BUS_OFF) { 584 hi3110_clean(net); 585 } else { 586 frame = (struct can_frame *)priv->tx_skb->data; 587 hi3110_hw_tx(spi, frame); 588 priv->tx_len = 1 + frame->can_dlc; 589 can_put_echo_skb(priv->tx_skb, net, 0); 590 priv->tx_skb = NULL; 591 } 592 } 593 mutex_unlock(&priv->hi3110_lock); 594} 595 596static void hi3110_restart_work_handler(struct work_struct *ws) 597{ 598 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 599 restart_work); 600 struct spi_device *spi = priv->spi; 601 struct net_device *net = priv->net; 602 603 mutex_lock(&priv->hi3110_lock); 604 if (priv->after_suspend) { 605 hi3110_hw_reset(spi); 606 hi3110_setup(net); 607 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 608 hi3110_set_normal_mode(spi); 609 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 610 netif_device_attach(net); 611 hi3110_clean(net); 612 hi3110_set_normal_mode(spi); 613 netif_wake_queue(net); 614 } else { 615 hi3110_hw_sleep(spi); 616 } 617 priv->after_suspend = 0; 618 priv->force_quit = 0; 619 } 620 621 if (priv->restart_tx) { 622 priv->restart_tx = 0; 623 hi3110_hw_reset(spi); 624 hi3110_setup(net); 625 hi3110_clean(net); 626 hi3110_set_normal_mode(spi); 627 netif_wake_queue(net); 628 } 629 mutex_unlock(&priv->hi3110_lock); 630} 631 632static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 633{ 634 struct hi3110_priv *priv = dev_id; 635 struct spi_device *spi = priv->spi; 636 struct net_device *net = priv->net; 637 638 mutex_lock(&priv->hi3110_lock); 639 640 while (!priv->force_quit) { 641 enum can_state new_state; 642 u8 intf, eflag, statf; 643 644 while (!(HI3110_STAT_RXFMTY & 645 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 646 hi3110_hw_rx(spi); 647 } 648 649 intf = hi3110_read(spi, HI3110_READ_INTF); 650 eflag = hi3110_read(spi, HI3110_READ_ERR); 651 /* Update can state */ 652 if (eflag & HI3110_ERR_BUSOFF) 653 new_state = CAN_STATE_BUS_OFF; 654 else if (eflag & HI3110_ERR_PASSIVE_MASK) 655 new_state = CAN_STATE_ERROR_PASSIVE; 656 else if (statf & HI3110_STAT_ERRW) 657 new_state = CAN_STATE_ERROR_WARNING; 658 else 659 new_state = CAN_STATE_ERROR_ACTIVE; 660 661 if (new_state != priv->can.state) { 662 struct can_frame *cf; 663 struct sk_buff *skb; 664 enum can_state rx_state, tx_state; 665 u8 rxerr, txerr; 666 667 skb = alloc_can_err_skb(net, &cf); 668 if (!skb) 669 break; 670 671 txerr = hi3110_read(spi, HI3110_READ_TEC); 672 rxerr = hi3110_read(spi, HI3110_READ_REC); 673 tx_state = txerr >= rxerr ? new_state : 0; 674 rx_state = txerr <= rxerr ? new_state : 0; 675 can_change_state(net, cf, tx_state, rx_state); 676 netif_rx_ni(skb); 677 678 if (new_state == CAN_STATE_BUS_OFF) { 679 can_bus_off(net); 680 if (priv->can.restart_ms == 0) { 681 priv->force_quit = 1; 682 hi3110_hw_sleep(spi); 683 break; 684 } 685 } else { 686 cf->data[6] = txerr; 687 cf->data[7] = rxerr; 688 } 689 } 690 691 /* Update bus errors */ 692 if ((intf & HI3110_INT_BUSERR) && 693 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 694 struct can_frame *cf; 695 struct sk_buff *skb; 696 697 /* Check for protocol errors */ 698 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 699 skb = alloc_can_err_skb(net, &cf); 700 if (!skb) 701 break; 702 703 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 704 priv->can.can_stats.bus_error++; 705 priv->net->stats.rx_errors++; 706 if (eflag & HI3110_ERR_BITERR) 707 cf->data[2] |= CAN_ERR_PROT_BIT; 708 else if (eflag & HI3110_ERR_FRMERR) 709 cf->data[2] |= CAN_ERR_PROT_FORM; 710 else if (eflag & HI3110_ERR_STUFERR) 711 cf->data[2] |= CAN_ERR_PROT_STUFF; 712 else if (eflag & HI3110_ERR_CRCERR) 713 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 714 else if (eflag & HI3110_ERR_ACKERR) 715 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 716 717 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 718 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 719 netdev_dbg(priv->net, "Bus Error\n"); 720 netif_rx_ni(skb); 721 } 722 } 723 724 if (priv->tx_len && statf & HI3110_STAT_TXMTY) { 725 net->stats.tx_packets++; 726 net->stats.tx_bytes += priv->tx_len - 1; 727 can_led_event(net, CAN_LED_EVENT_TX); 728 if (priv->tx_len) { 729 can_get_echo_skb(net, 0); 730 priv->tx_len = 0; 731 } 732 netif_wake_queue(net); 733 } 734 735 if (intf == 0) 736 break; 737 } 738 mutex_unlock(&priv->hi3110_lock); 739 return IRQ_HANDLED; 740} 741 742static int hi3110_open(struct net_device *net) 743{ 744 struct hi3110_priv *priv = netdev_priv(net); 745 struct spi_device *spi = priv->spi; 746 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; 747 int ret; 748 749 ret = open_candev(net); 750 if (ret) 751 return ret; 752 753 mutex_lock(&priv->hi3110_lock); 754 hi3110_power_enable(priv->transceiver, 1); 755 756 priv->force_quit = 0; 757 priv->tx_skb = NULL; 758 priv->tx_len = 0; 759 760 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 761 flags, DEVICE_NAME, priv); 762 if (ret) { 763 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 764 goto out_close; 765 } 766 767 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 768 0); 769 if (!priv->wq) { 770 ret = -ENOMEM; 771 goto out_free_irq; 772 } 773 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 774 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 775 776 ret = hi3110_hw_reset(spi); 777 if (ret) 778 goto out_free_wq; 779 780 ret = hi3110_setup(net); 781 if (ret) 782 goto out_free_wq; 783 784 ret = hi3110_set_normal_mode(spi); 785 if (ret) 786 goto out_free_wq; 787 788 can_led_event(net, CAN_LED_EVENT_OPEN); 789 netif_wake_queue(net); 790 mutex_unlock(&priv->hi3110_lock); 791 792 return 0; 793 794 out_free_wq: 795 destroy_workqueue(priv->wq); 796 out_free_irq: 797 free_irq(spi->irq, priv); 798 hi3110_hw_sleep(spi); 799 out_close: 800 hi3110_power_enable(priv->transceiver, 0); 801 close_candev(net); 802 mutex_unlock(&priv->hi3110_lock); 803 return ret; 804} 805 806static const struct net_device_ops hi3110_netdev_ops = { 807 .ndo_open = hi3110_open, 808 .ndo_stop = hi3110_stop, 809 .ndo_start_xmit = hi3110_hard_start_xmit, 810}; 811 812static const struct of_device_id hi3110_of_match[] = { 813 { 814 .compatible = "holt,hi3110", 815 .data = (void *)CAN_HI3110_HI3110, 816 }, 817 { } 818}; 819MODULE_DEVICE_TABLE(of, hi3110_of_match); 820 821static const struct spi_device_id hi3110_id_table[] = { 822 { 823 .name = "hi3110", 824 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 825 }, 826 { } 827}; 828MODULE_DEVICE_TABLE(spi, hi3110_id_table); 829 830static int hi3110_can_probe(struct spi_device *spi) 831{ 832 const struct of_device_id *of_id = of_match_device(hi3110_of_match, 833 &spi->dev); 834 struct net_device *net; 835 struct hi3110_priv *priv; 836 struct clk *clk; 837 int freq, ret; 838 839 clk = devm_clk_get(&spi->dev, NULL); 840 if (IS_ERR(clk)) { 841 dev_err(&spi->dev, "no CAN clock source defined\n"); 842 return PTR_ERR(clk); 843 } 844 freq = clk_get_rate(clk); 845 846 /* Sanity check */ 847 if (freq > 40000000) 848 return -ERANGE; 849 850 /* Allocate can/net device */ 851 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 852 if (!net) 853 return -ENOMEM; 854 855 if (!IS_ERR(clk)) { 856 ret = clk_prepare_enable(clk); 857 if (ret) 858 goto out_free; 859 } 860 861 net->netdev_ops = &hi3110_netdev_ops; 862 net->flags |= IFF_ECHO; 863 864 priv = netdev_priv(net); 865 priv->can.bittiming_const = &hi3110_bittiming_const; 866 priv->can.do_set_mode = hi3110_do_set_mode; 867 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 868 priv->can.clock.freq = freq / 2; 869 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 870 CAN_CTRLMODE_LOOPBACK | 871 CAN_CTRLMODE_LISTENONLY | 872 CAN_CTRLMODE_BERR_REPORTING; 873 874 if (of_id) 875 priv->model = (enum hi3110_model)of_id->data; 876 else 877 priv->model = spi_get_device_id(spi)->driver_data; 878 priv->net = net; 879 priv->clk = clk; 880 881 spi_set_drvdata(spi, priv); 882 883 /* Configure the SPI bus */ 884 spi->bits_per_word = 8; 885 ret = spi_setup(spi); 886 if (ret) 887 goto out_clk; 888 889 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 890 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 891 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 892 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 893 ret = -EPROBE_DEFER; 894 goto out_clk; 895 } 896 897 ret = hi3110_power_enable(priv->power, 1); 898 if (ret) 899 goto out_clk; 900 901 priv->spi = spi; 902 mutex_init(&priv->hi3110_lock); 903 904 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 905 GFP_KERNEL); 906 if (!priv->spi_tx_buf) { 907 ret = -ENOMEM; 908 goto error_probe; 909 } 910 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 911 GFP_KERNEL); 912 913 if (!priv->spi_rx_buf) { 914 ret = -ENOMEM; 915 goto error_probe; 916 } 917 918 SET_NETDEV_DEV(net, &spi->dev); 919 920 ret = hi3110_hw_probe(spi); 921 if (ret) { 922 if (ret == -ENODEV) 923 dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n", 924 priv->model); 925 goto error_probe; 926 } 927 hi3110_hw_sleep(spi); 928 929 ret = register_candev(net); 930 if (ret) 931 goto error_probe; 932 933 devm_can_led_init(net); 934 netdev_info(net, "%x successfully initialized.\n", priv->model); 935 936 return 0; 937 938 error_probe: 939 hi3110_power_enable(priv->power, 0); 940 941 out_clk: 942 if (!IS_ERR(clk)) 943 clk_disable_unprepare(clk); 944 945 out_free: 946 free_candev(net); 947 948 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 949 return ret; 950} 951 952static int hi3110_can_remove(struct spi_device *spi) 953{ 954 struct hi3110_priv *priv = spi_get_drvdata(spi); 955 struct net_device *net = priv->net; 956 957 unregister_candev(net); 958 959 hi3110_power_enable(priv->power, 0); 960 961 if (!IS_ERR(priv->clk)) 962 clk_disable_unprepare(priv->clk); 963 964 free_candev(net); 965 966 return 0; 967} 968 969static int __maybe_unused hi3110_can_suspend(struct device *dev) 970{ 971 struct spi_device *spi = to_spi_device(dev); 972 struct hi3110_priv *priv = spi_get_drvdata(spi); 973 struct net_device *net = priv->net; 974 975 priv->force_quit = 1; 976 disable_irq(spi->irq); 977 978 /* Note: at this point neither IST nor workqueues are running. 979 * open/stop cannot be called anyway so locking is not needed 980 */ 981 if (netif_running(net)) { 982 netif_device_detach(net); 983 984 hi3110_hw_sleep(spi); 985 hi3110_power_enable(priv->transceiver, 0); 986 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 987 } else { 988 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 989 } 990 991 if (!IS_ERR_OR_NULL(priv->power)) { 992 regulator_disable(priv->power); 993 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 994 } 995 996 return 0; 997} 998 999static int __maybe_unused hi3110_can_resume(struct device *dev) 1000{ 1001 struct spi_device *spi = to_spi_device(dev); 1002 struct hi3110_priv *priv = spi_get_drvdata(spi); 1003 1004 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 1005 hi3110_power_enable(priv->power, 1); 1006 1007 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 1008 hi3110_power_enable(priv->transceiver, 1); 1009 queue_work(priv->wq, &priv->restart_work); 1010 } else { 1011 priv->after_suspend = 0; 1012 } 1013 1014 priv->force_quit = 0; 1015 enable_irq(spi->irq); 1016 return 0; 1017} 1018 1019static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1020 1021static struct spi_driver hi3110_can_driver = { 1022 .driver = { 1023 .name = DEVICE_NAME, 1024 .of_match_table = hi3110_of_match, 1025 .pm = &hi3110_can_pm_ops, 1026 }, 1027 .id_table = hi3110_id_table, 1028 .probe = hi3110_can_probe, 1029 .remove = hi3110_can_remove, 1030}; 1031 1032module_spi_driver(hi3110_can_driver); 1033 1034MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1035MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1036MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1037MODULE_LICENSE("GPL v2"); 1038