1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38#include <linux/pinctrl/consumer.h> 39 40#include <linux/can.h> 41#include <linux/can/dev.h> 42#include <linux/can/error.h> 43#include <linux/can/led.h> 44 45#include "c_can.h" 46 47/* Number of interface registers */ 48#define IF_ENUM_REG_LEN 11 49#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 50 51/* control extension register D_CAN specific */ 52#define CONTROL_EX_PDR BIT(8) 53 54/* control register */ 55#define CONTROL_SWR BIT(15) 56#define CONTROL_TEST BIT(7) 57#define CONTROL_CCE BIT(6) 58#define CONTROL_DISABLE_AR BIT(5) 59#define CONTROL_ENABLE_AR (0 << 5) 60#define CONTROL_EIE BIT(3) 61#define CONTROL_SIE BIT(2) 62#define CONTROL_IE BIT(1) 63#define CONTROL_INIT BIT(0) 64 65#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 66 67/* test register */ 68#define TEST_RX BIT(7) 69#define TEST_TX1 BIT(6) 70#define TEST_TX2 BIT(5) 71#define TEST_LBACK BIT(4) 72#define TEST_SILENT BIT(3) 73#define TEST_BASIC BIT(2) 74 75/* status register */ 76#define STATUS_PDA BIT(10) 77#define STATUS_BOFF BIT(7) 78#define STATUS_EWARN BIT(6) 79#define STATUS_EPASS BIT(5) 80#define STATUS_RXOK BIT(4) 81#define STATUS_TXOK BIT(3) 82 83/* error counter register */ 84#define ERR_CNT_TEC_MASK 0xff 85#define ERR_CNT_TEC_SHIFT 0 86#define ERR_CNT_REC_SHIFT 8 87#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 88#define ERR_CNT_RP_SHIFT 15 89#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 90 91/* bit-timing register */ 92#define BTR_BRP_MASK 0x3f 93#define BTR_BRP_SHIFT 0 94#define BTR_SJW_SHIFT 6 95#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 96#define BTR_TSEG1_SHIFT 8 97#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 98#define BTR_TSEG2_SHIFT 12 99#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 100 101/* interrupt register */ 102#define INT_STS_PENDING 0x8000 103 104/* brp extension register */ 105#define BRP_EXT_BRPE_MASK 0x0f 106#define BRP_EXT_BRPE_SHIFT 0 107 108/* IFx command request */ 109#define IF_COMR_BUSY BIT(15) 110 111/* IFx command mask */ 112#define IF_COMM_WR BIT(7) 113#define IF_COMM_MASK BIT(6) 114#define IF_COMM_ARB BIT(5) 115#define IF_COMM_CONTROL BIT(4) 116#define IF_COMM_CLR_INT_PND BIT(3) 117#define IF_COMM_TXRQST BIT(2) 118#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 119#define IF_COMM_DATAA BIT(1) 120#define IF_COMM_DATAB BIT(0) 121 122/* TX buffer setup */ 123#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 124 IF_COMM_TXRQST | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127/* For the low buffers we clear the interrupt bit, but keep newdat */ 128#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 130 IF_COMM_DATAA | IF_COMM_DATAB) 131 132/* For the high buffers we clear the interrupt bit and newdat */ 133#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 134 135 136/* Receive setup of message objects */ 137#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 138 139/* Invalidation of message objects */ 140#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 141 142/* IFx arbitration */ 143#define IF_ARB_MSGVAL BIT(31) 144#define IF_ARB_MSGXTD BIT(30) 145#define IF_ARB_TRANSMIT BIT(29) 146 147/* IFx message control */ 148#define IF_MCONT_NEWDAT BIT(15) 149#define IF_MCONT_MSGLST BIT(14) 150#define IF_MCONT_INTPND BIT(13) 151#define IF_MCONT_UMASK BIT(12) 152#define IF_MCONT_TXIE BIT(11) 153#define IF_MCONT_RXIE BIT(10) 154#define IF_MCONT_RMTEN BIT(9) 155#define IF_MCONT_TXRQST BIT(8) 156#define IF_MCONT_EOB BIT(7) 157#define IF_MCONT_DLC_MASK 0xf 158 159#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 160#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 161 162#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 163 164/* 165 * Use IF1 for RX and IF2 for TX 166 */ 167#define IF_RX 0 168#define IF_TX 1 169 170/* minimum timeout for checking BUSY status */ 171#define MIN_TIMEOUT_VALUE 6 172 173/* Wait for ~1 sec for INIT bit */ 174#define INIT_WAIT_MS 1000 175 176/* napi related */ 177#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 178 179/* c_can lec values */ 180enum c_can_lec_type { 181 LEC_NO_ERROR = 0, 182 LEC_STUFF_ERROR, 183 LEC_FORM_ERROR, 184 LEC_ACK_ERROR, 185 LEC_BIT1_ERROR, 186 LEC_BIT0_ERROR, 187 LEC_CRC_ERROR, 188 LEC_UNUSED, 189 LEC_MASK = LEC_UNUSED, 190}; 191 192/* 193 * c_can error types: 194 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 195 */ 196enum c_can_bus_error_types { 197 C_CAN_NO_ERROR = 0, 198 C_CAN_BUS_OFF, 199 C_CAN_ERROR_WARNING, 200 C_CAN_ERROR_PASSIVE, 201}; 202 203static const struct can_bittiming_const c_can_bittiming_const = { 204 .name = KBUILD_MODNAME, 205 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 206 .tseg1_max = 16, 207 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 208 .tseg2_max = 8, 209 .sjw_max = 4, 210 .brp_min = 1, 211 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 212 .brp_inc = 1, 213}; 214 215static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 216{ 217 if (priv->device) 218 pm_runtime_get_sync(priv->device); 219} 220 221static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 222{ 223 if (priv->device) 224 pm_runtime_put_sync(priv->device); 225} 226 227static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 228{ 229 if (priv->raminit) 230 priv->raminit(priv, enable); 231} 232 233static void c_can_irq_control(struct c_can_priv *priv, bool enable) 234{ 235 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 236 237 if (enable) 238 ctrl |= CONTROL_IRQMSK; 239 240 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 241} 242 243static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 244{ 245 struct c_can_priv *priv = netdev_priv(dev); 246 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 247 248 priv->write_reg32(priv, reg, (cmd << 16) | obj); 249 250 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 251 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 252 return; 253 udelay(1); 254 } 255 netdev_err(dev, "Updating object timed out\n"); 256 257} 258 259static inline void c_can_object_get(struct net_device *dev, int iface, 260 u32 obj, u32 cmd) 261{ 262 c_can_obj_update(dev, iface, cmd, obj); 263} 264 265static inline void c_can_object_put(struct net_device *dev, int iface, 266 u32 obj, u32 cmd) 267{ 268 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 269} 270 271/* 272 * Note: According to documentation clearing TXIE while MSGVAL is set 273 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 274 * load significantly. 275 */ 276static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 277{ 278 struct c_can_priv *priv = netdev_priv(dev); 279 280 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 281 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 282} 283 284static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 285{ 286 struct c_can_priv *priv = netdev_priv(dev); 287 288 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 289 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 290 c_can_inval_tx_object(dev, iface, obj); 291} 292 293static void c_can_setup_tx_object(struct net_device *dev, int iface, 294 struct can_frame *frame, int idx) 295{ 296 struct c_can_priv *priv = netdev_priv(dev); 297 u16 ctrl = IF_MCONT_TX | frame->can_dlc; 298 bool rtr = frame->can_id & CAN_RTR_FLAG; 299 u32 arb = IF_ARB_MSGVAL; 300 int i; 301 302 if (frame->can_id & CAN_EFF_FLAG) { 303 arb |= frame->can_id & CAN_EFF_MASK; 304 arb |= IF_ARB_MSGXTD; 305 } else { 306 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 307 } 308 309 if (!rtr) 310 arb |= IF_ARB_TRANSMIT; 311 312 /* 313 * If we change the DIR bit, we need to invalidate the buffer 314 * first, i.e. clear the MSGVAL flag in the arbiter. 315 */ 316 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 317 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 318 319 c_can_inval_msg_object(dev, iface, obj); 320 change_bit(idx, &priv->tx_dir); 321 } 322 323 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 324 325 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 326 327 if (priv->type == BOSCH_D_CAN) { 328 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); 329 330 for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) { 331 data = (u32)frame->data[i]; 332 data |= (u32)frame->data[i + 1] << 8; 333 data |= (u32)frame->data[i + 2] << 16; 334 data |= (u32)frame->data[i + 3] << 24; 335 priv->write_reg32(priv, dreg, data); 336 } 337 } else { 338 for (i = 0; i < frame->can_dlc; i += 2) { 339 priv->write_reg(priv, 340 C_CAN_IFACE(DATA1_REG, iface) + i / 2, 341 frame->data[i] | 342 (frame->data[i + 1] << 8)); 343 } 344 } 345} 346 347static int c_can_handle_lost_msg_obj(struct net_device *dev, 348 int iface, int objno, u32 ctrl) 349{ 350 struct net_device_stats *stats = &dev->stats; 351 struct c_can_priv *priv = netdev_priv(dev); 352 struct can_frame *frame; 353 struct sk_buff *skb; 354 355 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 356 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 357 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 358 359 stats->rx_errors++; 360 stats->rx_over_errors++; 361 362 /* create an error msg */ 363 skb = alloc_can_err_skb(dev, &frame); 364 if (unlikely(!skb)) 365 return 0; 366 367 frame->can_id |= CAN_ERR_CRTL; 368 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 369 370 netif_receive_skb(skb); 371 return 1; 372} 373 374static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 375{ 376 struct net_device_stats *stats = &dev->stats; 377 struct c_can_priv *priv = netdev_priv(dev); 378 struct can_frame *frame; 379 struct sk_buff *skb; 380 u32 arb, data; 381 382 skb = alloc_can_skb(dev, &frame); 383 if (!skb) { 384 stats->rx_dropped++; 385 return -ENOMEM; 386 } 387 388 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 389 390 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 391 392 if (arb & IF_ARB_MSGXTD) 393 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 394 else 395 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 396 397 if (arb & IF_ARB_TRANSMIT) { 398 frame->can_id |= CAN_RTR_FLAG; 399 } else { 400 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 401 402 if (priv->type == BOSCH_D_CAN) { 403 for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) { 404 data = priv->read_reg32(priv, dreg); 405 frame->data[i] = data; 406 frame->data[i + 1] = data >> 8; 407 frame->data[i + 2] = data >> 16; 408 frame->data[i + 3] = data >> 24; 409 } 410 } else { 411 for (i = 0; i < frame->can_dlc; i += 2, dreg++) { 412 data = priv->read_reg(priv, dreg); 413 frame->data[i] = data; 414 frame->data[i + 1] = data >> 8; 415 } 416 } 417 } 418 419 stats->rx_packets++; 420 stats->rx_bytes += frame->can_dlc; 421 422 netif_receive_skb(skb); 423 return 0; 424} 425 426static void c_can_setup_receive_object(struct net_device *dev, int iface, 427 u32 obj, u32 mask, u32 id, u32 mcont) 428{ 429 struct c_can_priv *priv = netdev_priv(dev); 430 431 mask |= BIT(29); 432 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 433 434 id |= IF_ARB_MSGVAL; 435 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 436 437 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 438 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 439} 440 441static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 442 struct net_device *dev) 443{ 444 struct can_frame *frame = (struct can_frame *)skb->data; 445 struct c_can_priv *priv = netdev_priv(dev); 446 u32 idx, obj; 447 448 if (can_dropped_invalid_skb(dev, skb)) 449 return NETDEV_TX_OK; 450 /* 451 * This is not a FIFO. C/D_CAN sends out the buffers 452 * prioritized. The lowest buffer number wins. 453 */ 454 idx = fls(atomic_read(&priv->tx_active)); 455 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 456 457 /* If this is the last buffer, stop the xmit queue */ 458 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1) 459 netif_stop_queue(dev); 460 /* 461 * Store the message in the interface so we can call 462 * can_put_echo_skb(). We must do this before we enable 463 * transmit as we might race against do_tx(). 464 */ 465 c_can_setup_tx_object(dev, IF_TX, frame, idx); 466 priv->dlc[idx] = frame->can_dlc; 467 can_put_echo_skb(skb, dev, idx); 468 469 /* Update the active bits */ 470 atomic_add((1 << idx), &priv->tx_active); 471 /* Start transmission */ 472 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); 473 474 return NETDEV_TX_OK; 475} 476 477static int c_can_wait_for_ctrl_init(struct net_device *dev, 478 struct c_can_priv *priv, u32 init) 479{ 480 int retry = 0; 481 482 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 483 udelay(10); 484 if (retry++ > 1000) { 485 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 486 return -EIO; 487 } 488 } 489 return 0; 490} 491 492static int c_can_set_bittiming(struct net_device *dev) 493{ 494 unsigned int reg_btr, reg_brpe, ctrl_save; 495 u8 brp, brpe, sjw, tseg1, tseg2; 496 u32 ten_bit_brp; 497 struct c_can_priv *priv = netdev_priv(dev); 498 const struct can_bittiming *bt = &priv->can.bittiming; 499 int res; 500 501 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 502 ten_bit_brp = bt->brp - 1; 503 brp = ten_bit_brp & BTR_BRP_MASK; 504 brpe = ten_bit_brp >> 6; 505 506 sjw = bt->sjw - 1; 507 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 508 tseg2 = bt->phase_seg2 - 1; 509 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 510 (tseg2 << BTR_TSEG2_SHIFT); 511 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 512 513 netdev_info(dev, 514 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 515 516 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 517 ctrl_save &= ~CONTROL_INIT; 518 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 519 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 520 if (res) 521 return res; 522 523 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 524 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 525 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 526 527 return c_can_wait_for_ctrl_init(dev, priv, 0); 528} 529 530/* 531 * Configure C_CAN message objects for Tx and Rx purposes: 532 * C_CAN provides a total of 32 message objects that can be configured 533 * either for Tx or Rx purposes. Here the first 16 message objects are used as 534 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 535 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 536 * See user guide document for further details on configuring message 537 * objects. 538 */ 539static void c_can_configure_msg_objects(struct net_device *dev) 540{ 541 int i; 542 543 /* first invalidate all message objects */ 544 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 545 c_can_inval_msg_object(dev, IF_RX, i); 546 547 /* setup receive message objects */ 548 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 549 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 550 551 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 552 IF_MCONT_RCV_EOB); 553} 554 555static int c_can_software_reset(struct net_device *dev) 556{ 557 struct c_can_priv *priv = netdev_priv(dev); 558 int retry = 0; 559 560 if (priv->type != BOSCH_D_CAN) 561 return 0; 562 563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); 564 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { 565 msleep(20); 566 if (retry++ > 100) { 567 netdev_err(dev, "CCTRL: software reset failed\n"); 568 return -EIO; 569 } 570 } 571 572 return 0; 573} 574 575/* 576 * Configure C_CAN chip: 577 * - enable/disable auto-retransmission 578 * - set operating mode 579 * - configure message objects 580 */ 581static int c_can_chip_config(struct net_device *dev) 582{ 583 struct c_can_priv *priv = netdev_priv(dev); 584 int err; 585 586 err = c_can_software_reset(dev); 587 if (err) 588 return err; 589 590 /* enable automatic retransmission */ 591 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 592 593 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 594 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 595 /* loopback + silent mode : useful for hot self-test */ 596 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 597 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 598 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 599 /* loopback mode : useful for self-test function */ 600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 601 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 602 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 603 /* silent mode : bus-monitoring mode */ 604 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 605 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 606 } 607 608 /* configure message objects */ 609 c_can_configure_msg_objects(dev); 610 611 /* set a `lec` value so that we can check for updates later */ 612 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 613 614 /* Clear all internal status */ 615 atomic_set(&priv->tx_active, 0); 616 priv->rxmasked = 0; 617 priv->tx_dir = 0; 618 619 /* set bittiming params */ 620 return c_can_set_bittiming(dev); 621} 622 623static int c_can_start(struct net_device *dev) 624{ 625 struct c_can_priv *priv = netdev_priv(dev); 626 int err; 627 struct pinctrl *p; 628 629 /* basic c_can configuration */ 630 err = c_can_chip_config(dev); 631 if (err) 632 return err; 633 634 /* Setup the command for new messages */ 635 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 636 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 637 638 priv->can.state = CAN_STATE_ERROR_ACTIVE; 639 640 /* Attempt to use "active" if available else use "default" */ 641 p = pinctrl_get_select(priv->device, "active"); 642 if (!IS_ERR(p)) 643 pinctrl_put(p); 644 else 645 pinctrl_pm_select_default_state(priv->device); 646 647 return 0; 648} 649 650static void c_can_stop(struct net_device *dev) 651{ 652 struct c_can_priv *priv = netdev_priv(dev); 653 654 c_can_irq_control(priv, false); 655 656 /* put ctrl to init on stop to end ongoing transmission */ 657 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); 658 659 /* deactivate pins */ 660 pinctrl_pm_select_sleep_state(dev->dev.parent); 661 priv->can.state = CAN_STATE_STOPPED; 662} 663 664static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 665{ 666 struct c_can_priv *priv = netdev_priv(dev); 667 int err; 668 669 switch (mode) { 670 case CAN_MODE_START: 671 err = c_can_start(dev); 672 if (err) 673 return err; 674 netif_wake_queue(dev); 675 c_can_irq_control(priv, true); 676 break; 677 default: 678 return -EOPNOTSUPP; 679 } 680 681 return 0; 682} 683 684static int __c_can_get_berr_counter(const struct net_device *dev, 685 struct can_berr_counter *bec) 686{ 687 unsigned int reg_err_counter; 688 struct c_can_priv *priv = netdev_priv(dev); 689 690 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 691 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 692 ERR_CNT_REC_SHIFT; 693 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 694 695 return 0; 696} 697 698static int c_can_get_berr_counter(const struct net_device *dev, 699 struct can_berr_counter *bec) 700{ 701 struct c_can_priv *priv = netdev_priv(dev); 702 int err; 703 704 c_can_pm_runtime_get_sync(priv); 705 err = __c_can_get_berr_counter(dev, bec); 706 c_can_pm_runtime_put_sync(priv); 707 708 return err; 709} 710 711static void c_can_do_tx(struct net_device *dev) 712{ 713 struct c_can_priv *priv = netdev_priv(dev); 714 struct net_device_stats *stats = &dev->stats; 715 u32 idx, obj, pkts = 0, bytes = 0, pend, clr; 716 717 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 718 719 while ((idx = ffs(pend))) { 720 idx--; 721 pend &= ~(1 << idx); 722 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 723 c_can_inval_tx_object(dev, IF_RX, obj); 724 can_get_echo_skb(dev, idx); 725 bytes += priv->dlc[idx]; 726 pkts++; 727 } 728 729 /* Clear the bits in the tx_active mask */ 730 atomic_sub(clr, &priv->tx_active); 731 732 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) 733 netif_wake_queue(dev); 734 735 if (pkts) { 736 stats->tx_bytes += bytes; 737 stats->tx_packets += pkts; 738 can_led_event(dev, CAN_LED_EVENT_TX); 739 } 740} 741 742/* 743 * If we have a gap in the pending bits, that means we either 744 * raced with the hardware or failed to readout all upper 745 * objects in the last run due to quota limit. 746 */ 747static u32 c_can_adjust_pending(u32 pend) 748{ 749 u32 weight, lasts; 750 751 if (pend == RECEIVE_OBJECT_BITS) 752 return pend; 753 754 /* 755 * If the last set bit is larger than the number of pending 756 * bits we have a gap. 757 */ 758 weight = hweight32(pend); 759 lasts = fls(pend); 760 761 /* If the bits are linear, nothing to do */ 762 if (lasts == weight) 763 return pend; 764 765 /* 766 * Find the first set bit after the gap. We walk backwards 767 * from the last set bit. 768 */ 769 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 770 771 return pend & ~((1 << lasts) - 1); 772} 773 774static inline void c_can_rx_object_get(struct net_device *dev, 775 struct c_can_priv *priv, u32 obj) 776{ 777 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 778} 779 780static inline void c_can_rx_finalize(struct net_device *dev, 781 struct c_can_priv *priv, u32 obj) 782{ 783 if (priv->type != BOSCH_D_CAN) 784 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 785} 786 787static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 788 u32 pend, int quota) 789{ 790 u32 pkts = 0, ctrl, obj; 791 792 while ((obj = ffs(pend)) && quota > 0) { 793 pend &= ~BIT(obj - 1); 794 795 c_can_rx_object_get(dev, priv, obj); 796 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 797 798 if (ctrl & IF_MCONT_MSGLST) { 799 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 800 801 pkts += n; 802 quota -= n; 803 continue; 804 } 805 806 /* 807 * This really should not happen, but this covers some 808 * odd HW behaviour. Do not remove that unless you 809 * want to brick your machine. 810 */ 811 if (!(ctrl & IF_MCONT_NEWDAT)) 812 continue; 813 814 /* read the data from the message object */ 815 c_can_read_msg_object(dev, IF_RX, ctrl); 816 817 c_can_rx_finalize(dev, priv, obj); 818 819 pkts++; 820 quota--; 821 } 822 823 return pkts; 824} 825 826static inline u32 c_can_get_pending(struct c_can_priv *priv) 827{ 828 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 829 830 return pend; 831} 832 833/* 834 * theory of operation: 835 * 836 * c_can core saves a received CAN message into the first free message 837 * object it finds free (starting with the lowest). Bits NEWDAT and 838 * INTPND are set for this message object indicating that a new message 839 * has arrived. To work-around this issue, we keep two groups of message 840 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 841 * 842 * We clear the newdat bit right away. 843 * 844 * This can result in packet reordering when the readout is slow. 845 */ 846static int c_can_do_rx_poll(struct net_device *dev, int quota) 847{ 848 struct c_can_priv *priv = netdev_priv(dev); 849 u32 pkts = 0, pend = 0, toread, n; 850 851 /* 852 * It is faster to read only one 16bit register. This is only possible 853 * for a maximum number of 16 objects. 854 */ 855 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 856 "Implementation does not support more message objects than 16"); 857 858 while (quota > 0) { 859 if (!pend) { 860 pend = c_can_get_pending(priv); 861 if (!pend) 862 break; 863 /* 864 * If the pending field has a gap, handle the 865 * bits above the gap first. 866 */ 867 toread = c_can_adjust_pending(pend); 868 } else { 869 toread = pend; 870 } 871 /* Remove the bits from pend */ 872 pend &= ~toread; 873 /* Read the objects */ 874 n = c_can_read_objects(dev, priv, toread, quota); 875 pkts += n; 876 quota -= n; 877 } 878 879 if (pkts) 880 can_led_event(dev, CAN_LED_EVENT_RX); 881 882 return pkts; 883} 884 885static int c_can_handle_state_change(struct net_device *dev, 886 enum c_can_bus_error_types error_type) 887{ 888 unsigned int reg_err_counter; 889 unsigned int rx_err_passive; 890 struct c_can_priv *priv = netdev_priv(dev); 891 struct net_device_stats *stats = &dev->stats; 892 struct can_frame *cf; 893 struct sk_buff *skb; 894 struct can_berr_counter bec; 895 896 switch (error_type) { 897 case C_CAN_NO_ERROR: 898 priv->can.state = CAN_STATE_ERROR_ACTIVE; 899 break; 900 case C_CAN_ERROR_WARNING: 901 /* error warning state */ 902 priv->can.can_stats.error_warning++; 903 priv->can.state = CAN_STATE_ERROR_WARNING; 904 break; 905 case C_CAN_ERROR_PASSIVE: 906 /* error passive state */ 907 priv->can.can_stats.error_passive++; 908 priv->can.state = CAN_STATE_ERROR_PASSIVE; 909 break; 910 case C_CAN_BUS_OFF: 911 /* bus-off state */ 912 priv->can.state = CAN_STATE_BUS_OFF; 913 priv->can.can_stats.bus_off++; 914 break; 915 default: 916 break; 917 } 918 919 /* propagate the error condition to the CAN stack */ 920 skb = alloc_can_err_skb(dev, &cf); 921 if (unlikely(!skb)) 922 return 0; 923 924 __c_can_get_berr_counter(dev, &bec); 925 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 926 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 927 ERR_CNT_RP_SHIFT; 928 929 switch (error_type) { 930 case C_CAN_NO_ERROR: 931 /* error warning state */ 932 cf->can_id |= CAN_ERR_CRTL; 933 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 934 cf->data[6] = bec.txerr; 935 cf->data[7] = bec.rxerr; 936 break; 937 case C_CAN_ERROR_WARNING: 938 /* error warning state */ 939 cf->can_id |= CAN_ERR_CRTL; 940 cf->data[1] = (bec.txerr > bec.rxerr) ? 941 CAN_ERR_CRTL_TX_WARNING : 942 CAN_ERR_CRTL_RX_WARNING; 943 cf->data[6] = bec.txerr; 944 cf->data[7] = bec.rxerr; 945 946 break; 947 case C_CAN_ERROR_PASSIVE: 948 /* error passive state */ 949 cf->can_id |= CAN_ERR_CRTL; 950 if (rx_err_passive) 951 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 952 if (bec.txerr > 127) 953 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 954 955 cf->data[6] = bec.txerr; 956 cf->data[7] = bec.rxerr; 957 break; 958 case C_CAN_BUS_OFF: 959 /* bus-off state */ 960 cf->can_id |= CAN_ERR_BUSOFF; 961 can_bus_off(dev); 962 break; 963 default: 964 break; 965 } 966 967 stats->rx_packets++; 968 stats->rx_bytes += cf->can_dlc; 969 netif_receive_skb(skb); 970 971 return 1; 972} 973 974static int c_can_handle_bus_err(struct net_device *dev, 975 enum c_can_lec_type lec_type) 976{ 977 struct c_can_priv *priv = netdev_priv(dev); 978 struct net_device_stats *stats = &dev->stats; 979 struct can_frame *cf; 980 struct sk_buff *skb; 981 982 /* 983 * early exit if no lec update or no error. 984 * no lec update means that no CAN bus event has been detected 985 * since CPU wrote 0x7 value to status reg. 986 */ 987 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 988 return 0; 989 990 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 991 return 0; 992 993 /* common for all type of bus errors */ 994 priv->can.can_stats.bus_error++; 995 stats->rx_errors++; 996 997 /* propagate the error condition to the CAN stack */ 998 skb = alloc_can_err_skb(dev, &cf); 999 if (unlikely(!skb)) 1000 return 0; 1001 1002 /* 1003 * check for 'last error code' which tells us the 1004 * type of the last error to occur on the CAN bus 1005 */ 1006 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1007 1008 switch (lec_type) { 1009 case LEC_STUFF_ERROR: 1010 netdev_dbg(dev, "stuff error\n"); 1011 cf->data[2] |= CAN_ERR_PROT_STUFF; 1012 break; 1013 case LEC_FORM_ERROR: 1014 netdev_dbg(dev, "form error\n"); 1015 cf->data[2] |= CAN_ERR_PROT_FORM; 1016 break; 1017 case LEC_ACK_ERROR: 1018 netdev_dbg(dev, "ack error\n"); 1019 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 1020 break; 1021 case LEC_BIT1_ERROR: 1022 netdev_dbg(dev, "bit1 error\n"); 1023 cf->data[2] |= CAN_ERR_PROT_BIT1; 1024 break; 1025 case LEC_BIT0_ERROR: 1026 netdev_dbg(dev, "bit0 error\n"); 1027 cf->data[2] |= CAN_ERR_PROT_BIT0; 1028 break; 1029 case LEC_CRC_ERROR: 1030 netdev_dbg(dev, "CRC error\n"); 1031 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1032 break; 1033 default: 1034 break; 1035 } 1036 1037 stats->rx_packets++; 1038 stats->rx_bytes += cf->can_dlc; 1039 netif_receive_skb(skb); 1040 return 1; 1041} 1042 1043static int c_can_poll(struct napi_struct *napi, int quota) 1044{ 1045 struct net_device *dev = napi->dev; 1046 struct c_can_priv *priv = netdev_priv(dev); 1047 u16 curr, last = priv->last_status; 1048 int work_done = 0; 1049 1050 /* Only read the status register if a status interrupt was pending */ 1051 if (atomic_xchg(&priv->sie_pending, 0)) { 1052 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1053 /* Ack status on C_CAN. D_CAN is self clearing */ 1054 if (priv->type != BOSCH_D_CAN) 1055 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1056 } else { 1057 /* no change detected ... */ 1058 curr = last; 1059 } 1060 1061 /* handle state changes */ 1062 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1063 netdev_dbg(dev, "entered error warning state\n"); 1064 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1065 } 1066 1067 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1068 netdev_dbg(dev, "entered error passive state\n"); 1069 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1070 } 1071 1072 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1073 netdev_dbg(dev, "entered bus off state\n"); 1074 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1075 goto end; 1076 } 1077 1078 /* handle bus recovery events */ 1079 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1080 netdev_dbg(dev, "left bus off state\n"); 1081 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1082 } 1083 1084 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1085 netdev_dbg(dev, "left error passive state\n"); 1086 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1087 } 1088 1089 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { 1090 netdev_dbg(dev, "left error warning state\n"); 1091 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); 1092 } 1093 1094 /* handle lec errors on the bus */ 1095 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1096 1097 /* Handle Tx/Rx events. We do this unconditionally */ 1098 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1099 c_can_do_tx(dev); 1100 1101end: 1102 if (work_done < quota) { 1103 napi_complete_done(napi, work_done); 1104 /* enable all IRQs if we are not in bus off state */ 1105 if (priv->can.state != CAN_STATE_BUS_OFF) 1106 c_can_irq_control(priv, true); 1107 } 1108 1109 return work_done; 1110} 1111 1112static irqreturn_t c_can_isr(int irq, void *dev_id) 1113{ 1114 struct net_device *dev = (struct net_device *)dev_id; 1115 struct c_can_priv *priv = netdev_priv(dev); 1116 int reg_int; 1117 1118 reg_int = priv->read_reg(priv, C_CAN_INT_REG); 1119 if (!reg_int) 1120 return IRQ_NONE; 1121 1122 /* save for later use */ 1123 if (reg_int & INT_STS_PENDING) 1124 atomic_set(&priv->sie_pending, 1); 1125 1126 /* disable all interrupts and schedule the NAPI */ 1127 c_can_irq_control(priv, false); 1128 napi_schedule(&priv->napi); 1129 1130 return IRQ_HANDLED; 1131} 1132 1133static int c_can_open(struct net_device *dev) 1134{ 1135 int err; 1136 struct c_can_priv *priv = netdev_priv(dev); 1137 1138 c_can_pm_runtime_get_sync(priv); 1139 c_can_reset_ram(priv, true); 1140 1141 /* open the can device */ 1142 err = open_candev(dev); 1143 if (err) { 1144 netdev_err(dev, "failed to open can device\n"); 1145 goto exit_open_fail; 1146 } 1147 1148 /* register interrupt handler */ 1149 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1150 dev); 1151 if (err < 0) { 1152 netdev_err(dev, "failed to request interrupt\n"); 1153 goto exit_irq_fail; 1154 } 1155 1156 /* start the c_can controller */ 1157 err = c_can_start(dev); 1158 if (err) 1159 goto exit_start_fail; 1160 1161 can_led_event(dev, CAN_LED_EVENT_OPEN); 1162 1163 napi_enable(&priv->napi); 1164 /* enable status change, error and module interrupts */ 1165 c_can_irq_control(priv, true); 1166 netif_start_queue(dev); 1167 1168 return 0; 1169 1170exit_start_fail: 1171 free_irq(dev->irq, dev); 1172exit_irq_fail: 1173 close_candev(dev); 1174exit_open_fail: 1175 c_can_reset_ram(priv, false); 1176 c_can_pm_runtime_put_sync(priv); 1177 return err; 1178} 1179 1180static int c_can_close(struct net_device *dev) 1181{ 1182 struct c_can_priv *priv = netdev_priv(dev); 1183 1184 netif_stop_queue(dev); 1185 napi_disable(&priv->napi); 1186 c_can_stop(dev); 1187 free_irq(dev->irq, dev); 1188 close_candev(dev); 1189 1190 c_can_reset_ram(priv, false); 1191 c_can_pm_runtime_put_sync(priv); 1192 1193 can_led_event(dev, CAN_LED_EVENT_STOP); 1194 1195 return 0; 1196} 1197 1198struct net_device *alloc_c_can_dev(void) 1199{ 1200 struct net_device *dev; 1201 struct c_can_priv *priv; 1202 1203 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1204 if (!dev) 1205 return NULL; 1206 1207 priv = netdev_priv(dev); 1208 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1209 1210 priv->dev = dev; 1211 priv->can.bittiming_const = &c_can_bittiming_const; 1212 priv->can.do_set_mode = c_can_set_mode; 1213 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1214 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1215 CAN_CTRLMODE_LISTENONLY | 1216 CAN_CTRLMODE_BERR_REPORTING; 1217 1218 return dev; 1219} 1220EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1221 1222#ifdef CONFIG_PM 1223int c_can_power_down(struct net_device *dev) 1224{ 1225 u32 val; 1226 unsigned long time_out; 1227 struct c_can_priv *priv = netdev_priv(dev); 1228 1229 if (!(dev->flags & IFF_UP)) 1230 return 0; 1231 1232 WARN_ON(priv->type != BOSCH_D_CAN); 1233 1234 /* set PDR value so the device goes to power down mode */ 1235 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1236 val |= CONTROL_EX_PDR; 1237 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1238 1239 /* Wait for the PDA bit to get set */ 1240 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1241 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1242 time_after(time_out, jiffies)) 1243 cpu_relax(); 1244 1245 if (time_after(jiffies, time_out)) 1246 return -ETIMEDOUT; 1247 1248 c_can_stop(dev); 1249 1250 c_can_reset_ram(priv, false); 1251 c_can_pm_runtime_put_sync(priv); 1252 1253 return 0; 1254} 1255EXPORT_SYMBOL_GPL(c_can_power_down); 1256 1257int c_can_power_up(struct net_device *dev) 1258{ 1259 u32 val; 1260 unsigned long time_out; 1261 struct c_can_priv *priv = netdev_priv(dev); 1262 int ret; 1263 1264 if (!(dev->flags & IFF_UP)) 1265 return 0; 1266 1267 WARN_ON(priv->type != BOSCH_D_CAN); 1268 1269 c_can_pm_runtime_get_sync(priv); 1270 c_can_reset_ram(priv, true); 1271 1272 /* Clear PDR and INIT bits */ 1273 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1274 val &= ~CONTROL_EX_PDR; 1275 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1276 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1277 val &= ~CONTROL_INIT; 1278 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1279 1280 /* Wait for the PDA bit to get clear */ 1281 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1282 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1283 time_after(time_out, jiffies)) 1284 cpu_relax(); 1285 1286 if (time_after(jiffies, time_out)) { 1287 ret = -ETIMEDOUT; 1288 goto err_out; 1289 } 1290 1291 ret = c_can_start(dev); 1292 if (ret) 1293 goto err_out; 1294 1295 c_can_irq_control(priv, true); 1296 1297 return 0; 1298 1299err_out: 1300 c_can_reset_ram(priv, false); 1301 c_can_pm_runtime_put_sync(priv); 1302 1303 return ret; 1304} 1305EXPORT_SYMBOL_GPL(c_can_power_up); 1306#endif 1307 1308void free_c_can_dev(struct net_device *dev) 1309{ 1310 struct c_can_priv *priv = netdev_priv(dev); 1311 1312 netif_napi_del(&priv->napi); 1313 free_candev(dev); 1314} 1315EXPORT_SYMBOL_GPL(free_c_can_dev); 1316 1317static const struct net_device_ops c_can_netdev_ops = { 1318 .ndo_open = c_can_open, 1319 .ndo_stop = c_can_close, 1320 .ndo_start_xmit = c_can_start_xmit, 1321 .ndo_change_mtu = can_change_mtu, 1322}; 1323 1324int register_c_can_dev(struct net_device *dev) 1325{ 1326 int err; 1327 1328 /* Deactivate pins to prevent DRA7 DCAN IP from being 1329 * stuck in transition when module is disabled. 1330 * Pins are activated in c_can_start() and deactivated 1331 * in c_can_stop() 1332 */ 1333 pinctrl_pm_select_sleep_state(dev->dev.parent); 1334 1335 dev->flags |= IFF_ECHO; /* we support local echo */ 1336 dev->netdev_ops = &c_can_netdev_ops; 1337 1338 err = register_candev(dev); 1339 if (!err) 1340 devm_can_led_init(dev); 1341 return err; 1342} 1343EXPORT_SYMBOL_GPL(register_c_can_dev); 1344 1345void unregister_c_can_dev(struct net_device *dev) 1346{ 1347 unregister_candev(dev); 1348} 1349EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1350 1351MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1352MODULE_LICENSE("GPL v2"); 1353MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1354