1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7#include <linux/mtd/spi-nor.h>
8
9#include "core.h"
10
11static int
12is25lp256_post_bfpt_fixups(struct spi_nor *nor,
13			   const struct sfdp_parameter_header *bfpt_header,
14			   const struct sfdp_bfpt *bfpt,
15			   struct spi_nor_flash_parameter *params)
16{
17	/*
18	 * IS25LP256 supports 4B opcodes, but the BFPT advertises a
19	 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
20	 * Overwrite the address width advertised by the BFPT.
21	 */
22	if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
23		BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
24		nor->addr_width = 4;
25
26	return 0;
27}
28
29static struct spi_nor_fixups is25lp256_fixups = {
30	.post_bfpt = is25lp256_post_bfpt_fixups,
31};
32
33static const struct flash_info issi_parts[] = {
34	/* ISSI */
35	{ "is25cd512",  INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },
36	{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024,   8,
37			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
38	{ "is25lp016d", INFO(0x9d6015, 0, 64 * 1024,  32,
39			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
40	{ "is25lp080d", INFO(0x9d6014, 0, 64 * 1024,  16,
41			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
42	{ "is25lp032",  INFO(0x9d6016, 0, 64 * 1024,  64,
43			     SECT_4K | SPI_NOR_DUAL_READ) },
44	{ "is25lp064",  INFO(0x9d6017, 0, 64 * 1024, 128,
45			     SECT_4K | SPI_NOR_DUAL_READ) },
46	{ "is25lp128",  INFO(0x9d6018, 0, 64 * 1024, 256,
47			     SECT_4K | SPI_NOR_DUAL_READ) },
48	{ "is25lp256",  INFO(0x9d6019, 0, 64 * 1024, 512,
49			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
50			     SPI_NOR_4B_OPCODES)
51		.fixups = &is25lp256_fixups },
52	{ "is25wp032",  INFO(0x9d7016, 0, 64 * 1024,  64,
53			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
54	{ "is25wp064",  INFO(0x9d7017, 0, 64 * 1024, 128,
55			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
56	{ "is25wp128",  INFO(0x9d7018, 0, 64 * 1024, 256,
57			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
58	{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
59			    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
60			    SPI_NOR_4B_OPCODES)
61		.fixups = &is25lp256_fixups },
62
63	/* PMC */
64	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
65	{ "pm25lv010",   INFO(0,        0, 32 * 1024,    4, SECT_4K_PMC) },
66	{ "pm25lq032",   INFO(0x7f9d46, 0, 64 * 1024,   64, SECT_4K) },
67};
68
69static void issi_default_init(struct spi_nor *nor)
70{
71	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
72}
73
74static const struct spi_nor_fixups issi_fixups = {
75	.default_init = issi_default_init,
76};
77
78const struct spi_nor_manufacturer spi_nor_issi = {
79	.name = "issi",
80	.parts = issi_parts,
81	.nparts = ARRAY_SIZE(issi_parts),
82	.fixups = &issi_fixups,
83};
84