1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ASPEED Static Memory Controller driver 4 * 5 * Copyright (c) 2015-2016, IBM Corporation. 6 */ 7 8#include <linux/bug.h> 9#include <linux/device.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/mutex.h> 13#include <linux/mtd/mtd.h> 14#include <linux/mtd/partitions.h> 15#include <linux/mtd/spi-nor.h> 16#include <linux/of.h> 17#include <linux/of_platform.h> 18#include <linux/sizes.h> 19#include <linux/sysfs.h> 20 21#define DEVICE_NAME "aspeed-smc" 22 23/* 24 * The driver only support SPI flash 25 */ 26enum aspeed_smc_flash_type { 27 smc_type_nor = 0, 28 smc_type_nand = 1, 29 smc_type_spi = 2, 30}; 31 32struct aspeed_smc_chip; 33 34struct aspeed_smc_info { 35 u32 maxsize; /* maximum size of chip window */ 36 u8 nce; /* number of chip enables */ 37 bool hastype; /* flash type field exists in config reg */ 38 u8 we0; /* shift for write enable bit for CE0 */ 39 u8 ctl0; /* offset in regs of ctl for CE0 */ 40 41 void (*set_4b)(struct aspeed_smc_chip *chip); 42}; 43 44static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); 45static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); 46 47static const struct aspeed_smc_info fmc_2400_info = { 48 .maxsize = 64 * 1024 * 1024, 49 .nce = 5, 50 .hastype = true, 51 .we0 = 16, 52 .ctl0 = 0x10, 53 .set_4b = aspeed_smc_chip_set_4b, 54}; 55 56static const struct aspeed_smc_info spi_2400_info = { 57 .maxsize = 64 * 1024 * 1024, 58 .nce = 1, 59 .hastype = false, 60 .we0 = 0, 61 .ctl0 = 0x04, 62 .set_4b = aspeed_smc_chip_set_4b_spi_2400, 63}; 64 65static const struct aspeed_smc_info fmc_2500_info = { 66 .maxsize = 256 * 1024 * 1024, 67 .nce = 3, 68 .hastype = true, 69 .we0 = 16, 70 .ctl0 = 0x10, 71 .set_4b = aspeed_smc_chip_set_4b, 72}; 73 74static const struct aspeed_smc_info spi_2500_info = { 75 .maxsize = 128 * 1024 * 1024, 76 .nce = 2, 77 .hastype = false, 78 .we0 = 16, 79 .ctl0 = 0x10, 80 .set_4b = aspeed_smc_chip_set_4b, 81}; 82 83enum aspeed_smc_ctl_reg_value { 84 smc_base, /* base value without mode for other commands */ 85 smc_read, /* command reg for (maybe fast) reads */ 86 smc_write, /* command reg for writes */ 87 smc_max, 88}; 89 90struct aspeed_smc_controller; 91 92struct aspeed_smc_chip { 93 int cs; 94 struct aspeed_smc_controller *controller; 95 void __iomem *ctl; /* control register */ 96 void __iomem *ahb_base; /* base of chip window */ 97 u32 ahb_window_size; /* chip mapping window size */ 98 u32 ctl_val[smc_max]; /* control settings */ 99 enum aspeed_smc_flash_type type; /* what type of flash */ 100 struct spi_nor nor; 101}; 102 103struct aspeed_smc_controller { 104 struct device *dev; 105 106 struct mutex mutex; /* controller access mutex */ 107 const struct aspeed_smc_info *info; /* type info of controller */ 108 void __iomem *regs; /* controller registers */ 109 void __iomem *ahb_base; /* per-chip windows resource */ 110 u32 ahb_window_size; /* full mapping window size */ 111 112 struct aspeed_smc_chip *chips[]; /* pointers to attached chips */ 113}; 114 115/* 116 * SPI Flash Configuration Register (AST2500 SPI) 117 * or 118 * Type setting Register (AST2500 FMC). 119 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the 120 * driver does not support it. 121 */ 122#define CONFIG_REG 0x0 123#define CONFIG_DISABLE_LEGACY BIT(31) /* 1 */ 124 125#define CONFIG_CE2_WRITE BIT(18) 126#define CONFIG_CE1_WRITE BIT(17) 127#define CONFIG_CE0_WRITE BIT(16) 128 129#define CONFIG_CE2_TYPE BIT(4) /* AST2500 FMC only */ 130#define CONFIG_CE1_TYPE BIT(2) /* AST2500 FMC only */ 131#define CONFIG_CE0_TYPE BIT(0) /* AST2500 FMC only */ 132 133/* 134 * CE Control Register 135 */ 136#define CE_CONTROL_REG 0x4 137 138/* 139 * CEx Control Register 140 */ 141#define CONTROL_AAF_MODE BIT(31) 142#define CONTROL_IO_MODE_MASK GENMASK(30, 28) 143#define CONTROL_IO_DUAL_DATA BIT(29) 144#define CONTROL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 145#define CONTROL_IO_QUAD_DATA BIT(30) 146#define CONTROL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 147#define CONTROL_CE_INACTIVE_SHIFT 24 148#define CONTROL_CE_INACTIVE_MASK GENMASK(27, \ 149 CONTROL_CE_INACTIVE_SHIFT) 150/* 0 = 16T ... 15 = 1T T=HCLK */ 151#define CONTROL_COMMAND_SHIFT 16 152#define CONTROL_DUMMY_COMMAND_OUT BIT(15) 153#define CONTROL_IO_DUMMY_HI BIT(14) 154#define CONTROL_IO_DUMMY_HI_SHIFT 14 155#define CONTROL_CLK_DIV4 BIT(13) /* others */ 156#define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */ 157#define CONTROL_RW_MERGE BIT(12) 158#define CONTROL_IO_DUMMY_LO_SHIFT 6 159#define CONTROL_IO_DUMMY_LO GENMASK(7, \ 160 CONTROL_IO_DUMMY_LO_SHIFT) 161#define CONTROL_IO_DUMMY_MASK (CONTROL_IO_DUMMY_HI | \ 162 CONTROL_IO_DUMMY_LO) 163#define CONTROL_IO_DUMMY_SET(dummy) \ 164 (((((dummy) >> 2) & 0x1) << CONTROL_IO_DUMMY_HI_SHIFT) | \ 165 (((dummy) & 0x3) << CONTROL_IO_DUMMY_LO_SHIFT)) 166 167#define CONTROL_CLOCK_FREQ_SEL_SHIFT 8 168#define CONTROL_CLOCK_FREQ_SEL_MASK GENMASK(11, \ 169 CONTROL_CLOCK_FREQ_SEL_SHIFT) 170#define CONTROL_LSB_FIRST BIT(5) 171#define CONTROL_CLOCK_MODE_3 BIT(4) 172#define CONTROL_IN_DUAL_DATA BIT(3) 173#define CONTROL_CE_STOP_ACTIVE_CONTROL BIT(2) 174#define CONTROL_COMMAND_MODE_MASK GENMASK(1, 0) 175#define CONTROL_COMMAND_MODE_NORMAL 0 176#define CONTROL_COMMAND_MODE_FREAD 1 177#define CONTROL_COMMAND_MODE_WRITE 2 178#define CONTROL_COMMAND_MODE_USER 3 179 180#define CONTROL_KEEP_MASK \ 181 (CONTROL_AAF_MODE | CONTROL_CE_INACTIVE_MASK | CONTROL_CLK_DIV4 | \ 182 CONTROL_CLOCK_FREQ_SEL_MASK | CONTROL_LSB_FIRST | CONTROL_CLOCK_MODE_3) 183 184/* 185 * The Segment Register uses a 8MB unit to encode the start address 186 * and the end address of the mapping window of a flash SPI slave : 187 * 188 * | byte 1 | byte 2 | byte 3 | byte 4 | 189 * +--------+--------+--------+--------+ 190 * | end | start | 0 | 0 | 191 */ 192#define SEGMENT_ADDR_REG0 0x30 193#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23) 194#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23) 195#define SEGMENT_ADDR_VALUE(start, end) \ 196 (((((start) >> 23) & 0xFF) << 16) | ((((end) >> 23) & 0xFF) << 24)) 197#define SEGMENT_ADDR_REG(controller, cs) \ 198 ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4) 199 200/* 201 * In user mode all data bytes read or written to the chip decode address 202 * range are transferred to or from the SPI bus. The range is treated as a 203 * fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned 204 * to its size. The address within the multiple 8kB range is ignored when 205 * sending bytes to the SPI bus. 206 * 207 * On the arm architecture, as of Linux version 4.3, memcpy_fromio and 208 * memcpy_toio on little endian targets use the optimized memcpy routines 209 * that were designed for well behavied memory storage. These routines 210 * have a stutter if the source and destination are not both word aligned, 211 * once with a duplicate access to the source after aligning to the 212 * destination to a word boundary, and again with a duplicate access to 213 * the source when the final byte count is not word aligned. 214 * 215 * When writing or reading the fifo this stutter discards data or sends 216 * too much data to the fifo and can not be used by this driver. 217 * 218 * While the low level io string routines that implement the insl family do 219 * the desired accesses and memory increments, the cross architecture io 220 * macros make them essentially impossible to use on a memory mapped address 221 * instead of a a token from the call to iomap of an io port. 222 * 223 * These fifo routines use readl and friends to a constant io port and update 224 * the memory buffer pointer and count via explicit code. The final updates 225 * to len are optimistically suppressed. 226 */ 227static int aspeed_smc_read_from_ahb(void *buf, void __iomem *src, size_t len) 228{ 229 size_t offset = 0; 230 231 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) && 232 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 233 ioread32_rep(src, buf, len >> 2); 234 offset = len & ~0x3; 235 len -= offset; 236 } 237 ioread8_rep(src, (u8 *)buf + offset, len); 238 return 0; 239} 240 241static int aspeed_smc_write_to_ahb(void __iomem *dst, const void *buf, 242 size_t len) 243{ 244 size_t offset = 0; 245 246 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) && 247 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 248 iowrite32_rep(dst, buf, len >> 2); 249 offset = len & ~0x3; 250 len -= offset; 251 } 252 iowrite8_rep(dst, (const u8 *)buf + offset, len); 253 return 0; 254} 255 256static inline u32 aspeed_smc_chip_write_bit(struct aspeed_smc_chip *chip) 257{ 258 return BIT(chip->controller->info->we0 + chip->cs); 259} 260 261static void aspeed_smc_chip_check_config(struct aspeed_smc_chip *chip) 262{ 263 struct aspeed_smc_controller *controller = chip->controller; 264 u32 reg; 265 266 reg = readl(controller->regs + CONFIG_REG); 267 268 if (reg & aspeed_smc_chip_write_bit(chip)) 269 return; 270 271 dev_dbg(controller->dev, "config write is not set ! @%p: 0x%08x\n", 272 controller->regs + CONFIG_REG, reg); 273 reg |= aspeed_smc_chip_write_bit(chip); 274 writel(reg, controller->regs + CONFIG_REG); 275} 276 277static void aspeed_smc_start_user(struct spi_nor *nor) 278{ 279 struct aspeed_smc_chip *chip = nor->priv; 280 u32 ctl = chip->ctl_val[smc_base]; 281 282 /* 283 * When the chip is controlled in user mode, we need write 284 * access to send the opcodes to it. So check the config. 285 */ 286 aspeed_smc_chip_check_config(chip); 287 288 ctl |= CONTROL_COMMAND_MODE_USER | 289 CONTROL_CE_STOP_ACTIVE_CONTROL; 290 writel(ctl, chip->ctl); 291 292 ctl &= ~CONTROL_CE_STOP_ACTIVE_CONTROL; 293 writel(ctl, chip->ctl); 294} 295 296static void aspeed_smc_stop_user(struct spi_nor *nor) 297{ 298 struct aspeed_smc_chip *chip = nor->priv; 299 300 u32 ctl = chip->ctl_val[smc_read]; 301 u32 ctl2 = ctl | CONTROL_COMMAND_MODE_USER | 302 CONTROL_CE_STOP_ACTIVE_CONTROL; 303 304 writel(ctl2, chip->ctl); /* stop user CE control */ 305 writel(ctl, chip->ctl); /* default to fread or read mode */ 306} 307 308static int aspeed_smc_prep(struct spi_nor *nor) 309{ 310 struct aspeed_smc_chip *chip = nor->priv; 311 312 mutex_lock(&chip->controller->mutex); 313 return 0; 314} 315 316static void aspeed_smc_unprep(struct spi_nor *nor) 317{ 318 struct aspeed_smc_chip *chip = nor->priv; 319 320 mutex_unlock(&chip->controller->mutex); 321} 322 323static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, 324 size_t len) 325{ 326 struct aspeed_smc_chip *chip = nor->priv; 327 328 aspeed_smc_start_user(nor); 329 aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1); 330 aspeed_smc_read_from_ahb(buf, chip->ahb_base, len); 331 aspeed_smc_stop_user(nor); 332 return 0; 333} 334 335static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, 336 size_t len) 337{ 338 struct aspeed_smc_chip *chip = nor->priv; 339 340 aspeed_smc_start_user(nor); 341 aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1); 342 aspeed_smc_write_to_ahb(chip->ahb_base, buf, len); 343 aspeed_smc_stop_user(nor); 344 return 0; 345} 346 347static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr) 348{ 349 struct aspeed_smc_chip *chip = nor->priv; 350 __be32 temp; 351 u32 cmdaddr; 352 353 switch (nor->addr_width) { 354 default: 355 WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n", 356 nor->addr_width); 357 fallthrough; 358 case 3: 359 cmdaddr = addr & 0xFFFFFF; 360 cmdaddr |= cmd << 24; 361 362 temp = cpu_to_be32(cmdaddr); 363 aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4); 364 break; 365 case 4: 366 temp = cpu_to_be32(addr); 367 aspeed_smc_write_to_ahb(chip->ahb_base, &cmd, 1); 368 aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4); 369 break; 370 } 371} 372 373static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from, 374 size_t len, u_char *read_buf) 375{ 376 struct aspeed_smc_chip *chip = nor->priv; 377 int i; 378 u8 dummy = 0xFF; 379 380 aspeed_smc_start_user(nor); 381 aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from); 382 for (i = 0; i < chip->nor.read_dummy / 8; i++) 383 aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy)); 384 385 aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len); 386 aspeed_smc_stop_user(nor); 387 return len; 388} 389 390static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to, 391 size_t len, const u_char *write_buf) 392{ 393 struct aspeed_smc_chip *chip = nor->priv; 394 395 aspeed_smc_start_user(nor); 396 aspeed_smc_send_cmd_addr(nor, nor->program_opcode, to); 397 aspeed_smc_write_to_ahb(chip->ahb_base, write_buf, len); 398 aspeed_smc_stop_user(nor); 399 return len; 400} 401 402static int aspeed_smc_unregister(struct aspeed_smc_controller *controller) 403{ 404 struct aspeed_smc_chip *chip; 405 int n; 406 407 for (n = 0; n < controller->info->nce; n++) { 408 chip = controller->chips[n]; 409 if (chip) 410 mtd_device_unregister(&chip->nor.mtd); 411 } 412 413 return 0; 414} 415 416static int aspeed_smc_remove(struct platform_device *dev) 417{ 418 return aspeed_smc_unregister(platform_get_drvdata(dev)); 419} 420 421static const struct of_device_id aspeed_smc_matches[] = { 422 { .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info }, 423 { .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info }, 424 { .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info }, 425 { .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info }, 426 { } 427}; 428MODULE_DEVICE_TABLE(of, aspeed_smc_matches); 429 430/* 431 * Each chip has a mapping window defined by a segment address 432 * register defining a start and an end address on the AHB bus. These 433 * addresses can be configured to fit the chip size and offer a 434 * contiguous memory region across chips. For the moment, we only 435 * check that each chip segment is valid. 436 */ 437static void __iomem *aspeed_smc_chip_base(struct aspeed_smc_chip *chip, 438 struct resource *res) 439{ 440 struct aspeed_smc_controller *controller = chip->controller; 441 u32 offset = 0; 442 u32 reg; 443 444 if (controller->info->nce > 1) { 445 reg = readl(SEGMENT_ADDR_REG(controller, chip->cs)); 446 447 if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg)) 448 return NULL; 449 450 offset = SEGMENT_ADDR_START(reg) - res->start; 451 } 452 453 return controller->ahb_base + offset; 454} 455 456static u32 aspeed_smc_ahb_base_phy(struct aspeed_smc_controller *controller) 457{ 458 u32 seg0_val = readl(SEGMENT_ADDR_REG(controller, 0)); 459 460 return SEGMENT_ADDR_START(seg0_val); 461} 462 463static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, 464 u32 size) 465{ 466 struct aspeed_smc_controller *controller = chip->controller; 467 void __iomem *seg_reg; 468 u32 seg_oldval, seg_newval, ahb_base_phy, end; 469 470 ahb_base_phy = aspeed_smc_ahb_base_phy(controller); 471 472 seg_reg = SEGMENT_ADDR_REG(controller, cs); 473 seg_oldval = readl(seg_reg); 474 475 /* 476 * If the chip size is not specified, use the default segment 477 * size, but take into account the possible overlap with the 478 * previous segment 479 */ 480 if (!size) 481 size = SEGMENT_ADDR_END(seg_oldval) - start; 482 483 /* 484 * The segment cannot exceed the maximum window size of the 485 * controller. 486 */ 487 if (start + size > ahb_base_phy + controller->ahb_window_size) { 488 size = ahb_base_phy + controller->ahb_window_size - start; 489 dev_warn(chip->nor.dev, "CE%d window resized to %dMB", 490 cs, size >> 20); 491 } 492 493 end = start + size; 494 seg_newval = SEGMENT_ADDR_VALUE(start, end); 495 writel(seg_newval, seg_reg); 496 497 /* 498 * Restore default value if something goes wrong. The chip 499 * might have set some bogus value and we would loose access 500 * to the chip. 501 */ 502 if (seg_newval != readl(seg_reg)) { 503 dev_err(chip->nor.dev, "CE%d window invalid", cs); 504 writel(seg_oldval, seg_reg); 505 start = SEGMENT_ADDR_START(seg_oldval); 506 end = SEGMENT_ADDR_END(seg_oldval); 507 size = end - start; 508 } 509 510 dev_info(chip->nor.dev, "CE%d window [ 0x%.8x - 0x%.8x ] %dMB", 511 cs, start, end, size >> 20); 512 513 return size; 514} 515 516/* 517 * The segment register defines the mapping window on the AHB bus and 518 * it needs to be configured depending on the chip size. The segment 519 * register of the following CE also needs to be tuned in order to 520 * provide a contiguous window across multiple chips. 521 * 522 * This is expected to be called in increasing CE order 523 */ 524static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip) 525{ 526 struct aspeed_smc_controller *controller = chip->controller; 527 u32 ahb_base_phy, start; 528 u32 size = chip->nor.mtd.size; 529 530 /* 531 * Each controller has a chip size limit for direct memory 532 * access 533 */ 534 if (size > controller->info->maxsize) 535 size = controller->info->maxsize; 536 537 /* 538 * The AST2400 SPI controller only handles one chip and does 539 * not have segment registers. Let's use the chip size for the 540 * AHB window. 541 */ 542 if (controller->info == &spi_2400_info) 543 goto out; 544 545 /* 546 * The AST2500 SPI controller has a HW bug when the CE0 chip 547 * size reaches 128MB. Enforce a size limit of 120MB to 548 * prevent the controller from using bogus settings in the 549 * segment register. 550 */ 551 if (chip->cs == 0 && controller->info == &spi_2500_info && 552 size == SZ_128M) { 553 size = 120 << 20; 554 dev_info(chip->nor.dev, 555 "CE%d window resized to %dMB (AST2500 HW quirk)", 556 chip->cs, size >> 20); 557 } 558 559 ahb_base_phy = aspeed_smc_ahb_base_phy(controller); 560 561 /* 562 * As a start address for the current segment, use the default 563 * start address if we are handling CE0 or use the previous 564 * segment ending address 565 */ 566 if (chip->cs) { 567 u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1)); 568 569 start = SEGMENT_ADDR_END(prev); 570 } else { 571 start = ahb_base_phy; 572 } 573 574 size = chip_set_segment(chip, chip->cs, start, size); 575 576 /* Update chip base address on the AHB bus */ 577 chip->ahb_base = controller->ahb_base + (start - ahb_base_phy); 578 579 /* 580 * Now, make sure the next segment does not overlap with the 581 * current one we just configured, even if there is no 582 * available chip. That could break access in Command Mode. 583 */ 584 if (chip->cs < controller->info->nce - 1) 585 chip_set_segment(chip, chip->cs + 1, start + size, 0); 586 587out: 588 if (size < chip->nor.mtd.size) 589 dev_warn(chip->nor.dev, 590 "CE%d window too small for chip %dMB", 591 chip->cs, (u32)chip->nor.mtd.size >> 20); 592 593 return size; 594} 595 596static void aspeed_smc_chip_enable_write(struct aspeed_smc_chip *chip) 597{ 598 struct aspeed_smc_controller *controller = chip->controller; 599 u32 reg; 600 601 reg = readl(controller->regs + CONFIG_REG); 602 603 reg |= aspeed_smc_chip_write_bit(chip); 604 writel(reg, controller->regs + CONFIG_REG); 605} 606 607static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type) 608{ 609 struct aspeed_smc_controller *controller = chip->controller; 610 u32 reg; 611 612 chip->type = type; 613 614 reg = readl(controller->regs + CONFIG_REG); 615 reg &= ~(3 << (chip->cs * 2)); 616 reg |= chip->type << (chip->cs * 2); 617 writel(reg, controller->regs + CONFIG_REG); 618} 619 620/* 621 * The first chip of the AST2500 FMC flash controller is strapped by 622 * hardware, or autodetected, but other chips need to be set. Enforce 623 * the 4B setting for all chips. 624 */ 625static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip) 626{ 627 struct aspeed_smc_controller *controller = chip->controller; 628 u32 reg; 629 630 reg = readl(controller->regs + CE_CONTROL_REG); 631 reg |= 1 << chip->cs; 632 writel(reg, controller->regs + CE_CONTROL_REG); 633} 634 635/* 636 * The AST2400 SPI flash controller does not have a CE Control 637 * register. It uses the CE0 control register to set 4Byte mode at the 638 * controller level. 639 */ 640static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip) 641{ 642 chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B; 643 chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B; 644} 645 646static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip, 647 struct resource *res) 648{ 649 struct aspeed_smc_controller *controller = chip->controller; 650 const struct aspeed_smc_info *info = controller->info; 651 u32 reg, base_reg; 652 653 /* 654 * Always turn on the write enable bit to allow opcodes to be 655 * sent in user mode. 656 */ 657 aspeed_smc_chip_enable_write(chip); 658 659 /* The driver only supports SPI type flash */ 660 if (info->hastype) 661 aspeed_smc_chip_set_type(chip, smc_type_spi); 662 663 /* 664 * Configure chip base address in memory 665 */ 666 chip->ahb_base = aspeed_smc_chip_base(chip, res); 667 if (!chip->ahb_base) { 668 dev_warn(chip->nor.dev, "CE%d window closed", chip->cs); 669 return -EINVAL; 670 } 671 672 /* 673 * Get value of the inherited control register. U-Boot usually 674 * does some timing calibration on the FMC chip, so it's good 675 * to keep them. In the future, we should handle calibration 676 * from Linux. 677 */ 678 reg = readl(chip->ctl); 679 dev_dbg(controller->dev, "control register: %08x\n", reg); 680 681 base_reg = reg & CONTROL_KEEP_MASK; 682 if (base_reg != reg) { 683 dev_dbg(controller->dev, 684 "control register changed to: %08x\n", 685 base_reg); 686 } 687 chip->ctl_val[smc_base] = base_reg; 688 689 /* 690 * Retain the prior value of the control register as the 691 * default if it was normal access mode. Otherwise start with 692 * the sanitized base value set to read mode. 693 */ 694 if ((reg & CONTROL_COMMAND_MODE_MASK) == 695 CONTROL_COMMAND_MODE_NORMAL) 696 chip->ctl_val[smc_read] = reg; 697 else 698 chip->ctl_val[smc_read] = chip->ctl_val[smc_base] | 699 CONTROL_COMMAND_MODE_NORMAL; 700 701 dev_dbg(controller->dev, "default control register: %08x\n", 702 chip->ctl_val[smc_read]); 703 return 0; 704} 705 706static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip) 707{ 708 struct aspeed_smc_controller *controller = chip->controller; 709 const struct aspeed_smc_info *info = controller->info; 710 u32 cmd; 711 712 if (chip->nor.addr_width == 4 && info->set_4b) 713 info->set_4b(chip); 714 715 /* This is for direct AHB access when using Command Mode. */ 716 chip->ahb_window_size = aspeed_smc_chip_set_segment(chip); 717 718 /* 719 * base mode has not been optimized yet. use it for writes. 720 */ 721 chip->ctl_val[smc_write] = chip->ctl_val[smc_base] | 722 chip->nor.program_opcode << CONTROL_COMMAND_SHIFT | 723 CONTROL_COMMAND_MODE_WRITE; 724 725 dev_dbg(controller->dev, "write control register: %08x\n", 726 chip->ctl_val[smc_write]); 727 728 /* 729 * TODO: Adjust clocks if fast read is supported and interpret 730 * SPI NOR flags to adjust controller settings. 731 */ 732 if (chip->nor.read_proto == SNOR_PROTO_1_1_1) { 733 if (chip->nor.read_dummy == 0) 734 cmd = CONTROL_COMMAND_MODE_NORMAL; 735 else 736 cmd = CONTROL_COMMAND_MODE_FREAD; 737 } else { 738 dev_err(chip->nor.dev, "unsupported SPI read mode\n"); 739 return -EINVAL; 740 } 741 742 chip->ctl_val[smc_read] |= cmd | 743 CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8); 744 745 dev_dbg(controller->dev, "base control register: %08x\n", 746 chip->ctl_val[smc_read]); 747 return 0; 748} 749 750static const struct spi_nor_controller_ops aspeed_smc_controller_ops = { 751 .prepare = aspeed_smc_prep, 752 .unprepare = aspeed_smc_unprep, 753 .read_reg = aspeed_smc_read_reg, 754 .write_reg = aspeed_smc_write_reg, 755 .read = aspeed_smc_read_user, 756 .write = aspeed_smc_write_user, 757}; 758 759static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, 760 struct device_node *np, struct resource *r) 761{ 762 const struct spi_nor_hwcaps hwcaps = { 763 .mask = SNOR_HWCAPS_READ | 764 SNOR_HWCAPS_READ_FAST | 765 SNOR_HWCAPS_PP, 766 }; 767 const struct aspeed_smc_info *info = controller->info; 768 struct device *dev = controller->dev; 769 struct device_node *child; 770 unsigned int cs; 771 int ret = -ENODEV; 772 773 for_each_available_child_of_node(np, child) { 774 struct aspeed_smc_chip *chip; 775 struct spi_nor *nor; 776 struct mtd_info *mtd; 777 778 /* This driver does not support NAND or NOR flash devices. */ 779 if (!of_device_is_compatible(child, "jedec,spi-nor")) 780 continue; 781 782 ret = of_property_read_u32(child, "reg", &cs); 783 if (ret) { 784 dev_err(dev, "Couldn't not read chip select.\n"); 785 break; 786 } 787 788 if (cs >= info->nce) { 789 dev_err(dev, "Chip select %d out of range.\n", 790 cs); 791 ret = -ERANGE; 792 break; 793 } 794 795 if (controller->chips[cs]) { 796 dev_err(dev, "Chip select %d already in use by %s\n", 797 cs, dev_name(controller->chips[cs]->nor.dev)); 798 ret = -EBUSY; 799 break; 800 } 801 802 chip = devm_kzalloc(controller->dev, sizeof(*chip), GFP_KERNEL); 803 if (!chip) { 804 ret = -ENOMEM; 805 break; 806 } 807 808 chip->controller = controller; 809 chip->ctl = controller->regs + info->ctl0 + cs * 4; 810 chip->cs = cs; 811 812 nor = &chip->nor; 813 mtd = &nor->mtd; 814 815 nor->dev = dev; 816 nor->priv = chip; 817 spi_nor_set_flash_node(nor, child); 818 nor->controller_ops = &aspeed_smc_controller_ops; 819 820 ret = aspeed_smc_chip_setup_init(chip, r); 821 if (ret) 822 break; 823 824 /* 825 * TODO: Add support for Dual and Quad SPI protocols 826 * attach when board support is present as determined 827 * by of property. 828 */ 829 ret = spi_nor_scan(nor, NULL, &hwcaps); 830 if (ret) 831 break; 832 833 ret = aspeed_smc_chip_setup_finish(chip); 834 if (ret) 835 break; 836 837 ret = mtd_device_register(mtd, NULL, 0); 838 if (ret) 839 break; 840 841 controller->chips[cs] = chip; 842 } 843 844 if (ret) { 845 of_node_put(child); 846 aspeed_smc_unregister(controller); 847 } 848 849 return ret; 850} 851 852static int aspeed_smc_probe(struct platform_device *pdev) 853{ 854 struct device_node *np = pdev->dev.of_node; 855 struct device *dev = &pdev->dev; 856 struct aspeed_smc_controller *controller; 857 const struct of_device_id *match; 858 const struct aspeed_smc_info *info; 859 struct resource *res; 860 int ret; 861 862 match = of_match_device(aspeed_smc_matches, &pdev->dev); 863 if (!match || !match->data) 864 return -ENODEV; 865 info = match->data; 866 867 controller = devm_kzalloc(&pdev->dev, 868 struct_size(controller, chips, info->nce), 869 GFP_KERNEL); 870 if (!controller) 871 return -ENOMEM; 872 controller->info = info; 873 controller->dev = dev; 874 875 mutex_init(&controller->mutex); 876 platform_set_drvdata(pdev, controller); 877 878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 879 controller->regs = devm_ioremap_resource(dev, res); 880 if (IS_ERR(controller->regs)) 881 return PTR_ERR(controller->regs); 882 883 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 884 controller->ahb_base = devm_ioremap_resource(dev, res); 885 if (IS_ERR(controller->ahb_base)) 886 return PTR_ERR(controller->ahb_base); 887 888 controller->ahb_window_size = resource_size(res); 889 890 ret = aspeed_smc_setup_flash(controller, np, res); 891 if (ret) 892 dev_err(dev, "Aspeed SMC probe failed %d\n", ret); 893 894 return ret; 895} 896 897static struct platform_driver aspeed_smc_driver = { 898 .probe = aspeed_smc_probe, 899 .remove = aspeed_smc_remove, 900 .driver = { 901 .name = DEVICE_NAME, 902 .of_match_table = aspeed_smc_matches, 903 } 904}; 905 906module_platform_driver(aspeed_smc_driver); 907 908MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver"); 909MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>"); 910MODULE_LICENSE("GPL v2"); 911