1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others 4 * 5 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. 6 * Jason ported to M54418TWR and MVFA5 (VF610). 7 * Authors: Stefan Agner <stefan.agner@toradex.com> 8 * Bill Pringlemeir <bpringlemeir@nbsps.com> 9 * Shaohui Xie <b21989@freescale.com> 10 * Jason Jin <Jason.jin@freescale.com> 11 * 12 * Based on original driver mpc5121_nfc.c. 13 * 14 * Limitations: 15 * - Untested on MPC5125 and M54418. 16 * - DMA and pipelining not used. 17 * - 2K pages or less. 18 * - HW ECC: Only 2K page with 64+ OOB. 19 * - HW ECC: Only 24 and 32-bit error correction implemented. 20 */ 21 22#include <linux/module.h> 23#include <linux/bitops.h> 24#include <linux/clk.h> 25#include <linux/delay.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/io.h> 29#include <linux/mtd/mtd.h> 30#include <linux/mtd/rawnand.h> 31#include <linux/mtd/partitions.h> 32#include <linux/of_device.h> 33#include <linux/platform_device.h> 34#include <linux/slab.h> 35#include <linux/swab.h> 36 37#define DRV_NAME "vf610_nfc" 38 39/* Register Offsets */ 40#define NFC_FLASH_CMD1 0x3F00 41#define NFC_FLASH_CMD2 0x3F04 42#define NFC_COL_ADDR 0x3F08 43#define NFC_ROW_ADDR 0x3F0c 44#define NFC_ROW_ADDR_INC 0x3F14 45#define NFC_FLASH_STATUS1 0x3F18 46#define NFC_FLASH_STATUS2 0x3F1c 47#define NFC_CACHE_SWAP 0x3F28 48#define NFC_SECTOR_SIZE 0x3F2c 49#define NFC_FLASH_CONFIG 0x3F30 50#define NFC_IRQ_STATUS 0x3F38 51 52/* Addresses for NFC MAIN RAM BUFFER areas */ 53#define NFC_MAIN_AREA(n) ((n) * 0x1000) 54 55#define PAGE_2K 0x0800 56#define OOB_64 0x0040 57#define OOB_MAX 0x0100 58 59/* NFC_CMD2[CODE] controller cycle bit masks */ 60#define COMMAND_CMD_BYTE1 BIT(14) 61#define COMMAND_CAR_BYTE1 BIT(13) 62#define COMMAND_CAR_BYTE2 BIT(12) 63#define COMMAND_RAR_BYTE1 BIT(11) 64#define COMMAND_RAR_BYTE2 BIT(10) 65#define COMMAND_RAR_BYTE3 BIT(9) 66#define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1) 67#define COMMAND_WRITE_DATA BIT(8) 68#define COMMAND_CMD_BYTE2 BIT(7) 69#define COMMAND_RB_HANDSHAKE BIT(6) 70#define COMMAND_READ_DATA BIT(5) 71#define COMMAND_CMD_BYTE3 BIT(4) 72#define COMMAND_READ_STATUS BIT(3) 73#define COMMAND_READ_ID BIT(2) 74 75/* NFC ECC mode define */ 76#define ECC_BYPASS 0 77#define ECC_45_BYTE 6 78#define ECC_60_BYTE 7 79 80/*** Register Mask and bit definitions */ 81 82/* NFC_FLASH_CMD1 Field */ 83#define CMD_BYTE2_MASK 0xFF000000 84#define CMD_BYTE2_SHIFT 24 85 86/* NFC_FLASH_CM2 Field */ 87#define CMD_BYTE1_MASK 0xFF000000 88#define CMD_BYTE1_SHIFT 24 89#define CMD_CODE_MASK 0x00FFFF00 90#define CMD_CODE_SHIFT 8 91#define BUFNO_MASK 0x00000006 92#define BUFNO_SHIFT 1 93#define START_BIT BIT(0) 94 95/* NFC_COL_ADDR Field */ 96#define COL_ADDR_MASK 0x0000FFFF 97#define COL_ADDR_SHIFT 0 98#define COL_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos))) 99 100/* NFC_ROW_ADDR Field */ 101#define ROW_ADDR_MASK 0x00FFFFFF 102#define ROW_ADDR_SHIFT 0 103#define ROW_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos))) 104 105#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 106#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 107#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 108#define ROW_ADDR_CHIP_SEL_SHIFT 24 109 110/* NFC_FLASH_STATUS2 Field */ 111#define STATUS_BYTE1_MASK 0x000000FF 112 113/* NFC_FLASH_CONFIG Field */ 114#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 115#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 116#define CONFIG_ECC_SRAM_REQ_BIT BIT(21) 117#define CONFIG_DMA_REQ_BIT BIT(20) 118#define CONFIG_ECC_MODE_MASK 0x000E0000 119#define CONFIG_ECC_MODE_SHIFT 17 120#define CONFIG_FAST_FLASH_BIT BIT(16) 121#define CONFIG_16BIT BIT(7) 122#define CONFIG_BOOT_MODE_BIT BIT(6) 123#define CONFIG_ADDR_AUTO_INCR_BIT BIT(5) 124#define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4) 125#define CONFIG_PAGE_CNT_MASK 0xF 126#define CONFIG_PAGE_CNT_SHIFT 0 127 128/* NFC_IRQ_STATUS Field */ 129#define IDLE_IRQ_BIT BIT(29) 130#define IDLE_EN_BIT BIT(20) 131#define CMD_DONE_CLEAR_BIT BIT(18) 132#define IDLE_CLEAR_BIT BIT(17) 133 134/* 135 * ECC status - seems to consume 8 bytes (double word). The documented 136 * status byte is located in the lowest byte of the second word (which is 137 * the 4th or 7th byte depending on endianness). 138 * Calculate an offset to store the ECC status at the end of the buffer. 139 */ 140#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8) 141 142#define ECC_STATUS 0x4 143#define ECC_STATUS_MASK 0x80 144#define ECC_STATUS_ERR_COUNT 0x3F 145 146enum vf610_nfc_variant { 147 NFC_VFC610 = 1, 148}; 149 150struct vf610_nfc { 151 struct nand_controller base; 152 struct nand_chip chip; 153 struct device *dev; 154 void __iomem *regs; 155 struct completion cmd_done; 156 /* Status and ID are in alternate locations. */ 157 enum vf610_nfc_variant variant; 158 struct clk *clk; 159 /* 160 * Indicate that user data is accessed (full page/oob). This is 161 * useful to indicate the driver whether to swap byte endianness. 162 * See comments in vf610_nfc_rd_from_sram/vf610_nfc_wr_to_sram. 163 */ 164 bool data_access; 165 u32 ecc_mode; 166}; 167 168static inline struct vf610_nfc *chip_to_nfc(struct nand_chip *chip) 169{ 170 return container_of(chip, struct vf610_nfc, chip); 171} 172 173static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) 174{ 175 return readl(nfc->regs + reg); 176} 177 178static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) 179{ 180 writel(val, nfc->regs + reg); 181} 182 183static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) 184{ 185 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); 186} 187 188static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) 189{ 190 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); 191} 192 193static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, 194 u32 mask, u32 shift, u32 val) 195{ 196 vf610_nfc_write(nfc, reg, 197 (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); 198} 199 200static inline bool vf610_nfc_kernel_is_little_endian(void) 201{ 202#ifdef __LITTLE_ENDIAN 203 return true; 204#else 205 return false; 206#endif 207} 208 209/** 210 * Read accessor for internal SRAM buffer 211 * @dst: destination address in regular memory 212 * @src: source address in SRAM buffer 213 * @len: bytes to copy 214 * @fix_endian: Fix endianness if required 215 * 216 * Use this accessor for the internal SRAM buffers. On the ARM 217 * Freescale Vybrid SoC it's known that the driver can treat 218 * the SRAM buffer as if it's memory. Other platform might need 219 * to treat the buffers differently. 220 * 221 * The controller stores bytes from the NAND chip internally in big 222 * endianness. On little endian platforms such as Vybrid this leads 223 * to reversed byte order. 224 * For performance reason (and earlier probably due to unawareness) 225 * the driver avoids correcting endianness where it has control over 226 * write and read side (e.g. page wise data access). 227 */ 228static inline void vf610_nfc_rd_from_sram(void *dst, const void __iomem *src, 229 size_t len, bool fix_endian) 230{ 231 if (vf610_nfc_kernel_is_little_endian() && fix_endian) { 232 unsigned int i; 233 234 for (i = 0; i < len; i += 4) { 235 u32 val = swab32(__raw_readl(src + i)); 236 237 memcpy(dst + i, &val, min(sizeof(val), len - i)); 238 } 239 } else { 240 memcpy_fromio(dst, src, len); 241 } 242} 243 244/** 245 * Write accessor for internal SRAM buffer 246 * @dst: destination address in SRAM buffer 247 * @src: source address in regular memory 248 * @len: bytes to copy 249 * @fix_endian: Fix endianness if required 250 * 251 * Use this accessor for the internal SRAM buffers. On the ARM 252 * Freescale Vybrid SoC it's known that the driver can treat 253 * the SRAM buffer as if it's memory. Other platform might need 254 * to treat the buffers differently. 255 * 256 * The controller stores bytes from the NAND chip internally in big 257 * endianness. On little endian platforms such as Vybrid this leads 258 * to reversed byte order. 259 * For performance reason (and earlier probably due to unawareness) 260 * the driver avoids correcting endianness where it has control over 261 * write and read side (e.g. page wise data access). 262 */ 263static inline void vf610_nfc_wr_to_sram(void __iomem *dst, const void *src, 264 size_t len, bool fix_endian) 265{ 266 if (vf610_nfc_kernel_is_little_endian() && fix_endian) { 267 unsigned int i; 268 269 for (i = 0; i < len; i += 4) { 270 u32 val; 271 272 memcpy(&val, src + i, min(sizeof(val), len - i)); 273 __raw_writel(swab32(val), dst + i); 274 } 275 } else { 276 memcpy_toio(dst, src, len); 277 } 278} 279 280/* Clear flags for upcoming command */ 281static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) 282{ 283 u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS); 284 285 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; 286 vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); 287} 288 289static void vf610_nfc_done(struct vf610_nfc *nfc) 290{ 291 unsigned long timeout = msecs_to_jiffies(100); 292 293 /* 294 * Barrier is needed after this write. This write need 295 * to be done before reading the next register the first 296 * time. 297 * vf610_nfc_set implicates such a barrier by using writel 298 * to write to the register. 299 */ 300 vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); 301 vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT); 302 303 if (!wait_for_completion_timeout(&nfc->cmd_done, timeout)) 304 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n"); 305 306 vf610_nfc_clear_status(nfc); 307} 308 309static irqreturn_t vf610_nfc_irq(int irq, void *data) 310{ 311 struct vf610_nfc *nfc = data; 312 313 vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); 314 complete(&nfc->cmd_done); 315 316 return IRQ_HANDLED; 317} 318 319static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode) 320{ 321 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, 322 CONFIG_ECC_MODE_MASK, 323 CONFIG_ECC_MODE_SHIFT, ecc_mode); 324} 325 326static inline void vf610_nfc_run(struct vf610_nfc *nfc, u32 col, u32 row, 327 u32 cmd1, u32 cmd2, u32 trfr_sz) 328{ 329 vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK, 330 COL_ADDR_SHIFT, col); 331 332 vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, 333 ROW_ADDR_SHIFT, row); 334 335 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, trfr_sz); 336 vf610_nfc_write(nfc, NFC_FLASH_CMD1, cmd1); 337 vf610_nfc_write(nfc, NFC_FLASH_CMD2, cmd2); 338 339 dev_dbg(nfc->dev, 340 "col 0x%04x, row 0x%08x, cmd1 0x%08x, cmd2 0x%08x, len %d\n", 341 col, row, cmd1, cmd2, trfr_sz); 342 343 vf610_nfc_done(nfc); 344} 345 346static inline const struct nand_op_instr * 347vf610_get_next_instr(const struct nand_subop *subop, int *op_id) 348{ 349 if (*op_id + 1 >= subop->ninstrs) 350 return NULL; 351 352 (*op_id)++; 353 354 return &subop->instrs[*op_id]; 355} 356 357static int vf610_nfc_cmd(struct nand_chip *chip, 358 const struct nand_subop *subop) 359{ 360 const struct nand_op_instr *instr; 361 struct vf610_nfc *nfc = chip_to_nfc(chip); 362 int op_id = -1, trfr_sz = 0, offset = 0; 363 u32 col = 0, row = 0, cmd1 = 0, cmd2 = 0, code = 0; 364 bool force8bit = false; 365 366 /* 367 * Some ops are optional, but the hardware requires the operations 368 * to be in this exact order. 369 * The op parser enforces the order and makes sure that there isn't 370 * a read and write element in a single operation. 371 */ 372 instr = vf610_get_next_instr(subop, &op_id); 373 if (!instr) 374 return -EINVAL; 375 376 if (instr && instr->type == NAND_OP_CMD_INSTR) { 377 cmd2 |= instr->ctx.cmd.opcode << CMD_BYTE1_SHIFT; 378 code |= COMMAND_CMD_BYTE1; 379 380 instr = vf610_get_next_instr(subop, &op_id); 381 } 382 383 if (instr && instr->type == NAND_OP_ADDR_INSTR) { 384 int naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 385 int i = nand_subop_get_addr_start_off(subop, op_id); 386 387 for (; i < naddrs; i++) { 388 u8 val = instr->ctx.addr.addrs[i]; 389 390 if (i < 2) 391 col |= COL_ADDR(i, val); 392 else 393 row |= ROW_ADDR(i - 2, val); 394 } 395 code |= COMMAND_NADDR_BYTES(naddrs); 396 397 instr = vf610_get_next_instr(subop, &op_id); 398 } 399 400 if (instr && instr->type == NAND_OP_DATA_OUT_INSTR) { 401 trfr_sz = nand_subop_get_data_len(subop, op_id); 402 offset = nand_subop_get_data_start_off(subop, op_id); 403 force8bit = instr->ctx.data.force_8bit; 404 405 /* 406 * Don't fix endianness on page access for historical reasons. 407 * See comment in vf610_nfc_wr_to_sram 408 */ 409 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0) + offset, 410 instr->ctx.data.buf.out + offset, 411 trfr_sz, !nfc->data_access); 412 code |= COMMAND_WRITE_DATA; 413 414 instr = vf610_get_next_instr(subop, &op_id); 415 } 416 417 if (instr && instr->type == NAND_OP_CMD_INSTR) { 418 cmd1 |= instr->ctx.cmd.opcode << CMD_BYTE2_SHIFT; 419 code |= COMMAND_CMD_BYTE2; 420 421 instr = vf610_get_next_instr(subop, &op_id); 422 } 423 424 if (instr && instr->type == NAND_OP_WAITRDY_INSTR) { 425 code |= COMMAND_RB_HANDSHAKE; 426 427 instr = vf610_get_next_instr(subop, &op_id); 428 } 429 430 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) { 431 trfr_sz = nand_subop_get_data_len(subop, op_id); 432 offset = nand_subop_get_data_start_off(subop, op_id); 433 force8bit = instr->ctx.data.force_8bit; 434 435 code |= COMMAND_READ_DATA; 436 } 437 438 if (force8bit && (chip->options & NAND_BUSWIDTH_16)) 439 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 440 441 cmd2 |= code << CMD_CODE_SHIFT; 442 443 vf610_nfc_run(nfc, col, row, cmd1, cmd2, trfr_sz); 444 445 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) { 446 /* 447 * Don't fix endianness on page access for historical reasons. 448 * See comment in vf610_nfc_rd_from_sram 449 */ 450 vf610_nfc_rd_from_sram(instr->ctx.data.buf.in + offset, 451 nfc->regs + NFC_MAIN_AREA(0) + offset, 452 trfr_sz, !nfc->data_access); 453 } 454 455 if (force8bit && (chip->options & NAND_BUSWIDTH_16)) 456 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 457 458 return 0; 459} 460 461static const struct nand_op_parser vf610_nfc_op_parser = NAND_OP_PARSER( 462 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd, 463 NAND_OP_PARSER_PAT_CMD_ELEM(true), 464 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5), 465 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, PAGE_2K + OOB_MAX), 466 NAND_OP_PARSER_PAT_CMD_ELEM(true), 467 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 468 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd, 469 NAND_OP_PARSER_PAT_CMD_ELEM(true), 470 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5), 471 NAND_OP_PARSER_PAT_CMD_ELEM(true), 472 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 473 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, PAGE_2K + OOB_MAX)), 474 ); 475 476/* 477 * This function supports Vybrid only (MPC5125 would have full RB and four CS) 478 */ 479static void vf610_nfc_select_target(struct nand_chip *chip, unsigned int cs) 480{ 481 struct vf610_nfc *nfc = chip_to_nfc(chip); 482 u32 tmp; 483 484 /* Vybrid only (MPC5125 would have full RB and four CS) */ 485 if (nfc->variant != NFC_VFC610) 486 return; 487 488 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR); 489 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); 490 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; 491 tmp |= BIT(cs) << ROW_ADDR_CHIP_SEL_SHIFT; 492 493 vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp); 494} 495 496static int vf610_nfc_exec_op(struct nand_chip *chip, 497 const struct nand_operation *op, 498 bool check_only) 499{ 500 if (!check_only) 501 vf610_nfc_select_target(chip, op->cs); 502 503 return nand_op_parser_exec_op(chip, &vf610_nfc_op_parser, op, 504 check_only); 505} 506 507static inline int vf610_nfc_correct_data(struct nand_chip *chip, uint8_t *dat, 508 uint8_t *oob, int page) 509{ 510 struct vf610_nfc *nfc = chip_to_nfc(chip); 511 struct mtd_info *mtd = nand_to_mtd(chip); 512 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS; 513 u8 ecc_status; 514 u8 ecc_count; 515 int flips_threshold = nfc->chip.ecc.strength / 2; 516 517 ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff; 518 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT; 519 520 if (!(ecc_status & ECC_STATUS_MASK)) 521 return ecc_count; 522 523 nfc->data_access = true; 524 nand_read_oob_op(&nfc->chip, page, 0, oob, mtd->oobsize); 525 nfc->data_access = false; 526 527 /* 528 * On an erased page, bit count (including OOB) should be zero or 529 * at least less then half of the ECC strength. 530 */ 531 return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob, 532 mtd->oobsize, NULL, 0, 533 flips_threshold); 534} 535 536static void vf610_nfc_fill_row(struct nand_chip *chip, int page, u32 *code, 537 u32 *row) 538{ 539 *row = ROW_ADDR(0, page & 0xff) | ROW_ADDR(1, page >> 8); 540 *code |= COMMAND_RAR_BYTE1 | COMMAND_RAR_BYTE2; 541 542 if (chip->options & NAND_ROW_ADDR_3) { 543 *row |= ROW_ADDR(2, page >> 16); 544 *code |= COMMAND_RAR_BYTE3; 545 } 546} 547 548static int vf610_nfc_read_page(struct nand_chip *chip, uint8_t *buf, 549 int oob_required, int page) 550{ 551 struct vf610_nfc *nfc = chip_to_nfc(chip); 552 struct mtd_info *mtd = nand_to_mtd(chip); 553 int trfr_sz = mtd->writesize + mtd->oobsize; 554 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0; 555 int stat; 556 557 vf610_nfc_select_target(chip, chip->cur_cs); 558 559 cmd2 |= NAND_CMD_READ0 << CMD_BYTE1_SHIFT; 560 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2; 561 562 vf610_nfc_fill_row(chip, page, &code, &row); 563 564 cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT; 565 code |= COMMAND_CMD_BYTE2 | COMMAND_RB_HANDSHAKE | COMMAND_READ_DATA; 566 567 cmd2 |= code << CMD_CODE_SHIFT; 568 569 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); 570 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz); 571 vf610_nfc_ecc_mode(nfc, ECC_BYPASS); 572 573 /* 574 * Don't fix endianness on page access for historical reasons. 575 * See comment in vf610_nfc_rd_from_sram 576 */ 577 vf610_nfc_rd_from_sram(buf, nfc->regs + NFC_MAIN_AREA(0), 578 mtd->writesize, false); 579 if (oob_required) 580 vf610_nfc_rd_from_sram(chip->oob_poi, 581 nfc->regs + NFC_MAIN_AREA(0) + 582 mtd->writesize, 583 mtd->oobsize, false); 584 585 stat = vf610_nfc_correct_data(chip, buf, chip->oob_poi, page); 586 587 if (stat < 0) { 588 mtd->ecc_stats.failed++; 589 return 0; 590 } else { 591 mtd->ecc_stats.corrected += stat; 592 return stat; 593 } 594} 595 596static int vf610_nfc_write_page(struct nand_chip *chip, const uint8_t *buf, 597 int oob_required, int page) 598{ 599 struct vf610_nfc *nfc = chip_to_nfc(chip); 600 struct mtd_info *mtd = nand_to_mtd(chip); 601 int trfr_sz = mtd->writesize + mtd->oobsize; 602 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0; 603 u8 status; 604 int ret; 605 606 vf610_nfc_select_target(chip, chip->cur_cs); 607 608 cmd2 |= NAND_CMD_SEQIN << CMD_BYTE1_SHIFT; 609 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2; 610 611 vf610_nfc_fill_row(chip, page, &code, &row); 612 613 cmd1 |= NAND_CMD_PAGEPROG << CMD_BYTE2_SHIFT; 614 code |= COMMAND_CMD_BYTE2 | COMMAND_WRITE_DATA; 615 616 /* 617 * Don't fix endianness on page access for historical reasons. 618 * See comment in vf610_nfc_wr_to_sram 619 */ 620 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0), buf, 621 mtd->writesize, false); 622 623 code |= COMMAND_RB_HANDSHAKE; 624 cmd2 |= code << CMD_CODE_SHIFT; 625 626 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); 627 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz); 628 vf610_nfc_ecc_mode(nfc, ECC_BYPASS); 629 630 ret = nand_status_op(chip, &status); 631 if (ret) 632 return ret; 633 634 if (status & NAND_STATUS_FAIL) 635 return -EIO; 636 637 return 0; 638} 639 640static int vf610_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, 641 int oob_required, int page) 642{ 643 struct vf610_nfc *nfc = chip_to_nfc(chip); 644 int ret; 645 646 nfc->data_access = true; 647 ret = nand_read_page_raw(chip, buf, oob_required, page); 648 nfc->data_access = false; 649 650 return ret; 651} 652 653static int vf610_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf, 654 int oob_required, int page) 655{ 656 struct vf610_nfc *nfc = chip_to_nfc(chip); 657 struct mtd_info *mtd = nand_to_mtd(chip); 658 int ret; 659 660 nfc->data_access = true; 661 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 662 if (!ret && oob_required) 663 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, 664 false); 665 nfc->data_access = false; 666 667 if (ret) 668 return ret; 669 670 return nand_prog_page_end_op(chip); 671} 672 673static int vf610_nfc_read_oob(struct nand_chip *chip, int page) 674{ 675 struct vf610_nfc *nfc = chip_to_nfc(chip); 676 int ret; 677 678 nfc->data_access = true; 679 ret = nand_read_oob_std(chip, page); 680 nfc->data_access = false; 681 682 return ret; 683} 684 685static int vf610_nfc_write_oob(struct nand_chip *chip, int page) 686{ 687 struct mtd_info *mtd = nand_to_mtd(chip); 688 struct vf610_nfc *nfc = chip_to_nfc(chip); 689 int ret; 690 691 nfc->data_access = true; 692 ret = nand_prog_page_begin_op(chip, page, mtd->writesize, 693 chip->oob_poi, mtd->oobsize); 694 nfc->data_access = false; 695 696 if (ret) 697 return ret; 698 699 return nand_prog_page_end_op(chip); 700} 701 702static const struct of_device_id vf610_nfc_dt_ids[] = { 703 { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 }, 704 { /* sentinel */ } 705}; 706MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids); 707 708static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc) 709{ 710 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 711 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); 712 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); 713 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); 714 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); 715 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); 716 vf610_nfc_ecc_mode(nfc, ECC_BYPASS); 717 718 /* Disable virtual pages, only one elementary transfer unit */ 719 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, 720 CONFIG_PAGE_CNT_SHIFT, 1); 721} 722 723static void vf610_nfc_init_controller(struct vf610_nfc *nfc) 724{ 725 if (nfc->chip.options & NAND_BUSWIDTH_16) 726 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 727 else 728 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 729 730 if (nfc->chip.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 731 /* Set ECC status offset in SRAM */ 732 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, 733 CONFIG_ECC_SRAM_ADDR_MASK, 734 CONFIG_ECC_SRAM_ADDR_SHIFT, 735 ECC_SRAM_ADDR >> 3); 736 737 /* Enable ECC status in SRAM */ 738 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); 739 } 740} 741 742static int vf610_nfc_attach_chip(struct nand_chip *chip) 743{ 744 struct mtd_info *mtd = nand_to_mtd(chip); 745 struct vf610_nfc *nfc = chip_to_nfc(chip); 746 747 vf610_nfc_init_controller(nfc); 748 749 /* Bad block options. */ 750 if (chip->bbt_options & NAND_BBT_USE_FLASH) 751 chip->bbt_options |= NAND_BBT_NO_OOB; 752 753 /* Single buffer only, max 256 OOB minus ECC status */ 754 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) { 755 dev_err(nfc->dev, "Unsupported flash page size\n"); 756 return -ENXIO; 757 } 758 759 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 760 return 0; 761 762 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { 763 dev_err(nfc->dev, "Unsupported flash with hwecc\n"); 764 return -ENXIO; 765 } 766 767 if (chip->ecc.size != mtd->writesize) { 768 dev_err(nfc->dev, "Step size needs to be page size\n"); 769 return -ENXIO; 770 } 771 772 /* Only 64 byte ECC layouts known */ 773 if (mtd->oobsize > 64) 774 mtd->oobsize = 64; 775 776 /* Use default large page ECC layout defined in NAND core */ 777 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 778 if (chip->ecc.strength == 32) { 779 nfc->ecc_mode = ECC_60_BYTE; 780 chip->ecc.bytes = 60; 781 } else if (chip->ecc.strength == 24) { 782 nfc->ecc_mode = ECC_45_BYTE; 783 chip->ecc.bytes = 45; 784 } else { 785 dev_err(nfc->dev, "Unsupported ECC strength\n"); 786 return -ENXIO; 787 } 788 789 chip->ecc.read_page = vf610_nfc_read_page; 790 chip->ecc.write_page = vf610_nfc_write_page; 791 chip->ecc.read_page_raw = vf610_nfc_read_page_raw; 792 chip->ecc.write_page_raw = vf610_nfc_write_page_raw; 793 chip->ecc.read_oob = vf610_nfc_read_oob; 794 chip->ecc.write_oob = vf610_nfc_write_oob; 795 796 chip->ecc.size = PAGE_2K; 797 798 return 0; 799} 800 801static const struct nand_controller_ops vf610_nfc_controller_ops = { 802 .attach_chip = vf610_nfc_attach_chip, 803 .exec_op = vf610_nfc_exec_op, 804 805}; 806 807static int vf610_nfc_probe(struct platform_device *pdev) 808{ 809 struct vf610_nfc *nfc; 810 struct resource *res; 811 struct mtd_info *mtd; 812 struct nand_chip *chip; 813 struct device_node *child; 814 const struct of_device_id *of_id; 815 int err; 816 int irq; 817 818 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); 819 if (!nfc) 820 return -ENOMEM; 821 822 nfc->dev = &pdev->dev; 823 chip = &nfc->chip; 824 mtd = nand_to_mtd(chip); 825 826 mtd->owner = THIS_MODULE; 827 mtd->dev.parent = nfc->dev; 828 mtd->name = DRV_NAME; 829 830 irq = platform_get_irq(pdev, 0); 831 if (irq <= 0) 832 return -EINVAL; 833 834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 835 nfc->regs = devm_ioremap_resource(nfc->dev, res); 836 if (IS_ERR(nfc->regs)) 837 return PTR_ERR(nfc->regs); 838 839 nfc->clk = devm_clk_get(&pdev->dev, NULL); 840 if (IS_ERR(nfc->clk)) 841 return PTR_ERR(nfc->clk); 842 843 err = clk_prepare_enable(nfc->clk); 844 if (err) { 845 dev_err(nfc->dev, "Unable to enable clock!\n"); 846 return err; 847 } 848 849 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev); 850 if (!of_id) { 851 err = -ENODEV; 852 goto err_disable_clk; 853 } 854 855 nfc->variant = (enum vf610_nfc_variant)of_id->data; 856 857 for_each_available_child_of_node(nfc->dev->of_node, child) { 858 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) { 859 860 if (nand_get_flash_node(chip)) { 861 dev_err(nfc->dev, 862 "Only one NAND chip supported!\n"); 863 err = -EINVAL; 864 of_node_put(child); 865 goto err_disable_clk; 866 } 867 868 nand_set_flash_node(chip, child); 869 } 870 } 871 872 if (!nand_get_flash_node(chip)) { 873 dev_err(nfc->dev, "NAND chip sub-node missing!\n"); 874 err = -ENODEV; 875 goto err_disable_clk; 876 } 877 878 chip->options |= NAND_NO_SUBPAGE_WRITE; 879 880 init_completion(&nfc->cmd_done); 881 882 err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, nfc); 883 if (err) { 884 dev_err(nfc->dev, "Error requesting IRQ!\n"); 885 goto err_disable_clk; 886 } 887 888 vf610_nfc_preinit_controller(nfc); 889 890 nand_controller_init(&nfc->base); 891 nfc->base.ops = &vf610_nfc_controller_ops; 892 chip->controller = &nfc->base; 893 894 /* Scan the NAND chip */ 895 err = nand_scan(chip, 1); 896 if (err) 897 goto err_disable_clk; 898 899 platform_set_drvdata(pdev, nfc); 900 901 /* Register device in MTD */ 902 err = mtd_device_register(mtd, NULL, 0); 903 if (err) 904 goto err_cleanup_nand; 905 return 0; 906 907err_cleanup_nand: 908 nand_cleanup(chip); 909err_disable_clk: 910 clk_disable_unprepare(nfc->clk); 911 return err; 912} 913 914static int vf610_nfc_remove(struct platform_device *pdev) 915{ 916 struct vf610_nfc *nfc = platform_get_drvdata(pdev); 917 struct nand_chip *chip = &nfc->chip; 918 int ret; 919 920 ret = mtd_device_unregister(nand_to_mtd(chip)); 921 WARN_ON(ret); 922 nand_cleanup(chip); 923 clk_disable_unprepare(nfc->clk); 924 return 0; 925} 926 927#ifdef CONFIG_PM_SLEEP 928static int vf610_nfc_suspend(struct device *dev) 929{ 930 struct vf610_nfc *nfc = dev_get_drvdata(dev); 931 932 clk_disable_unprepare(nfc->clk); 933 return 0; 934} 935 936static int vf610_nfc_resume(struct device *dev) 937{ 938 struct vf610_nfc *nfc = dev_get_drvdata(dev); 939 int err; 940 941 err = clk_prepare_enable(nfc->clk); 942 if (err) 943 return err; 944 945 vf610_nfc_preinit_controller(nfc); 946 vf610_nfc_init_controller(nfc); 947 return 0; 948} 949#endif 950 951static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume); 952 953static struct platform_driver vf610_nfc_driver = { 954 .driver = { 955 .name = DRV_NAME, 956 .of_match_table = vf610_nfc_dt_ids, 957 .pm = &vf610_nfc_pm_ops, 958 }, 959 .probe = vf610_nfc_probe, 960 .remove = vf610_nfc_remove, 961}; 962 963module_platform_driver(vf610_nfc_driver); 964 965MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); 966MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver"); 967MODULE_LICENSE("GPL"); 968