1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2015 Broadcom Corporation
4 */
5
6#ifndef __BRCMNAND_H__
7#define __BRCMNAND_H__
8
9#include <linux/types.h>
10#include <linux/io.h>
11
12struct platform_device;
13struct dev_pm_ops;
14struct brcmnand_io_ops;
15
16/* Special register offset constant to intercept a non-MMIO access
17 * to the flash cache register space. This is intentionally large
18 * not to overlap with an existing offset.
19 */
20#define BRCMNAND_NON_MMIO_FC_ADDR	0xffffffff
21
22struct brcmnand_soc {
23	bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
24	void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
25	void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
26				 bool is_param);
27	const struct brcmnand_io_ops *ops;
28};
29
30struct brcmnand_io_ops {
31	u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset);
32	void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset);
33};
34
35static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
36						 bool is_param)
37{
38	if (soc && soc->prepare_data_bus)
39		soc->prepare_data_bus(soc, true, is_param);
40}
41
42static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
43						   bool is_param)
44{
45	if (soc && soc->prepare_data_bus)
46		soc->prepare_data_bus(soc, false, is_param);
47}
48
49static inline u32 brcmnand_readl(void __iomem *addr)
50{
51	/*
52	 * MIPS endianness is configured by boot strap, which also reverses all
53	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
54	 * endian I/O).
55	 *
56	 * Other architectures (e.g., ARM) either do not support big endian, or
57	 * else leave I/O in little endian mode.
58	 */
59	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
60		return __raw_readl(addr);
61	else
62		return readl_relaxed(addr);
63}
64
65static inline void brcmnand_writel(u32 val, void __iomem *addr)
66{
67	/* See brcmnand_readl() comments */
68	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
69		__raw_writel(val, addr);
70	else
71		writel_relaxed(val, addr);
72}
73
74static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc)
75{
76	return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
77}
78
79static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset)
80{
81	return soc->ops->read_reg(soc, offset);
82}
83
84static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,
85				      u32 offset)
86{
87	soc->ops->write_reg(soc, val, offset);
88}
89
90int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
91int brcmnand_remove(struct platform_device *pdev);
92
93extern const struct dev_pm_ops brcmnand_pm_ops;
94
95#endif /* __BRCMNAND_H__ */
96