1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright © 2010-2015 Broadcom Corporation 4 */ 5 6#include <linux/clk.h> 7#include <linux/module.h> 8#include <linux/init.h> 9#include <linux/delay.h> 10#include <linux/device.h> 11#include <linux/platform_device.h> 12#include <linux/err.h> 13#include <linux/completion.h> 14#include <linux/interrupt.h> 15#include <linux/spinlock.h> 16#include <linux/dma-mapping.h> 17#include <linux/ioport.h> 18#include <linux/bug.h> 19#include <linux/kernel.h> 20#include <linux/bitops.h> 21#include <linux/mm.h> 22#include <linux/mtd/mtd.h> 23#include <linux/mtd/rawnand.h> 24#include <linux/mtd/partitions.h> 25#include <linux/of.h> 26#include <linux/of_platform.h> 27#include <linux/slab.h> 28#include <linux/static_key.h> 29#include <linux/list.h> 30#include <linux/log2.h> 31 32#include "brcmnand.h" 33 34/* 35 * This flag controls if WP stays on between erase/write commands to mitigate 36 * flash corruption due to power glitches. Values: 37 * 0: NAND_WP is not used or not available 38 * 1: NAND_WP is set by default, cleared for erase/write operations 39 * 2: NAND_WP is always cleared 40 */ 41static int wp_on = 1; 42module_param(wp_on, int, 0444); 43 44/*********************************************************************** 45 * Definitions 46 ***********************************************************************/ 47 48#define DRV_NAME "brcmnand" 49 50#define CMD_NULL 0x00 51#define CMD_PAGE_READ 0x01 52#define CMD_SPARE_AREA_READ 0x02 53#define CMD_STATUS_READ 0x03 54#define CMD_PROGRAM_PAGE 0x04 55#define CMD_PROGRAM_SPARE_AREA 0x05 56#define CMD_COPY_BACK 0x06 57#define CMD_DEVICE_ID_READ 0x07 58#define CMD_BLOCK_ERASE 0x08 59#define CMD_FLASH_RESET 0x09 60#define CMD_BLOCKS_LOCK 0x0a 61#define CMD_BLOCKS_LOCK_DOWN 0x0b 62#define CMD_BLOCKS_UNLOCK 0x0c 63#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d 64#define CMD_PARAMETER_READ 0x0e 65#define CMD_PARAMETER_CHANGE_COL 0x0f 66#define CMD_LOW_LEVEL_OP 0x10 67 68struct brcm_nand_dma_desc { 69 u32 next_desc; 70 u32 next_desc_ext; 71 u32 cmd_irq; 72 u32 dram_addr; 73 u32 dram_addr_ext; 74 u32 tfr_len; 75 u32 total_len; 76 u32 flash_addr; 77 u32 flash_addr_ext; 78 u32 cs; 79 u32 pad2[5]; 80 u32 status_valid; 81} __packed; 82 83/* Bitfields for brcm_nand_dma_desc::status_valid */ 84#define FLASH_DMA_ECC_ERROR (1 << 8) 85#define FLASH_DMA_CORR_ERROR (1 << 9) 86 87/* Bitfields for DMA_MODE */ 88#define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ 89#define FLASH_DMA_MODE_MODE BIT(0) /* link list */ 90#define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \ 91 FLASH_DMA_MODE_MODE) 92 93/* 512B flash cache in the NAND controller HW */ 94#define FC_SHIFT 9U 95#define FC_BYTES 512U 96#define FC_WORDS (FC_BYTES >> 2) 97 98#define BRCMNAND_MIN_PAGESIZE 512 99#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) 100#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) 101 102#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 103#define NAND_POLL_STATUS_TIMEOUT_MS 100 104 105#define EDU_CMD_WRITE 0x00 106#define EDU_CMD_READ 0x01 107#define EDU_STATUS_ACTIVE BIT(0) 108#define EDU_ERR_STATUS_ERRACK BIT(0) 109#define EDU_DONE_MASK GENMASK(1, 0) 110 111#define EDU_CONFIG_MODE_NAND BIT(0) 112#define EDU_CONFIG_SWAP_BYTE BIT(1) 113#ifdef CONFIG_CPU_BIG_ENDIAN 114#define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE 115#else 116#define EDU_CONFIG_SWAP_CFG 0 117#endif 118 119/* edu registers */ 120enum edu_reg { 121 EDU_CONFIG = 0, 122 EDU_DRAM_ADDR, 123 EDU_EXT_ADDR, 124 EDU_LENGTH, 125 EDU_CMD, 126 EDU_STOP, 127 EDU_STATUS, 128 EDU_DONE, 129 EDU_ERR_STATUS, 130}; 131 132static const u16 edu_regs[] = { 133 [EDU_CONFIG] = 0x00, 134 [EDU_DRAM_ADDR] = 0x04, 135 [EDU_EXT_ADDR] = 0x08, 136 [EDU_LENGTH] = 0x0c, 137 [EDU_CMD] = 0x10, 138 [EDU_STOP] = 0x14, 139 [EDU_STATUS] = 0x18, 140 [EDU_DONE] = 0x1c, 141 [EDU_ERR_STATUS] = 0x20, 142}; 143 144/* flash_dma registers */ 145enum flash_dma_reg { 146 FLASH_DMA_REVISION = 0, 147 FLASH_DMA_FIRST_DESC, 148 FLASH_DMA_FIRST_DESC_EXT, 149 FLASH_DMA_CTRL, 150 FLASH_DMA_MODE, 151 FLASH_DMA_STATUS, 152 FLASH_DMA_INTERRUPT_DESC, 153 FLASH_DMA_INTERRUPT_DESC_EXT, 154 FLASH_DMA_ERROR_STATUS, 155 FLASH_DMA_CURRENT_DESC, 156 FLASH_DMA_CURRENT_DESC_EXT, 157}; 158 159/* flash_dma registers v0*/ 160static const u16 flash_dma_regs_v0[] = { 161 [FLASH_DMA_REVISION] = 0x00, 162 [FLASH_DMA_FIRST_DESC] = 0x04, 163 [FLASH_DMA_CTRL] = 0x08, 164 [FLASH_DMA_MODE] = 0x0c, 165 [FLASH_DMA_STATUS] = 0x10, 166 [FLASH_DMA_INTERRUPT_DESC] = 0x14, 167 [FLASH_DMA_ERROR_STATUS] = 0x18, 168 [FLASH_DMA_CURRENT_DESC] = 0x1c, 169}; 170 171/* flash_dma registers v1*/ 172static const u16 flash_dma_regs_v1[] = { 173 [FLASH_DMA_REVISION] = 0x00, 174 [FLASH_DMA_FIRST_DESC] = 0x04, 175 [FLASH_DMA_FIRST_DESC_EXT] = 0x08, 176 [FLASH_DMA_CTRL] = 0x0c, 177 [FLASH_DMA_MODE] = 0x10, 178 [FLASH_DMA_STATUS] = 0x14, 179 [FLASH_DMA_INTERRUPT_DESC] = 0x18, 180 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c, 181 [FLASH_DMA_ERROR_STATUS] = 0x20, 182 [FLASH_DMA_CURRENT_DESC] = 0x24, 183 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28, 184}; 185 186/* flash_dma registers v4 */ 187static const u16 flash_dma_regs_v4[] = { 188 [FLASH_DMA_REVISION] = 0x00, 189 [FLASH_DMA_FIRST_DESC] = 0x08, 190 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c, 191 [FLASH_DMA_CTRL] = 0x10, 192 [FLASH_DMA_MODE] = 0x14, 193 [FLASH_DMA_STATUS] = 0x18, 194 [FLASH_DMA_INTERRUPT_DESC] = 0x20, 195 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24, 196 [FLASH_DMA_ERROR_STATUS] = 0x28, 197 [FLASH_DMA_CURRENT_DESC] = 0x30, 198 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, 199}; 200 201/* Controller feature flags */ 202enum { 203 BRCMNAND_HAS_1K_SECTORS = BIT(0), 204 BRCMNAND_HAS_PREFETCH = BIT(1), 205 BRCMNAND_HAS_CACHE_MODE = BIT(2), 206 BRCMNAND_HAS_WP = BIT(3), 207}; 208 209struct brcmnand_host; 210 211static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key); 212 213struct brcmnand_controller { 214 struct device *dev; 215 struct nand_controller controller; 216 void __iomem *nand_base; 217 void __iomem *nand_fc; /* flash cache */ 218 void __iomem *flash_dma_base; 219 unsigned int irq; 220 unsigned int dma_irq; 221 int nand_version; 222 223 /* Some SoCs provide custom interrupt status register(s) */ 224 struct brcmnand_soc *soc; 225 226 /* Some SoCs have a gateable clock for the controller */ 227 struct clk *clk; 228 229 int cmd_pending; 230 bool dma_pending; 231 bool edu_pending; 232 struct completion done; 233 struct completion dma_done; 234 struct completion edu_done; 235 236 /* List of NAND hosts (one for each chip-select) */ 237 struct list_head host_list; 238 239 /* EDU info, per-transaction */ 240 const u16 *edu_offsets; 241 void __iomem *edu_base; 242 int edu_irq; 243 int edu_count; 244 u64 edu_dram_addr; 245 u32 edu_ext_addr; 246 u32 edu_cmd; 247 u32 edu_config; 248 249 /* flash_dma reg */ 250 const u16 *flash_dma_offsets; 251 struct brcm_nand_dma_desc *dma_desc; 252 dma_addr_t dma_pa; 253 254 int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf, 255 u32 len, u8 dma_cmd); 256 257 /* in-memory cache of the FLASH_CACHE, used only for some commands */ 258 u8 flash_cache[FC_BYTES]; 259 260 /* Controller revision details */ 261 const u16 *reg_offsets; 262 unsigned int reg_spacing; /* between CS1, CS2, ... regs */ 263 const u8 *cs_offsets; /* within each chip-select */ 264 const u8 *cs0_offsets; /* within CS0, if different */ 265 unsigned int max_block_size; 266 const unsigned int *block_sizes; 267 unsigned int max_page_size; 268 const unsigned int *page_sizes; 269 unsigned int page_size_shift; 270 unsigned int max_oob; 271 u32 ecc_level_shift; 272 u32 features; 273 274 /* for low-power standby/resume only */ 275 u32 nand_cs_nand_select; 276 u32 nand_cs_nand_xor; 277 u32 corr_stat_threshold; 278 u32 flash_dma_mode; 279 u32 flash_edu_mode; 280 bool pio_poll_mode; 281}; 282 283struct brcmnand_cfg { 284 u64 device_size; 285 unsigned int block_size; 286 unsigned int page_size; 287 unsigned int spare_area_size; 288 unsigned int device_width; 289 unsigned int col_adr_bytes; 290 unsigned int blk_adr_bytes; 291 unsigned int ful_adr_bytes; 292 unsigned int sector_size_1k; 293 unsigned int ecc_level; 294 /* use for low-power standby/resume only */ 295 u32 acc_control; 296 u32 config; 297 u32 config_ext; 298 u32 timing_1; 299 u32 timing_2; 300}; 301 302struct brcmnand_host { 303 struct list_head node; 304 305 struct nand_chip chip; 306 struct platform_device *pdev; 307 int cs; 308 309 unsigned int last_cmd; 310 unsigned int last_byte; 311 u64 last_addr; 312 struct brcmnand_cfg hwcfg; 313 struct brcmnand_controller *ctrl; 314}; 315 316enum brcmnand_reg { 317 BRCMNAND_CMD_START = 0, 318 BRCMNAND_CMD_EXT_ADDRESS, 319 BRCMNAND_CMD_ADDRESS, 320 BRCMNAND_INTFC_STATUS, 321 BRCMNAND_CS_SELECT, 322 BRCMNAND_CS_XOR, 323 BRCMNAND_LL_OP, 324 BRCMNAND_CS0_BASE, 325 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ 326 BRCMNAND_CORR_THRESHOLD, 327 BRCMNAND_CORR_THRESHOLD_EXT, 328 BRCMNAND_UNCORR_COUNT, 329 BRCMNAND_CORR_COUNT, 330 BRCMNAND_CORR_EXT_ADDR, 331 BRCMNAND_CORR_ADDR, 332 BRCMNAND_UNCORR_EXT_ADDR, 333 BRCMNAND_UNCORR_ADDR, 334 BRCMNAND_SEMAPHORE, 335 BRCMNAND_ID, 336 BRCMNAND_ID_EXT, 337 BRCMNAND_LL_RDATA, 338 BRCMNAND_OOB_READ_BASE, 339 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ 340 BRCMNAND_OOB_WRITE_BASE, 341 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ 342 BRCMNAND_FC_BASE, 343}; 344 345/* BRCMNAND v2.1-v2.2 */ 346static const u16 brcmnand_regs_v21[] = { 347 [BRCMNAND_CMD_START] = 0x04, 348 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 349 [BRCMNAND_CMD_ADDRESS] = 0x0c, 350 [BRCMNAND_INTFC_STATUS] = 0x5c, 351 [BRCMNAND_CS_SELECT] = 0x14, 352 [BRCMNAND_CS_XOR] = 0x18, 353 [BRCMNAND_LL_OP] = 0, 354 [BRCMNAND_CS0_BASE] = 0x40, 355 [BRCMNAND_CS1_BASE] = 0, 356 [BRCMNAND_CORR_THRESHOLD] = 0, 357 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 358 [BRCMNAND_UNCORR_COUNT] = 0, 359 [BRCMNAND_CORR_COUNT] = 0, 360 [BRCMNAND_CORR_EXT_ADDR] = 0x60, 361 [BRCMNAND_CORR_ADDR] = 0x64, 362 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68, 363 [BRCMNAND_UNCORR_ADDR] = 0x6c, 364 [BRCMNAND_SEMAPHORE] = 0x50, 365 [BRCMNAND_ID] = 0x54, 366 [BRCMNAND_ID_EXT] = 0, 367 [BRCMNAND_LL_RDATA] = 0, 368 [BRCMNAND_OOB_READ_BASE] = 0x20, 369 [BRCMNAND_OOB_READ_10_BASE] = 0, 370 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 371 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 372 [BRCMNAND_FC_BASE] = 0x200, 373}; 374 375/* BRCMNAND v3.3-v4.0 */ 376static const u16 brcmnand_regs_v33[] = { 377 [BRCMNAND_CMD_START] = 0x04, 378 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 379 [BRCMNAND_CMD_ADDRESS] = 0x0c, 380 [BRCMNAND_INTFC_STATUS] = 0x6c, 381 [BRCMNAND_CS_SELECT] = 0x14, 382 [BRCMNAND_CS_XOR] = 0x18, 383 [BRCMNAND_LL_OP] = 0x178, 384 [BRCMNAND_CS0_BASE] = 0x40, 385 [BRCMNAND_CS1_BASE] = 0xd0, 386 [BRCMNAND_CORR_THRESHOLD] = 0x84, 387 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 388 [BRCMNAND_UNCORR_COUNT] = 0, 389 [BRCMNAND_CORR_COUNT] = 0, 390 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 391 [BRCMNAND_CORR_ADDR] = 0x74, 392 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 393 [BRCMNAND_UNCORR_ADDR] = 0x7c, 394 [BRCMNAND_SEMAPHORE] = 0x58, 395 [BRCMNAND_ID] = 0x60, 396 [BRCMNAND_ID_EXT] = 0x64, 397 [BRCMNAND_LL_RDATA] = 0x17c, 398 [BRCMNAND_OOB_READ_BASE] = 0x20, 399 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 400 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 401 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 402 [BRCMNAND_FC_BASE] = 0x200, 403}; 404 405/* BRCMNAND v5.0 */ 406static const u16 brcmnand_regs_v50[] = { 407 [BRCMNAND_CMD_START] = 0x04, 408 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 409 [BRCMNAND_CMD_ADDRESS] = 0x0c, 410 [BRCMNAND_INTFC_STATUS] = 0x6c, 411 [BRCMNAND_CS_SELECT] = 0x14, 412 [BRCMNAND_CS_XOR] = 0x18, 413 [BRCMNAND_LL_OP] = 0x178, 414 [BRCMNAND_CS0_BASE] = 0x40, 415 [BRCMNAND_CS1_BASE] = 0xd0, 416 [BRCMNAND_CORR_THRESHOLD] = 0x84, 417 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 418 [BRCMNAND_UNCORR_COUNT] = 0, 419 [BRCMNAND_CORR_COUNT] = 0, 420 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 421 [BRCMNAND_CORR_ADDR] = 0x74, 422 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 423 [BRCMNAND_UNCORR_ADDR] = 0x7c, 424 [BRCMNAND_SEMAPHORE] = 0x58, 425 [BRCMNAND_ID] = 0x60, 426 [BRCMNAND_ID_EXT] = 0x64, 427 [BRCMNAND_LL_RDATA] = 0x17c, 428 [BRCMNAND_OOB_READ_BASE] = 0x20, 429 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 430 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 431 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, 432 [BRCMNAND_FC_BASE] = 0x200, 433}; 434 435/* BRCMNAND v6.0 - v7.1 */ 436static const u16 brcmnand_regs_v60[] = { 437 [BRCMNAND_CMD_START] = 0x04, 438 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 439 [BRCMNAND_CMD_ADDRESS] = 0x0c, 440 [BRCMNAND_INTFC_STATUS] = 0x14, 441 [BRCMNAND_CS_SELECT] = 0x18, 442 [BRCMNAND_CS_XOR] = 0x1c, 443 [BRCMNAND_LL_OP] = 0x20, 444 [BRCMNAND_CS0_BASE] = 0x50, 445 [BRCMNAND_CS1_BASE] = 0, 446 [BRCMNAND_CORR_THRESHOLD] = 0xc0, 447 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, 448 [BRCMNAND_UNCORR_COUNT] = 0xfc, 449 [BRCMNAND_CORR_COUNT] = 0x100, 450 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 451 [BRCMNAND_CORR_ADDR] = 0x110, 452 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 453 [BRCMNAND_UNCORR_ADDR] = 0x118, 454 [BRCMNAND_SEMAPHORE] = 0x150, 455 [BRCMNAND_ID] = 0x194, 456 [BRCMNAND_ID_EXT] = 0x198, 457 [BRCMNAND_LL_RDATA] = 0x19c, 458 [BRCMNAND_OOB_READ_BASE] = 0x200, 459 [BRCMNAND_OOB_READ_10_BASE] = 0, 460 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 461 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 462 [BRCMNAND_FC_BASE] = 0x400, 463}; 464 465/* BRCMNAND v7.1 */ 466static const u16 brcmnand_regs_v71[] = { 467 [BRCMNAND_CMD_START] = 0x04, 468 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 469 [BRCMNAND_CMD_ADDRESS] = 0x0c, 470 [BRCMNAND_INTFC_STATUS] = 0x14, 471 [BRCMNAND_CS_SELECT] = 0x18, 472 [BRCMNAND_CS_XOR] = 0x1c, 473 [BRCMNAND_LL_OP] = 0x20, 474 [BRCMNAND_CS0_BASE] = 0x50, 475 [BRCMNAND_CS1_BASE] = 0, 476 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 477 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 478 [BRCMNAND_UNCORR_COUNT] = 0xfc, 479 [BRCMNAND_CORR_COUNT] = 0x100, 480 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 481 [BRCMNAND_CORR_ADDR] = 0x110, 482 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 483 [BRCMNAND_UNCORR_ADDR] = 0x118, 484 [BRCMNAND_SEMAPHORE] = 0x150, 485 [BRCMNAND_ID] = 0x194, 486 [BRCMNAND_ID_EXT] = 0x198, 487 [BRCMNAND_LL_RDATA] = 0x19c, 488 [BRCMNAND_OOB_READ_BASE] = 0x200, 489 [BRCMNAND_OOB_READ_10_BASE] = 0, 490 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 491 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 492 [BRCMNAND_FC_BASE] = 0x400, 493}; 494 495/* BRCMNAND v7.2 */ 496static const u16 brcmnand_regs_v72[] = { 497 [BRCMNAND_CMD_START] = 0x04, 498 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 499 [BRCMNAND_CMD_ADDRESS] = 0x0c, 500 [BRCMNAND_INTFC_STATUS] = 0x14, 501 [BRCMNAND_CS_SELECT] = 0x18, 502 [BRCMNAND_CS_XOR] = 0x1c, 503 [BRCMNAND_LL_OP] = 0x20, 504 [BRCMNAND_CS0_BASE] = 0x50, 505 [BRCMNAND_CS1_BASE] = 0, 506 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 507 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 508 [BRCMNAND_UNCORR_COUNT] = 0xfc, 509 [BRCMNAND_CORR_COUNT] = 0x100, 510 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 511 [BRCMNAND_CORR_ADDR] = 0x110, 512 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 513 [BRCMNAND_UNCORR_ADDR] = 0x118, 514 [BRCMNAND_SEMAPHORE] = 0x150, 515 [BRCMNAND_ID] = 0x194, 516 [BRCMNAND_ID_EXT] = 0x198, 517 [BRCMNAND_LL_RDATA] = 0x19c, 518 [BRCMNAND_OOB_READ_BASE] = 0x200, 519 [BRCMNAND_OOB_READ_10_BASE] = 0, 520 [BRCMNAND_OOB_WRITE_BASE] = 0x400, 521 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 522 [BRCMNAND_FC_BASE] = 0x600, 523}; 524 525enum brcmnand_cs_reg { 526 BRCMNAND_CS_CFG_EXT = 0, 527 BRCMNAND_CS_CFG, 528 BRCMNAND_CS_ACC_CONTROL, 529 BRCMNAND_CS_TIMING1, 530 BRCMNAND_CS_TIMING2, 531}; 532 533/* Per chip-select offsets for v7.1 */ 534static const u8 brcmnand_cs_offsets_v71[] = { 535 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 536 [BRCMNAND_CS_CFG_EXT] = 0x04, 537 [BRCMNAND_CS_CFG] = 0x08, 538 [BRCMNAND_CS_TIMING1] = 0x0c, 539 [BRCMNAND_CS_TIMING2] = 0x10, 540}; 541 542/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ 543static const u8 brcmnand_cs_offsets[] = { 544 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 545 [BRCMNAND_CS_CFG_EXT] = 0x04, 546 [BRCMNAND_CS_CFG] = 0x04, 547 [BRCMNAND_CS_TIMING1] = 0x08, 548 [BRCMNAND_CS_TIMING2] = 0x0c, 549}; 550 551/* Per chip-select offset for <= v5.0 on CS0 only */ 552static const u8 brcmnand_cs_offsets_cs0[] = { 553 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 554 [BRCMNAND_CS_CFG_EXT] = 0x08, 555 [BRCMNAND_CS_CFG] = 0x08, 556 [BRCMNAND_CS_TIMING1] = 0x10, 557 [BRCMNAND_CS_TIMING2] = 0x14, 558}; 559 560/* 561 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had 562 * one config register, but once the bitfields overflowed, newer controllers 563 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. 564 */ 565enum { 566 CFG_BLK_ADR_BYTES_SHIFT = 8, 567 CFG_COL_ADR_BYTES_SHIFT = 12, 568 CFG_FUL_ADR_BYTES_SHIFT = 16, 569 CFG_BUS_WIDTH_SHIFT = 23, 570 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), 571 CFG_DEVICE_SIZE_SHIFT = 24, 572 573 /* Only for v2.1 */ 574 CFG_PAGE_SIZE_SHIFT_v2_1 = 30, 575 576 /* Only for pre-v7.1 (with no CFG_EXT register) */ 577 CFG_PAGE_SIZE_SHIFT = 20, 578 CFG_BLK_SIZE_SHIFT = 28, 579 580 /* Only for v7.1+ (with CFG_EXT register) */ 581 CFG_EXT_PAGE_SIZE_SHIFT = 0, 582 CFG_EXT_BLK_SIZE_SHIFT = 4, 583}; 584 585/* BRCMNAND_INTFC_STATUS */ 586enum { 587 INTFC_FLASH_STATUS = GENMASK(7, 0), 588 589 INTFC_ERASED = BIT(27), 590 INTFC_OOB_VALID = BIT(28), 591 INTFC_CACHE_VALID = BIT(29), 592 INTFC_FLASH_READY = BIT(30), 593 INTFC_CTLR_READY = BIT(31), 594}; 595 596/*********************************************************************** 597 * NAND ACC CONTROL bitfield 598 * 599 * Some bits have remained constant throughout hardware revision, while 600 * others have shifted around. 601 ***********************************************************************/ 602 603/* Constant for all versions (where supported) */ 604enum { 605 /* See BRCMNAND_HAS_CACHE_MODE */ 606 ACC_CONTROL_CACHE_MODE = BIT(22), 607 608 /* See BRCMNAND_HAS_PREFETCH */ 609 ACC_CONTROL_PREFETCH = BIT(23), 610 611 ACC_CONTROL_PAGE_HIT = BIT(24), 612 ACC_CONTROL_WR_PREEMPT = BIT(25), 613 ACC_CONTROL_PARTIAL_PAGE = BIT(26), 614 ACC_CONTROL_RD_ERASED = BIT(27), 615 ACC_CONTROL_FAST_PGM_RDIN = BIT(28), 616 ACC_CONTROL_WR_ECC = BIT(30), 617 ACC_CONTROL_RD_ECC = BIT(31), 618}; 619 620#define ACC_CONTROL_ECC_SHIFT 16 621/* Only for v7.2 */ 622#define ACC_CONTROL_ECC_EXT_SHIFT 13 623 624static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) 625{ 626 return static_branch_unlikely(&brcmnand_soc_has_ops_key); 627} 628 629static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) 630{ 631 if (brcmnand_non_mmio_ops(ctrl)) 632 return brcmnand_soc_read(ctrl->soc, offs); 633 return brcmnand_readl(ctrl->nand_base + offs); 634} 635 636static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, 637 u32 val) 638{ 639 if (brcmnand_non_mmio_ops(ctrl)) 640 brcmnand_soc_write(ctrl->soc, val, offs); 641 else 642 brcmnand_writel(val, ctrl->nand_base + offs); 643} 644 645static int brcmnand_revision_init(struct brcmnand_controller *ctrl) 646{ 647 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; 648 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; 649 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 }; 650 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 }; 651 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 }; 652 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 }; 653 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 }; 654 655 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; 656 657 /* Only support v2.1+ */ 658 if (ctrl->nand_version < 0x0201) { 659 dev_err(ctrl->dev, "version %#x not supported\n", 660 ctrl->nand_version); 661 return -ENODEV; 662 } 663 664 /* Register offsets */ 665 if (ctrl->nand_version >= 0x0702) 666 ctrl->reg_offsets = brcmnand_regs_v72; 667 else if (ctrl->nand_version == 0x0701) 668 ctrl->reg_offsets = brcmnand_regs_v71; 669 else if (ctrl->nand_version >= 0x0600) 670 ctrl->reg_offsets = brcmnand_regs_v60; 671 else if (ctrl->nand_version >= 0x0500) 672 ctrl->reg_offsets = brcmnand_regs_v50; 673 else if (ctrl->nand_version >= 0x0303) 674 ctrl->reg_offsets = brcmnand_regs_v33; 675 else if (ctrl->nand_version >= 0x0201) 676 ctrl->reg_offsets = brcmnand_regs_v21; 677 678 /* Chip-select stride */ 679 if (ctrl->nand_version >= 0x0701) 680 ctrl->reg_spacing = 0x14; 681 else 682 ctrl->reg_spacing = 0x10; 683 684 /* Per chip-select registers */ 685 if (ctrl->nand_version >= 0x0701) { 686 ctrl->cs_offsets = brcmnand_cs_offsets_v71; 687 } else { 688 ctrl->cs_offsets = brcmnand_cs_offsets; 689 690 /* v3.3-5.0 have a different CS0 offset layout */ 691 if (ctrl->nand_version >= 0x0303 && 692 ctrl->nand_version <= 0x0500) 693 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; 694 } 695 696 /* Page / block sizes */ 697 if (ctrl->nand_version >= 0x0701) { 698 /* >= v7.1 use nice power-of-2 values! */ 699 ctrl->max_page_size = 16 * 1024; 700 ctrl->max_block_size = 2 * 1024 * 1024; 701 } else { 702 if (ctrl->nand_version >= 0x0304) 703 ctrl->page_sizes = page_sizes_v3_4; 704 else if (ctrl->nand_version >= 0x0202) 705 ctrl->page_sizes = page_sizes_v2_2; 706 else 707 ctrl->page_sizes = page_sizes_v2_1; 708 709 if (ctrl->nand_version >= 0x0202) 710 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; 711 else 712 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; 713 714 if (ctrl->nand_version >= 0x0600) 715 ctrl->block_sizes = block_sizes_v6; 716 else if (ctrl->nand_version >= 0x0400) 717 ctrl->block_sizes = block_sizes_v4; 718 else if (ctrl->nand_version >= 0x0202) 719 ctrl->block_sizes = block_sizes_v2_2; 720 else 721 ctrl->block_sizes = block_sizes_v2_1; 722 723 if (ctrl->nand_version < 0x0400) { 724 if (ctrl->nand_version < 0x0202) 725 ctrl->max_page_size = 2048; 726 else 727 ctrl->max_page_size = 4096; 728 ctrl->max_block_size = 512 * 1024; 729 } 730 } 731 732 /* Maximum spare area sector size (per 512B) */ 733 if (ctrl->nand_version == 0x0702) 734 ctrl->max_oob = 128; 735 else if (ctrl->nand_version >= 0x0600) 736 ctrl->max_oob = 64; 737 else if (ctrl->nand_version >= 0x0500) 738 ctrl->max_oob = 32; 739 else 740 ctrl->max_oob = 16; 741 742 /* v6.0 and newer (except v6.1) have prefetch support */ 743 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) 744 ctrl->features |= BRCMNAND_HAS_PREFETCH; 745 746 /* 747 * v6.x has cache mode, but it's implemented differently. Ignore it for 748 * now. 749 */ 750 if (ctrl->nand_version >= 0x0700) 751 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; 752 753 if (ctrl->nand_version >= 0x0500) 754 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; 755 756 if (ctrl->nand_version >= 0x0700) 757 ctrl->features |= BRCMNAND_HAS_WP; 758 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) 759 ctrl->features |= BRCMNAND_HAS_WP; 760 761 /* v7.2 has different ecc level shift in the acc register */ 762 if (ctrl->nand_version == 0x0702) 763 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; 764 else 765 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; 766 767 return 0; 768} 769 770static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) 771{ 772 /* flash_dma register offsets */ 773 if (ctrl->nand_version >= 0x0703) 774 ctrl->flash_dma_offsets = flash_dma_regs_v4; 775 else if (ctrl->nand_version == 0x0602) 776 ctrl->flash_dma_offsets = flash_dma_regs_v0; 777 else 778 ctrl->flash_dma_offsets = flash_dma_regs_v1; 779} 780 781static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, 782 enum brcmnand_reg reg) 783{ 784 u16 offs = ctrl->reg_offsets[reg]; 785 786 if (offs) 787 return nand_readreg(ctrl, offs); 788 else 789 return 0; 790} 791 792static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, 793 enum brcmnand_reg reg, u32 val) 794{ 795 u16 offs = ctrl->reg_offsets[reg]; 796 797 if (offs) 798 nand_writereg(ctrl, offs, val); 799} 800 801static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, 802 enum brcmnand_reg reg, u32 mask, unsigned 803 int shift, u32 val) 804{ 805 u32 tmp = brcmnand_read_reg(ctrl, reg); 806 807 tmp &= ~mask; 808 tmp |= val << shift; 809 brcmnand_write_reg(ctrl, reg, tmp); 810} 811 812static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) 813{ 814 if (brcmnand_non_mmio_ops(ctrl)) 815 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); 816 return __raw_readl(ctrl->nand_fc + word * 4); 817} 818 819static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, 820 int word, u32 val) 821{ 822 if (brcmnand_non_mmio_ops(ctrl)) 823 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); 824 else 825 __raw_writel(val, ctrl->nand_fc + word * 4); 826} 827 828static inline void edu_writel(struct brcmnand_controller *ctrl, 829 enum edu_reg reg, u32 val) 830{ 831 u16 offs = ctrl->edu_offsets[reg]; 832 833 brcmnand_writel(val, ctrl->edu_base + offs); 834} 835 836static inline u32 edu_readl(struct brcmnand_controller *ctrl, 837 enum edu_reg reg) 838{ 839 u16 offs = ctrl->edu_offsets[reg]; 840 841 return brcmnand_readl(ctrl->edu_base + offs); 842} 843 844static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) 845{ 846 847 /* Clear error addresses */ 848 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); 849 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); 850 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); 851 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); 852} 853 854static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) 855{ 856 u64 err_addr; 857 858 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); 859 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 860 BRCMNAND_UNCORR_EXT_ADDR) 861 & 0xffff) << 32); 862 863 return err_addr; 864} 865 866static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) 867{ 868 u64 err_addr; 869 870 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); 871 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 872 BRCMNAND_CORR_EXT_ADDR) 873 & 0xffff) << 32); 874 875 return err_addr; 876} 877 878static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr) 879{ 880 struct nand_chip *chip = mtd_to_nand(mtd); 881 struct brcmnand_host *host = nand_get_controller_data(chip); 882 struct brcmnand_controller *ctrl = host->ctrl; 883 884 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 885 (host->cs << 16) | ((addr >> 32) & 0xffff)); 886 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 887 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 888 lower_32_bits(addr)); 889 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 890} 891 892static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, 893 enum brcmnand_cs_reg reg) 894{ 895 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; 896 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; 897 u8 cs_offs; 898 899 if (cs == 0 && ctrl->cs0_offsets) 900 cs_offs = ctrl->cs0_offsets[reg]; 901 else 902 cs_offs = ctrl->cs_offsets[reg]; 903 904 if (cs && offs_cs1) 905 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; 906 907 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; 908} 909 910static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) 911{ 912 if (ctrl->nand_version < 0x0600) 913 return 1; 914 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); 915} 916 917static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) 918{ 919 struct brcmnand_controller *ctrl = host->ctrl; 920 unsigned int shift = 0, bits; 921 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; 922 int cs = host->cs; 923 924 if (!ctrl->reg_offsets[reg]) 925 return; 926 927 if (ctrl->nand_version == 0x0702) 928 bits = 7; 929 else if (ctrl->nand_version >= 0x0600) 930 bits = 6; 931 else if (ctrl->nand_version >= 0x0500) 932 bits = 5; 933 else 934 bits = 4; 935 936 if (ctrl->nand_version >= 0x0702) { 937 if (cs >= 4) 938 reg = BRCMNAND_CORR_THRESHOLD_EXT; 939 shift = (cs % 4) * bits; 940 } else if (ctrl->nand_version >= 0x0600) { 941 if (cs >= 5) 942 reg = BRCMNAND_CORR_THRESHOLD_EXT; 943 shift = (cs % 5) * bits; 944 } 945 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); 946} 947 948static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) 949{ 950 if (ctrl->nand_version < 0x0602) 951 return 24; 952 return 0; 953} 954 955static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) 956{ 957 if (ctrl->nand_version == 0x0702) 958 return GENMASK(7, 0); 959 else if (ctrl->nand_version >= 0x0600) 960 return GENMASK(6, 0); 961 else if (ctrl->nand_version >= 0x0303) 962 return GENMASK(5, 0); 963 else 964 return GENMASK(4, 0); 965} 966 967static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) 968{ 969 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; 970 971 mask <<= ACC_CONTROL_ECC_SHIFT; 972 973 /* v7.2 includes additional ECC levels */ 974 if (ctrl->nand_version == 0x0702) 975 mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; 976 977 return mask; 978} 979 980static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) 981{ 982 struct brcmnand_controller *ctrl = host->ctrl; 983 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 984 u32 acc_control = nand_readreg(ctrl, offs); 985 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; 986 987 if (en) { 988 acc_control |= ecc_flags; /* enable RD/WR ECC */ 989 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 990 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; 991 } else { 992 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ 993 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 994 } 995 996 nand_writereg(ctrl, offs, acc_control); 997} 998 999static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) 1000{ 1001 if (ctrl->nand_version >= 0x0702) 1002 return 9; 1003 else if (ctrl->nand_version >= 0x0600) 1004 return 7; 1005 else if (ctrl->nand_version >= 0x0500) 1006 return 6; 1007 else 1008 return -1; 1009} 1010 1011static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) 1012{ 1013 struct brcmnand_controller *ctrl = host->ctrl; 1014 int shift = brcmnand_sector_1k_shift(ctrl); 1015 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1016 BRCMNAND_CS_ACC_CONTROL); 1017 1018 if (shift < 0) 1019 return 0; 1020 1021 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; 1022} 1023 1024static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) 1025{ 1026 struct brcmnand_controller *ctrl = host->ctrl; 1027 int shift = brcmnand_sector_1k_shift(ctrl); 1028 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1029 BRCMNAND_CS_ACC_CONTROL); 1030 u32 tmp; 1031 1032 if (shift < 0) 1033 return; 1034 1035 tmp = nand_readreg(ctrl, acc_control_offs); 1036 tmp &= ~(1 << shift); 1037 tmp |= (!!val) << shift; 1038 nand_writereg(ctrl, acc_control_offs, tmp); 1039} 1040 1041/*********************************************************************** 1042 * CS_NAND_SELECT 1043 ***********************************************************************/ 1044 1045enum { 1046 CS_SELECT_NAND_WP = BIT(29), 1047 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), 1048}; 1049 1050static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, 1051 u32 mask, u32 expected_val, 1052 unsigned long timeout_ms) 1053{ 1054 unsigned long limit; 1055 u32 val; 1056 1057 if (!timeout_ms) 1058 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 1059 1060 limit = jiffies + msecs_to_jiffies(timeout_ms); 1061 do { 1062 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1063 if ((val & mask) == expected_val) 1064 return 0; 1065 1066 cpu_relax(); 1067 } while (time_after(limit, jiffies)); 1068 1069 /* 1070 * do a final check after time out in case the CPU was busy and the driver 1071 * did not get enough time to perform the polling to avoid false alarms 1072 */ 1073 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1074 if ((val & mask) == expected_val) 1075 return 0; 1076 1077 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", 1078 expected_val, val & mask); 1079 1080 return -ETIMEDOUT; 1081} 1082 1083static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) 1084{ 1085 u32 val = en ? CS_SELECT_NAND_WP : 0; 1086 1087 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); 1088} 1089 1090/*********************************************************************** 1091 * Flash DMA 1092 ***********************************************************************/ 1093 1094static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 1095{ 1096 return ctrl->flash_dma_base; 1097} 1098 1099static inline bool has_edu(struct brcmnand_controller *ctrl) 1100{ 1101 return ctrl->edu_base; 1102} 1103 1104static inline bool use_dma(struct brcmnand_controller *ctrl) 1105{ 1106 return has_flash_dma(ctrl) || has_edu(ctrl); 1107} 1108 1109static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) 1110{ 1111 if (ctrl->pio_poll_mode) 1112 return; 1113 1114 if (has_flash_dma(ctrl)) { 1115 ctrl->flash_dma_base = NULL; 1116 disable_irq(ctrl->dma_irq); 1117 } 1118 1119 disable_irq(ctrl->irq); 1120 ctrl->pio_poll_mode = true; 1121} 1122 1123static inline bool flash_dma_buf_ok(const void *buf) 1124{ 1125 return buf && !is_vmalloc_addr(buf) && 1126 likely(IS_ALIGNED((uintptr_t)buf, 4)); 1127} 1128 1129static inline void flash_dma_writel(struct brcmnand_controller *ctrl, 1130 enum flash_dma_reg dma_reg, u32 val) 1131{ 1132 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1133 1134 brcmnand_writel(val, ctrl->flash_dma_base + offs); 1135} 1136 1137static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, 1138 enum flash_dma_reg dma_reg) 1139{ 1140 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1141 1142 return brcmnand_readl(ctrl->flash_dma_base + offs); 1143} 1144 1145/* Low-level operation types: command, address, write, or read */ 1146enum brcmnand_llop_type { 1147 LL_OP_CMD, 1148 LL_OP_ADDR, 1149 LL_OP_WR, 1150 LL_OP_RD, 1151}; 1152 1153/*********************************************************************** 1154 * Internal support functions 1155 ***********************************************************************/ 1156 1157static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, 1158 struct brcmnand_cfg *cfg) 1159{ 1160 if (ctrl->nand_version <= 0x0701) 1161 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && 1162 cfg->ecc_level == 15; 1163 else 1164 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && 1165 cfg->ecc_level == 15) || 1166 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); 1167} 1168 1169/* 1170 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given 1171 * the layout/configuration. 1172 * Returns -ERRCODE on failure. 1173 */ 1174static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section, 1175 struct mtd_oob_region *oobregion) 1176{ 1177 struct nand_chip *chip = mtd_to_nand(mtd); 1178 struct brcmnand_host *host = nand_get_controller_data(chip); 1179 struct brcmnand_cfg *cfg = &host->hwcfg; 1180 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1181 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1182 1183 if (section >= sectors) 1184 return -ERANGE; 1185 1186 oobregion->offset = (section * sas) + 6; 1187 oobregion->length = 3; 1188 1189 return 0; 1190} 1191 1192static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section, 1193 struct mtd_oob_region *oobregion) 1194{ 1195 struct nand_chip *chip = mtd_to_nand(mtd); 1196 struct brcmnand_host *host = nand_get_controller_data(chip); 1197 struct brcmnand_cfg *cfg = &host->hwcfg; 1198 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1199 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1200 u32 next; 1201 1202 if (section > sectors) 1203 return -ERANGE; 1204 1205 next = (section * sas); 1206 if (section < sectors) 1207 next += 6; 1208 1209 if (section) { 1210 oobregion->offset = ((section - 1) * sas) + 9; 1211 } else { 1212 if (cfg->page_size > 512) { 1213 /* Large page NAND uses first 2 bytes for BBI */ 1214 oobregion->offset = 2; 1215 } else { 1216 /* Small page NAND uses last byte before ECC for BBI */ 1217 oobregion->offset = 0; 1218 next--; 1219 } 1220 } 1221 1222 oobregion->length = next - oobregion->offset; 1223 1224 return 0; 1225} 1226 1227static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = { 1228 .ecc = brcmnand_hamming_ooblayout_ecc, 1229 .free = brcmnand_hamming_ooblayout_free, 1230}; 1231 1232static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section, 1233 struct mtd_oob_region *oobregion) 1234{ 1235 struct nand_chip *chip = mtd_to_nand(mtd); 1236 struct brcmnand_host *host = nand_get_controller_data(chip); 1237 struct brcmnand_cfg *cfg = &host->hwcfg; 1238 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1239 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1240 1241 if (section >= sectors) 1242 return -ERANGE; 1243 1244 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; 1245 oobregion->length = chip->ecc.bytes; 1246 1247 return 0; 1248} 1249 1250static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section, 1251 struct mtd_oob_region *oobregion) 1252{ 1253 struct nand_chip *chip = mtd_to_nand(mtd); 1254 struct brcmnand_host *host = nand_get_controller_data(chip); 1255 struct brcmnand_cfg *cfg = &host->hwcfg; 1256 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1257 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1258 1259 if (section >= sectors) 1260 return -ERANGE; 1261 1262 if (sas <= chip->ecc.bytes) 1263 return 0; 1264 1265 oobregion->offset = section * sas; 1266 oobregion->length = sas - chip->ecc.bytes; 1267 1268 if (!section) { 1269 oobregion->offset++; 1270 oobregion->length--; 1271 } 1272 1273 return 0; 1274} 1275 1276static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section, 1277 struct mtd_oob_region *oobregion) 1278{ 1279 struct nand_chip *chip = mtd_to_nand(mtd); 1280 struct brcmnand_host *host = nand_get_controller_data(chip); 1281 struct brcmnand_cfg *cfg = &host->hwcfg; 1282 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1283 1284 if (section > 1 || sas - chip->ecc.bytes < 6 || 1285 (section && sas - chip->ecc.bytes == 6)) 1286 return -ERANGE; 1287 1288 if (!section) { 1289 oobregion->offset = 0; 1290 oobregion->length = 5; 1291 } else { 1292 oobregion->offset = 6; 1293 oobregion->length = sas - chip->ecc.bytes - 6; 1294 } 1295 1296 return 0; 1297} 1298 1299static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = { 1300 .ecc = brcmnand_bch_ooblayout_ecc, 1301 .free = brcmnand_bch_ooblayout_free_lp, 1302}; 1303 1304static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = { 1305 .ecc = brcmnand_bch_ooblayout_ecc, 1306 .free = brcmnand_bch_ooblayout_free_sp, 1307}; 1308 1309static int brcmstb_choose_ecc_layout(struct brcmnand_host *host) 1310{ 1311 struct brcmnand_cfg *p = &host->hwcfg; 1312 struct mtd_info *mtd = nand_to_mtd(&host->chip); 1313 struct nand_ecc_ctrl *ecc = &host->chip.ecc; 1314 unsigned int ecc_level = p->ecc_level; 1315 int sas = p->spare_area_size << p->sector_size_1k; 1316 int sectors = p->page_size / (512 << p->sector_size_1k); 1317 1318 if (p->sector_size_1k) 1319 ecc_level <<= 1; 1320 1321 if (is_hamming_ecc(host->ctrl, p)) { 1322 ecc->bytes = 3 * sectors; 1323 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops); 1324 return 0; 1325 } 1326 1327 /* 1328 * CONTROLLER_VERSION: 1329 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) 1330 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) 1331 * But we will just be conservative. 1332 */ 1333 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); 1334 if (p->page_size == 512) 1335 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops); 1336 else 1337 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops); 1338 1339 if (ecc->bytes >= sas) { 1340 dev_err(&host->pdev->dev, 1341 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", 1342 ecc->bytes, sas); 1343 return -EINVAL; 1344 } 1345 1346 return 0; 1347} 1348 1349static void brcmnand_wp(struct mtd_info *mtd, int wp) 1350{ 1351 struct nand_chip *chip = mtd_to_nand(mtd); 1352 struct brcmnand_host *host = nand_get_controller_data(chip); 1353 struct brcmnand_controller *ctrl = host->ctrl; 1354 1355 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { 1356 static int old_wp = -1; 1357 int ret; 1358 1359 if (old_wp != wp) { 1360 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); 1361 old_wp = wp; 1362 } 1363 1364 /* 1365 * make sure ctrl/flash ready before and after 1366 * changing state of #WP pin 1367 */ 1368 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | 1369 NAND_STATUS_READY, 1370 NAND_CTRL_RDY | 1371 NAND_STATUS_READY, 0); 1372 if (ret) 1373 return; 1374 1375 brcmnand_set_wp(ctrl, wp); 1376 nand_status_op(chip, NULL); 1377 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ 1378 ret = bcmnand_ctrl_poll_status(ctrl, 1379 NAND_CTRL_RDY | 1380 NAND_STATUS_READY | 1381 NAND_STATUS_WP, 1382 NAND_CTRL_RDY | 1383 NAND_STATUS_READY | 1384 (wp ? 0 : NAND_STATUS_WP), 0); 1385 1386 if (ret) 1387 dev_err_ratelimited(&host->pdev->dev, 1388 "nand #WP expected %s\n", 1389 wp ? "on" : "off"); 1390 } 1391} 1392 1393/* Helper functions for reading and writing OOB registers */ 1394static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) 1395{ 1396 u16 offset0, offset10, reg_offs; 1397 1398 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; 1399 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; 1400 1401 if (offs >= ctrl->max_oob) 1402 return 0x77; 1403 1404 if (offs >= 16 && offset10) 1405 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1406 else 1407 reg_offs = offset0 + (offs & ~0x03); 1408 1409 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); 1410} 1411 1412static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, 1413 u32 data) 1414{ 1415 u16 offset0, offset10, reg_offs; 1416 1417 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; 1418 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; 1419 1420 if (offs >= ctrl->max_oob) 1421 return; 1422 1423 if (offs >= 16 && offset10) 1424 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1425 else 1426 reg_offs = offset0 + (offs & ~0x03); 1427 1428 nand_writereg(ctrl, reg_offs, data); 1429} 1430 1431/* 1432 * read_oob_from_regs - read data from OOB registers 1433 * @ctrl: NAND controller 1434 * @i: sub-page sector index 1435 * @oob: buffer to read to 1436 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1437 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1438 */ 1439static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, 1440 int sas, int sector_1k) 1441{ 1442 int tbytes = sas << sector_1k; 1443 int j; 1444 1445 /* Adjust OOB values for 1K sector size */ 1446 if (sector_1k && (i & 0x01)) 1447 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1448 tbytes = min_t(int, tbytes, ctrl->max_oob); 1449 1450 for (j = 0; j < tbytes; j++) 1451 oob[j] = oob_reg_read(ctrl, j); 1452 return tbytes; 1453} 1454 1455/* 1456 * write_oob_to_regs - write data to OOB registers 1457 * @i: sub-page sector index 1458 * @oob: buffer to write from 1459 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1460 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1461 */ 1462static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, 1463 const u8 *oob, int sas, int sector_1k) 1464{ 1465 int tbytes = sas << sector_1k; 1466 int j, k = 0; 1467 u32 last = 0xffffffff; 1468 u8 *plast = (u8 *)&last; 1469 1470 /* Adjust OOB values for 1K sector size */ 1471 if (sector_1k && (i & 0x01)) 1472 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1473 tbytes = min_t(int, tbytes, ctrl->max_oob); 1474 1475 /* 1476 * tbytes may not be multiple of words. Make sure we don't read out of 1477 * the boundary and stop at last word. 1478 */ 1479 for (j = 0; (j + 3) < tbytes; j += 4) 1480 oob_reg_write(ctrl, j, 1481 (oob[j + 0] << 24) | 1482 (oob[j + 1] << 16) | 1483 (oob[j + 2] << 8) | 1484 (oob[j + 3] << 0)); 1485 1486 /* handle the remaing bytes */ 1487 while (j < tbytes) 1488 plast[k++] = oob[j++]; 1489 1490 if (tbytes & 0x3) 1491 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); 1492 1493 return tbytes; 1494} 1495 1496static void brcmnand_edu_init(struct brcmnand_controller *ctrl) 1497{ 1498 /* initialize edu */ 1499 edu_writel(ctrl, EDU_ERR_STATUS, 0); 1500 edu_readl(ctrl, EDU_ERR_STATUS); 1501 edu_writel(ctrl, EDU_DONE, 0); 1502 edu_writel(ctrl, EDU_DONE, 0); 1503 edu_writel(ctrl, EDU_DONE, 0); 1504 edu_writel(ctrl, EDU_DONE, 0); 1505 edu_readl(ctrl, EDU_DONE); 1506} 1507 1508/* edu irq */ 1509static irqreturn_t brcmnand_edu_irq(int irq, void *data) 1510{ 1511 struct brcmnand_controller *ctrl = data; 1512 1513 if (ctrl->edu_count) { 1514 ctrl->edu_count--; 1515 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) 1516 udelay(1); 1517 edu_writel(ctrl, EDU_DONE, 0); 1518 edu_readl(ctrl, EDU_DONE); 1519 } 1520 1521 if (ctrl->edu_count) { 1522 ctrl->edu_dram_addr += FC_BYTES; 1523 ctrl->edu_ext_addr += FC_BYTES; 1524 1525 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1526 edu_readl(ctrl, EDU_DRAM_ADDR); 1527 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1528 edu_readl(ctrl, EDU_EXT_ADDR); 1529 1530 mb(); /* flush previous writes */ 1531 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1532 edu_readl(ctrl, EDU_CMD); 1533 1534 return IRQ_HANDLED; 1535 } 1536 1537 complete(&ctrl->edu_done); 1538 1539 return IRQ_HANDLED; 1540} 1541 1542static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 1543{ 1544 struct brcmnand_controller *ctrl = data; 1545 1546 /* Discard all NAND_CTLRDY interrupts during DMA */ 1547 if (ctrl->dma_pending) 1548 return IRQ_HANDLED; 1549 1550 /* check if you need to piggy back on the ctrlrdy irq */ 1551 if (ctrl->edu_pending) { 1552 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) 1553 /* Discard interrupts while using dedicated edu irq */ 1554 return IRQ_HANDLED; 1555 1556 /* no registered edu irq, call handler */ 1557 return brcmnand_edu_irq(irq, data); 1558 } 1559 1560 complete(&ctrl->done); 1561 return IRQ_HANDLED; 1562} 1563 1564/* Handle SoC-specific interrupt hardware */ 1565static irqreturn_t brcmnand_irq(int irq, void *data) 1566{ 1567 struct brcmnand_controller *ctrl = data; 1568 1569 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) 1570 return brcmnand_ctlrdy_irq(irq, data); 1571 1572 return IRQ_NONE; 1573} 1574 1575static irqreturn_t brcmnand_dma_irq(int irq, void *data) 1576{ 1577 struct brcmnand_controller *ctrl = data; 1578 1579 complete(&ctrl->dma_done); 1580 1581 return IRQ_HANDLED; 1582} 1583 1584static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) 1585{ 1586 struct brcmnand_controller *ctrl = host->ctrl; 1587 int ret; 1588 u64 cmd_addr; 1589 1590 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1591 1592 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); 1593 1594 /* 1595 * If we came here through _panic_write and there is a pending 1596 * command, try to wait for it. If it times out, rather than 1597 * hitting BUG_ON, just return so we don't crash while crashing. 1598 */ 1599 if (oops_in_progress) { 1600 if (ctrl->cmd_pending && 1601 bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) 1602 return; 1603 } else 1604 BUG_ON(ctrl->cmd_pending != 0); 1605 ctrl->cmd_pending = cmd; 1606 1607 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 1608 WARN_ON(ret); 1609 1610 mb(); /* flush previous writes */ 1611 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, 1612 cmd << brcmnand_cmd_shift(ctrl)); 1613} 1614 1615/*********************************************************************** 1616 * NAND MTD API: read/program/erase 1617 ***********************************************************************/ 1618 1619static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat, 1620 unsigned int ctrl) 1621{ 1622 /* intentionally left blank */ 1623} 1624 1625static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip) 1626{ 1627 struct brcmnand_host *host = nand_get_controller_data(chip); 1628 struct brcmnand_controller *ctrl = host->ctrl; 1629 struct mtd_info *mtd = nand_to_mtd(chip); 1630 bool err = false; 1631 int sts; 1632 1633 if (mtd->oops_panic_write) { 1634 /* switch to interrupt polling and PIO mode */ 1635 disable_ctrl_irqs(ctrl); 1636 sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, 1637 NAND_CTRL_RDY, 0); 1638 err = (sts < 0) ? true : false; 1639 } else { 1640 unsigned long timeo = msecs_to_jiffies( 1641 NAND_POLL_STATUS_TIMEOUT_MS); 1642 /* wait for completion interrupt */ 1643 sts = wait_for_completion_timeout(&ctrl->done, timeo); 1644 err = (sts <= 0) ? true : false; 1645 } 1646 1647 return err; 1648} 1649 1650static int brcmnand_waitfunc(struct nand_chip *chip) 1651{ 1652 struct brcmnand_host *host = nand_get_controller_data(chip); 1653 struct brcmnand_controller *ctrl = host->ctrl; 1654 bool err = false; 1655 1656 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 1657 if (ctrl->cmd_pending) 1658 err = brcmstb_nand_wait_for_completion(chip); 1659 1660 if (err) { 1661 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) 1662 >> brcmnand_cmd_shift(ctrl); 1663 1664 dev_err_ratelimited(ctrl->dev, 1665 "timeout waiting for command %#02x\n", cmd); 1666 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", 1667 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); 1668 } 1669 ctrl->cmd_pending = 0; 1670 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1671 INTFC_FLASH_STATUS; 1672} 1673 1674enum { 1675 LLOP_RE = BIT(16), 1676 LLOP_WE = BIT(17), 1677 LLOP_ALE = BIT(18), 1678 LLOP_CLE = BIT(19), 1679 LLOP_RETURN_IDLE = BIT(31), 1680 1681 LLOP_DATA_MASK = GENMASK(15, 0), 1682}; 1683 1684static int brcmnand_low_level_op(struct brcmnand_host *host, 1685 enum brcmnand_llop_type type, u32 data, 1686 bool last_op) 1687{ 1688 struct nand_chip *chip = &host->chip; 1689 struct brcmnand_controller *ctrl = host->ctrl; 1690 u32 tmp; 1691 1692 tmp = data & LLOP_DATA_MASK; 1693 switch (type) { 1694 case LL_OP_CMD: 1695 tmp |= LLOP_WE | LLOP_CLE; 1696 break; 1697 case LL_OP_ADDR: 1698 /* WE | ALE */ 1699 tmp |= LLOP_WE | LLOP_ALE; 1700 break; 1701 case LL_OP_WR: 1702 /* WE */ 1703 tmp |= LLOP_WE; 1704 break; 1705 case LL_OP_RD: 1706 /* RE */ 1707 tmp |= LLOP_RE; 1708 break; 1709 } 1710 if (last_op) 1711 /* RETURN_IDLE */ 1712 tmp |= LLOP_RETURN_IDLE; 1713 1714 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); 1715 1716 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); 1717 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); 1718 1719 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); 1720 return brcmnand_waitfunc(chip); 1721} 1722 1723static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command, 1724 int column, int page_addr) 1725{ 1726 struct mtd_info *mtd = nand_to_mtd(chip); 1727 struct brcmnand_host *host = nand_get_controller_data(chip); 1728 struct brcmnand_controller *ctrl = host->ctrl; 1729 u64 addr = (u64)page_addr << chip->page_shift; 1730 int native_cmd = 0; 1731 1732 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || 1733 command == NAND_CMD_RNDOUT) 1734 addr = (u64)column; 1735 /* Avoid propagating a negative, don't-care address */ 1736 else if (page_addr < 0) 1737 addr = 0; 1738 1739 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, 1740 (unsigned long long)addr); 1741 1742 host->last_cmd = command; 1743 host->last_byte = 0; 1744 host->last_addr = addr; 1745 1746 switch (command) { 1747 case NAND_CMD_RESET: 1748 native_cmd = CMD_FLASH_RESET; 1749 break; 1750 case NAND_CMD_STATUS: 1751 native_cmd = CMD_STATUS_READ; 1752 break; 1753 case NAND_CMD_READID: 1754 native_cmd = CMD_DEVICE_ID_READ; 1755 break; 1756 case NAND_CMD_READOOB: 1757 native_cmd = CMD_SPARE_AREA_READ; 1758 break; 1759 case NAND_CMD_ERASE1: 1760 native_cmd = CMD_BLOCK_ERASE; 1761 brcmnand_wp(mtd, 0); 1762 break; 1763 case NAND_CMD_PARAM: 1764 native_cmd = CMD_PARAMETER_READ; 1765 break; 1766 case NAND_CMD_SET_FEATURES: 1767 case NAND_CMD_GET_FEATURES: 1768 brcmnand_low_level_op(host, LL_OP_CMD, command, false); 1769 brcmnand_low_level_op(host, LL_OP_ADDR, column, false); 1770 break; 1771 case NAND_CMD_RNDOUT: 1772 native_cmd = CMD_PARAMETER_CHANGE_COL; 1773 addr &= ~((u64)(FC_BYTES - 1)); 1774 /* 1775 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 1776 * NB: hwcfg.sector_size_1k may not be initialized yet 1777 */ 1778 if (brcmnand_get_sector_size_1k(host)) { 1779 host->hwcfg.sector_size_1k = 1780 brcmnand_get_sector_size_1k(host); 1781 brcmnand_set_sector_size_1k(host, 0); 1782 } 1783 break; 1784 } 1785 1786 if (!native_cmd) 1787 return; 1788 1789 brcmnand_set_cmd_addr(mtd, addr); 1790 brcmnand_send_cmd(host, native_cmd); 1791 brcmnand_waitfunc(chip); 1792 1793 if (native_cmd == CMD_PARAMETER_READ || 1794 native_cmd == CMD_PARAMETER_CHANGE_COL) { 1795 /* Copy flash cache word-wise */ 1796 u32 *flash_cache = (u32 *)ctrl->flash_cache; 1797 int i; 1798 1799 brcmnand_soc_data_bus_prepare(ctrl->soc, true); 1800 1801 /* 1802 * Must cache the FLASH_CACHE now, since changes in 1803 * SECTOR_SIZE_1K may invalidate it 1804 */ 1805 for (i = 0; i < FC_WORDS; i++) 1806 /* 1807 * Flash cache is big endian for parameter pages, at 1808 * least on STB SoCs 1809 */ 1810 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); 1811 1812 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); 1813 1814 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ 1815 if (host->hwcfg.sector_size_1k) 1816 brcmnand_set_sector_size_1k(host, 1817 host->hwcfg.sector_size_1k); 1818 } 1819 1820 /* Re-enable protection is necessary only after erase */ 1821 if (command == NAND_CMD_ERASE1) 1822 brcmnand_wp(mtd, 1); 1823} 1824 1825static uint8_t brcmnand_read_byte(struct nand_chip *chip) 1826{ 1827 struct brcmnand_host *host = nand_get_controller_data(chip); 1828 struct brcmnand_controller *ctrl = host->ctrl; 1829 uint8_t ret = 0; 1830 int addr, offs; 1831 1832 switch (host->last_cmd) { 1833 case NAND_CMD_READID: 1834 if (host->last_byte < 4) 1835 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> 1836 (24 - (host->last_byte << 3)); 1837 else if (host->last_byte < 8) 1838 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> 1839 (56 - (host->last_byte << 3)); 1840 break; 1841 1842 case NAND_CMD_READOOB: 1843 ret = oob_reg_read(ctrl, host->last_byte); 1844 break; 1845 1846 case NAND_CMD_STATUS: 1847 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1848 INTFC_FLASH_STATUS; 1849 if (wp_on) /* hide WP status */ 1850 ret |= NAND_STATUS_WP; 1851 break; 1852 1853 case NAND_CMD_PARAM: 1854 case NAND_CMD_RNDOUT: 1855 addr = host->last_addr + host->last_byte; 1856 offs = addr & (FC_BYTES - 1); 1857 1858 /* At FC_BYTES boundary, switch to next column */ 1859 if (host->last_byte > 0 && offs == 0) 1860 nand_change_read_column_op(chip, addr, NULL, 0, false); 1861 1862 ret = ctrl->flash_cache[offs]; 1863 break; 1864 case NAND_CMD_GET_FEATURES: 1865 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { 1866 ret = 0; 1867 } else { 1868 bool last = host->last_byte == 1869 ONFI_SUBFEATURE_PARAM_LEN - 1; 1870 brcmnand_low_level_op(host, LL_OP_RD, 0, last); 1871 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; 1872 } 1873 } 1874 1875 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); 1876 host->last_byte++; 1877 1878 return ret; 1879} 1880 1881static void brcmnand_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 1882{ 1883 int i; 1884 1885 for (i = 0; i < len; i++, buf++) 1886 *buf = brcmnand_read_byte(chip); 1887} 1888 1889static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf, 1890 int len) 1891{ 1892 int i; 1893 struct brcmnand_host *host = nand_get_controller_data(chip); 1894 1895 switch (host->last_cmd) { 1896 case NAND_CMD_SET_FEATURES: 1897 for (i = 0; i < len; i++) 1898 brcmnand_low_level_op(host, LL_OP_WR, buf[i], 1899 (i + 1) == len); 1900 break; 1901 default: 1902 BUG(); 1903 break; 1904 } 1905} 1906 1907/** 1908 * Kick EDU engine 1909 */ 1910static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 1911 u32 len, u8 cmd) 1912{ 1913 struct brcmnand_controller *ctrl = host->ctrl; 1914 unsigned long timeo = msecs_to_jiffies(200); 1915 int ret = 0; 1916 int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 1917 u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE); 1918 unsigned int trans = len >> FC_SHIFT; 1919 dma_addr_t pa; 1920 1921 pa = dma_map_single(ctrl->dev, buf, len, dir); 1922 if (dma_mapping_error(ctrl->dev, pa)) { 1923 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); 1924 return -ENOMEM; 1925 } 1926 1927 ctrl->edu_pending = true; 1928 ctrl->edu_dram_addr = pa; 1929 ctrl->edu_ext_addr = addr; 1930 ctrl->edu_cmd = edu_cmd; 1931 ctrl->edu_count = trans; 1932 1933 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1934 edu_readl(ctrl, EDU_DRAM_ADDR); 1935 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1936 edu_readl(ctrl, EDU_EXT_ADDR); 1937 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); 1938 edu_readl(ctrl, EDU_LENGTH); 1939 1940 /* Start edu engine */ 1941 mb(); /* flush previous writes */ 1942 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1943 edu_readl(ctrl, EDU_CMD); 1944 1945 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { 1946 dev_err(ctrl->dev, 1947 "timeout waiting for EDU; status %#x, error status %#x\n", 1948 edu_readl(ctrl, EDU_STATUS), 1949 edu_readl(ctrl, EDU_ERR_STATUS)); 1950 } 1951 1952 dma_unmap_single(ctrl->dev, pa, len, dir); 1953 1954 /* for program page check NAND status */ 1955 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1956 INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) && 1957 edu_cmd == EDU_CMD_WRITE) { 1958 dev_info(ctrl->dev, "program failed at %llx\n", 1959 (unsigned long long)addr); 1960 ret = -EIO; 1961 } 1962 1963 /* Make sure the EDU status is clean */ 1964 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) 1965 dev_warn(ctrl->dev, "EDU still active: %#x\n", 1966 edu_readl(ctrl, EDU_STATUS)); 1967 1968 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { 1969 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", 1970 (unsigned long long)addr); 1971 ret = -EIO; 1972 } 1973 1974 ctrl->edu_pending = false; 1975 brcmnand_edu_init(ctrl); 1976 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ 1977 edu_readl(ctrl, EDU_STOP); 1978 1979 if (!ret && edu_cmd == EDU_CMD_READ) { 1980 u64 err_addr = 0; 1981 1982 /* 1983 * check for ECC errors here, subpage ECC errors are 1984 * retained in ECC error address register 1985 */ 1986 err_addr = brcmnand_get_uncorrecc_addr(ctrl); 1987 if (!err_addr) { 1988 err_addr = brcmnand_get_correcc_addr(ctrl); 1989 if (err_addr) 1990 ret = -EUCLEAN; 1991 } else 1992 ret = -EBADMSG; 1993 } 1994 1995 return ret; 1996} 1997 1998/** 1999 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 2000 * following ahead of time: 2001 * - Is this descriptor the beginning or end of a linked list? 2002 * - What is the (DMA) address of the next descriptor in the linked list? 2003 */ 2004static int brcmnand_fill_dma_desc(struct brcmnand_host *host, 2005 struct brcm_nand_dma_desc *desc, u64 addr, 2006 dma_addr_t buf, u32 len, u8 dma_cmd, 2007 bool begin, bool end, 2008 dma_addr_t next_desc) 2009{ 2010 memset(desc, 0, sizeof(*desc)); 2011 /* Descriptors are written in native byte order (wordwise) */ 2012 desc->next_desc = lower_32_bits(next_desc); 2013 desc->next_desc_ext = upper_32_bits(next_desc); 2014 desc->cmd_irq = (dma_cmd << 24) | 2015 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ 2016 (!!begin) | ((!!end) << 1); /* head, tail */ 2017#ifdef CONFIG_CPU_BIG_ENDIAN 2018 desc->cmd_irq |= 0x01 << 12; 2019#endif 2020 desc->dram_addr = lower_32_bits(buf); 2021 desc->dram_addr_ext = upper_32_bits(buf); 2022 desc->tfr_len = len; 2023 desc->total_len = len; 2024 desc->flash_addr = lower_32_bits(addr); 2025 desc->flash_addr_ext = upper_32_bits(addr); 2026 desc->cs = host->cs; 2027 desc->status_valid = 0x01; 2028 return 0; 2029} 2030 2031/** 2032 * Kick the FLASH_DMA engine, with a given DMA descriptor 2033 */ 2034static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) 2035{ 2036 struct brcmnand_controller *ctrl = host->ctrl; 2037 unsigned long timeo = msecs_to_jiffies(100); 2038 2039 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); 2040 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); 2041 if (ctrl->nand_version > 0x0602) { 2042 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, 2043 upper_32_bits(desc)); 2044 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); 2045 } 2046 2047 /* Start FLASH_DMA engine */ 2048 ctrl->dma_pending = true; 2049 mb(); /* flush previous writes */ 2050 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ 2051 2052 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { 2053 dev_err(ctrl->dev, 2054 "timeout waiting for DMA; status %#x, error status %#x\n", 2055 flash_dma_readl(ctrl, FLASH_DMA_STATUS), 2056 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); 2057 } 2058 ctrl->dma_pending = false; 2059 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ 2060} 2061 2062static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 2063 u32 len, u8 dma_cmd) 2064{ 2065 struct brcmnand_controller *ctrl = host->ctrl; 2066 dma_addr_t buf_pa; 2067 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2068 2069 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); 2070 if (dma_mapping_error(ctrl->dev, buf_pa)) { 2071 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); 2072 return -ENOMEM; 2073 } 2074 2075 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, 2076 dma_cmd, true, true, 0); 2077 2078 brcmnand_dma_run(host, ctrl->dma_pa); 2079 2080 dma_unmap_single(ctrl->dev, buf_pa, len, dir); 2081 2082 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) 2083 return -EBADMSG; 2084 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) 2085 return -EUCLEAN; 2086 2087 return 0; 2088} 2089 2090/* 2091 * Assumes proper CS is already set 2092 */ 2093static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 2094 u64 addr, unsigned int trans, u32 *buf, 2095 u8 *oob, u64 *err_addr) 2096{ 2097 struct brcmnand_host *host = nand_get_controller_data(chip); 2098 struct brcmnand_controller *ctrl = host->ctrl; 2099 int i, j, ret = 0; 2100 2101 brcmnand_clear_ecc_addr(ctrl); 2102 2103 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2104 brcmnand_set_cmd_addr(mtd, addr); 2105 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ 2106 brcmnand_send_cmd(host, CMD_PAGE_READ); 2107 brcmnand_waitfunc(chip); 2108 2109 if (likely(buf)) { 2110 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2111 2112 for (j = 0; j < FC_WORDS; j++, buf++) 2113 *buf = brcmnand_read_fc(ctrl, j); 2114 2115 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2116 } 2117 2118 if (oob) 2119 oob += read_oob_from_regs(ctrl, i, oob, 2120 mtd->oobsize / trans, 2121 host->hwcfg.sector_size_1k); 2122 2123 if (ret != -EBADMSG) { 2124 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); 2125 2126 if (*err_addr) 2127 ret = -EBADMSG; 2128 } 2129 2130 if (!ret) { 2131 *err_addr = brcmnand_get_correcc_addr(ctrl); 2132 2133 if (*err_addr) 2134 ret = -EUCLEAN; 2135 } 2136 } 2137 2138 return ret; 2139} 2140 2141/* 2142 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC 2143 * error 2144 * 2145 * Because the HW ECC signals an ECC error if an erase paged has even a single 2146 * bitflip, we must check each ECC error to see if it is actually an erased 2147 * page with bitflips, not a truly corrupted page. 2148 * 2149 * On a real error, return a negative error code (-EBADMSG for ECC error), and 2150 * buf will contain raw data. 2151 * Otherwise, buf gets filled with 0xffs and return the maximum number of 2152 * bitflips-per-ECC-sector to the caller. 2153 * 2154 */ 2155static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, 2156 struct nand_chip *chip, void *buf, u64 addr) 2157{ 2158 struct mtd_oob_region ecc; 2159 int i; 2160 int bitflips = 0; 2161 int page = addr >> chip->page_shift; 2162 int ret; 2163 void *ecc_bytes; 2164 void *ecc_chunk; 2165 2166 if (!buf) 2167 buf = nand_get_data_buf(chip); 2168 2169 /* read without ecc for verification */ 2170 ret = chip->ecc.read_page_raw(chip, buf, true, page); 2171 if (ret) 2172 return ret; 2173 2174 for (i = 0; i < chip->ecc.steps; i++) { 2175 ecc_chunk = buf + chip->ecc.size * i; 2176 2177 mtd_ooblayout_ecc(mtd, i, &ecc); 2178 ecc_bytes = chip->oob_poi + ecc.offset; 2179 2180 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, 2181 ecc_bytes, ecc.length, 2182 NULL, 0, 2183 chip->ecc.strength); 2184 if (ret < 0) 2185 return ret; 2186 2187 bitflips = max(bitflips, ret); 2188 } 2189 2190 return bitflips; 2191} 2192 2193static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, 2194 u64 addr, unsigned int trans, u32 *buf, u8 *oob) 2195{ 2196 struct brcmnand_host *host = nand_get_controller_data(chip); 2197 struct brcmnand_controller *ctrl = host->ctrl; 2198 u64 err_addr = 0; 2199 int err; 2200 bool retry = true; 2201 bool edu_err = false; 2202 2203 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); 2204 2205try_dmaread: 2206 brcmnand_clear_ecc_addr(ctrl); 2207 2208 if (ctrl->dma_trans && !oob && flash_dma_buf_ok(buf)) { 2209 err = ctrl->dma_trans(host, addr, buf, 2210 trans * FC_BYTES, 2211 CMD_PAGE_READ); 2212 2213 if (err) { 2214 if (mtd_is_bitflip_or_eccerr(err)) 2215 err_addr = addr; 2216 else 2217 return -EIO; 2218 } 2219 2220 if (has_edu(ctrl) && err_addr) 2221 edu_err = true; 2222 2223 } else { 2224 if (oob) 2225 memset(oob, 0x99, mtd->oobsize); 2226 2227 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2228 oob, &err_addr); 2229 } 2230 2231 if (mtd_is_eccerr(err)) { 2232 /* 2233 * On controller version and 7.0, 7.1 , DMA read after a 2234 * prior PIO read that reported uncorrectable error, 2235 * the DMA engine captures this error following DMA read 2236 * cleared only on subsequent DMA read, so just retry once 2237 * to clear a possible false error reported for current DMA 2238 * read 2239 */ 2240 if ((ctrl->nand_version == 0x0700) || 2241 (ctrl->nand_version == 0x0701)) { 2242 if (retry) { 2243 retry = false; 2244 goto try_dmaread; 2245 } 2246 } 2247 2248 /* 2249 * Controller version 7.2 has hw encoder to detect erased page 2250 * bitflips, apply sw verification for older controllers only 2251 */ 2252 if (ctrl->nand_version < 0x0702) { 2253 err = brcmstb_nand_verify_erased_page(mtd, chip, buf, 2254 addr); 2255 /* erased page bitflips corrected */ 2256 if (err >= 0) 2257 return err; 2258 } 2259 2260 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", 2261 (unsigned long long)err_addr); 2262 mtd->ecc_stats.failed++; 2263 /* NAND layer expects zero on ECC errors */ 2264 return 0; 2265 } 2266 2267 if (mtd_is_bitflip(err)) { 2268 unsigned int corrected = brcmnand_count_corrected(ctrl); 2269 2270 /* in case of EDU correctable error we read again using PIO */ 2271 if (edu_err) 2272 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2273 oob, &err_addr); 2274 2275 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", 2276 (unsigned long long)err_addr); 2277 mtd->ecc_stats.corrected += corrected; 2278 /* Always exceed the software-imposed threshold */ 2279 return max(mtd->bitflip_threshold, corrected); 2280 } 2281 2282 return 0; 2283} 2284 2285static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf, 2286 int oob_required, int page) 2287{ 2288 struct mtd_info *mtd = nand_to_mtd(chip); 2289 struct brcmnand_host *host = nand_get_controller_data(chip); 2290 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2291 2292 nand_read_page_op(chip, page, 0, NULL, 0); 2293 2294 return brcmnand_read(mtd, chip, host->last_addr, 2295 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 2296} 2297 2298static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 2299 int oob_required, int page) 2300{ 2301 struct brcmnand_host *host = nand_get_controller_data(chip); 2302 struct mtd_info *mtd = nand_to_mtd(chip); 2303 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2304 int ret; 2305 2306 nand_read_page_op(chip, page, 0, NULL, 0); 2307 2308 brcmnand_set_ecc_enabled(host, 0); 2309 ret = brcmnand_read(mtd, chip, host->last_addr, 2310 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 2311 brcmnand_set_ecc_enabled(host, 1); 2312 return ret; 2313} 2314 2315static int brcmnand_read_oob(struct nand_chip *chip, int page) 2316{ 2317 struct mtd_info *mtd = nand_to_mtd(chip); 2318 2319 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2320 mtd->writesize >> FC_SHIFT, 2321 NULL, (u8 *)chip->oob_poi); 2322} 2323 2324static int brcmnand_read_oob_raw(struct nand_chip *chip, int page) 2325{ 2326 struct mtd_info *mtd = nand_to_mtd(chip); 2327 struct brcmnand_host *host = nand_get_controller_data(chip); 2328 2329 brcmnand_set_ecc_enabled(host, 0); 2330 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2331 mtd->writesize >> FC_SHIFT, 2332 NULL, (u8 *)chip->oob_poi); 2333 brcmnand_set_ecc_enabled(host, 1); 2334 return 0; 2335} 2336 2337static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 2338 u64 addr, const u32 *buf, u8 *oob) 2339{ 2340 struct brcmnand_host *host = nand_get_controller_data(chip); 2341 struct brcmnand_controller *ctrl = host->ctrl; 2342 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; 2343 int status, ret = 0; 2344 2345 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); 2346 2347 if (unlikely((unsigned long)buf & 0x03)) { 2348 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); 2349 buf = (u32 *)((unsigned long)buf & ~0x03); 2350 } 2351 2352 brcmnand_wp(mtd, 0); 2353 2354 for (i = 0; i < ctrl->max_oob; i += 4) 2355 oob_reg_write(ctrl, i, 0xffffffff); 2356 2357 if (use_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 2358 if (ctrl->dma_trans(host, addr, (u32 *)buf, mtd->writesize, 2359 CMD_PROGRAM_PAGE)) 2360 2361 ret = -EIO; 2362 2363 goto out; 2364 } 2365 2366 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2367 /* full address MUST be set before populating FC */ 2368 brcmnand_set_cmd_addr(mtd, addr); 2369 2370 if (buf) { 2371 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2372 2373 for (j = 0; j < FC_WORDS; j++, buf++) 2374 brcmnand_write_fc(ctrl, j, *buf); 2375 2376 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2377 } else if (oob) { 2378 for (j = 0; j < FC_WORDS; j++) 2379 brcmnand_write_fc(ctrl, j, 0xffffffff); 2380 } 2381 2382 if (oob) { 2383 oob += write_oob_to_regs(ctrl, i, oob, 2384 mtd->oobsize / trans, 2385 host->hwcfg.sector_size_1k); 2386 } 2387 2388 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ 2389 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); 2390 status = brcmnand_waitfunc(chip); 2391 2392 if (status & NAND_STATUS_FAIL) { 2393 dev_info(ctrl->dev, "program failed at %llx\n", 2394 (unsigned long long)addr); 2395 ret = -EIO; 2396 goto out; 2397 } 2398 } 2399out: 2400 brcmnand_wp(mtd, 1); 2401 return ret; 2402} 2403 2404static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf, 2405 int oob_required, int page) 2406{ 2407 struct mtd_info *mtd = nand_to_mtd(chip); 2408 struct brcmnand_host *host = nand_get_controller_data(chip); 2409 void *oob = oob_required ? chip->oob_poi : NULL; 2410 2411 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2412 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2413 2414 return nand_prog_page_end_op(chip); 2415} 2416 2417static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 2418 int oob_required, int page) 2419{ 2420 struct mtd_info *mtd = nand_to_mtd(chip); 2421 struct brcmnand_host *host = nand_get_controller_data(chip); 2422 void *oob = oob_required ? chip->oob_poi : NULL; 2423 2424 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2425 brcmnand_set_ecc_enabled(host, 0); 2426 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2427 brcmnand_set_ecc_enabled(host, 1); 2428 2429 return nand_prog_page_end_op(chip); 2430} 2431 2432static int brcmnand_write_oob(struct nand_chip *chip, int page) 2433{ 2434 return brcmnand_write(nand_to_mtd(chip), chip, 2435 (u64)page << chip->page_shift, NULL, 2436 chip->oob_poi); 2437} 2438 2439static int brcmnand_write_oob_raw(struct nand_chip *chip, int page) 2440{ 2441 struct mtd_info *mtd = nand_to_mtd(chip); 2442 struct brcmnand_host *host = nand_get_controller_data(chip); 2443 int ret; 2444 2445 brcmnand_set_ecc_enabled(host, 0); 2446 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, 2447 (u8 *)chip->oob_poi); 2448 brcmnand_set_ecc_enabled(host, 1); 2449 2450 return ret; 2451} 2452 2453/*********************************************************************** 2454 * Per-CS setup (1 NAND device) 2455 ***********************************************************************/ 2456 2457static int brcmnand_set_cfg(struct brcmnand_host *host, 2458 struct brcmnand_cfg *cfg) 2459{ 2460 struct brcmnand_controller *ctrl = host->ctrl; 2461 struct nand_chip *chip = &host->chip; 2462 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2463 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2464 BRCMNAND_CS_CFG_EXT); 2465 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2466 BRCMNAND_CS_ACC_CONTROL); 2467 u8 block_size = 0, page_size = 0, device_size = 0; 2468 u32 tmp; 2469 2470 if (ctrl->block_sizes) { 2471 int i, found; 2472 2473 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) 2474 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { 2475 block_size = i; 2476 found = 1; 2477 } 2478 if (!found) { 2479 dev_warn(ctrl->dev, "invalid block size %u\n", 2480 cfg->block_size); 2481 return -EINVAL; 2482 } 2483 } else { 2484 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); 2485 } 2486 2487 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && 2488 cfg->block_size > ctrl->max_block_size)) { 2489 dev_warn(ctrl->dev, "invalid block size %u\n", 2490 cfg->block_size); 2491 block_size = 0; 2492 } 2493 2494 if (ctrl->page_sizes) { 2495 int i, found; 2496 2497 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) 2498 if (ctrl->page_sizes[i] == cfg->page_size) { 2499 page_size = i; 2500 found = 1; 2501 } 2502 if (!found) { 2503 dev_warn(ctrl->dev, "invalid page size %u\n", 2504 cfg->page_size); 2505 return -EINVAL; 2506 } 2507 } else { 2508 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); 2509 } 2510 2511 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && 2512 cfg->page_size > ctrl->max_page_size)) { 2513 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); 2514 return -EINVAL; 2515 } 2516 2517 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { 2518 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", 2519 (unsigned long long)cfg->device_size); 2520 return -EINVAL; 2521 } 2522 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); 2523 2524 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | 2525 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | 2526 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | 2527 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | 2528 (device_size << CFG_DEVICE_SIZE_SHIFT); 2529 if (cfg_offs == cfg_ext_offs) { 2530 tmp |= (page_size << ctrl->page_size_shift) | 2531 (block_size << CFG_BLK_SIZE_SHIFT); 2532 nand_writereg(ctrl, cfg_offs, tmp); 2533 } else { 2534 nand_writereg(ctrl, cfg_offs, tmp); 2535 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | 2536 (block_size << CFG_EXT_BLK_SIZE_SHIFT); 2537 nand_writereg(ctrl, cfg_ext_offs, tmp); 2538 } 2539 2540 tmp = nand_readreg(ctrl, acc_control_offs); 2541 tmp &= ~brcmnand_ecc_level_mask(ctrl); 2542 tmp &= ~brcmnand_spare_area_mask(ctrl); 2543 if (ctrl->nand_version >= 0x0302) { 2544 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; 2545 tmp |= cfg->spare_area_size; 2546 } 2547 nand_writereg(ctrl, acc_control_offs, tmp); 2548 2549 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); 2550 2551 /* threshold = ceil(BCH-level * 0.75) */ 2552 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); 2553 2554 return 0; 2555} 2556 2557static void brcmnand_print_cfg(struct brcmnand_host *host, 2558 char *buf, struct brcmnand_cfg *cfg) 2559{ 2560 buf += sprintf(buf, 2561 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", 2562 (unsigned long long)cfg->device_size >> 20, 2563 cfg->block_size >> 10, 2564 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, 2565 cfg->page_size >= 1024 ? "KiB" : "B", 2566 cfg->spare_area_size, cfg->device_width); 2567 2568 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ 2569 if (is_hamming_ecc(host->ctrl, cfg)) 2570 sprintf(buf, ", Hamming ECC"); 2571 else if (cfg->sector_size_1k) 2572 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); 2573 else 2574 sprintf(buf, ", BCH-%u", cfg->ecc_level); 2575} 2576 2577/* 2578 * Minimum number of bytes to address a page. Calculated as: 2579 * roundup(log2(size / page-size) / 8) 2580 * 2581 * NB: the following does not "round up" for non-power-of-2 'size'; but this is 2582 * OK because many other things will break if 'size' is irregular... 2583 */ 2584static inline int get_blk_adr_bytes(u64 size, u32 writesize) 2585{ 2586 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; 2587} 2588 2589static int brcmnand_setup_dev(struct brcmnand_host *host) 2590{ 2591 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2592 struct nand_chip *chip = &host->chip; 2593 const struct nand_ecc_props *requirements = 2594 nanddev_get_ecc_requirements(&chip->base); 2595 struct nand_memory_organization *memorg = 2596 nanddev_get_memorg(&chip->base); 2597 struct brcmnand_controller *ctrl = host->ctrl; 2598 struct brcmnand_cfg *cfg = &host->hwcfg; 2599 char msg[128]; 2600 u32 offs, tmp, oob_sector; 2601 int ret; 2602 2603 memset(cfg, 0, sizeof(*cfg)); 2604 2605 ret = of_property_read_u32(nand_get_flash_node(chip), 2606 "brcm,nand-oob-sector-size", 2607 &oob_sector); 2608 if (ret) { 2609 /* Use detected size */ 2610 cfg->spare_area_size = mtd->oobsize / 2611 (mtd->writesize >> FC_SHIFT); 2612 } else { 2613 cfg->spare_area_size = oob_sector; 2614 } 2615 if (cfg->spare_area_size > ctrl->max_oob) 2616 cfg->spare_area_size = ctrl->max_oob; 2617 /* 2618 * Set mtd and memorg oobsize to be consistent with controller's 2619 * spare_area_size, as the rest is inaccessible. 2620 */ 2621 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); 2622 memorg->oobsize = mtd->oobsize; 2623 2624 cfg->device_size = mtd->size; 2625 cfg->block_size = mtd->erasesize; 2626 cfg->page_size = mtd->writesize; 2627 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; 2628 cfg->col_adr_bytes = 2; 2629 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 2630 2631 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 2632 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 2633 chip->ecc.engine_type); 2634 return -EINVAL; 2635 } 2636 2637 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { 2638 if (chip->ecc.strength == 1 && chip->ecc.size == 512) 2639 /* Default to Hamming for 1-bit ECC, if unspecified */ 2640 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2641 else 2642 /* Otherwise, BCH */ 2643 chip->ecc.algo = NAND_ECC_ALGO_BCH; 2644 } 2645 2646 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && 2647 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { 2648 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 2649 chip->ecc.strength, chip->ecc.size); 2650 return -EINVAL; 2651 } 2652 2653 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2654 (!chip->ecc.size || !chip->ecc.strength)) { 2655 if (requirements->step_size && requirements->strength) { 2656 /* use detected ECC parameters */ 2657 chip->ecc.size = requirements->step_size; 2658 chip->ecc.strength = requirements->strength; 2659 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", 2660 chip->ecc.size, chip->ecc.strength); 2661 } 2662 } 2663 2664 switch (chip->ecc.size) { 2665 case 512: 2666 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 2667 cfg->ecc_level = 15; 2668 else 2669 cfg->ecc_level = chip->ecc.strength; 2670 cfg->sector_size_1k = 0; 2671 break; 2672 case 1024: 2673 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { 2674 dev_err(ctrl->dev, "1KB sectors not supported\n"); 2675 return -EINVAL; 2676 } 2677 if (chip->ecc.strength & 0x1) { 2678 dev_err(ctrl->dev, 2679 "odd ECC not supported with 1KB sectors\n"); 2680 return -EINVAL; 2681 } 2682 2683 cfg->ecc_level = chip->ecc.strength >> 1; 2684 cfg->sector_size_1k = 1; 2685 break; 2686 default: 2687 dev_err(ctrl->dev, "unsupported ECC size: %d\n", 2688 chip->ecc.size); 2689 return -EINVAL; 2690 } 2691 2692 cfg->ful_adr_bytes = cfg->blk_adr_bytes; 2693 if (mtd->writesize > 512) 2694 cfg->ful_adr_bytes += cfg->col_adr_bytes; 2695 else 2696 cfg->ful_adr_bytes += 1; 2697 2698 ret = brcmnand_set_cfg(host, cfg); 2699 if (ret) 2700 return ret; 2701 2702 brcmnand_set_ecc_enabled(host, 1); 2703 2704 brcmnand_print_cfg(host, msg, cfg); 2705 dev_info(ctrl->dev, "detected %s\n", msg); 2706 2707 /* Configure ACC_CONTROL */ 2708 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 2709 tmp = nand_readreg(ctrl, offs); 2710 tmp &= ~ACC_CONTROL_PARTIAL_PAGE; 2711 tmp &= ~ACC_CONTROL_RD_ERASED; 2712 2713 /* We need to turn on Read from erased paged protected by ECC */ 2714 if (ctrl->nand_version >= 0x0702) 2715 tmp |= ACC_CONTROL_RD_ERASED; 2716 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; 2717 if (ctrl->features & BRCMNAND_HAS_PREFETCH) 2718 tmp &= ~ACC_CONTROL_PREFETCH; 2719 2720 nand_writereg(ctrl, offs, tmp); 2721 2722 return 0; 2723} 2724 2725static int brcmnand_attach_chip(struct nand_chip *chip) 2726{ 2727 struct mtd_info *mtd = nand_to_mtd(chip); 2728 struct brcmnand_host *host = nand_get_controller_data(chip); 2729 int ret; 2730 2731 chip->options |= NAND_NO_SUBPAGE_WRITE; 2732 /* 2733 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA 2734 * to/from, and have nand_base pass us a bounce buffer instead, as 2735 * needed. 2736 */ 2737 chip->options |= NAND_USES_DMA; 2738 2739 if (chip->bbt_options & NAND_BBT_USE_FLASH) 2740 chip->bbt_options |= NAND_BBT_NO_OOB; 2741 2742 if (brcmnand_setup_dev(host)) 2743 return -ENXIO; 2744 2745 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; 2746 2747 /* only use our internal HW threshold */ 2748 mtd->bitflip_threshold = 1; 2749 2750 ret = brcmstb_choose_ecc_layout(host); 2751 2752 /* If OOB is written with ECC enabled it will cause ECC errors */ 2753 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { 2754 chip->ecc.write_oob = brcmnand_write_oob_raw; 2755 chip->ecc.read_oob = brcmnand_read_oob_raw; 2756 } 2757 2758 return ret; 2759} 2760 2761static const struct nand_controller_ops brcmnand_controller_ops = { 2762 .attach_chip = brcmnand_attach_chip, 2763}; 2764 2765static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) 2766{ 2767 struct brcmnand_controller *ctrl = host->ctrl; 2768 struct platform_device *pdev = host->pdev; 2769 struct mtd_info *mtd; 2770 struct nand_chip *chip; 2771 int ret; 2772 u16 cfg_offs; 2773 2774 ret = of_property_read_u32(dn, "reg", &host->cs); 2775 if (ret) { 2776 dev_err(&pdev->dev, "can't get chip-select\n"); 2777 return -ENXIO; 2778 } 2779 2780 mtd = nand_to_mtd(&host->chip); 2781 chip = &host->chip; 2782 2783 nand_set_flash_node(chip, dn); 2784 nand_set_controller_data(chip, host); 2785 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", 2786 host->cs); 2787 if (!mtd->name) 2788 return -ENOMEM; 2789 2790 mtd->owner = THIS_MODULE; 2791 mtd->dev.parent = &pdev->dev; 2792 2793 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; 2794 chip->legacy.cmdfunc = brcmnand_cmdfunc; 2795 chip->legacy.waitfunc = brcmnand_waitfunc; 2796 chip->legacy.read_byte = brcmnand_read_byte; 2797 chip->legacy.read_buf = brcmnand_read_buf; 2798 chip->legacy.write_buf = brcmnand_write_buf; 2799 2800 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2801 chip->ecc.read_page = brcmnand_read_page; 2802 chip->ecc.write_page = brcmnand_write_page; 2803 chip->ecc.read_page_raw = brcmnand_read_page_raw; 2804 chip->ecc.write_page_raw = brcmnand_write_page_raw; 2805 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; 2806 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; 2807 chip->ecc.read_oob = brcmnand_read_oob; 2808 chip->ecc.write_oob = brcmnand_write_oob; 2809 2810 chip->controller = &ctrl->controller; 2811 2812 /* 2813 * The bootloader might have configured 16bit mode but 2814 * NAND READID command only works in 8bit mode. We force 2815 * 8bit mode here to ensure that NAND READID commands works. 2816 */ 2817 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2818 nand_writereg(ctrl, cfg_offs, 2819 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); 2820 2821 ret = nand_scan(chip, 1); 2822 if (ret) 2823 return ret; 2824 2825 ret = mtd_device_register(mtd, NULL, 0); 2826 if (ret) 2827 nand_cleanup(chip); 2828 2829 return ret; 2830} 2831 2832static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, 2833 int restore) 2834{ 2835 struct brcmnand_controller *ctrl = host->ctrl; 2836 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2837 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2838 BRCMNAND_CS_CFG_EXT); 2839 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2840 BRCMNAND_CS_ACC_CONTROL); 2841 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); 2842 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); 2843 2844 if (restore) { 2845 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); 2846 if (cfg_offs != cfg_ext_offs) 2847 nand_writereg(ctrl, cfg_ext_offs, 2848 host->hwcfg.config_ext); 2849 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); 2850 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); 2851 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); 2852 } else { 2853 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); 2854 if (cfg_offs != cfg_ext_offs) 2855 host->hwcfg.config_ext = 2856 nand_readreg(ctrl, cfg_ext_offs); 2857 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); 2858 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); 2859 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); 2860 } 2861} 2862 2863static int brcmnand_suspend(struct device *dev) 2864{ 2865 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2866 struct brcmnand_host *host; 2867 2868 list_for_each_entry(host, &ctrl->host_list, node) 2869 brcmnand_save_restore_cs_config(host, 0); 2870 2871 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); 2872 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); 2873 ctrl->corr_stat_threshold = 2874 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); 2875 2876 if (has_flash_dma(ctrl)) 2877 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 2878 else if (has_edu(ctrl)) 2879 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2880 2881 return 0; 2882} 2883 2884static int brcmnand_resume(struct device *dev) 2885{ 2886 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2887 struct brcmnand_host *host; 2888 2889 if (has_flash_dma(ctrl)) { 2890 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 2891 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 2892 } 2893 2894 if (has_edu(ctrl)) { 2895 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2896 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); 2897 edu_readl(ctrl, EDU_CONFIG); 2898 brcmnand_edu_init(ctrl); 2899 } 2900 2901 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); 2902 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); 2903 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, 2904 ctrl->corr_stat_threshold); 2905 if (ctrl->soc) { 2906 /* Clear/re-enable interrupt */ 2907 ctrl->soc->ctlrdy_ack(ctrl->soc); 2908 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 2909 } 2910 2911 list_for_each_entry(host, &ctrl->host_list, node) { 2912 struct nand_chip *chip = &host->chip; 2913 2914 brcmnand_save_restore_cs_config(host, 1); 2915 2916 /* Reset the chip, required by some chips after power-up */ 2917 nand_reset_op(chip); 2918 } 2919 2920 return 0; 2921} 2922 2923const struct dev_pm_ops brcmnand_pm_ops = { 2924 .suspend = brcmnand_suspend, 2925 .resume = brcmnand_resume, 2926}; 2927EXPORT_SYMBOL_GPL(brcmnand_pm_ops); 2928 2929static const struct of_device_id brcmnand_of_match[] = { 2930 { .compatible = "brcm,brcmnand-v2.1" }, 2931 { .compatible = "brcm,brcmnand-v2.2" }, 2932 { .compatible = "brcm,brcmnand-v4.0" }, 2933 { .compatible = "brcm,brcmnand-v5.0" }, 2934 { .compatible = "brcm,brcmnand-v6.0" }, 2935 { .compatible = "brcm,brcmnand-v6.1" }, 2936 { .compatible = "brcm,brcmnand-v6.2" }, 2937 { .compatible = "brcm,brcmnand-v7.0" }, 2938 { .compatible = "brcm,brcmnand-v7.1" }, 2939 { .compatible = "brcm,brcmnand-v7.2" }, 2940 { .compatible = "brcm,brcmnand-v7.3" }, 2941 {}, 2942}; 2943MODULE_DEVICE_TABLE(of, brcmnand_of_match); 2944 2945/*********************************************************************** 2946 * Platform driver setup (per controller) 2947 ***********************************************************************/ 2948static int brcmnand_edu_setup(struct platform_device *pdev) 2949{ 2950 struct device *dev = &pdev->dev; 2951 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 2952 struct resource *res; 2953 int ret; 2954 2955 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); 2956 if (res) { 2957 ctrl->edu_base = devm_ioremap_resource(dev, res); 2958 if (IS_ERR(ctrl->edu_base)) 2959 return PTR_ERR(ctrl->edu_base); 2960 2961 ctrl->edu_offsets = edu_regs; 2962 2963 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | 2964 EDU_CONFIG_SWAP_CFG); 2965 edu_readl(ctrl, EDU_CONFIG); 2966 2967 /* initialize edu */ 2968 brcmnand_edu_init(ctrl); 2969 2970 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); 2971 if (ctrl->edu_irq < 0) { 2972 dev_warn(dev, 2973 "FLASH EDU enabled, using ctlrdy irq\n"); 2974 } else { 2975 ret = devm_request_irq(dev, ctrl->edu_irq, 2976 brcmnand_edu_irq, 0, 2977 "brcmnand-edu", ctrl); 2978 if (ret < 0) { 2979 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", 2980 ctrl->edu_irq, ret); 2981 return ret; 2982 } 2983 2984 dev_info(dev, "FLASH EDU enabled using irq %u\n", 2985 ctrl->edu_irq); 2986 } 2987 } 2988 2989 return 0; 2990} 2991 2992int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 2993{ 2994 struct device *dev = &pdev->dev; 2995 struct device_node *dn = dev->of_node, *child; 2996 struct brcmnand_controller *ctrl; 2997 struct resource *res; 2998 int ret; 2999 3000 /* We only support device-tree instantiation */ 3001 if (!dn) 3002 return -ENODEV; 3003 3004 if (!of_match_node(brcmnand_of_match, dn)) 3005 return -ENODEV; 3006 3007 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 3008 if (!ctrl) 3009 return -ENOMEM; 3010 3011 dev_set_drvdata(dev, ctrl); 3012 ctrl->dev = dev; 3013 3014 /* Enable the static key if the soc provides I/O operations indicating 3015 * that a non-memory mapped IO access path must be used 3016 */ 3017 if (brcmnand_soc_has_ops(ctrl->soc)) 3018 static_branch_enable(&brcmnand_soc_has_ops_key); 3019 3020 init_completion(&ctrl->done); 3021 init_completion(&ctrl->dma_done); 3022 init_completion(&ctrl->edu_done); 3023 nand_controller_init(&ctrl->controller); 3024 ctrl->controller.ops = &brcmnand_controller_ops; 3025 INIT_LIST_HEAD(&ctrl->host_list); 3026 3027 /* NAND register range */ 3028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3029 ctrl->nand_base = devm_ioremap_resource(dev, res); 3030 if (IS_ERR(ctrl->nand_base)) 3031 return PTR_ERR(ctrl->nand_base); 3032 3033 /* Enable clock before using NAND registers */ 3034 ctrl->clk = devm_clk_get(dev, "nand"); 3035 if (!IS_ERR(ctrl->clk)) { 3036 ret = clk_prepare_enable(ctrl->clk); 3037 if (ret) 3038 return ret; 3039 } else { 3040 ret = PTR_ERR(ctrl->clk); 3041 if (ret == -EPROBE_DEFER) 3042 return ret; 3043 3044 ctrl->clk = NULL; 3045 } 3046 3047 /* Initialize NAND revision */ 3048 ret = brcmnand_revision_init(ctrl); 3049 if (ret) 3050 goto err; 3051 3052 /* 3053 * Most chips have this cache at a fixed offset within 'nand' block. 3054 * Some must specify this region separately. 3055 */ 3056 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); 3057 if (res) { 3058 ctrl->nand_fc = devm_ioremap_resource(dev, res); 3059 if (IS_ERR(ctrl->nand_fc)) { 3060 ret = PTR_ERR(ctrl->nand_fc); 3061 goto err; 3062 } 3063 } else { 3064 ctrl->nand_fc = ctrl->nand_base + 3065 ctrl->reg_offsets[BRCMNAND_FC_BASE]; 3066 } 3067 3068 /* FLASH_DMA */ 3069 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); 3070 if (res) { 3071 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); 3072 if (IS_ERR(ctrl->flash_dma_base)) { 3073 ret = PTR_ERR(ctrl->flash_dma_base); 3074 goto err; 3075 } 3076 3077 /* initialize the dma version */ 3078 brcmnand_flash_dma_revision_init(ctrl); 3079 3080 ret = -EIO; 3081 if (ctrl->nand_version >= 0x0700) 3082 ret = dma_set_mask_and_coherent(&pdev->dev, 3083 DMA_BIT_MASK(40)); 3084 if (ret) 3085 ret = dma_set_mask_and_coherent(&pdev->dev, 3086 DMA_BIT_MASK(32)); 3087 if (ret) 3088 goto err; 3089 3090 /* linked-list and stop on error */ 3091 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); 3092 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 3093 3094 /* Allocate descriptor(s) */ 3095 ctrl->dma_desc = dmam_alloc_coherent(dev, 3096 sizeof(*ctrl->dma_desc), 3097 &ctrl->dma_pa, GFP_KERNEL); 3098 if (!ctrl->dma_desc) { 3099 ret = -ENOMEM; 3100 goto err; 3101 } 3102 3103 ctrl->dma_irq = platform_get_irq(pdev, 1); 3104 if ((int)ctrl->dma_irq < 0) { 3105 dev_err(dev, "missing FLASH_DMA IRQ\n"); 3106 ret = -ENODEV; 3107 goto err; 3108 } 3109 3110 ret = devm_request_irq(dev, ctrl->dma_irq, 3111 brcmnand_dma_irq, 0, DRV_NAME, 3112 ctrl); 3113 if (ret < 0) { 3114 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3115 ctrl->dma_irq, ret); 3116 goto err; 3117 } 3118 3119 dev_info(dev, "enabling FLASH_DMA\n"); 3120 /* set flash dma transfer function to call */ 3121 ctrl->dma_trans = brcmnand_dma_trans; 3122 } else { 3123 ret = brcmnand_edu_setup(pdev); 3124 if (ret < 0) 3125 goto err; 3126 3127 if (has_edu(ctrl)) 3128 /* set edu transfer function to call */ 3129 ctrl->dma_trans = brcmnand_edu_trans; 3130 } 3131 3132 /* Disable automatic device ID config, direct addressing */ 3133 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, 3134 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); 3135 /* Disable XOR addressing */ 3136 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); 3137 3138 if (ctrl->features & BRCMNAND_HAS_WP) { 3139 /* Permanently disable write protection */ 3140 if (wp_on == 2) 3141 brcmnand_set_wp(ctrl, false); 3142 } else { 3143 wp_on = 0; 3144 } 3145 3146 /* IRQ */ 3147 ctrl->irq = platform_get_irq(pdev, 0); 3148 if ((int)ctrl->irq < 0) { 3149 dev_err(dev, "no IRQ defined\n"); 3150 ret = -ENODEV; 3151 goto err; 3152 } 3153 3154 /* 3155 * Some SoCs integrate this controller (e.g., its interrupt bits) in 3156 * interesting ways 3157 */ 3158 if (soc) { 3159 ctrl->soc = soc; 3160 3161 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, 3162 DRV_NAME, ctrl); 3163 3164 /* Enable interrupt */ 3165 ctrl->soc->ctlrdy_ack(ctrl->soc); 3166 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 3167 } else { 3168 /* Use standard interrupt infrastructure */ 3169 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, 3170 DRV_NAME, ctrl); 3171 } 3172 if (ret < 0) { 3173 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3174 ctrl->irq, ret); 3175 goto err; 3176 } 3177 3178 for_each_available_child_of_node(dn, child) { 3179 if (of_device_is_compatible(child, "brcm,nandcs")) { 3180 struct brcmnand_host *host; 3181 3182 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 3183 if (!host) { 3184 of_node_put(child); 3185 ret = -ENOMEM; 3186 goto err; 3187 } 3188 host->pdev = pdev; 3189 host->ctrl = ctrl; 3190 3191 ret = brcmnand_init_cs(host, child); 3192 if (ret) { 3193 devm_kfree(dev, host); 3194 continue; /* Try all chip-selects */ 3195 } 3196 3197 list_add_tail(&host->node, &ctrl->host_list); 3198 } 3199 } 3200 3201 /* No chip-selects could initialize properly */ 3202 if (list_empty(&ctrl->host_list)) { 3203 ret = -ENODEV; 3204 goto err; 3205 } 3206 3207 return 0; 3208 3209err: 3210 clk_disable_unprepare(ctrl->clk); 3211 return ret; 3212 3213} 3214EXPORT_SYMBOL_GPL(brcmnand_probe); 3215 3216int brcmnand_remove(struct platform_device *pdev) 3217{ 3218 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 3219 struct brcmnand_host *host; 3220 struct nand_chip *chip; 3221 int ret; 3222 3223 list_for_each_entry(host, &ctrl->host_list, node) { 3224 chip = &host->chip; 3225 ret = mtd_device_unregister(nand_to_mtd(chip)); 3226 WARN_ON(ret); 3227 nand_cleanup(chip); 3228 } 3229 3230 clk_disable_unprepare(ctrl->clk); 3231 3232 dev_set_drvdata(&pdev->dev, NULL); 3233 3234 return 0; 3235} 3236EXPORT_SYMBOL_GPL(brcmnand_remove); 3237 3238MODULE_LICENSE("GPL v2"); 3239MODULE_AUTHOR("Kevin Cernekee"); 3240MODULE_AUTHOR("Brian Norris"); 3241MODULE_DESCRIPTION("NAND driver for Broadcom chips"); 3242MODULE_ALIAS("platform:brcmnand"); 3243