1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *  Copyright (C) 2004 Embedded Edge, LLC
4 */
5
6#include <linux/slab.h>
7#include <linux/module.h>
8#include <linux/interrupt.h>
9#include <linux/mtd/mtd.h>
10#include <linux/mtd/rawnand.h>
11#include <linux/mtd/partitions.h>
12#include <linux/platform_device.h>
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15#include <asm/mach-au1x00/au1550nd.h>
16
17
18struct au1550nd_ctx {
19	struct nand_controller controller;
20	struct nand_chip chip;
21
22	int cs;
23	void __iomem *base;
24};
25
26static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
27{
28	return container_of(this, struct au1550nd_ctx, chip);
29}
30
31/**
32 * au_write_buf -  write buffer to chip
33 * @this:	NAND chip object
34 * @buf:	data buffer
35 * @len:	number of bytes to write
36 *
37 * write function for 8bit buswidth
38 */
39static void au_write_buf(struct nand_chip *this, const void *buf,
40			 unsigned int len)
41{
42	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
43	const u8 *p = buf;
44	int i;
45
46	for (i = 0; i < len; i++) {
47		writeb(p[i], ctx->base + MEM_STNAND_DATA);
48		wmb(); /* drain writebuffer */
49	}
50}
51
52/**
53 * au_read_buf -  read chip data into buffer
54 * @this:	NAND chip object
55 * @buf:	buffer to store date
56 * @len:	number of bytes to read
57 *
58 * read function for 8bit buswidth
59 */
60static void au_read_buf(struct nand_chip *this, void *buf,
61			unsigned int len)
62{
63	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
64	u8 *p = buf;
65	int i;
66
67	for (i = 0; i < len; i++) {
68		p[i] = readb(ctx->base + MEM_STNAND_DATA);
69		wmb(); /* drain writebuffer */
70	}
71}
72
73/**
74 * au_write_buf16 -  write buffer to chip
75 * @this:	NAND chip object
76 * @buf:	data buffer
77 * @len:	number of bytes to write
78 *
79 * write function for 16bit buswidth
80 */
81static void au_write_buf16(struct nand_chip *this, const void *buf,
82			   unsigned int len)
83{
84	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
85	const u16 *p = buf;
86	unsigned int i;
87
88	len >>= 1;
89	for (i = 0; i < len; i++) {
90		writew(p[i], ctx->base + MEM_STNAND_DATA);
91		wmb(); /* drain writebuffer */
92	}
93}
94
95/**
96 * au_read_buf16 -  read chip data into buffer
97 * @this:	NAND chip object
98 * @buf:	buffer to store date
99 * @len:	number of bytes to read
100 *
101 * read function for 16bit buswidth
102 */
103static void au_read_buf16(struct nand_chip *this, void *buf, unsigned int len)
104{
105	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
106	unsigned int i;
107	u16 *p = buf;
108
109	len >>= 1;
110	for (i = 0; i < len; i++) {
111		p[i] = readw(ctx->base + MEM_STNAND_DATA);
112		wmb(); /* drain writebuffer */
113	}
114}
115
116static int find_nand_cs(unsigned long nand_base)
117{
118	void __iomem *base =
119			(void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
120	unsigned long addr, staddr, start, mask, end;
121	int i;
122
123	for (i = 0; i < 4; i++) {
124		addr = 0x1000 + (i * 0x10);			/* CSx */
125		staddr = __raw_readl(base + addr + 0x08);	/* STADDRx */
126		/* figure out the decoded range of this CS */
127		start = (staddr << 4) & 0xfffc0000;
128		mask = (staddr << 18) & 0xfffc0000;
129		end = (start | (start - 1)) & ~(start ^ mask);
130		if ((nand_base >= start) && (nand_base < end))
131			return i;
132	}
133
134	return -ENODEV;
135}
136
137static int au1550nd_waitrdy(struct nand_chip *this, unsigned int timeout_ms)
138{
139	unsigned long timeout_jiffies = jiffies;
140
141	timeout_jiffies += msecs_to_jiffies(timeout_ms) + 1;
142	do {
143		if (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1)
144			return 0;
145
146		usleep_range(10, 100);
147	} while (time_before(jiffies, timeout_jiffies));
148
149	return -ETIMEDOUT;
150}
151
152static int au1550nd_exec_instr(struct nand_chip *this,
153			       const struct nand_op_instr *instr)
154{
155	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
156	unsigned int i;
157	int ret = 0;
158
159	switch (instr->type) {
160	case NAND_OP_CMD_INSTR:
161		writeb(instr->ctx.cmd.opcode,
162		       ctx->base + MEM_STNAND_CMD);
163		/* Drain the writebuffer */
164		wmb();
165		break;
166
167	case NAND_OP_ADDR_INSTR:
168		for (i = 0; i < instr->ctx.addr.naddrs; i++) {
169			writeb(instr->ctx.addr.addrs[i],
170			       ctx->base + MEM_STNAND_ADDR);
171			/* Drain the writebuffer */
172			wmb();
173		}
174		break;
175
176	case NAND_OP_DATA_IN_INSTR:
177		if ((this->options & NAND_BUSWIDTH_16) &&
178		    !instr->ctx.data.force_8bit)
179			au_read_buf16(this, instr->ctx.data.buf.in,
180				      instr->ctx.data.len);
181		else
182			au_read_buf(this, instr->ctx.data.buf.in,
183				    instr->ctx.data.len);
184		break;
185
186	case NAND_OP_DATA_OUT_INSTR:
187		if ((this->options & NAND_BUSWIDTH_16) &&
188		    !instr->ctx.data.force_8bit)
189			au_write_buf16(this, instr->ctx.data.buf.out,
190				       instr->ctx.data.len);
191		else
192			au_write_buf(this, instr->ctx.data.buf.out,
193				     instr->ctx.data.len);
194		break;
195
196	case NAND_OP_WAITRDY_INSTR:
197		ret = au1550nd_waitrdy(this, instr->ctx.waitrdy.timeout_ms);
198		break;
199	default:
200		return -EINVAL;
201	}
202
203	if (instr->delay_ns)
204		ndelay(instr->delay_ns);
205
206	return ret;
207}
208
209static int au1550nd_exec_op(struct nand_chip *this,
210			    const struct nand_operation *op,
211			    bool check_only)
212{
213	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
214	unsigned int i;
215	int ret;
216
217	if (check_only)
218		return 0;
219
220	/* assert (force assert) chip enable */
221	alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
222	/* Drain the writebuffer */
223	wmb();
224
225	for (i = 0; i < op->ninstrs; i++) {
226		ret = au1550nd_exec_instr(this, &op->instrs[i]);
227		if (ret)
228			break;
229	}
230
231	/* deassert chip enable */
232	alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
233	/* Drain the writebuffer */
234	wmb();
235
236	return ret;
237}
238
239static int au1550nd_attach_chip(struct nand_chip *chip)
240{
241	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
242	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
243		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
244
245	return 0;
246}
247
248static const struct nand_controller_ops au1550nd_ops = {
249	.exec_op = au1550nd_exec_op,
250	.attach_chip = au1550nd_attach_chip,
251};
252
253static int au1550nd_probe(struct platform_device *pdev)
254{
255	struct au1550nd_platdata *pd;
256	struct au1550nd_ctx *ctx;
257	struct nand_chip *this;
258	struct mtd_info *mtd;
259	struct resource *r;
260	int ret, cs;
261
262	pd = dev_get_platdata(&pdev->dev);
263	if (!pd) {
264		dev_err(&pdev->dev, "missing platform data\n");
265		return -ENODEV;
266	}
267
268	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
269	if (!ctx)
270		return -ENOMEM;
271
272	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
273	if (!r) {
274		dev_err(&pdev->dev, "no NAND memory resource\n");
275		ret = -ENODEV;
276		goto out1;
277	}
278	if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
279		dev_err(&pdev->dev, "cannot claim NAND memory area\n");
280		ret = -ENOMEM;
281		goto out1;
282	}
283
284	ctx->base = ioremap(r->start, 0x1000);
285	if (!ctx->base) {
286		dev_err(&pdev->dev, "cannot remap NAND memory area\n");
287		ret = -ENODEV;
288		goto out2;
289	}
290
291	this = &ctx->chip;
292	mtd = nand_to_mtd(this);
293	mtd->dev.parent = &pdev->dev;
294
295	/* figure out which CS# r->start belongs to */
296	cs = find_nand_cs(r->start);
297	if (cs < 0) {
298		dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
299		ret = -ENODEV;
300		goto out3;
301	}
302	ctx->cs = cs;
303
304	nand_controller_init(&ctx->controller);
305	ctx->controller.ops = &au1550nd_ops;
306	this->controller = &ctx->controller;
307
308	if (pd->devwidth)
309		this->options |= NAND_BUSWIDTH_16;
310
311	/*
312	 * This driver assumes that the default ECC engine should be TYPE_SOFT.
313	 * Set ->engine_type before registering the NAND devices in order to
314	 * provide a driver specific default value.
315	 */
316	this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
317
318	ret = nand_scan(this, 1);
319	if (ret) {
320		dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
321		goto out3;
322	}
323
324	mtd_device_register(mtd, pd->parts, pd->num_parts);
325
326	platform_set_drvdata(pdev, ctx);
327
328	return 0;
329
330out3:
331	iounmap(ctx->base);
332out2:
333	release_mem_region(r->start, resource_size(r));
334out1:
335	kfree(ctx);
336	return ret;
337}
338
339static int au1550nd_remove(struct platform_device *pdev)
340{
341	struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
342	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343	struct nand_chip *chip = &ctx->chip;
344	int ret;
345
346	ret = mtd_device_unregister(nand_to_mtd(chip));
347	WARN_ON(ret);
348	nand_cleanup(chip);
349	iounmap(ctx->base);
350	release_mem_region(r->start, 0x1000);
351	kfree(ctx);
352	return 0;
353}
354
355static struct platform_driver au1550nd_driver = {
356	.driver = {
357		.name	= "au1550-nand",
358	},
359	.probe		= au1550nd_probe,
360	.remove		= au1550nd_remove,
361};
362
363module_platform_driver(au1550nd_driver);
364
365MODULE_LICENSE("GPL");
366MODULE_AUTHOR("Embedded Edge, LLC");
367MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
368